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SZNUP4114

型号：

SZNUP4114

品牌：

ONSEMI[ ONSEMI ]

页数：

9 页

PDF大小：

138 K

下载PDF手册
NUP4114 Series,  
SZNUP4114 Series  
Transient Voltage  
Suppressors  
ESD Protection Diodes with Low  
Clamping Voltage  
http://onsemi.com  
The NUP4114 transient voltage suppressors are designed to protect  
high speed data lines from ESD. Ultra−low capacitance and high level  
of ESD protection make these devices well suited for use in USB 2.0  
high speed applications.  
5
1
6
3
4
Features  
• Low Clamping Voltage  
• Small Body Outline Dimensions on SC−88 Package:  
0.082″ x 0.078″ (2.10 mm x 1.25 mm)  
2
• Low Body Height: 0.043″ (1.10 mm)  
MARKING  
DIAGRAMS  
• Stand−off Voltage: 5.5 V  
• Low Leakage  
• Response Time is Typically < 1.0 ns  
• IEC61000−4−2 Level 4 ESD Protection  
• These Devices are Pb−Free and are RoHS Compliant  
• AEC−Q101 Qualified and PPAP Capable − SZNUP4114  
6
SC−88  
W1 SUFFIX  
CASE 419B  
X2 MG  
G
1
1
1
6
• SZ Prefix for Automotive and Other Applications Requiring Unique  
Site and Control Change Requirements  
SC−88  
W1 SUFFIX  
CASE 419B  
Typical Applications  
X4 MG  
G
• LVDS  
• USB 2.0 High Speed Data Line and Power Line Protection  
• Digital Video Interface (DVI) and HDMI  
• Monitors and Flat Panel Displays  
• High Speed Communication Line Protection  
• Notebook Computers  
1
6
TSOP−6  
CASE 318G  
STYLE 12  
P4H MG  
G
1
1
• Gigabit Ethernet  
MAXIMUM RATINGS (T = 25°C unless otherwise noted)  
SOT−563  
CASE 463A  
6
J
P4MG  
G
Rating  
Symbol  
Value  
−40 to +125  
−55 to +150  
260  
Unit  
°C  
1
1
Operating Junction Temperature Range  
Storage Temperature Range  
T
J
XXX = Specific Device Code  
T
stg  
°C  
M
G
= Date Code  
= Pb−Free Package  
Lead Solder Temperature −  
Maximum (10 Seconds)  
T
L
°C  
(Note: Microdot may be in either location)  
IEC 61000−4−2 (ESD)  
Contact  
Air  
8
15  
kV  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 4 of this data sheet.  
Stresses exceeding those listed in the Maximum Ratings table may damage the  
device. If any of these limits are exceeded, device functionality should not be  
assumed, damage may occur and reliability may be affected.  
See Application Note AND8308/D for further description of survivability specs.  
© Semiconductor Components Industries, LLC, 2014  
1
Publication Order Number:  
September, 2014 − Rev. 3  
NUP4114/D  
NUP4114 Series, SZNUP4114 Series  
ELECTRICAL CHARACTERISTICS  
(T = 25°C unless otherwise noted)  
A
I
I
F
Symbol  
Parameter  
Maximum Reverse Peak Pulse Current  
Clamping Voltage @ I  
I
PP  
V
C
PP  
V
Working Peak Reverse Voltage  
RWM  
V
C
V
V
BR RWM  
V
I
R
Maximum Reverse Leakage Current @ V  
RWM  
I
V
F
R
T
I
V
Breakdown Voltage @ I  
Test Current  
BR  
T
I
T
I
F
Forward Current  
V
F
Forward Voltage @ I  
F
I
PP  
P
pk  
Peak Power Dissipation  
C
Capacitance @ V = 0 and f = 1.0 MHz  
Uni−Directional TVS  
R
*See Application Note AND8308/D for detailed explanations of  
datasheet parameters.  
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise specified)  
J
Parameter  
Reverse Working Voltage  
Breakdown Voltage  
Symbol  
Conditions  
Min  
Typ  
Max  
Unit  
V
V
RWM  
(Note 1)  
I = 1 mA, (Note 2)  
5.5  
V
BR  
5.5  
V
T
Reverse Leakage Current  
Clamping Voltage  
I
V
= 5.5 V  
1.0  
9.0  
10  
mA  
V
R
RWM  
V
I
PP  
I
PP  
I
PP  
= 5 A (Note 3)  
= 8 A (Note 3)  
= 1 A (Note 4)  
C
C
Clamping Voltage  
V
V
V
V
Clamping Voltage  
8.3  
10  
V
C
ESD Clamping Voltage  
Maximum Peak Pulse Current  
Junction Capacitance  
Junction Capacitance  
Per IEC61000−4−2 (Note 5)  
See Figures 1 & 2  
C
I
PP  
8x20 ms Waveform (Note 3)  
12  
0.6  
0.3  
A
C
C
V
= 0 V, f = 1 MHz between I/O Pins and GND  
= 0 V, f = 1 MHz between I/O Pins  
pF  
pF  
J
J
R
R
V
1. TVS devices are normally selected according to the working peak reverse voltage (V  
or continuous peak operating voltage level.  
), which should be equal or greater than the DC  
RWM  
2. V is measured at pulse test current I .  
BR  
T
3. Nonrepetitive current pulse (Pin 5 to Pin 2)  
4. Nonrepetitive current pulse (I/O to GND).  
5. For test procedure see Figures 3 and 4 and Application Note AND8307/D.  
6. Include SZ−prefix devices where applicable.  
Figure 1. ESD Clamping Voltage Screenshot  
Positive 8 kV Contact per IEC61000−4−2  
Figure 2. ESD Clamping Voltage Screenshot  
Negative 8 kV Contact per IEC61000−4−2  
http://onsemi.com  
2
 
NUP4114 Series, SZNUP4114 Series  
IEC61000−4−2 Waveform  
IEC 61000−4−2 Spec.  
I
peak  
First Peak  
Current  
(A)  
100%  
90%  
Test Volt-  
age (kV)  
Current at  
30 ns (A)  
Current at  
60 ns (A)  
Level  
1
2
3
4
2
4
6
8
7.5  
15  
4
8
2
4
6
8
I @ 30 ns  
22.5  
30  
12  
16  
I @ 60 ns  
10%  
t
P
= 0.7 ns to 1 ns  
Figure 3. IEC61000−4−2 Spec  
Oscilloscope  
ESD Gun  
TVS  
50 W  
Cable  
50 W  
Figure 4. Diagram of ESD Test Setup  
The following is taken from Application Note  
AND8308/D − Interpretation of Datasheet Parameters  
for ESD Devices.  
systems such as cell phones or laptop computers it is not  
clearly defined in the spec how to specify a clamping voltage  
at the device level. ON Semiconductor has developed a way  
to examine the entire voltage waveform across the ESD  
protection diode over the time domain of an ESD pulse in the  
form of an oscilloscope screenshot, which can be found on  
the datasheets for all ESD protection diodes. For more  
information on how ON Semiconductor creates these  
screenshots and how to interpret them please refer to  
AND8307/D.  
ESD Voltage Clamping  
For sensitive circuit elements it is important to limit the  
voltage that an IC will be exposed to during an ESD event  
to as low a voltage as possible. The ESD clamping voltage  
is the voltage drop across the ESD protection diode during  
an ESD event per the IEC61000−4−2 waveform. Since the  
IEC61000−4−2 was written as a pass/fail spec for larger  
100  
t
r
PEAK VALUE I  
@ 8 ms  
RSM  
90  
80  
70  
60  
50  
40  
30  
20  
PULSE WIDTH (t ) IS DEFINED  
P
AS THAT POINT WHERE THE  
PEAK CURRENT DECAY = 8 ms  
HALF VALUE I /2 @ 20 ms  
RSM  
t
P
10  
0
0
20  
40  
t, TIME (ms)  
60  
80  
Figure 5. 8 X 20 ms Pulse Waveform  
http://onsemi.com  
3
NUP4114 Series, SZNUP4114 Series  
Figure 6. 500 MHz Data Pattern  
ORDERING INFORMATION  
Device  
†
Marking  
Package  
Shipping  
NUP4114UCLW1T2G  
X2  
SC−88  
(Pb−Free)  
3000 / Tape & Reel  
3000 / Tape & Reel  
4000 / Tape & Reel  
3000 / Tape & Reel  
3000 / Tape & Reel  
3000 / Tape & Reel  
NUP4114UCW1T2G  
NUP4114UPXV6T1G  
NUP4114HMR6T1G  
SZNUP4114UCLW1T2G  
SZNUP4114HMR6T1G  
X4  
P4  
SC−88  
(Pb−Free)  
SOT−563  
(Pb−Free)  
P4H  
X2  
TSOP−6  
(Pb−Free)  
SC−88  
(Pb−Free)  
P4H  
TSOP−6  
(Pb−Free)  
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging  
Specifications Brochure, BRD8011/D.  
http://onsemi.com  
4
NUP4114 Series, SZNUP4114 Series  
APPLICATIONS INFORMATION  
Option 2  
The new NUP4114 is a low capacitance TVS diode array  
designed to protect sensitive electronics such as  
communications systems, computers, and computer  
peripherals against damage due to ESD events or transient  
overvoltage conditions. Because of its low capacitance, it  
can be used in high speed I/O data lines. The integrated  
design of the NUP4114 offers low capacitance steering  
diodes and a TVS diode integrated in a single package  
(TSOP−6). If a transient condition occurs, the steering  
diodes will drive the transient to the positive rail of the  
power supply or to ground. The TVS device protects the  
power line against overvoltage conditions to avoid damage  
to the power supply and any downstream components.  
Protection of four data lines with bias and power supply  
isolation resistor.  
I/O 1  
I/O 2  
V
CC  
1
2
3
6
5
4
10 k  
I/O 3  
I/O 4  
NUP4114 Configuration Options  
The NUP4114 is able to protect up to four data lines  
against transient overvoltage conditions by driving them to  
a fixed reference point for clamping purposes. The steering  
diodes will be forward biased whenever the voltage on the  
The NUP4114 can be isolated from the power supply by  
connecting a series resistor between pin 5 and V . A 10 kW  
CC  
resistor is recommended for this application. This will  
maintain a bias on the internal TVS and steering diodes,  
reducing their capacitance.  
protected line exceeds the reference voltage (V or  
f
V
CC  
+ V ). The diodes will force the transient current to  
f
bypass the sensitive circuit.  
Option 3  
Data lines are connected at pins 1, 3, 4 and 6. The negative  
reference is connected at pin 2. This pin must be connected  
directly to ground by using a ground plane to minimize the  
PCB’s ground inductance. It is very important to reduce the  
PCB trace lengths as much as possible to minimize parasitic  
inductances.  
Protection of four data lines using the internal TVS diode  
as reference.  
I/O 1  
I/O 2  
1
2
3
6
5
4
Option 1  
Protection of four data lines and the power supply using  
NC  
V
CC  
as reference.  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
1
2
3
6
5
4
V
CC  
In applications lacking a positive supply reference or  
those cases in which a fully isolated power supply is  
required, the internal TVS can be used as the reference. For  
these applications, pin 5 is not connected. In this  
configuration, the steering diodes will conduct whenever the  
voltage on the protected line exceeds the working voltage of  
I/O 3  
I/O 4  
the TVS plus one diode drop (V = V + VTVS).  
C
f
ESD Protection of Power Supply Lines  
For this configuration, connect pin 5 directly to the  
When using diodes for data line protection, referencing to  
a supply rail provides advantages. Biasing the diodes  
reduces their capacitance and minimizes signal distortion.  
positive supply rail (V ), the data lines are referenced to  
CC  
the supply voltage. The internal TVS diode prevents  
overvoltage on the supply rail. Biasing of the steering diodes  
reduces their capacitance.  
http://onsemi.com  
5
NUP4114 Series, SZNUP4114 Series  
Implementing this topology with discrete devices does have  
disadvantages. This configuration is shown below:  
layout. Taking care to minimize the effects of parasitic  
inductance will provide significant benefits in transient  
immunity.  
Even with good board layout, some disadvantages are still  
present when discrete diodes are used to suppress ESD  
events across datalines and the supply rail. Discrete diodes  
with good transient power capability will have larger die and  
therefore higher capacitance. This capacitance becomes  
problematic as transmission frequencies increase. Reducing  
capacitance generally requires reducing die size. These  
small die will have higher forward voltage characteristics at  
typical ESD transient current levels. This voltage combined  
with the smaller die can result in device failure.  
Power  
Supply  
I
ESDpos  
V
CC  
I
ESDpos  
D1  
D2  
Protected  
Device  
I
Data Line  
ESDneg  
VF + V  
CC  
I
ESDneg  
The ON Semiconductor NUP4114 was developed to  
overcome the disadvantages encountered when using  
discrete diodes for ESD protection. This device integrates a  
TVS diode within a network of steering diodes.  
−VF  
Looking at the figure above, it can be seen that when a  
positive ESD condition occurs, diode D1 will be forward  
biased while diode D2 will be forward biased when a  
negative ESD condition occurs. For slower transient  
conditions, this system may be approximated as follows:  
5
For positive pulse conditions:  
V = V + V  
c
CC  
fD1  
1
6
3
4
For negative pulse conditions:  
V = −V  
c
fD2  
ESD events can have rise times on the order of some  
number of nanoseconds. Under these conditions, the effect  
of parasitic inductance must be considered. A pictorial  
representation of this is shown below.  
2
Figure 7. NUP4114 Equivalent Circuit  
During an ESD condition, the ESD current will be driven  
to ground through the TVS diode as shown below.  
Power  
Supply  
I
ESDpos  
V
CC  
Power  
Supply  
I
ESDpos  
D1  
D2  
I
Protected  
Device  
ESDneg  
V
CC  
Data Line  
I
ESDpos  
D1  
D2  
V
= V + Vf + (L diESD/dt)  
C
CC  
I
ESDneg  
Protected  
Device  
Data Line  
V
C
= −Vf − (L diESD/dt)  
An approximation of the clamping voltage for these fast  
transients would be:  
For positive pulse conditions:  
V = V + Vf + (L diESD/dt)  
c
CC  
The resulting clamping voltage on the protected IC will  
be:  
V = VF + V  
For negative pulse conditions:  
V = −V – (L diESD/dt)  
As shown in the formulas, the clamping voltage (V ) not  
c
f
.
TVS  
c
c
The clamping voltage of the TVS diode depends on the  
magnitude of the ESD current. The steering diodes are fast  
switching devices with unique forward voltage and low  
capacitance characteristics.  
only depends on the Vf of the steering diodes but also on the  
L diESD/dt factor. A relatively small trace inductance can  
result in hundreds of volts appearing on the supply rail. This  
endangers both the power supply and anything attached to  
that rail. This highlights the importance of good board  
http://onsemi.com  
6
NUP4114 Series, SZNUP4114 Series  
PACKAGE DIMENSIONS  
TSOP−6  
CASE 318G−02  
ISSUE U  
NOTES:  
D
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.  
2. CONTROLLING DIMENSION: MILLIMETERS.  
H
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM  
LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL.  
4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,  
PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR  
GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSIONS D  
AND E1 ARE DETERMINED AT DATUM H.  
6
1
5
4
L2  
GAUGE  
PLANE  
E1  
E
5. PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE.  
2
3
L
MILLIMETERS  
SEATING  
PLANE  
M
C
NOTE 5  
DIM  
A
A1  
b
c
D
E
E1  
e
L
MIN  
0.90  
0.01  
0.25  
0.10  
2.90  
2.50  
1.30  
0.85  
0.20  
NOM  
1.00  
MAX  
1.10  
0.10  
0.50  
0.26  
3.10  
3.00  
1.70  
1.05  
0.60  
b
DETAIL Z  
e
0.06  
0.38  
0.18  
3.00  
c
2.75  
A
0.05  
1.50  
0.95  
0.40  
A1  
L2  
M
0.25 BSC  
−
DETAIL Z  
0°  
10°  
RECOMMENDED  
SOLDERING FOOTPRINT*  
6X  
0.60  
6X  
0.95  
3.20  
0.95  
PITCH  
DIMENSIONS: MILLIMETERS  
*For additional information on our Pb−Free strategy and soldering  
details, please download the ON Semiconductor Soldering and  
Mounting Techniques Reference Manual, SOLDERRM/D.  
http://onsemi.com  
7
NUP4114 Series, SZNUP4114 Series  
PACKAGE DIMENSIONS  
SC−88/SC70−6/SOT−363  
D
CASE 419B−02  
ISSUE W  
NOTES:  
e
1. DIMENSIONING AND TOLERANCING PER ANSI  
Y14.5M, 1982.  
2. CONTROLLING DIMENSION: INCH.  
3. 419B−01 OBSOLETE, NEW STANDARD 419B−02.  
6
1
5
2
4
3
MILLIMETERS  
DIM MIN NOM MAX  
0.80  
INCHES  
NOM MAX  
1.10 0.031 0.037 0.043  
0.10 0.000 0.002 0.004  
0.008 REF  
H
−E−  
MIN  
E
A
0.95  
0.05  
A1 0.00  
A3  
0.20 REF  
0.21  
0.14  
2.00  
1.25  
b
C
D
E
e
0.10  
0.10  
1.80  
1.15  
0.30 0.004 0.008 0.012  
0.25 0.004 0.005 0.010  
2.20 0.070 0.078 0.086  
1.35 0.045 0.049 0.053  
0.026 BSC  
b 6 PL  
M
M
E
0.2 (0.008)  
0.65 BSC  
0.20  
L
0.10  
2.00  
0.30 0.004 0.008 0.012  
2.20 0.078 0.082 0.086  
H
2.10  
E
A3  
C
A
A1  
L
SOLDERING FOOTPRINT*  
0.50  
0.0197  
0.65  
0.025  
0.65  
0.025  
0.40  
0.0157  
1.9  
0.0748  
mm  
inches  
ǒ
Ǔ
SCALE 20:1  
SC−88/SC70−6/SOT−363  
*For additional information on our Pb−Free strategy and soldering  
details, please download the ON Semiconductor Soldering and  
Mounting Techniques Reference Manual, SOLDERRM/D.  
http://onsemi.com  
8
NUP4114 Series, SZNUP4114 Series  
PACKAGE DIMENSIONS  
SOT−563, 6 LEAD  
CASE 463A−01  
ISSUE F  
NOTES:  
1. DIMENSIONING AND TOLERANCING PER ANSI  
Y14.5M, 1982.  
D
2. CONTROLLING DIMENSION: MILLIMETERS  
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD  
FINISH THICKNESS. MINIMUM LEAD THICKNESS  
IS THE MINIMUM THICKNESS OF BASE MATERIAL.  
A
−X−  
L
6
5
2
4
3
MILLIMETERS  
DIM MIN NOM MAX  
INCHES  
NOM MAX  
E
−Y−  
MIN  
H
E
A
b
C
D
E
e
0.50  
0.17  
0.08  
1.50  
1.10  
0.55  
0.22  
0.12  
1.60  
1.20  
0.60 0.020 0.021 0.023  
0.27 0.007 0.009 0.011  
0.18 0.003 0.005 0.007  
1.70 0.059 0.062 0.066  
1.30 0.043 0.047 0.051  
0.02 BSC  
1
b 56 PL  
C
0.5 BSC  
0.20  
e
M
0.08 (0.003)  
X Y  
L
0.10  
1.50  
0.30 0.004 0.008 0.012  
1.70 0.059 0.062 0.066  
H
1.60  
E
SOLDERING FOOTPRINT*  
0.3  
0.0118  
0.45  
0.0177  
1.0  
0.0394  
1.35  
0.0531  
0.5  
0.5  
0.0197 0.0197  
mm  
inches  
ǒ
Ǔ
SCALE 20:1  
*For additional information on our Pb−Free strategy and soldering  
details, please download the ON Semiconductor Soldering and  
Mounting Techniques Reference Manual, SOLDERRM/D.  
ON Semiconductor and the  
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.  
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed  
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation  
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and  
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets  
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each  
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,  
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which  
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or  
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and  
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim  
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable  
copyright laws and is not for resale in any manner.  
PUBLICATION ORDERING INFORMATION  
LITERATURE FULFILLMENT:  
N. American Technical Support: 800−282−9855 Toll Free  
USA/Canada  
Europe, Middle East and Africa Technical Support:  
Phone: 421 33 790 2910  
Japan Customer Focus Center  
Phone: 81−3−5817−1050  
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NUP4114/D  
厂商 型号 描述 页数 下载

ETC

 		SZN-002T-P0.7K [ Crimping tools ] 6 页

ETC

 		SZN-003T-P0.7K [ Crimping tools ] 6 页

SSDI

 		SZN4460 3.3 - 200伏齐纳二极管[ 3.3 – 200 VOLTS ZENER DIODES ] 2 页

SSDI

 		SZN4460C [ Zener Diode, 6.2V V(Z), 2%, 1.5W, Silicon, Unidirectional, HERMETIC SEALED, GLASS PACKAGE-2 ] 2 页

SSDI

 		SZN4460CSMS [ Zener Diode, 6.2V V(Z), 2%, 1.5W, Silicon, Unidirectional, HERMETIC SEALED, GLASS, SMS, 2 PIN ] 2 页

SSDI

 		SZN4460CSMSNGC [ Zener Diode ] 2 页

SSDI

 		SZN4460CSMSS [ 暂无描述 ] 2 页

SSDI

 		SZN4460CSMSTX [ Zener Diode, 6.2V V(Z), 2%, 1.5W, Silicon, Unidirectional, HERMETIC SEALED, GLASS, SMS, 2 PIN ] 2 页

SSDI

 		SZN4460CSMSTXV [ Zener Diode, 6.2V V(Z), 2%, 1.5W, Silicon, Unidirectional, HERMETIC SEALED, GLASS, SMS, 2 PIN ] 2 页

SSDI

 		SZN4460CSMTXV [ Zener Diode ] 2 页

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