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NYT6-5D6DT4G

型号：

NYT6-5D6DT4G

品牌：

ONSEMI[ ONSEMI ]

页数：

7 页

PDF大小：

124 K

下载PDF手册
NYT6-5D6DTG,  
NYT6-5D6DT4G  
Sensitive Gate Triacs  
Silicon Bidirectional Thyristors  
Designed for high volume, low cost, industrial and consumer  
applications such as motor control; process control; temperature, light  
and speed control.  
http://onsemi.com  
TRIACS  
6.0 AMPERES RMS  
600 VOLTS  
Features  
• Passivated Die for Reliability and Uniformity  
• Four−Quadrant Triggering  
• Blocking Voltage to 600 V  
• On−State Current Rating of 6.0 A RMS at 93°C  
• Low Level Triggering and Holding Characteristics  
• Epoxy Meets UL 94 V−0 @ 0.125 in  
• These are Pb−Free Devices  
MT2  
MT1  
G
MARKING  
DIAGRAMS  
MAXIMUM RATINGS (T = 25°C unless otherwise noted)  
J
Rating  
Symbol  
Value  
Unit  
4
DPAK  
CASE 369C  
STYLE 6  
YWW  
NYT  
6−5D6G  
Peak Repetitive Off−State Voltage (Note 1)  
V
V
600  
V
DRM,  
(T = −40 to 110°C, Sine Wave,  
J
RRM  
2
1
50 to 60 Hz, Gate Open)  
3
On−State RMS Current  
I
6.0  
60  
A
A
T(RMS)  
(Full Cycle Sine Wave, 60 Hz, T = 85°C)  
C
4
Peak Non-Repetitive Surge Current  
(One Full Cycle, 60 Hz, T  
I
TSM  
= 25°C)  
Jinitial  
IPAK  
CASE 369D  
STYLE 6  
YWW  
NYT  
6−5D6G  
2
2
Circuit Fusing Consideration (t = 8.3 msec)  
I t  
6.6  
2.0  
A sec  
1
Peak Gate Power  
P
W
W
A
GM  
2
(Pulse Width ≤ 10 ꢀ sec, T = 93°C)  
C
3
Average Gate Power  
P
1.0  
4.0  
5.0  
G(AV)  
Y
WW  
= Year  
= Work Week  
NYT6−5D6= Device Code  
(t = 8.3 msec, T = 93°C)  
C
Peak Gate Current  
I
GM  
(Pulse Width ≤ 20 ꢀ sec, T = 93°C)  
C
G
= Pb−Free Package  
Peak Gate Voltage  
V
V
GM  
(Pulse Width ≤ 20 ꢀ sec, T = 93°C)  
C
PIN ASSIGNMENT  
Operating Junction Temperature Range  
Storage Temperature Range  
T
−40 to 110  
−40 to 150  
°C  
°C  
J
1
Main Terminal 1  
T
stg  
2
3
4
Main Terminal 2  
Gate  
Stresses exceeding Maximum Ratings may damage the device. Maximum  
Ratings are stress ratings only. Functional operation above the Recommended  
Operating Conditions is not implied. Extended exposure to stresses above the  
Recommended Operating Conditions may affect device reliability.  
Main Terminal 2  
1. V  
and V  
for all types can be applied on a continuous basis. Blocking  
DRM  
RRM  
voltages shall not be tested with a constant current source such that the  
voltage ratings of the device are exceeded.  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 2 of this data sheet.  
©
Semiconductor Components Industries, LLC, 2012  
1
Publication Order Number:  
October, 2012 − Rev. 2  
NYT6−5D6D/D  
 
NYT6−5D6DTG, NYT6−5D6DT4G  
THERMAL CHARACTERISTICS  
Characteristic  
Symbol  
Max  
Unit  
Thermal Resistance, − Junction−to−Case  
− Junction−to−Ambient  
R
ꢁ
JC  
R
ꢁ
JA  
R
ꢁ
JA  
3.5  
88  
80  
°C/W  
− Junction−to−Ambient (Note 2)  
Maximum Lead Temperature for Soldering Purposes (Note 3)  
T
260  
°C  
L
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted; Electricals apply in both directions)  
Characteristic  
Symbol  
Min  
Typ  
Max  
Unit  
OFF CHARACTERISTICS  
Peak Repetitive Forward or Reverse Blocking Current  
T = 25°C  
J
I
−
−
−
−
0.001  
0.5  
mA  
J
DRM,  
RRM  
(VAK = Rated V or V ; Gate Open)  
T = 110°C  
I
DRM  
RRM  
ON CHARACTERISTICS  
Forward On−State Voltage (I  
=
ꢀ8.5 A)  
V
TM  
−
−
1.6  
V
TM  
Gate Trigger Current (Continuous dc) (V = 12 V, R = 30 ꢂ)  
I
mA  
D
L
GT  
MT2(+), G(+)  
MT2(+), G(−)  
MT2(−), G(−)  
MT2(−), G(+)  
−
−
−
−
−
−
−
−
5.0  
5.0  
5.0  
10  
Gate Trigger Voltage (V = 12 V, R = 30 ꢂ)  
V
V
V
D
L
GT  
MT2(+), G(+)  
MT2(+), G(−)  
MT2(−), G(−)  
MT2(−), G(+)  
−
−
−
−
−
−
−
−
1.3  
1.3  
1.3  
1.3  
Gate Non−Trigger Voltage (Continuous dc) − (V = 12 V, R = 30 ꢂ, T = 110°C)  
All Four Quadrants  
V
GD  
0.2  
0.4  
−
D
L
J
Holding Current (V = 12 V, Initiating Current = ꢀ100 mA)  
I
−
−
20  
mA  
mA  
D
H
Latching Current (V = 12 V, I = 60 mA)  
I
L
D
G
MT2(+), G(+)  
MT2(+), G(−)  
MT2(−), G(−)  
MT2(−), G(+)  
−
−
−
−
30  
30  
30  
30  
−
−
−
DYNAMIC CHARACTERISTICS  
Rate of Change of Commutating Current  
di/dt(c)  
A/ms  
(V = 200 V, I = 1.8 A, Commutating dv/dt = 1.0 V/ꢀ sec, T = 110°C, f = 250 Hz,  
−
1.5  
−
D
TM  
J
CL = 5.0 ꢀ fd, LL = 80 mH, RS = 56 ꢂ, CS = 0.03 ꢀ fd) With snubber  
Critical Rate of Rise of Off−State Voltage  
dv/dt  
dI/dt  
V/ꢀ s  
A/ꢀ s  
(V = 0.67 X Rated V  
, Exponential Waveform, Gate Open, T = 110°C)  
60  
−
−
−
D
DRM  
J
Critical Rate of Rise of On−State Current  
(T = 110°C, f = 120 Hz, I = 2 x I , tr ≤ 100 ns)  
−
50  
J
G
GT  
2. These ratings are applicable when surface mounted on the minimum pad sizes recommended.  
3. 1/8″ from case for 10 seconds.  
4. Pulse Test: Pulse Width ≤ 2.0 msec, Duty Cycle ≤ 2%.  
ORDERING INFORMATION  
†
Device  
NYT6−5D6DTG  
Package Type  
Package  
Shipping  
IPAK  
(Pb−Free)  
369D  
75 Units / Rail  
NYT6−5D6DT4G  
DPAK  
(Pb−Free)  
369C  
2500 / Tape & Reel  
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging  
Specifications Brochure, BRD8011/D.  
http://onsemi.com  
2
 
NYT6−5D6DTG, NYT6−5D6DT4G  
Voltage Current Characteristic of Triacs  
(Bidirectional Device)  
+ Current  
Quadrant 1  
MainTerminal 2 +  
Symbol  
Parameter  
V
TM  
V
Peak Repetitive Forward Off−State Voltage  
Peak Forward Blocking Current  
DRM  
DRM  
on state  
I
I
H
I
at V  
RRM  
V
Peak Repetitive Reverse Off−State Voltage  
Peak Reverse Blocking Current  
RRM  
RRM  
RRM  
I
V
Maximum On−State Voltage  
+ Voltage  
DRM  
off state  
TM  
I
H
I
at V  
DRM  
I
H
Holding Current  
Quadrant 3  
MainTerminal 2 −  
V
TM  
Quadrant Definitions for a Triac  
MT2 POSITIVE  
(Positive Half Cycle)  
+
(+) MT2  
(+) MT2  
Quadrant II  
Quadrant I  
(−) I  
(+) I  
GT  
GT  
GATE  
GATE  
MT1  
MT1  
REF  
REF  
I
−
+ I  
GT  
GT  
(−) MT2  
(−) MT2  
Quadrant III  
Quadrant IV  
(+) I  
(−) I  
GT  
GT  
GATE  
GATE  
MT1  
REF  
MT1  
REF  
−
MT2 NEGATIVE  
(Negative Half Cycle)  
All polarities are referenced to MT1.  
With in−phase signals (using standard AC lines) quadrants I and III are used.  
http://onsemi.com  
3
NYT6−5D6DTG, NYT6−5D6DT4G  
110  
105  
6.0  
5.0  
dc  
180°  
α
120°  
ꢃ = 30°  
α
90°  
60°  
4.0  
3.0  
2.0  
90°  
ꢃ = CONDUCTION ANGLE  
100  
95  
α
α
60°  
120°  
ꢃ = 30°  
ꢃ = CONDUCTION ANGLE  
1.0  
0
180°  
dc  
90  
0
0.5  
1.0  
1.5  
2.0  
2.5  
3.0  
3.5  
4.0  
0
0.5  
1.0  
1.5  
2.0  
2.5  
3.0  
3.5 4.0  
I , RMS ON−STATE CURRENT (A)  
T(RMS)  
I , RMS ON−STATE CURRENT (A)  
T(RMS)  
Figure 1. RMS Current Derating  
Figure 2. On−State Power Dissipation  
100  
1.0  
0.1  
10  
Z
= R  
Sr(t)  
ꢁ
JC(t)  
ꢁ
JC(t)  
T = 125°C  
J
0.01  
0.1  
1.0  
10  
100  
1000  
10 k  
1
t, TIME (ms)  
Figure 4. Transient Thermal Response  
T = 25°C  
J
0.1  
0.01  
T = −40°C  
J
0.001  
0
0.5  
1
1.5  
2
2.5  
3
3.5  
4
V , INSTANTANEOUS ON-STATE VOLTAGE (V)  
T
Figure 3. Maximum On−State Voltage  
Characteristics  
http://onsemi.com  
4
NYT6−5D6DTG, NYT6−5D6DT4G  
21  
18  
15  
12  
9
0.9  
Q4  
0.8  
Q1 & Q3  
0.7  
0.6  
0.5  
0.4  
0.3  
Q2  
Q4  
Q2 & Q3  
6
Q1  
3
0
−40 −20 −10  
5
20 35 50 65 80 95 110 125  
−40 −20 −10  
5
20 35 50 65 80 95 110 125  
T , JUNCTION TEMPERATURE (°C)  
J
T , JUNCTION TEMPERATURE (°C)  
J
Figure 5. Typical Gate Trigger Current  
Figure 6. Typical Gate Trigger Voltage  
18  
16  
14  
12  
10  
8
10  
8
Q2  
MTI1 Negative  
6
Q3 & Q4  
4
6
Q1  
4
MTI1 Positive  
2
2
0
0
−40 −20 −10  
5
20 35 50 65 80 95 110 125  
−40 −20 −10  
5
20 35 50 65 80 95 110 125  
T , JUNCTION TEMPERATURE (°C)  
J
T , JUNCTION TEMPERATURE (°C)  
J
Figure 7. Typical Latching Current  
Figure 8. Typical Holding Current  
http://onsemi.com  
5
NYT6−5D6DTG, NYT6−5D6DT4G  
PACKAGE DIMENSIONS  
DPAK (SINGLE GAUGE)  
CASE 369C  
ISSUE D  
NOTES:  
1. DIMENSIONING AND TOLERANCING PER ASME  
Y14.5M, 1994.  
C
A
D
2. CONTROLLING DIMENSION: INCHES.  
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DI-  
MENSIONS b3, L3 and Z.  
A
E
c2  
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD  
FLASH, PROTRUSIONS, OR BURRS. MOLD  
FLASH, PROTRUSIONS, OR GATE BURRS SHALL  
NOT EXCEED 0.006 INCHES PER SIDE.  
5. DIMENSIONS D AND E ARE DETERMINED AT THE  
OUTERMOST EXTREMES OF THE PLASTIC BODY.  
6. DATUMS A AND B ARE DETERMINED AT DATUM  
PLANE H.  
b3  
B
4
2
L3  
L4  
Z
H
DETAIL A  
1
3
INCHES  
DIM MIN MAX  
0.086 0.094  
A1 0.000 0.005  
0.025 0.035  
MILLIMETERS  
MIN  
2.18  
0.00  
0.63  
0.76  
4.57  
0.46  
0.46  
5.97  
6.35  
MAX  
2.38  
0.13  
0.89  
1.14  
5.46  
0.61  
0.61  
6.22  
6.73  
A
b2  
c
b
b
b2 0.030 0.045  
b3 0.180 0.215  
M
0.005 (0.13)  
C
H
e
c
0.018 0.024  
c2 0.018 0.024  
GAUGE  
PLANE  
SEATING  
PLANE  
L2  
C
D
E
e
0.235 0.245  
0.250 0.265  
0.090 BSC  
2.29 BSC  
9.40 10.41  
1.40 1.78  
2.74 REF  
0.51 BSC  
0.89 1.27  
H
L
L1  
L2  
0.370 0.410  
0.055 0.070  
0.108 REF  
L
A1  
L1  
0.020 BSC  
DETAIL A  
L3 0.035 0.050  
ROTATED 905 CW  
L4  
Z
−−− 0.040  
0.155 −−−  
−−−  
3.93  
1.01  
−−−  
STYLE 6:  
PIN 1. MT1  
2. MT2  
SOLDERING FOOTPRINT*  
3. GATE  
4. MT2  
6.20  
0.244  
3.00  
0.118  
2.58  
0.102  
5.80  
0.228  
1.60  
0.063  
6.17  
0.243  
mm  
inches  
ǒ
Ǔ
SCALE 3:1  
*For additional information on our Pb−Free strategy and soldering  
details, please download the ON Semiconductor Soldering and  
Mounting Techniques Reference Manual, SOLDERRM/D.  
http://onsemi.com  
6
NYT6−5D6DTG, NYT6−5D6DT4G  
PACKAGE DIMENSIONS  
IPAK  
CASE 369D  
ISSUE C  
C
B
R
NOTES:  
1. DIMENSIONING AND TOLERANCING PER  
ANSI Y14.5M, 1982.  
2. CONTROLLING DIMENSION: INCH.  
V
S
E
INCHES  
DIM MIN MAX  
MILLIMETERS  
4
2
MIN  
5.97  
6.35  
2.19  
0.69  
0.46  
0.94  
MAX  
6.35  
6.73  
2.38  
0.88  
0.58  
1.14  
Z
A
B
C
D
E
F
G
H
J
K
R
S
V
Z
0.235 0.245  
0.250 0.265  
0.086 0.094  
0.027 0.035  
0.018 0.023  
0.037 0.045  
0.090 BSC  
0.034 0.040  
0.018 0.023  
0.350 0.380  
0.180 0.215  
0.025 0.040  
0.035 0.050  
A
K
1
3
−T−  
SEATING  
PLANE  
2.29 BSC  
0.87  
0.46  
8.89  
4.45  
0.63  
0.89  
3.93  
1.01  
0.58  
9.65  
5.45  
1.01  
1.27  
−−−  
J
F
H
0.155  
−−−  
D 3 PL  
STYLE 6:  
PIN 1. MT1  
2. MT2  
G
M
T
0.13 (0.005)  
3. GATE  
4. MT2  
ON Semiconductor and  
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,  
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC  
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any  
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without  
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications  
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC  
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for  
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where  
personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and  
its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,  
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture  
of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.  
PUBLICATION ORDERING INFORMATION  
LITERATURE FULFILLMENT:  
N. American Technical Support: 800−282−9855 Toll Free  
USA/Canada  
Europe, Middle East and Africa Technical Support:  
Phone: 421 33 790 2910  
Japan Customer Focus Center  
Phone: 81−3−5817−1050  
ON Semiconductor Website: www.onsemi.com  
Order Literature: http://www.onsemi.com/orderlit  
Literature Distribution Center for ON Semiconductor  
P.O. Box 5163, Denver, Colorado 80217 USA  
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada  
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada  
Email: orderlit@onsemi.com  
For additional information, please contact your local  
Sales Representative  
NYT6−5D6D/D  
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 		NYT6-5D6DTG [ Sensitive Gate Triacs ] 7 页

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