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8R9306NLGI

型号：

8R9306NLGI

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

19 页

PDF大小：

654 K

下载PDF手册
TM  
2.5V LVDS, 1:6 Clock Buffer Terabuffer II  
IDT8R9306I  
DATASHEET  
General Description  
Features  
The IDT8R9306I 2.5V differential clock buffer is a user-selectable  
differential input to six LVDS outputs. The fanout from a differential  
input to six LVDS outputs reduces loading on the preceding driver  
and provides an efficient clock distribution network. The IDT8R9306I  
can act as a translator from a differential HSTL, eHSTL, LVPECL  
(2.5V), LVPECL (3.3V), CML, or LVDS input to LVDS outputs. A  
single-ended 3.3V, 2.5V LVTTL input can also be used to translate to  
LVDS outputs. The redundant input capability allows for an  
asynchronous change-over from a primary clock source to a  
secondary clock source. Selectable reference inputs are controlled  
by SEL.  
• Guaranteed low skew: 40ps (maximum)  
• Very low duty cycle distortion: <125ps (maximum)  
• High speed propagation delay: <1.75ns (maximum)  
• Up to 1GHz operation  
• Selectable inputs  
• Hot insertable and over-voltage tolerant inputs  
• 3.3V/2.5V LVTTL, HSTL eHSTL, LVPECL (2.5V), LVPECL (3.3V),  
CML or LVDS input interface  
• Selectable differential inputs to six LVDS outputs  
• Power-down mode  
• 2.5V VDD  
• -40°C to 85°C ambient operating temperature  
• Available in VFQFPN package  
The IDT8R9306I outputs can be asynchronously enabled/disabled.  
When disabled, the outputs will drive to the value selected by the GL  
pin. Multiple power and grounds reduce noise.  
Applications  
• Clock distribution  
Pin Assignment  
21 20 19 18 17 16 15  
nc 22  
VDD  
14  
nQ5 23  
13 nQ3  
24  
Q3  
Q5  
12  
11  
GND  
nQ6 25  
nQ2  
26  
10 Q2  
Q6  
27  
VDD  
VDD  
GL  
9
8
SEL 28  
1
2
3
4
5
6
7
IDT8R9306I  
28-Lead VFQFPN  
6mm x 6mm x 0.9mm package body  
EPad 4.8mm x 4.8mm  
NL Package  
Top View  
IDT8R9306NLI REVISION D AUGUST 21, 2013  
1
©2013 Integrated Device Technology, Inc.  
IDT8R9306I Data Sheet  
2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II  
Block Diagram  
GL  
nG  
Q1  
OUTPUT  
CONTROL  
nQ1  
nPD  
Q2  
OUTPUT  
CONTROL  
nQ2  
A1  
1
0
nA1  
Q3  
OUTPUT  
CONTROL  
nQ3  
A2  
Q4  
OUTPUT  
CONTROL  
nA2  
nQ4  
Q5  
OUTPUT  
SEL  
CONTROL  
nQ5  
Q6  
OUTPUT  
CONTROL  
nQ6  
IDT8R9306NLI REVISION D AUGUST 21, 2013  
2
©2013 Integrated Device Technology, Inc.  
IDT8R9306I Data Sheet  
2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II  
Pin Descriptions and Characteristics  
Table 1. Pin Descriptions  
Name  
Type  
Description  
A[1:2]  
Input  
Input  
Adjustable (1, 4) Clock input. A[1:2] is the "true" side of the differential clock input.  
Complementary clock inputs. nA[1:2] is the complementary side of A[1:2]. For LVTTL  
single-ended operation, nA[1:2] should be set to the desired toggle voltage for A[1:2]:  
3.3V LVTTL VREF = 1650mV  
nA[1:2]  
Adjustable (1, 4)  
2.5V LVTTL VREF = 1250mV  
Gate control for differential outputs Q[1:6] and nQ[1:6]. When nG is LOW, the differential  
nG  
GL  
Input  
Input  
LVTTL  
LVTTL  
outputs are active. When nG is HIGH, the differential outputs are asynchronously driven to  
the level designated by GL(2). See Table 3A.  
Specifies output disable level. If HIGH, "true" outputs disable HIGH and "complementary"  
outputs disable LOW. If LOW, "true" outputs disable LOW and "complementary" outputs  
disable HIGH. See Table 3A.  
Q[1:6]  
Output  
Output  
LVDS  
LVDS  
Clock outputs.  
nQ[1:6]  
Complementary clock outputs.  
Reference clock select. When LOW, selects A2 and nA2. When HIGH, selects A1 and nA1.  
See Table 3B.  
SEL  
nPD  
Input  
Input  
LVTTL  
LVTTL  
Power-down control. Shuts off entire chip. If LOW, the device goes into low power mode.  
Inputs and outputs are disabled. Both "true" and “complementary” outputs will pull to VDD.  
Set HIGH for normal operation.(3)  
VDD  
GND  
nc  
Power  
Power  
Power supply for the device core and inputs.  
Power supply return for all power.  
No connect; recommended to connect to GND.  
NOTES:  
1
Inputs are capable of translating the following interface standards:  
Single-ended 3.3V and 2.5V LVTTL levels  
Differential HSTL and eHSTL levels  
Differential LVPECL (2.5V) and LVPECL (3.3V) levels  
Differential LVDS levels  
Differential CML levels  
2.  
3.  
4.  
Because the gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control  
signals to minimize the possibility of runt pulses or be able to tolerate them in down stream circuitry.  
It is recommended that the outputs be disabled before entering power-down mode. It is also recommended that the outputs remain  
disabled until the device completes power-up after asserting nPD.  
The user must take precautions with any differential input interface standard being used in order to prevent instability when there is  
no input signal.  
Table 2. Pin Characteristics, TA = +25°C, F = 1.0MHz)  
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
CIN  
Input Capacitance  
3
pF  
NOTE: This parameter is measured at characterization but not tested.  
IDT8R9306NLI REVISION D AUGUST 21, 2013  
3
©2013 Integrated Device Technology, Inc.  
IDT8R9306I Data Sheet  
2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II  
Function Tables  
Table 3A. Gate Control Output Table  
Control Output  
Outputs  
GL  
0
nG  
0
Q[1:6]  
Toggling  
LOW  
nQ[1:6]  
Toggling  
HIGH  
0
1
1
0
Toggling  
HIGH  
Toggling  
LOW  
1
1
Table 3B. Input Selection Table  
Selection SEL pin  
Inputs  
A2, nA2  
A1, nA1  
0
1
Absolute Maximum Ratings  
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress  
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC  
Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.  
Item  
Rating  
Power Supply Voltage, VDD  
Input Voltage, VI  
-0.5V to +3.6V  
-0.5V to +3.6V  
Output Voltage, VO  
Not to exceed 3.6V  
-0.5 to VDD +0.5V  
Storage Temperature, TSTG  
Junction Temperature, TJ  
-65C to 150C  
150C  
Recommended Operating Range  
Symbol  
TA  
Description  
Minimum  
Typical  
+25  
Maximum  
+85  
Units  
C  
Ambient Operating Temperature  
Internal Power Supply Voltage  
-40  
2.3  
VDD  
2.5  
2.7  
V
IDT8R9306NLI REVISION D AUGUST 21, 2013  
4
©2013 Integrated Device Technology, Inc.  
IDT8R9306I Data Sheet  
2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II  
DC Electrical Characteristics  
Table 4A. LVDS Power Supply DC Characteristics , T = -40°C to 85°C  
(1)  
A
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical(2)  
Maximum  
Units  
VDD = Max.,  
All Input Clocks = LOW(2)  
Outputs enabled  
Quiescent VDD Power Supply  
Current  
IDDQ  
;
240  
mA  
Total Power VDD Supply  
Current  
VDD = 2.7V;  
REFERENCE Clock = 1GHz  
ITOT  
IPD  
250  
5
mA  
mA  
F
Total Power Down Supply  
Current  
nPD = LOW  
NOTE 1: These power consumption characteristics are for all the valid input interfaces and cover the worst case conditions.  
NOTE 2: The true input is held LOW and the complementary input is held HIGH.  
(1)  
Table 4B. LVCMOS/LVTTL DC Characteristics , T = -40°C to 85°C  
A
Symbol  
IIH  
Parameter  
Test Conditions  
VDD = 2.7V  
Minimum  
Typical(2)  
Maximum  
Units  
µA  
µA  
V
Input High Current  
Input Low Current  
Clamp Diode Voltage  
DC Input Voltage  
DC Input High Voltage  
DC Input Low Voltage  
5
5
IIL  
VDD = 2.7V  
VIK  
VDD = 2.3V, IIN = -18mA  
-0.7  
-1.2  
3.6  
VIN  
-0.3  
1.7  
V
VIH  
V
VIL  
0.7  
V
DC Input Threshold Crossing  
Voltage  
VTHI  
VDD/2  
V
3.3V LVTTL  
2.5V LVTTL  
1.65  
1.25  
V
V
Single-Ended Reference  
Voltage (3)  
VREF  
NOTE 1: See Recommended Operating Range table.  
NOTE 2: Typical values are at VDD = 2.5V, +25°C ambient.  
NOTE 3: For A[1:2] single-ended operation, nA[1:2] is tied to a DC reference voltage.  
(1)  
Table 4C. Differential DC Characteristics , T = -40°C to 85°C  
A
Symbol  
IIH  
Parameter  
Test Conditions  
VDD = 2.7V  
Minimum  
Typical(2)  
Maximum  
Units  
µA  
µA  
V
Input High Current  
Input Low Current  
Clamp Diode Voltage  
DC Input Voltage  
DC Differential Voltage(3)  
5
5
IIL  
VDD = 2.7V  
VIK  
VDD = 2.3V, IIN = -18mA  
-0.7  
-1.2  
3.6  
VIN  
-0.3  
0.1  
V
VDIF  
V
DC Common Mode Input  
Voltage  
VCM  
0.05  
VDD  
V
NOTE 1: See Recommended Operating Range table.  
NOTE 2: Typical values are at VDD = 2.5V, +25°C ambient.  
NOTE 3: VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is  
the "complement" input level. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC  
differential voltage must be achieved to guarantee switching to a new state.  
NOTE 4: VCM specifies the maximum allowable range of (VTR + VCP) /2.  
IDT8R9306NLI REVISION D AUGUST 21, 2013  
5
©2013 Integrated Device Technology, Inc.  
IDT8R9306I Data Sheet  
2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II  
(1)  
Table 4D. LVDS DC Characteristics , T = -40°C to 85°C  
A
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical(2)  
Maximum  
Units  
Differential Output Voltage for  
the  
VOT(+)  
247  
454  
mV  
True Binary State  
Differential Output Voltage for  
the  
False Binary State  
VOT(–)  
VOT  
VOS  
247  
454  
50  
mV  
mV  
V
Change in VOT Between  
Complementary Output  
States  
Output Common Mode  
Voltage  
(Offset Voltage)  
1.125  
1.2  
1.375  
50  
Change in VOS Between  
Complementary Output  
States  
VOS  
mV  
IOS  
Outputs Short Circuit Current  
VOUT+ and VOUT– = 0V  
12  
6
24  
12  
mA  
mA  
Differential Outputs Short  
Circuit Current  
IOSD  
VOUT+ = VOUT–  
NOTE 1: See Recommended Operating Range table.  
NOTE 2: Typical values are at VDD = 2.5V, +25°C ambient.  
AC Electrical Characteristics  
Table 5A. HSTL Differential Input AC Characteristics, T = -40°C to 85°C  
A
Symbol  
VDIF  
VX  
Parameter  
Input Signal Swing(1)  
Differential Input Signal Crossing Point(2)  
Value  
1
Units  
V
750  
50  
mV  
%
DH  
Duty Cycle  
VTHI  
tR / tF  
Input Timing Measurement Reference Level(3)  
Input Signal Edge Rate(4)  
Crossing Point  
2
V
V/ns  
NOTE 1. The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE)  
environment. This device meets the VDIF (AC) specification under actual use conditions.  
NOTE 2. A 750mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment.  
This device meets the VX specification under actual use conditions.  
NOTE 3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.  
NOTE 4. The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.  
IDT8R9306NLI REVISION D AUGUST 21, 2013  
6
©2013 Integrated Device Technology, Inc.  
IDT8R9306I Data Sheet  
2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II  
Table 5B. eHSTL AC Differential Input Characteristics, T = -40°C to 85°C  
A
Symbol  
VDIF  
VX  
Parameter  
Input Signal Swing(1)  
Differential Input Signal Crossing Point(2)  
Value  
Units  
V
1
900  
mV  
%
DH  
Duty Cycle  
50  
VTHI  
tR / tF  
Input Timing Measurement Reference Level(3)  
Input Signal Edge Rate(4)  
Crossing Point  
2
V
V/ns  
NOTE 1: The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE)  
environment. This device meets the VDIF (AC) specification under actual use conditions.  
NOTE 2: A 900mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment.  
This device meets the VX specification under actual use conditions.  
NOTE 3: In all cases, input waveform timing is marked at the differential cross-point of the input signals.  
NOTE 4: The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.  
Table 5C. LVPECL (2.5V) and LVPECL (3.3V) Differential Input AC Characteristics, T = -40°C to 85°C  
A
Symbol Parameter  
Maximum  
Units  
mV  
mV  
mV  
%
VDIF  
Input Signal Swing(1)  
732  
LVPECL  
LVPECL  
1082  
VX  
Differential Input Cross Point Voltage(2)  
1880  
DH  
Duty Cycle  
50  
VTHI  
tR / tF  
Input Timing Measurement Reference Level(3)  
Input Signal Edge Rate(4)  
Crossing Point  
2
V
V/ns  
NOTE 1: The 732mV peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE)  
environment. This device meets the VDIF (AC) specification under actual use conditions.  
NOTE 2: A 1082mV LVPECL (2.5V) and 1880 LVPECL (3.3V) crossing point level is specified to allow consistent, repeatable results in an  
automatic test equipment (ATE) environment. This device meets the VX specification under actual use conditions.  
NOTE 3: In all cases, input waveform timing is marked at the differential cross-point of the input signals.  
NOTE 4: The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.  
Table 5D. LVDS Differential Input AC Characteristics, T = -40°C to 85°C  
A
Symbol Parameter  
Maximum  
Units  
mV  
V
VDIF  
VX  
Input Signal Swing(1)  
Differential Input Cross Point Voltage(2)  
400  
1.2  
DH  
Duty Cycle  
50  
%
VTHI  
tR / tF  
Input Timing Measurement Reference Level(3)  
Input Signal Edge Rate(4)  
Crossing Point  
2
V
V/ns  
NOTE 1: The 400mV peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE)  
environment. This device meets the VDIF (AC) specification under actual use conditions.  
NOTE 2: A 1.2V crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This  
device meets the VX specification under actual use conditions.  
NOTE 3: In all cases, input waveform timing is marked at the differential cross-point of the input signals.  
NOTE 4: The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.  
IDT8R9306NLI REVISION D AUGUST 21, 2013  
7
©2013 Integrated Device Technology, Inc.  
IDT8R9306I Data Sheet  
2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II  
(1)  
Table 5E. AC Differential Input Characteristics , T = -40°C to 85°C  
A
Symbol  
VDIF  
VX  
Parameter  
Minimum  
0.1  
Typical  
Maximum  
3.6  
Units  
V
AC Differential Voltage(2)  
Differential Input Cross Point Voltage  
Common Mode Input Voltage Range(3)  
Input Voltage  
0.05  
VDD  
V
VCM  
VIN  
0.05  
VDD  
V
-0.3  
3.6  
V/ns  
NOTE 1: The output will not change state until the inputs have crossed and the minimum differential voltage range defined by VDIF has been  
met or exceeded.  
NOTE 2: VDIF specifies the minimum input voltage (VTR – VCP) required for switching where VTR is the “true” input level and VCP is the  
“complement” input level. The AC differential voltage must be achieved to guarantee switching to a new state.  
NOTE 3: IVCM specified the maximum allowable range of (VTR + VCP) /2.  
(1,5)  
Table 5F. AC Characteristics  
, T = -40°C to 85°C  
A
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
Same Device Output Pin-to-Pin  
Skew (2)  
tsk(o)  
40  
ps  
tsk(p)  
Pulse Skew(3)  
Part-to-Part Skew(4)  
125  
300  
ps  
ps  
tsk(pp)  
25MHz, Integration Range  
12kHz – 10MHz  
0.541  
0.159  
0.185  
ps  
ps  
ps  
125MHz,IntegrationRange  
12kHz – 20MHz  
tJIT  
RMS Additive Phase Jitter  
156.25MHz, Integration  
Range 12kHz – 20MHz  
tpLH  
tpHL  
fo  
Propagation Delay, Low-to-High  
Propagation Delay, High-to-Low  
Frequency Range(6)  
1.25  
1.25  
1.75  
1.75  
1
ns  
ns  
A Crosspoint to Qx, nQx  
Crosspoint  
GHz  
Output Gate Enable Crossing  
tPGE  
3.5  
3.5  
100  
ns  
ns  
µS  
V
THI-to-Qx, nQx Crosspoint  
Output Gate Enable Crossing  
VTHI-to-Qx, nQx Crosspoint Driven to  
tPGD  
GL Designated Level  
nPD Crossing VTHI-to-Qx = VDD  
nQx = VDD  
,
tPWRDN  
Output Gate Disable Crossing VTHI to  
nQx Driven to GL Designated Level  
Output Rise.Fall Time(6)  
tPWRUP  
tR / tF  
100  
600  
µS  
ps  
125  
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is  
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium  
has been reached under these conditions.  
NOTE 1: AC propagation measurements should not be taken within the first 100 cycles of startup.  
NOTE 2: Skew measured between crosspoints of all differential output pairs under identical input and output interfaces, transitions and load  
conditions on any one device.  
NOTE 3: Skew measured is the difference between propagation delay times tpHL and tpLH of any differential output pair under identical input  
and output interfaces, transitions and load conditions on any one device.  
NOTE 4: Skew measured is the magnitude of the difference in propagation times between any single differential output pair of two devices,  
given identical transitions and load conditions at identical VDD levels and temperature.  
NOTE 5: All parameters are tested with a 50% input duty cycle.  
NOTE 6: Guaranteed by design but not production tested.  
IDT8R9306NLI REVISION D AUGUST 21, 2013  
8
©2013 Integrated Device Technology, Inc.  
IDT8R9306I Data Sheet  
2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II  
Differential AC Timing Waveforms  
Output Propagation and Skew Waveforms  
1/fo  
+ VDIF  
V
DIF = 0  
A[1:2] - nA[1:2]  
- VDIF  
t
PHL  
t
PLH  
+ VDIF  
V
DIF = 0  
- VDIF  
Qn - nQn  
t
SK(O)  
t
SK(O)  
+ VDIF  
V
DIF = 0  
- VDIF  
Qm - nQm  
NOTE 1: Pulse skew is calculated using the following expression:  
tsk(p) = |tpHL – tpLH  
|
Note that the tpHL and tpLH shown above are not valid measurements for this calculation because they are not taken from the same pulse.  
NOTE 2: AC propagation measurements should not be taken within the first 100 cycles of startup.  
Differential Gate Disabled/Enable Showing Runt Pulse Generation  
+ VDIF  
VDIF = 0  
- VDIF  
A[1:2] - nA[1:2]  
VIH  
VTHI  
VIL  
GL  
tPLH  
VIH  
VTHI  
VIL  
nG  
tPGD  
tPGE  
+ VDIF  
VDIF = 0  
- VDIF  
Qn - nQn  
NOTE 1: As shown, it is possible to generate runt pulses on gate disable and enable of the outputs. It is the user’s responsibility to time the nG  
signal to avoid this problem.  
IDT8R9306NLI REVISION D AUGUST 21, 2013  
9
©2013 Integrated Device Technology, Inc.  
IDT8R9306I Data Sheet  
2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II  
Power Down Timing  
+VDIF  
VDIF=0  
-VDIF  
A1 - nA1  
+VDIF  
VDIF=0  
-VDIF  
A2 - nA2  
nG  
VIH  
VTHI  
VIL  
VIH  
VTHI  
VIL  
nPD  
+VDIF  
VDIF=0  
-VDIF  
Qn - nQn  
NOTE 1: It is recommended that outputs be disabled before entering power-down mode. It is also recommended that the outputs remain  
disabled until the device completes power-up after asserting nPD.  
NOTE 2: The Power Down Timing diagram assumes that GL is HIGH.  
NOTE 3: It should be noted that during power-down mode, the outputs are both pulled to VDD. In the Power Down Timing diagram this is  
shown when Qx, nQx goes to VDIF = 0.  
IDT8R9306NLI REVISION D AUGUST 21, 2013  
10  
©2013 Integrated Device Technology, Inc.  
IDT8R9306I Data Sheet  
2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II  
Test Circuit for Differential Input  
~50  
VIN  
Transmission Line  
VDD/2  
A
A
D.U.T.  
Pulse  
Generator  
~50  
nVIN  
Transmission Line  
-VDD/2  
Scope  
50  
50  
Table 6A. Differential Input Test Conditions  
Symbol  
VDD = 2.5V 0.2V  
Unit  
VTHI  
Crossing of A and nA  
V
IDT8R9306NLI REVISION D AUGUST 21, 2013  
11  
©2013 Integrated Device Technology, Inc.  
IDT8R9306I Data Sheet  
2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II  
Test Circuit for DC Outputs and Power Down Tests  
VDD  
A
Qn  
Pulse  
RL  
RL  
Generator  
nA  
D.U.T.  
VOS  
VOD  
nQn  
Test Circuit for Propagation, Skew, and Gate Enable/Disable Timing  
~50  
VIN  
Transmission Line  
VDD/2  
A
D.U.T.  
Pulse  
Generator  
A
~50  
nVIN  
Transmission Line  
-VDD/2  
Scope  
50  
50  
Table 6B. LVDS Differential Output Test Conditions  
Symbol  
VDD = 2.5V 0.2V  
Unit  
pF  
pF  
0(1)  
8(1,2)  
50  
CL  
RL  
NOTE 1: Specifications only apply to “Normal Operations” test condition. The TIA/EIA specification load is for reference only.  
NOTE 2: The scope inputs are assumed to have a 2pF load to ground. TIA/EIA – 644 specifies 5pF between the output pair.  
With CL = 8pF, this gives the test circuit appropriate 5pF equivalent load.  
IDT8R9306NLI REVISION D AUGUST 21, 2013  
12  
©2013 Integrated Device Technology, Inc.  
IDT8R9306I Data Sheet  
2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II  
Applications Information  
Recommendations for Unused Output Pins  
Inputs:  
Outputs:  
LVCMOS Control Pins  
LVDS Outputs  
The input controls must not be treated as unused inputs. All control  
pins are floating and have no default state. Each must be configured  
All unused LVDS output pairs can be either left floating or terminated  
with 100across. If they are left floating, we recommend that there  
is no trace attached.  
by tying a 1kresistor to either ground or VDD  
.
Clock Input  
For applications not requiring the use of the second input clock  
Ax/nAx, it can be left floating. Though not required, but for additional  
protection, a 1kresistor can be tied from Ax to ground and a 1k  
resistor can be tied from nAx to VDD  
.
IDT8R9306NLI REVISION D AUGUST 21, 2013  
13  
©2013 Integrated Device Technology, Inc.  
IDT8R9306I Data Sheet  
2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II  
VFQFPN EPAD Thermal Release Path  
In order to maximize both the removal of heat from the package and  
the electrical performance, a land pattern must be incorporated on  
the Printed Circuit Board (PCB) within the footprint of the package  
corresponding to the exposed metal pad or exposed heat slug on the  
package, as shown in Figure 1. The solderable area on the PCB, as  
defined by the solder mask, should be at least the same size/shape  
as the exposed pad/slug area on the package to maximize the  
thermal/electrical performance. Sufficient clearance should be  
designed on the PCB between the outer edges of the land pattern  
and the inner edges of pad pattern for the leads to avoid any shorts.  
and dependent upon the package power dissipation as well as  
electrical conductivity requirements. Thus, thermal and electrical  
analysis and/or testing are recommended to determine the minimum  
number needed. Maximum thermal and electrical performance is  
achieved when an array of vias is incorporated in the land pattern. It  
is recommended to use as many vias connected to ground as  
possible. It is also recommended that the via diameter should be 12  
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is  
desirable to avoid any solder wicking inside the via during the  
soldering process which may result in voids in solder between the  
exposed pad/slug and the thermal land. Precautions should be taken  
to eliminate any solder voids between the exposed heat slug and the  
land pattern. Note: These recommendations are to be used as a  
guideline only. For further information, please refer to the Application  
Note on the Surface Mount Assembly of Amkor’s Thermally/  
Electrically Enhance Leadframe Base Package, Amkor Technology.  
While the land pattern on the PCB provides a means of heat transfer  
and electrical grounding from the package to the board through a  
solder joint, thermal vias are necessary to effectively conduct from  
the surface of the PCB to the ground plane(s). The land pattern must  
be connected to ground through these vias. The vias act as “heat  
pipes”. The number of vias (i.e. “heat pipes”) are application specific  
SOLDER  
SOLDER  
PIN  
PIN  
EXPOSED HEAT SLUG  
PIN PAD  
GROUND PLANE  
LAND PATTERN  
(GROUND PAD)  
PIN PAD  
THERMAL VIA  
Figure 1. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)  
IDT8R9306NLI REVISION D AUGUST 21, 2013  
14  
©2013 Integrated Device Technology, Inc.  
IDT8R9306I Data Sheet  
2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II  
Package Drawing and Dimensions  
28 Lead VFQFPN Package Outline and Package Dimensions  
IDT8R9306NLI REVISION D AUGUST 21, 2013  
15  
©2013 Integrated Device Technology, Inc.  
IDT8R9306I Data Sheet  
2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II  
Package Drawing and Dimensions, Continued  
28 Lead VFQFPN Package Outline and Package Dimensions  
IDT8R9306NLI REVISION D AUGUST 21, 2013  
16  
©2013 Integrated Device Technology, Inc.  
IDT8R9306I Data Sheet  
2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II  
Ordering Information  
XX  
X
XXXXX  
IDT  
Package Process  
Device Type  
I
-40 C to +85 C (Industrial)  
NL  
NLG  
Thermall Enhanced Plastic Very Fine Pitch  
Quad Flat, “Green” Package  
8R9306I 2.5V 1:6 LVDS Clock Buffer Terabuffer II  
Table 8. Ordering Information  
Part/Order Number  
Marking  
Package  
“Lead-Free” 28 Lead VFQFPN  
“Lead-Free” 28 Lead VFQFPN  
Shipping Packaging  
Tray  
Temperature  
-40C to 85C  
-40C to 85C  
8R9306NLGI  
8R9306NLGI8  
IDT8R9306NLGI  
IDT8R9306NLGI  
Tape & Reel  
IDT8R9306NLI REVISION D AUGUST 21, 2013  
17  
©2013 Integrated Device Technology, Inc.  
IDT8R9306I Data Sheet  
2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II  
Revision History Sheet  
Rev  
Table  
Page  
Description of Change  
Date  
B
T5F  
9
1
Changed fo, Frequency Range Maximum from 1MHz to 1GHz.  
4/11/2012  
Features, first bullet: changed 25ps to 40ps  
Features, eighth bullet: changed two LVDS outputs to six LVDS outputs  
Pin Assignment: changed dimensions from 5mm x 5mm to 6mm x 6mm  
Pin Assignment: added EPad dimensions  
C
4A  
5F  
5
8
13  
15, 16  
17  
ITOT, Test Conditions: changed FREF Clock from 450MHz to 1GHz  
6/26/2013  
tsk(o): changed 25ps Max to 40ps Max  
Added: Recommendations for Unused Output Pins  
Updated Package Drawing  
8
Deleted quantity from Tape & Reel  
1, 14, 15,  
16, 17  
D
D
Changed VFQFN to VFQFPN.  
7/25/2013  
8/16/2013  
T1  
3
First row: Corrected typo - A[1:2].  
Added ‘I’ to Ordering Information diagram.  
17  
IDT8R9306NLI REVISION D AUGUST 21, 2013  
18  
©2013 Integrated Device Technology, Inc.  
IDT8R9306I Data Sheet  
2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II  
We’ve Got Your Timing Solution  
6024 Silver Creek Valley Road Sales  
Technical Support Sales  
800-345-7015 (inside USA)  
netcom@idt.com  
San Jose, California 95138  
+408-284-8200 (outside USA) +480-763-2056  
Fax: 408-284-2775  
www.IDT.com/go/contactIDT  
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,  
including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not  
guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the  
suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any  
license under intellectual property rights of IDT or any third parties.  
IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to signifi-  
cantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.  
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third  
party owners.  
Copyright 2013. All rights reserved.  
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 		8R9306NLGI8 [ 2.5V LVDS, 1:6 Clock Buffer Terabuffer ] 19 页

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