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8S58021AKILF

型号：

8S58021AKILF

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

18 页

PDF大小：

734 K

下载PDF手册
Differential-to-LVPECL/ECL Fanout Buffer  
ICS8S58021I  
DATA SHEET  
General Description  
Features  
The ICS8S58021I is a high speed 1-to-4 Differential-  
to-LVPECL/ECL Fanout Buffer. The ICS8S58021I is  
optimized for high speed and very low output skew,  
making it suitable for use in demanding applications  
such as SONET, 1 Gigabit and 10 Gigabit Ethernet,  
• Four LVPECL/ECL outputs  
S
IC  
• IN, nIN input can accept the following differential input levels:  
HiPerClockS™  
LVPECL, LVDS, CML  
• 50Ω internal input termination to VT  
• Output frequency: 2.5GHz (maximum)  
• Output skew: 30ps (maximum)  
and Fibre Channel. The internally terminated differential input and  
VREF_AC pin allow other differential signal families such as LVDS,  
LVPECL and CML to be easily interfaced to the input with minimal  
use of external components. The ICS8S58021I is packaged in a  
small 3mm x 3mm 16-pin VFQFN package which makes it ideal for  
use in space-constrained applications.  
• Part-to-part skew: 150ps (maximum)  
• Additive phase jitter, RMS: 0.02ps (typical)  
• Propagation Delay: 425ps (maximum)  
• LVPECL mode operating voltage supply range:  
VCC = 2.375V to 3.465V, VEE = 0V  
• ECL mode operating voltage supply range:  
VCC = 0V, VEE = -3.465V to 2.375V  
• -40°C to 85°C ambient operating temperature  
• Available in lead-free (RoHS 6) package  
Block Diagram  
Pin Assignment  
Q0  
16 15 14 13  
nQ0  
1
2
3
4
Q1  
IN  
VT  
12  
11  
10  
9
IN  
VT  
nIN  
nQ1  
Q2  
Q1  
VREF- AC  
nIN  
nQ2  
nQ1  
5
6
7
8
VREF_AC  
Q2  
ICS8S58021I  
nQ2  
16-Lead VFQFN  
3mm x 3mm x 0.925mm package body  
Q3  
K Package  
Top View  
nQ3  
ICS8S58021AKI REVISION A FEBRUARY 22, 2010  
1
©2010 Integrated Device Technology, Inc.  
ICS8S58021I Data Sheet  
DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER  
Table 1. Pin Descriptions  
Number  
Name  
Type  
Description  
Non-inverting LVPECL differential clock input.  
RT = 50Ω termination to VT.  
1
IN  
Input  
Input for termination. Both IN, nIN inputs are terminated to this pin. See Application Information  
section, Differential Input with Built-In 50Ω Termination Interface.  
2
VT  
Input  
3
4
VREF_AC  
nIN  
Output  
Input  
Reference voltage for AC-coupled applications.  
Inverting differential LVPECL clock input. RT = 50Ω termination to VT.  
Negative supply pins.  
5, 16  
6, 7  
VEE  
Power  
Output  
nQ3, Q3  
Differential output pair. LVPECL/ECL interface levels.  
8, 13  
Vcc  
Power  
Power supply pins.  
9, 10  
11, 12  
14, 15  
nQ2, Q2  
nQ1, Q1  
nQ0, Q0  
Output  
Output  
Output  
Differential output pair. LVPECL/ECL interface levels.  
Differential output pair. LVPECL/ECL interface levels.  
Differential output pair. LVPECL/ECL interface levels.  
ICS8S58021AKI REVISION A FEBRUARY 22, 2010  
2
©2010 Integrated Device Technology, Inc.  
ICS8S58021I Data Sheet  
DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER  
Absolute Maximum Ratings  
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.  
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond  
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for  
extended periods may affect product reliability.  
Item  
Rating  
Supply Voltage, VCC  
Negative Supply Voltage, VEE  
Inputs, VI (LVPECL mode)  
Inputs, VI (ECL mode)  
4.6V (LVPECL mode, VEE = 0V)  
-4.6V (ECL mode, VCC = 0V)  
-0.5V to VCC + 0.5V  
0.5V to VEE – 0.5V  
Outputs, IO  
Continuos Current  
Surge Current  
50mA  
100mA  
Input Current, IN, nIN  
25mA  
VT Current, IVT  
50mA  
Input Sink/Source, IREF_AC  
2mA  
Operating Temperature Range, TA  
Package Thermal Impedance, θJA, (Junction-to-Ambient)  
Storage Temperature, TSTG  
-40°C to +85°C  
74.7°C/W (0 mps)  
-65°C to 150°C  
DC Electrical Characteristics  
Table 2A. Power Supply DC Characteristics, VCC = 2.5V 5%, 3.3V 5%, TA = -40°C to 85°C  
Symbol Parameter  
VCC Positive Supply Voltage  
IEE Power Supply Current  
Test Conditions  
Minimum  
Typical  
Maximum  
3.465  
80  
Units  
V
2.375  
3.3  
mA  
Table 2B. Differential DC Characteristics, VCC = 2.5V 5%, 3.3V 5%, TA = -40°C to 85°C  
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
Differential Input Resistance;  
NOTE 1  
RIN  
(IN, nIN)  
40  
50  
60  
Ω
VIH  
Input High Voltage  
(IN, nIN)  
(IN, nIN)  
1.2  
0
VCC  
VIH – 0.15  
1.4  
V
V
VIL  
Input Low Voltage  
VIN  
Input Voltage Swing  
Differential Input Voltage Swing  
Input Current; NOTE 1  
Bias Voltage  
0.15  
0.3  
V
VDIFF_IN  
IIN  
2.8  
V
(IN, nIN)  
35  
mA  
V
VREF_AC  
VCC – 1.52  
VCC – 1.37  
VCC – 1.17  
NOTE 1: Guaranteed by design.  
ICS8S58021AKI REVISION A FEBRUARY 22, 2010  
3
©2010 Integrated Device Technology, Inc.  
ICS8S58021I Data Sheet  
DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER  
Table 2C. LVPECL DC Characteristics, VCC = 2.5V 5%, 3.3V 5%, TA = -40°C to 85°C  
Symbol  
VOH  
Parameter  
Test Conditions  
Minimum  
VCC – 1.16  
VCC – 1.955  
0.6  
Typical  
Maximum  
VCC – 0.765  
VCC – 1.57  
1.1  
Units  
Output High Voltage; NOTE 1  
Output Low Voltage; NOTE 1  
Output Voltage Swing  
VCC – 0.94  
VCC – 1.78  
V
V
V
V
VOL  
VOUT  
VDIFF_OUT Differential Output Voltage Swing  
1.2  
2.2  
NOTE 1: Outputs terminated with 50Ω to VCC – 2V.  
AC Electrical Characteristics  
Table 3. AC Characteristics, VCC = 0V; VEE = -3.3V 5%, -2.5V 5% or VCC = 2.5V 5%, 3.3V 5%, VEE = 0V,  
TA = -40°C to 85°C  
Symbol Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
2.5  
Units  
GHz  
ps  
fOUT  
Output Frequency  
tPD  
Propagation Delay; NOTE 1  
Output Skew; NOTE 2, 4  
200  
425  
tsk(o)  
tsk(pp)  
30  
ps  
Part-to-Part Skew; NOTE 3, 4  
150  
ps  
Buffer Additive Jitter; RMS; refer to  
Additive Phase Jitter Section  
156.25MHz, Integration Range:  
12kHz – 20MHz  
tjit  
0.02  
ps  
ps  
tR / tF  
Output Rise/Fall Time  
20% to 80%  
25  
250  
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is  
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium  
has been reached under these conditions.  
NOTE: All parameters characterized at ≤ 1GHz unless otherwise noted.  
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.  
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.  
Measured at the output differential cross points.  
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature and with equal load  
conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.  
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.  
ICS8S58021AKI REVISION A FEBRUARY 22, 2010  
4
©2010 Integrated Device Technology, Inc.  
ICS8S58021I Data Sheet  
DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER  
Additive Phase Jitter  
The spectral purity in a band at a specific offset from the fundamental  
compared to the power of the fundamental is called the dBc Phase  
Noise. This value is normally expressed using a Phase noise plot  
and is most often the specified plot in many applications. Phase noise  
is defined as the ratio of the noise power present in a 1Hz band at a  
specified offset from the fundamental frequency to the power value of  
the fundamental. This ratio is expressed in decibels (dBm) or a ratio  
of the power in the 1Hz band to the power in the fundamental. When  
the required offset is specified, the phase noise is called a dBc value,  
which simply means dBm at a specified offset from the fundamental.  
By investigating jitter in the frequency domain, we get a better  
understanding of its effects on the desired application over the entire  
time record of the signal. It is mathematically possible to calculate an  
expected bit error rate given a phase noise plot.  
156.25MHz  
RMS Phase Jitter (Random)  
12kHz to 20MHz = 0.02ps (typical)  
Offset from Carrier Frequency (Hz)  
As with most timing specifications, phase noise measurements has  
issues relating to the limitations of the equipment. Often the noise  
floor of the equipment is higher than the noise floor of the device. This  
is illustrated above. The device meets the noise floor of what is  
shown, but can actually be lower. The phase noise is dependent on  
the input source and measurement equipment.  
The source generator "Rohde & Schwarz SMA 100A Signal  
Generator, via the clock synthesis as external input to drive the input  
clock IN, nIN".  
ICS8S58021AKI REVISION A FEBRUARY 22, 2010  
5
©2010 Integrated Device Technology, Inc.  
ICS8S58021I Data Sheet  
DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER  
Parameter Measurement Information  
2V  
nQ0:nQ3  
Q0:Q3  
SCOPE  
80%  
tF  
80%  
tR  
V
Qx  
CC  
VOUT  
20%  
20%  
LVPECL  
nQx  
VEE  
-0.375V to -1.465V  
Output Load AC Test Circuit  
Output Rise/Fall Time  
Part 1  
nQx  
nQx  
Qx  
Qx  
nQy  
Part 2  
nQy  
Qy  
Qy  
tsk(o)  
tsk(pp)  
Part-to-Part Skew  
Output Skew  
nIN  
IN  
VDIFF_IN, VDIFF_OUT  
VIN, VOUT  
nQ0:nQ3  
Q0:Q3  
tPD  
Single-ended & Differential Input/Output Voltage Swing  
Propagation Delay  
ICS8S58021AKI REVISION A FEBRUARY 22, 2010  
6
©2010 Integrated Device Technology, Inc.  
ICS8S58021I Data Sheet  
DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER  
Application Information  
Recommendations for Unused Output Pins  
Outputs:  
LVPECL Outputs  
All unused LVPECL outputs can be left floating. We recommend that  
there is no trace attached. Both sides of the differential output pair  
should either be left floating or terminated.  
Wiring the Differential Input to Accept Single-Ended Levels  
Figure 1 shows how a differential input can be wired to accept single  
ended levels. The reference voltage VREF = VCC/2 is generated by  
the bias resistors R1 and R2. The bypass capacitor (C1) is used to  
help filter noise on the DC bias. This bias circuit should be located as  
close to the input pin as possible. The ratio of R1 and R2 might need  
to be adjusted to position the VREF in the center of the input voltage  
swing. For example, if the input clock swing is 2.5V and VCC = 3.3V,  
R1 and R2 value should be adjusted to set VREF at 1.25V. The values  
below are for when both the single ended swing and VCC are at the  
same voltage. This configuration requires that the sum of the output  
impedance of the driver (Ro) and the series resistance (Rs) equals  
the transmission line impedance. In addition, matched termination at  
the input will attenuate the signal in half. This can be done in one of  
two ways. First, R3 and R4 in parallel should equal the transmission  
line impedance. For most 50Ω applications, R3 and R4 can be 100Ω.  
The values of the resistors can be increased to reduce the loading for  
slower and weaker LVCMOS driver. When using single-ended  
signaling, the noise rejection benefits of differential signaling are  
reduced. Even though the differential input can handle full rail  
LVCMOS signaling, it is recommended that the amplitude be  
reduced. The datasheet specifies a lower differential amplitude,  
however this only applies to differential signals. For single-ended  
applications, the swing can be larger, however VIL cannot be less  
than -0.3V and VIH cannot be more than VCC + 0.3V. Though some  
of the recommended components might not be used, the pads  
should be placed in the layout. They can be utilized for debugging  
purposes. The datasheet specifications are characterized and  
guaranteed by using a differential signal.  
Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels  
ICS8S58021AKI REVISION A FEBRUARY 22, 2010  
7
©2010 Integrated Device Technology, Inc.  
ICS8S58021I Data Sheet  
DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER  
3.3V Differential Input with Built-In 50Ω Termination Interface  
The IN /nIN with built-in 50Ω terminations accept LVDS, LVPECL,  
CML and other differential signals. The differential signal must meet  
the VIN and VIH input requirements. Figures 2A to 2D show interface  
examples for the IN/nIN input with built-in 50Ω terminations driven by  
the most common driver types. The input interfaces suggested here  
are examples only. If the driver is from another vendor, use their  
termination recommendation. Please consult with the vendor of the  
driver component to confirm the driver termination requirements.  
3.3V  
3.3V  
3.3V  
3.3V  
Zo = 50Ω  
Zo = 50Ω  
Zo = 50Ω  
Zo = 50Ω  
IN  
IN  
VT  
nIN  
VT  
nIN  
Receiver  
With  
Receiver  
With  
LVPECL  
LVDS  
R1  
50  
Built-In  
50Ω  
Built-In  
50Ω  
Figure 2A. IN/nIN Input with Built-In 50Ω  
Figure 2B. IN/nIN Input with Built-In 50Ω  
Driven by an LVDS Driver  
Driven by an LVPECL Driver  
3.3V  
3.3V  
3.3V  
3.3V  
Zo = 50Ω  
Zo = 50Ω  
Zo = 50Ω  
IN  
IN  
VT  
nIN  
VT  
nIN  
Zo = 50Ω  
Receiver  
With  
Receiver  
With  
CML – Built-in 50Ω Pull-up  
CML – Open Collector  
Built-In  
50Ω  
Built-In  
50Ω  
Figure 2C. IN/nIN Input with Built-In 50Ω  
Figure 2D. IN/nIN Input with Built-In 50Ω  
Driven by a CML Driver with Open Collector  
Driven by a CML Driver with Built-In 50Ω  
Pullup  
ICS8S58021AKI REVISION A FEBRUARY 22, 2010  
8
©2010 Integrated Device Technology, Inc.  
ICS8S58021I Data Sheet  
DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER  
2.5V Differential Input with Built-In 50Ω Termination Interface  
The IN /nIN with built-in 50Ω terminations accept LVDS, LVPECL,  
CML and other differential signals. The differential signal must meet  
the VIN and VIH input requirements. Figures 3A to 3D show interface  
examples for the HiPerClockS IN/nIN with built-in 50Ω termination  
input driven by the most common driver types. The input interfaces  
suggested here are examples only. If the driver is from another  
vendor, use their termination recommendation. Please consult with  
the vendor of the driver component to confirm the driver termination  
requirements.  
2.5V  
2.5V  
2.5V  
3.3V or 2.5V  
Zo = 50Ω  
Zo = 50Ω  
Zo = 50Ω  
Zo = 50Ω  
IN  
IN  
VT  
nIN  
VT  
nIN  
Receiver  
With  
Receiver  
With  
LVPECL  
LVDS  
R1  
18  
Built-In  
50Ω  
Built-In  
50Ω  
Figure 3A. IN/nIN Input with Built-In 50Ω  
Figure 3B. IN/nIN Input with Built-In 50Ω  
Driven by an LVDS Driver  
Driven by an LVPECL Driver  
2.5V  
2.5V  
2.5V  
2.5V  
Zo = 50Ω  
Zo = 50Ω  
IN  
IN  
VT  
nIN  
VT  
nIN  
Zo = 50Ω  
Zo = 50Ω  
Receiver  
With  
Receiver  
With  
CML - Built-in 50Ω Pull-up  
CML  
Built-In  
50Ω  
Built-In  
50Ω  
Figure 3C. IN/nIN Input with Built-In 50Ω  
Figure 3D. IN/nIN Input with Built-In 50Ω  
Driven by a CML Driver with Open Collector  
Driven by a CML Driver with Built-In 50Ω  
Pullup  
ICS8S58021AKI REVISION A FEBRUARY 22, 2010  
9
©2010 Integrated Device Technology, Inc.  
ICS8S58021I Data Sheet  
DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER  
Termination for 3.3V LVPECL Outputs  
The clock layout topology shown below is a typical termination for  
LVPECL outputs. The two different layouts mentioned are  
recommended only as guidelines.  
transmission lines. Matched impedance techniques should be used  
to maximize operating frequency and minimize signal distortion.  
Figures 4A and 4B show two different layouts which are  
recommended only as guidelines. Other suitable clock layouts may  
exist and it would be recommended that the board designers simulate  
to guarantee compatibility across all printed circuit and clock  
component process variations.  
The differential outputs are low impedance follower outputs that  
generate ECL/LVPECL compatible outputs. Therefore, terminating  
resistors (DC current path to ground) or current sources must be  
used for functionality. These outputs are designed to drive 50Ω  
3.3V  
R3  
125Ω  
R4  
125Ω  
3.3V  
3.3V  
3.3V  
Z
o = 50Ω  
3.3V  
+
_
Z
o = 50Ω  
+
_
Input  
LVPECL  
Zo = 50Ω  
LVPECL  
Input  
Zo = 50Ω  
R1  
R2  
50Ω  
50Ω  
R1  
84Ω  
R2  
84Ω  
VCC - 2V  
1
RTT =  
* Zo  
RTT  
((VOH + VOL) / (VCC – 2)) – 2  
Figure 4A. 3.3V LVPECL Output Termination  
Figure 4B. 3.3V LVPECL Output Termination  
ICS8S58021AKI REVISION A FEBRUARY 22, 2010  
10  
©2010 Integrated Device Technology, Inc.  
ICS8S58021I Data Sheet  
DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER  
Termination for 2.5V LVPECL Outputs  
Figure 5A and Figure 5B show examples of termination for 2.5V  
LVPECL driver. These terminations are equivalent to terminating 50Ω  
to VCC – 2V. For VCC = 2.5V, the VCC – 2V is very close to ground  
level. The R3 in Figure 5B can be eliminated and the termination is  
shown in Figure 5C.  
2.5V  
VCC = 2.5V  
2.5V  
2.5V  
VCC = 2.5V  
R1  
R3  
50Ω  
250  
250  
+
50Ω  
50Ω  
+
–
50Ω  
–
2.5V LVPECL Driver  
R1  
50  
R2  
50  
2.5V LVPECL Driver  
R2  
62.5  
R4  
62.5  
R3  
18  
Figure 5A. 2.5V LVPECL Driver Termination Example  
Figure 5B. 2.5V LVPECL Driver Termination Example  
2.5V  
VCC = 2.5V  
50Ω  
+
50Ω  
–
2.5V LVPECL Driver  
R1  
50  
R2  
50  
Figure 5C. 2.5V LVPECL Driver Termination Example  
ICS8S58021AKI REVISION A FEBRUARY 22, 2010  
11  
©2010 Integrated Device Technology, Inc.  
ICS8S58021I Data Sheet  
DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER  
VFQFN EPAD Thermal Release Path  
In order to maximize both the removal of heat from the package and  
the electrical performance, a land pattern must be incorporated on  
the Printed Circuit Board (PCB) within the footprint of the package  
corresponding to the exposed metal pad or exposed heat slug on the  
package, as shown in Figure 6. The solderable area on the PCB, as  
defined by the solder mask, should be at least the same size/shape  
as the exposed pad/slug area on the package to maximize the  
thermal/electrical performance. Sufficient clearance should be  
designed on the PCB between the outer edges of the land pattern  
and the inner edges of pad pattern for the leads to avoid any shorts.  
and dependent upon the package power dissipation as well as  
electrical conductivity requirements. Thus, thermal and electrical  
analysis and/or testing are recommended to determine the minimum  
number needed. Maximum thermal and electrical performance is  
achieved when an array of vias is incorporated in the land pattern. It  
is recommended to use as many vias connected to ground as  
possible. It is also recommended that the via diameter should be 12  
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is  
desirable to avoid any solder wicking inside the via during the  
soldering process which may result in voids in solder between the  
exposed pad/slug and the thermal land. Precautions should be taken  
to eliminate any solder voids between the exposed heat slug and the  
land pattern. Note: These recommendations are to be used as a  
guideline only. For further information, please refer to the Application  
Note on the Surface Mount Assembly of Amkor’s Thermally/  
Electrically Enhance Leadframe Base Package, Amkor Technology.  
While the land pattern on the PCB provides a means of heat transfer  
and electrical grounding from the package to the board through a  
solder joint, thermal vias are necessary to effectively conduct from  
the surface of the PCB to the ground plane(s). The land pattern must  
be connected to ground through these vias. The vias act as “heat  
pipes”. The number of vias (i.e. “heat pipes”) are application specific  
SOLDER  
SOLDER  
PIN  
PIN  
EXPOSED HEAT SLUG  
PIN PAD  
GROUND PLANE  
LAND PATTERN  
(GROUND PAD)  
PIN PAD  
THERMAL VIA  
Figure 6. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)  
ICS8S58021AKI REVISION A FEBRUARY 22, 2010  
12  
©2010 Integrated Device Technology, Inc.  
ICS8S58021I Data Sheet  
DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER  
Power Considerations  
This section provides information on power dissipation and junction temperature for the ICS8S58021I.  
Equations and example calculations are also provided.  
1. Power Dissipation.  
The total power dissipation for the ICS8S58021I is the sum of the core power plus the power dissipation in the load(s).  
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.  
NOTE: Please refer to Section 3 for details on calculating power dissipation in the load.  
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 80mA = 277.2mW  
Power (outputs)MAX = 32.4mW/Loaded Output pair  
If all outputs are loaded, the total power is 4 * 32.4mW = 129.6mW  
Total Power_MAX (3.3V, with all outputs switching) = 277.2mW + 129.6mW = 406.8mW  
2. Junction Temperature.  
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The  
maximum recommended junction temperature f is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the  
bond wire and bond pad temperature remains below 125°C.  
The equation for Tj is as follows: Tj = θJA * Pd_total + TA  
Tj = Junction Temperature  
θJA = Junction-to-Ambient Thermal Resistance  
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)  
TA = Ambient Temperature  
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and  
a multi-layer board, the appropriate value is 74.7°C/W per Table 4 below.  
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:  
85°C + 0.407W * 74.7°C/W = 115.4°C. This is below the limit of 125°C.  
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of  
board (multi-layer).  
Table 4. Thermal Resistance θJA for 16 Lead VFQFN, Forced Convection  
θJA by Velocity  
Meters per Second  
0
1
2.5  
Multi-Layer PCB, JEDEC Standard Test Boards  
74.7°C/W  
65.3°C/W  
58.5°C/W  
ICS8S58021AKI REVISION A FEBRUARY 22, 2010  
13  
©2010 Integrated Device Technology, Inc.  
ICS8S58021I Data Sheet  
DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER  
3. Calculations and Equations.  
The purpose of this section is to calculate the power dissipation for the LVPECL output pair.  
The LVPECL output driver circuit and termination are shown in Figure 7.  
VCC  
Q1  
VOUT  
RL  
50Ω  
VCC - 2V  
Figure 7. LVPECL Driver Circuit and Termination  
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of  
VCC – 2V.  
•
•
For logic high, VOUT = VOH_MAX = VCC_MAX – 0.765V  
(VCC_MAX – VOH_MAX) = 0.765V  
For logic low, VOUT = VOL_MAX = VCC_MAX – 1.57V  
(VCC_MAX – VOL_MAX) = 1.57V  
Pd_H is power dissipation when the output drives high.  
Pd_L is the power dissipation when the output drives low.  
Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) =  
[(2V – 0.765V)/50Ω] * 0.765V = 18.9mW  
Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX) =  
[(2V – 1.57V)/50Ω] * 1.57V = 13.5mW  
Total Power Dissipation per output pair = Pd_H + Pd_L = 32.4mW  
ICS8S58021AKI REVISION A FEBRUARY 22, 2010  
14  
©2010 Integrated Device Technology, Inc.  
ICS8S58021I Data Sheet  
DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER  
Reliability Information  
Table 5. θJA vs. Air Flow Table for a 16 Lead VFQFN  
θJA by Velocity  
Meters per Second  
0
1
2.5  
Multi-Layer PCB, JEDEC Standard Test Boards  
74.7°C/W  
65.3°C/W  
58.5°C/W  
Transistor Count  
The transistor count for ICS8S58021I is: 262  
ICS8S58021AKI REVISION A FEBRUARY 22, 2010  
15  
©2010 Integrated Device Technology, Inc.  
ICS8S58021I Data Sheet  
DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER  
Package Outline and Package Dimensions  
Package Outline - K Suffix for 16 Lead VFQFN  
Seating Plane  
(Ref.)  
ND& NE  
Even  
(ND-1)x e  
(R ef.)  
A1  
Index Area  
L
A3  
E2  
e
N
N
(Typ.)  
2
If ND & NE  
are Even  
1
Anvil  
Singulation  
or  
Sawn  
Singulation  
2
(NE -1)x e  
(Re f.)  
E2  
2
Top View  
D
b
e
Thermal  
Base  
A
(Ref.)  
ND &NE  
Odd  
D2  
2
0. 08  
C
Chamfer 4x  
0.6 x 0.6 max  
OPTIONAL  
D2  
C
Bottom View w/Type A ID  
Bottom View w/Type B ID  
Bottom View w/Type C ID  
4
2
1
2
1
2
1
CHAMFER  
RADIUS  
N N-1  
4
N N-1  
DD  
N N-1  
4
4
There are 3 methods of indicating pin 1 corner  
at the back of the VFQFN package are:  
1. Type A: Chamfer on the paddle (near pin 1)  
2. Type B: Dummy pad between pin 1 and N.  
4
AA  
4
3. Type C: Mouse bite on the paddle (near pin 1)  
Table 6. Package Dimensions  
JEDEC Variation: VEED-2/-4  
All Dimensions in Millimeters  
Symbol  
Minimum  
Maximum  
N
16  
A
0.80  
0
1.00  
0.05  
A1  
A3  
0.25 Ref.  
b
ND & NE  
D & E  
D2 & E2  
e
0.18  
0.30  
4
3.00 Basic  
1.00  
0.30  
1.80  
0.50 Basic  
L
0.50  
Reference Document: JEDEC Publication 95, MO-220  
ICS8S58021AKI REVISION A FEBRUARY 22, 2010  
16  
©2010 Integrated Device Technology, Inc.  
ICS8S58021I Data Sheet  
DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER  
Ordering Information  
Table 7. Ordering Information  
Part/Order Number  
8S58021AKILF  
8S58021AKILFT  
Marking  
1AIL  
1AIL  
Package  
“Lead-Free” 16 Lead VFQFN  
“Lead-Free” 16 Lead VFQFN  
Shipping Packaging  
Tube  
2500 Tape & Reel  
Temperature  
-40°C to 85°C  
-40°C to 85°C  
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.  
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the  
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal  
commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without  
additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support  
devices or critical medical instruments.  
ICS8S58021AKI REVISION A FEBRUARY 22, 2010  
17  
©2010 Integrated Device Technology, Inc.  
ICS8S58021I Data Sheet  
DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER  
6024 Silver Creek Valley Road Sales  
Technical Support  
800-345-7015 (inside USA)  
netcom@idt.com  
+408-284-8200 (outside USA) +480-763-2056  
Fax: 408-284-2775  
San Jose, California 95138  
www.IDT.com/go/contactIDT  
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,  
including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not  
guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the  
suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any  
license under intellectual property rights of IDT or any third parties.  
IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT  
product in such a manner does so at their own risk, absent an express, written agreement by IDT.  
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third  
party owners.  
Copyright 2010. All rights reserved.  
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