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Crystal or Differential-to-Differential

Clock Fanout Buffer

8T39S08A

Datasheet

General Description

Features

The 8T39S08A is a high-performance clock fanout buffer. The input

clock can be selected from two differential inputs or one crystal input.

The internal oscillator circuit is automatically disabled if the crystal

input is not selected. The crystal pin can be driven by a single-ended

clock. The selected signal is distributed to eight differential outputs

which can be configured as LVPECL, LVDS and HCSL outputs. In

addition, an LVCMOS output is provided. All outputs can be disabled

into a high-impedance state. The device is designed for a signal

fanout of high-frequency, low phase-noise clock and data signal. The

outputs are at a defined level when inputs are open or tied to ground.

It is designed to operate from a 3.3V or 2.5V core power supply, and

either a 3.3V or 2.5V output operating supply.

• Two differential reference clock input pairs

• Differential input pairs can accept the following input levels:

LVPECL, LVDS, HCSL, HSTL and Single-ended

• Crystal Oscillator Interface

• Crystal input frequency range: 10MHz to 40MHz

• Maximum Output Frequency

LVPECL - 2GHz

LVDS

HCSL

- 2GHz

- 250MHz

LVCMOS - 250MHz

• Two banks, each has four differential output pairs that can be

configured as LVPECL or LVDS or HCSL

• One single-ended reference output with synchronous enable to

avoid clock glitch

• Output skew: 80ps (maximum)

(Bank A and Bank B at the same output level)

• Part-to-part skew: 200ps (typical)

• Additive RMS phase jitter@ 156.25MHz, (12kHz - 20MHz):

34.7fs (typical), 3.3V/ 3.3V

• Supply voltage modes:

V_DD/V_DDO

3.3V/3.3V

3.3V/2.5V

2.5V/2.5V

• -40°C to 85°C ambient operating temperature

• Lead-free (RoHS 6) packaging

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May 19, 2016

8T39S08A Datasheet

Block Diagram

PullDown

Pin Assignment

30 29 28 27 26 25 24 23 22 21

31

32

33

34

35

36

37

38

39

40

20

19

18

17

16

15

14

13

12

11

GND

SMODEB1

nCLK1

GND

SMODEB0

REF_SEL1

nCLK0

CLK1

CLK0

V^DD

8T39S08A

REF_SEL0

XTAL_OUT

XTAL_IN

VDD

REFOUT

VDDOREF

OE_SE

SMODEA1

GND

SMODEA0

1

2

3

4

5

6

7

8

9

10

40-pin, 6mm x 6mm VFQFN

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May 19, 2016

8T39S08A Datasheet

Pin Description and Pin Characteristic Tables

Table 1. Pin Descriptions

Number

Name

QA0

Type

Description

1

2

Output

Power

Output

Power

Output

Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels.

Output supply pin for Bank QA outputs.

nQA0

V_DDOA

QA1

3

4

Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels.

Output supply pin for Bank QA outputs.

5

nQA1

V_DDOA

QA2

6

7

Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels.

8

nQA2

QA3

9

10

nQA3

Output driver select for Bank A outputs. See Table 3F for function.

LVCMOS/LVTTL interface levels.

11

SMODEA0

Input

Pulldown

12

13

14

V_DD

Power

Input

Power supply pin.

XTAL_IN

XTAL_OUT

Crystal oscillator interface.

Output

Input clock selection. LVCMOS/LVTTL interface levels.

See Table 3A for function.

15

16

17

18

19

REF_SEL0

CLK0

Input

Pulldown

Pullup/

Pulldown

Non-inverting differential clock. Internally biased to 0.33V_DD.

Inverting differential clock. Internally biased to 0.4V_DD.

Pullup/

Pulldown

nCLK0

Input clock selection. LVCMOS/LVTTL interface levels.

See Table 3A for function.

REF_SEL1

SMODEB0

Pulldown

Output driver select for Bank B outputs. See Table 3G for function.

LVCMOS/LVTTL interface levels.

20

21

22

23

24

25

26

27

28

29

30

31

GND

nQB3

QB3

Power

Output

Power

Output

Power

Output

Power

Power supply ground.

Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels.

Output supply pin for Bank QB outputs.

nQB2

QB2

V_DDOB

nQB1

QB1

Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels.

Output supply pin for Bank QB outputs.

V_DDOB

nQB0

QB0

Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels.

Power supply ground.

GND

Output driver select for Bank B outputs. See Table 3G for function.

LVCMOS/LVTTL interface levels.

32

33

SMODEB1

nCLK1

Input

Pulldown

Pullup/

Pulldown

Inverting differential clock. Internally biased to 0.4V_DD.

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May 19, 2016

8T39S08A Datasheet

Number

Name

Type

Pullup/

Pulldown

Description

34

CLK1

Input

Non-inverting differential clock. Internally biased to 0.33V_DD.

Power supply pin.

35

36

37

38

V_DD

Power

Output

Power

Input

REFOUT

V_DDOREF

OE_SE

Single-ended reference clock output. LVCMOS/LVTTL interface levels.

Output supply pin for REFOUT output.

Pulldown Output enable. LVCMOS/LVTTL interface levels. See Table 3B.

Output driver select for Bank A outputs. See Table 3F for function.

LVCMOS/LVTTL interface levels.

39

SMODEA1

Input

Pulldown

40

0

GND

Power

Power supply ground.

ePAD

Connect ePAD to ground to ensure proper heat dissipation.

NOTE: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

OE_SE,

SMODEx[1:0],

REF_SEL[1:0]

Input

Capacitance

C_IN

2

pF

R_PULLDOWNInput Pulldown Resistor

50

100

75

k

pF

CLK0, CLK1

Input Pullup

Resistor

R_PULLUP

nCLK0, nCLK1

REFOUT

Power

V_DDOREF= 3.465V

5.3

C_PD

Dissipation

Capacitance

REFOUT

V

_DDOREF= 2.625V

6.3

pF

REFOUT

V_DDOREF= 3.3V

52

63



Output

Impedance

R_OUT

V

_DDOREF= 2.5V

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May 19, 2016

8T39S08A Datasheet

Function Tables

1

Table 3A. REF_SELx Function Table

Table 3B. OE_SE Function Table

OE_SE REFOUT

Control Input

Selected Input Reference Clock

REF_SEL[1:0]

0 (default)

1

High-Impedance

Enabled

00 (default)

CLK0, nCLK0

CLK1, nCLK1

XTAL

01

10

11

NOTE: 1. Synchronous output enable to avoid clock glitch.

XTAL

Table 3C. Input/Output Operation Table, OE_SE

Input Status

Output State

REFOUT

OE_SE

0 (default)

1

REF_SEL [1:0]

Don’t care

CLKx and nCLKx

Don’t Care

High Impedance

Fanout crystal oscillator

10 or 11

Don’t Care

CLK0 and nCLK0 are both open circuit

CLK0 and nCLK0 are tied to ground

CLK0 is high, nCLK0 is low

Logic Low

Logic High

Logic Low

Logic High

Logic Low

1

00 (default)

CLK0 is low, nCLK0 is high

CLK1 and nCLK1 are both open circuit

CLK1 and nCLK1 are tied to ground

CLK1 is high, nCLK1 is low

01

CLK1 is low, nCLK1 is high

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May 19, 2016

8T39S08A Datasheet

Table 3D. Input/Output Operation Table, SMODEA

Input Status

Output State

SMODEA[1:0]

11

REF_SEL[1:0]

Don’t care

10 or 11

CLKx and nCLKx

Don’t Care

QA[3:0], nQA[3:0]

High Impedance

00, 01 or 10

Don’t Care

Fanout crystal oscillator

QA[3:0] = Low

nQA3:0] = High

CLK0 and nCLK0 are both open circuit

CLK0 and nCLK0 are tied to ground

CLK0 is high, nCLK0 is low

QA[3:0] = Low

nQA[3:0] = High

00, 01 or 10

00 (default)

QA[3:0] = High

nQA[3:0] = Low

QA[3:0] = Low

nQA[3:0] = High

CLK0 is low, nCLK0 is high

QA[3:0] = Low

nQA[3:0] = High

CLK1 and nCLK1 are both open circuit

CLK1 and CLK1 are tied to ground.

CLK1 is high, nCLK1 is low

QA[3:0] = Low

nQA[3:0] = High

00, 01 or 10

01

QA[3:0] = High

nQA[3:0] = Low

QA[3:0] = Low

nQA[3:0] = High

CLK1 is low, nCLK1 is high

Table 3E. Input/Output Operation Table, SMODEB

Input Status

Output State

QB[3:0], nQB[3:0]

High Impedance

SMODEB[1:0]

11

REF_SEL[1:0]

Don’t care

10 or 11

CLKx and nCLKx

Don’t Care

00, 01 or 10

Don’t Care

Fanout crystal oscillator

QB[3:0] = Low

nQB[3:0] = High

CLK0 and nCLK0 are both open circuit

CLK0 and nCLK0 are tied to ground

CLK0 is high, nCLK0 is low

QB[3:0] = Low

nQB[3:0] = High

00, 01 or 10

00 (default)

QB[3:0] = High

nQB[3:0] = Low

QB[3:0] = Low

nQB[3:0] = High

CLK0 is low, nCLK0 is high

QB[3:0] = Low

nQB[3:0] = High

CLK1 and nCLK1 are both open circuit

CLK1 and nCLK1 are tied to ground

CLK1 is high, nCLK1 is low

QB[3:0] = Low

nQB[3:0] = High

00, 01 or 10

01

QB[3:0] = High

nQB[3:0] = Low

QB[3:0] = Low

nQB[3:0] = High

CLK1 is low, nCLK1 is high

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May 19, 2016

8T39S08A Datasheet

Table 3F. Output Level Selection Table, QA[3:0], nQA[3:0]

SMODEA1

SMODEA0

Output Type

LVPECL (default)

LVDS

0

1

0

1

0

1

HCSL

High-Impedance

Table 3G. Output Level Selection Table, QB[3:0], nQB[3:0]

SMODEB1

SMODEB0

Output Type

LVPECL (default)

LVDS

0

1

0

1

0

1

HCSL

High-Impedance

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May 19, 2016

8T39S08A Datasheet

Absolute Maximum Ratings

NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress

specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the DC Characteristics or

AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.

Item

Rating

Supply Voltage, V_DD

4.6V

Inputs, V_I

XTAL_IN

0V to 2V

Other Inputs

-0.5V to V_DD+ 0.5V

Outputs, V_O, (HCSL, LVCMOS)

-0.5V to V_DDOX¹+ 0.5V

Outputs, I_O, (LVPECL)

Continuous Current

Surge Current

50mA

100mA

Outputs, I_O, (LVDS)

Continuous Current

Surge Current

10mA

15mA

Junction Temperature

125°C

Storage Temperature, T_STG

-65°C to 150°C

NOTE: 1. V

denotes V

V

and V

DDOx

DDOA, DDOB DDOREF.

DC Electrical Characteristics

Table 4A. Power Supply DC Characteristics, V = V

= V

= 3.3V 5%, GND = 0V, T = -40°C to 85°C

DDOREF A

DD

DDOA

DDOB

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

V_DD

Power Supply Voltage

3.135

3.3

3.465

V

V_DDOA,

V_DDOB,V_DDOREF

Output Supply Voltage

3.135

3.3

3.465

V

I_DD

Power Supply Current

Output Supply Current¹

Power Supply Current

Output Supply Current²

SMODEA/B[1:0] = 01

95

165

150

85

115

195

175

105

75

mA

I

_DDOA+ I_DDOB

I_EE

SMODEA/B[1:0] = 00 (default)

SMODEA/B[1:0] = 10

I_DD

I_DDOA+ I_DDOB

SMODEA/B[1:0] = 10

60

NOTE: 1. Differential outputs are terminated with 100.

NOTE: 2. Differential outputs are running at 250MHz and floating.

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May 19, 2016

8T39S08A Datasheet

Table 4B. Power Supply DC Characteristics,

V

= 3.3V 5%, V

= V

= 2.5V 5%, GND = 0V, T = -40°C to 85°C

DD

DDOA

DDOB

DDOREF A

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

V_DD

Power Supply Voltage

3.135

3.3

3.465

V

V_DDOA,

V_DDOB,V_DDOREF

Output Supply Voltage

Power Supply Current

Output Supply Current¹

2.375

2.5

95

2.625

115

V

I_DD

SMODEA/B[1:0] = 01

mA

I_DDOA

+

165

195

I_DDOB+ I_DDOREF

I_EE

I_DD

I_DDOA

I_DDOB+ I_DDOREF

Power Supply Current

SMODEA/B[1:0] = 00 (default)

SMODEA/B[1:0] = 10

150

85

175

105

mA

+

Output Supply Current²

SMODEA/B[1:0] = 10

50

60

mA

NOTE: 1. Differential outputs are terminated with 100.

NOTE: 2. Differential outputs are running at 250MHz and floating.

Table 4C. Power Supply DC Characteristics, V = V

= V

= 2.5V 5%, GND = 0V, T = -40°C to 85°C

DDOREF A

DD

DDOA

DDOB

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

V_DD

Power Supply Voltage

2.375

2.5

2.625

V

V_DDOA,

V_DDOB,V_DDOREF

Output Supply Voltage

Power Supply Current

Output Supply Current¹

2.375

2.5

85

2.625

100

V

I_DD

SMODEA/B[1:0] = 01

mA

I_DDOA

+

160

190

I_DDOB+ I_DDOREF

I_EE

I_DD

I_DDOA

I_DDOB+ I_DDOREF

Power Supply Current

SMODEA/B[1:0] = 00 (default)

SMODEA/B[1:0] = 10

135

70

160

85

mA

+

Output Supply Current²

SMODEA/B[1:0] = 10

50

60

mA

NOTE: 1. Differential outputs are terminated with 100.

NOTE: 2. Differential outputs are running at 250MHz and floating.

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May 19, 2016

8T39S08A Datasheet

Table 4D. LVCMOS/LVTTL DC Characteristics,

= 3.3V 5%, 2.5V 5%, V = = 3.3V 5% or 2.5V 5%, GND = 0V, T = -40°C to 85°C

V

DD

DDOREF

A

Symbol Parameter

Test Conditions

_DD= 3.3V 5%

Minimum

Typical

Maximum

Units

OE_SE,

V

2

V_DD+ 0.3

V

Input

V_IH

SMODEA[1:0],

SMODEB[1:0],

REF_SEL[1:0]

High Voltage

V_DD= 2.5V 5%

V_DD= 3.3V 5%

1.7

-0.3

V_DD+ 0.3

0.8

V

OE_SE,

Input

V_IL

SMODEA[1:0],

SMODEB[1:0],

REF_SEL[1:0]

Low Voltage

V_DD= 2.5V 5%

0.7

OE_SE,

Input

I_IH

SMODEA[1:0],

SMODEB[1:0],

REF_SEL[1:0]

V_DD= V_IN= 3.465V or 2.625V

150

µA

High Current

OE_SE,

Input

I_IL

SMODEA[1:0],

SMODEB[1:0],

REF_SEL[1:0]

V_DD= 3.465V or 2.625V, V_IN= 0V

V_DDOREF= 3.3V 5%: I_OH= -1mA

-5

Low Current

REFOUT

2.6

1.8

V

Output

V_OH

High Voltage

V

_DDOREF= 2.5V 5%: I_OH= -1mA

Output

V_OL

V_DDOREF= 3.3V 5% or 2.5V 5%:

I_OL= 1mA

REFOUT

0.5

V

Low Voltage

Table 4E. Differential DC Characteristics, V = 3.3V 5% or 2.5V 5%, GND = 0V, T = -40°C to 85°C

DD

A

Symbol Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Input

I_IH

CLK[1:0],

nCLK[1:0]

V_DD= V_IN= 3.465V or 2.625V

150

µA

High Current

Input

I_IL

CLK[1:0],

nCLK[1:0]

V_DD= 3.465V or 2.625V,

V_IN= 0V

-150

µA

Low Current

V_PP

Peak-to-Peak Input Voltage¹

Common Mode Input Voltage^{1 2}

0.240

1.3

V

V_CMR

GND + 0.5

V_DD– 0.85

NOTE: 1. Input voltage should not be less than -0.3V, and greater than V_DD.

NOTE: 2. Common mode voltage is defined as the crosspoint.

1

Table 4F. LVPECL DC Characteristics, V

= V

= 3.3V 5%, GND = 0V, T = -40°C to 85°C

DDOB A

DDOA

Symbol Parameter

Test Conditions

Minimum

V_DDOX– 1.4

V_DDOX– 2.0

Typical

Maximum

Units

V_OH

V_OL

Output High Voltage²

Output Low Voltage²

V_DDOX– 0.8

V_DDOX– 1.6

V

Peak-to-Peak

Output Voltage Swing

V_SWING

0.6

1.0

V

NOTE: 1. V_DDOXdenotes V_DDOAand V_DDOB

NOTE: 2. Outputs terminated with 50to V_DDOX– 2V.

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May 19, 2016

8T39S08A Datasheet

1

Table 4G. LVPECL DC Characteristics,

Symbol Parameter

V

= V

= 2.5V 5%, GND = 0V, T = -40°C to 85°C

DDOA

DDOB A

Test Conditions

Minimum

V_DDOX– 1.4

V_DDOX– 2.0

Typical

Maximum

V_DDOX– 0.8

V_DDOX– 1.6

Units

V_OH

V_OL

Output High Voltage²

Output Low Voltage²

V

Peak-to-Peak Output

Voltage Swing

V_SWING

0.4

1.0

V

NOTE: 1. V_DDOXdenotes V_DDOAand V_DDOB

NOTE: 2. Outputs terminated with 50 to V_DDOX– 2V.

Table 4H. LVDS DC Characteristics, V

= V

= 3.3V 5%, GND = 0V, T = -40°C to 85°C

DDOB A

DDOA

Symbol Parameter

Test Conditions

Minimum

Typical

Maximum

Units

mV

V

V_OD

Differential Output Voltage

V_ODMagnitude Change

Offset Voltage

247

454

V_OD

V_OS

50

1.025

1.375

V_OS

V_OSMagnitude Change

50

mV

Table 4I. LVDS DC Characteristics, V

= V

= 2.5V 5%, GND = 0V, T = -40°C to 85°C

DDOB A

DDOA

Symbol Parameter

Test Conditions

Minimum

Typical

Maximum

Units

mV

V

V_OD

Differential Output Voltage

V_ODMagnitude Change

Offset Voltage

247

454

V_OD

V_OS

50

1.025

1.375

V_OS

V_OSMagnitude Change

50

mV

Table 5. Crystal Characteristics

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Mode of Oscillation

Fundamental

Frequency

10

40

50

7

MHz



Equivalent Series Resistance (ESR)

Shunt Capacitance

pF

Capacitive Loading (C_L)

12

18

pF

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May 19, 2016

8T39S08A Datasheet

AC Electrical Characteristics

1, 2

Table 6A. AC Characteristics, V = V

= V

= 3.3V 5%, GND = 0V, T = -40°C to 85°C

DD

DDOA

DDOB

DDOREF

A

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

LVDS, LVPECL

Outputs

2000

MHz

Output

f_OUT

Frequency

HCSL Outputs

REFOUT

250

MHz

Clock Frequency = 156.25MHz;

Input Clock from 8T49NS010,

Input Clock Jitter = 86.6fs;

SMODEA/B[1:0] = 00

Buffer Additive Phase Jitter, RMS:

Integration Range 12kHz - 20MHz

REF_SEL[1:0] = 00 or 01

t_jit

34.7

fs

LVPECL Outputs

-159.1

-157.0

-156.0

dBc/Hz

Offset Freq. >10MHz;

156.25MHz Clock Freq.

NF

Noise Floor

LVDS Outputs

HCSL Outputs

RMS Phase Jitter; 25MHz Integration

Range: 100Hz - 1MHz

tjit(Ø)

t_PD

REF_SEL[1:0] = 10 or 11³

0.176

ps

CLK0, nCLK0 or

SMODEA/B[1:0] = 00

SMODEA/B[1:0] = 01

SMODEA/B[1:0] = 10

0.28

0.90

0.75

2.65

80

ns

Propagation

Delay⁴

CLK1, nCLK1 to

any Qx, nQx

Outputs

ns

tsk(o)

tsk(pp)

V_OH

Output Skew^{5, 6}

Part-to-Part Skew^{6, 7}

Voltage High^{8, 9}

ps

200

ps

HCSL Outputs

T_A= 25°C DC Measurement,

R_T= 50 to GND

C_L5pF

520

920

mV

V_OL

Voltage Low^{8, 10}

-150

+150

mV

Absolute Crossing

Voltage^{8, 11, 12}

V_CROSS

160

460

140

4.0

HCSL Outputs

R_T= 50 to GND

C_L5pF

Total Variation of

V_CROSSover all

Edges^{8, 11, 13}

V_CROSS

mV

Rise/Fall

0.6

V/ns

Edge Rate^{3, 14, 15}

LVPECL Outputs

LVDS Outputs

HCSL Outputs

REFOUT

20% to 80%

150

400

450

300

650

750

55

ps

%

Output

Rise/Fall Time

t_R/ t_F

20% to 80%

with Crystal Input

45

odc

Output Duty Cycle¹⁶

with External 50%/ 50%

Duty Cycle Clock Input

55

%

MUX__ISOLATIONMUX Isolation

156.25MHz

75

dB

NOTE: 1. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the

device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications

after thermal equilibrium has been reached under these conditions.

NOTE: 2. All LVDS and LVPECL parameters characterized up to 1.5GHz. HCSL parameters characterized up to 250MHz.

NOTE: 3. Measurement taken from differential waveform.

NOTE: 4. Measured from the differential input crosspoint to the differential output crosspoint.

NOTE: 5. Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross-

point.

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May 19, 2016

8T39S08A Datasheet

NOTE: 6. This parameter is defined in accordance with JEDEC Standard 65.

NOTE: 7. Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency

and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross-

point.

NOTE: 8. Measurement taken from single-ended waveform.

NOTE: 9. Defined as the maximum instantaneous voltage including overshoot.

NOTE: 10. Defined as the minimum instantaneous voltage including undershoot.

NOTE: 11. Measured at crosspoint where the instantaneous voltage value of the rising edge of Qx equals the falling edge of nQx.

NOTE: 12. Refers to the total variation from the lowest crosspoint to the highest, regardless of which edge is crossing. Refers to all cros-

spoint for this measurement.

NOTE: 13. Defined as the total variation of all crossing voltages of rising Qx and falling nQx. This is the maximum allowed variance in

V_CROSSfor any particular system.

NOTE: 14. Measured from -150mV to +150mV on the differential waveform (Qx minus nQx). The signal must be monotonic through the

measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing.

NOTE: 15. Measured at 100MHz.

NOTE: 16. Measured for the following frequencies: 25MHz, 100MHz, 125MHz, 156.25MHz, 312.5MHz, 400MHz, and 644.5313MHz.

13

May 19, 2016

8T39S08A Datasheet

1, 2

Table 6B. AC Characteristics, V = 3.3V 5%, V

= V

= 2.5V 5%, GND = 0V, T = -40°C to 85°C

DD

DDOA

DDOB

DDOREF

A

Symbol

Parameter

Test Conditions

Minimum

Typical Maximum

Units

LVDS, LVPECL

Outputs

2000

MHz

f_OUT

Output Frequency

HCSL Outputs

REFOUT

250

MHz

Clock Frequency = 156.25MHz;

Input Clock from 8T49NS010,

Input Clock Jitter = 86.8fs;

SMODEA/B[1:0] = 00

Buffer Additive Phase Jitter, RMS:

Integration Range 12kHz - 20MHz

REF_SEL[1:0] = 00 or 01

t_jit

36.7

fs

LVPECL

-159.1

-157.0

-155.7

dBc/Hz

Offset Freq. >10MHz;

156.25MHz Clock Freq.

NF

Noise Floor

LVDS

HCSL

RMS Phase Jitter; 25MHz

Integration Range: 100Hz - 1MHz

tjit(Ø)

t_PD

REF_SEL[1:0] = 10 or 11³

0.191

ps

CLK0, nCLK0 or

SMODEA/B[1:0] = 00

SMODEA/B[1:0] = 01

SMODEA/B[1:0] = 10

0.225

0.275

0.9

0.80

ns

Propagation

Delay⁴

CLK1, nCLK1 to

any Qx, nQx

Outputs

0.80

2.80

ns

tsk(o)

tsk(pp)

V_OH

Output Skew^{5, 6}

Part-to-Part Skew^{6, 7}

Voltage High^{8, 9}

80

ps

200

ps

HCSL Outputs

T_A= 25°C DC Measurement,

R_T= 50 to GND

C_L5pF

520

920

mV

V_OL

Voltage Low^{8, 10}

-150

+150

460

mV

Absolute Crossing

Voltage^{8, 11, 12}

V_CROSS

HCSL Outputs

160

R_T= 50 to GND

C_L5pF

Total Variation of

V_CROSSover all

Edges^{8, 11, 13}

V_CROSS

140

4.0

mV

Rise/Fall

0.6

V/ns

ps

Edge Rate^{3, 14, 15}

LVPECL

Outputs

20% to 80%

150

300

LVDS

Outputs

Output

Rise/Fall Time

ps

t_R/ t_F

HCSL Outputs

REFOUT

20% to 80%

400

450

650

750

55

ps

%

with Crystal Input

45

odc

Output Duty Cycle¹⁶

with external 50%/ 50%

Duty Cycle Clock Input

55

%

MUX__ISOLATIONMUX Isolation

156.25MHz

75

dB

NOTE: 1. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the

device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications

after thermal equilibrium has been reached under these conditions.

NOTE: 2. All LVDS and LVPECL parameters characterized up to 1.5GHz. HCSL parameters characterized up to 250MHz.

NOTE: 3. Measurement taken from differential waveform.

NOTE: 4. Measured from the differential input crosspoint to the differential output crosspoint.

NOTE: 5. Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross-

point.

14

May 19, 2016

8T39S08A Datasheet

NOTE: 6. This parameter is defined in accordance with JEDEC Standard 65.

NOTE: 7. Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency

and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross-

point.

NOTE: 8. Measurement taken from single-ended waveform.

NOTE: 9. Defined as the maximum instantaneous voltage including overshoot.

NOTE: 10. Defined as the minimum instantaneous voltage including undershoot.

NOTE: 11. Measured at crosspoint where the instantaneous voltage value of the rising edge of Qx equals the falling edge of nQx.

NOTE: 12. Refers to the total variation from the lowest crosspoint to the highest, regardless of which edge is crossing. Refers to all cross-

point for this measurement.

NOTE: 13. Defined as the total variation of all crossing voltages of rising Qx and falling nQx, This is the maximum allowed variance in

Vcross for any particular system.

NOTE: 14. Measured from -150mV to +150mV on the differential waveform (Qx minus nQx). The signal must be monotonic through the

measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing.

NOTE: 15. Measured at 100MHz.

NOTE: 16. Measured for the following frequencies: 25MHz, 100MHz, 125MHz, 156.25MHz, 312.5MHz, 400MHz, and 644.5313MHz.

15

May 19, 2016

8T39S08A Datasheet

1, 2

Table 6C. AC Characteristics, V = V

= V

= 2.5V 5%, GND = 0V, T = -40°C to 85°C

DDOREF A

DD

DDOA

DDOB

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

LVDS, LVPECL

Outputs

2000

MHz

f_OUT

Output Frequency

HCSL Outputs

REFOUT

250

MHz

Clock Frequency = 156.25MHz;

Input Clock from 8T49NS010,

Input Clock Jitter = 86.8fs;

SMODEA/B[1:0] = 00

Buffer Additive Phase Jitter, RMS:

Integration Range 12kHz - 20MHz

REF_SEL[1:0] = 00 or 01

t_jit

37.1

fs

RMS Phase Jitter; 25MHz Integration

Range: 100Hz - 1MHz

tjit(Ø)

NF

REF_SEL[1:0] = 10 or 11³

0.371

ps

LVPECL

-159

-157

-155

dBc/Hz

ns

Offset Freq. >10MHz;

156.25MHz Clock Freq.

Noise Floor

LVDS

HCSL

CLK0, nCLK0 or

CLK1, nCLK1 to

any Qx, nQx

Outputs

SMODEA/B[1:0] = 00

SMODEA/B[1:0] = 01

SMODEA/B[1:0] = 10

0.275

0.9

0.75

2.80

80

Propagation

Delay⁴

ns

t_PD

ns

tsk(o)

tsk(pp)

V_OH

Output Skew^{5, 6}

Part-to-Part Skew^{6, 7}

Voltage High^{8, 9}

ps

200

ps

HCSL Outputs

T_A= 25°C DC Measurement,

R_T= 50 to GND

C_L5pF

520

920

mV

V_OL

Voltage Low^{8, 10}

-150

+150

mV

Absolute Crossing

Voltage^{8, 11, 12}

V_CROSS

HCSL Outputs

160

460

140

R_T= 50 to GND

C_L5pF

Total Variation of

V_CROSSover all

Edges^{8, 11, 13}

V_CROSS

mV

Rise/Fall

0.6

4.0

V/ns

ps

Edge Rate^{3, 14, 15}

LVPECL

Outputs

20% to 80%

150

300

Output

Rise/Fall Time

LVDS Outputs

HCSL Outputs

REFOUT

20% to 80%

150

400

450

300

650

750

55

ps

%

t_R/ t_F

20% to 80%

With Crystal Input

45

odc

Output Duty Cycle¹⁶

With external 50%/ 50% Duty

Cycle Clock Input

55

%

MUX__ISOLATIONMUX Isolation

156.25MHz

75

dB

NOTE: 1. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the

device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications

after thermal equilibrium has been reached under these conditions.

NOTE: 2. All LVDS and LVPECL parameters characterized up to 1.5GHz. HCSL parameters characterized up to 250MHz.

NOTE: 3. Measurement taken from differential waveform.

NOTE: 4. Measured from the differential input crosspoint to the differential output crosspoint.

NOTE: 5. Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross-

point.

16

May 19, 2016

8T39S08A Datasheet

NOTE: 6. This parameter is defined in accordance with JEDEC Standard 65.

NOTE: 7. Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency

and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross-

point.

NOTE: 8. Measurement taken from single-ended waveform.

NOTE: 9. Defined as the maximum instantaneous voltage including overshoot.

NOTE: 10. Defined as the minimum instantaneous voltage including undershoot.

NOTE: 11. Measured at crosspoint where the instantaneous voltage value of the rising edge of Qx equals the falling edge of nQx.

NOTE: 12. Refers to the total variation from the lowest crosspoint to the highest, regardless of which edge is crossing. Refers to all cross-

point for this measurement.

NOTE: 13. Defined as the total variation of all crossing voltages of rising Qx and falling nQx, This is the maximum allowed variance in

Vcross for any particular system.

NOTE: 14. Measured from -150mV to +150mV on the differential waveform (Qx minus nQx). The signal must be monotonic through the

measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing.

NOTE: 15. Measured at 100MHz.

NOTE: 16. Measured for the following frequencies: 25MHz, 100MHz, 125MHz, 156.25MHz, 312.5MHz, 400MHz, and 644.5313MHz.

17

May 19, 2016

8T39S08A Datasheet

Additive Phase Jitter

The spectral purity in a band at a specific offset from the fundamental

compared to the power of the fundamental is called the dBc Phase

Noise. This value is normally expressed using a Phase noise plot

and is most often the specified plot in many applications. Phase noise

is defined as the ratio of the noise power present in a 1Hz band at a

specified offset from the fundamental frequency to the power value of

the fundamental. This ratio is expressed in decibels (dBm) or a ratio

of the power in the 1Hz band to the power in the fundamental. When

the required offset is specified, the phase noise is called a dBc value,

which simply means dBm at a specified offset from the fundamental.

By investigating jitter in the frequency domain, we get a better

understanding of its effects on the desired application over the entire

time record of the signal. It is mathematically possible to calculate an

expected bit error rate given a phase noise plot.

Additive Phase Jitter @ 156.25MHz

12kHz to 20MHz = 34.7fs (typical)

Offset from Carrier Frequency (Hz)

As with most timing specifications, phase noise measurements have

issues relating to the limitations of the measurement equipment. The

noise floor of the equipment can be higher or lower than the noise

floor of the device. Additive phase noise is dependent on both the

noise floor of the input source and measurement equipment.

The additive phase jitter for this device was measured using an IDT

Clock Driver 8T49NS010 as an input source and Agilent E5052

phase noise analyzer.

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May 19, 2016

8T39S08A Datasheet

Applications Information

Recommendations for Unused Input and Output Pins

Inputs:

Outputs:

CLK/nCLK Inputs

LVCMOS Output (REFOUT)

For applications not requiring the use of the differential input, both

CLK and nCLK can be left floating. Though not required, but for

additional protection, a 1k resistor can be tied from CLK to ground.

If LVCMOS output is not used, then disable the output and it can be

left floating.

LVPECL and HCSL Outputs

Any unused output pairs can be left floating. We recommend that

there is no trace attached.

Crystal Inputs

For applications not requiring the use of the crystal oscillator input,

both XTAL_IN and XTAL_OUT can be left floating. Though not

required, but for additional protection, a 1k resistor can be tied from

XTAL_IN to ground.

LVDS Outputs

Any unused LVDS output pairs can be either left floating or

terminated with 100 across. If they are left floating, we recommend

that there is no trace attached.

LVCMOS Control Pins

All control pins have internal pulldowns; additional resistance is not

required but can be added for additional protection. A 1k resistor

can be used.

Differential Outputs

If all the outputs of any bank are not used, then disable all outputs to

High-Impedance.

Crystal Input Interface

The 8T39S08A has been characterized with 18pF parallel resonant

crystals. The capacitor values, C1 and C2, shown in Figure 1 below

were determined using an 18pF parallel resonant crystal and were

chosen to minimize the ppm error. In addition, the recommended

12pF parallel resonant crystal tuning is shown in Figure 2.The

optimum C1 and C2 values can be slightly adjusted for different

board layouts.

XTAL_IN

C1

27pF

X1

18pF Parallel Crystal

XTAL_OUT

C2

27pF

Power Up Ramp Sequence

This device has multiple supply pins dedicated for different blocks.

Output power supplies V_DDOx(V_DDOA, V_DDOB, V_DDOREF) must ramp

up before, or concurrently with core power supply V_DD.All power

supplies must ramp up in a linear fashion and monotonically. Both

Figure 1. Crystal Input Interface

V_DDOAand V_DDOBpower supplies must be powered-up even when

only one bank of outputs is in use.

XTAL_IN

C1

15pF

X1

12pF Parallel Crystal

XTAL_OUT

C2

15pF

Figure 2. Crystal Input Interface

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May 19, 2016

8T39S08A Datasheet

Overdriving the XTAL Interface

TheXTAL_INinputcanbe overdriven byan LVCMOSdriver orby one

side of a differential driver through an AC coupling capacitor. The

XTAL_OUT pin can be left floating. The amplitude of the input signal

should be between 500mV and 1.8V and the slew rate should not be

less than 0.2V/ns. For 3.3V LVCMOS inputs, the amplitude must be

reduced from full swing to at least half the swing in order to prevent

signal interference with the power rail and to reduce internal noise.

Figure 3A shows an example of the interface diagram for a high

speed 3.3V LVCMOS driver. This configuration requires that the sum

of the output impedance of the driver (Ro) and the series resistance

(Rs) equals the transmission line impedance. In addition, matched

termination at the crystal input will attenuate the signal in half. This

can be done in one of two ways. First, R1 and R2 in parallel should

equal the transmission line impedance. For most 50 applications,

R1 and R2 can be 100. This can also be accomplished by removing

R1 and changing R2 to 50. The values of the resistors can be

increased to reduce the loading for a slower and weaker LVCMOS

driver. Figure 3B shows an example of the interface diagram for an

LVPECL driver. This is a standard LVPECL termination with one side

of the driver feeding the XTAL_IN input. It is recommended that all

components in the schematics be placed in the layout. Though some

components might not be used, they can be utilized for debugging

purposes. The datasheet specifications are characterized and

guaranteed by using a quartz crystal as the input.

VCC

XTAL_OUT

R1

100

C1

Rs

Zo = 50 ohms

Ro

XTAL_IN

.1uf

R2

100

Zo = Ro + Rs

LVCMOS Driver

Figure 3A. General Diagram for LVCMOS Driver to XTAL Input Interface

XTAL_OUT

C2

Zo = 50 ohms

XTAL_I N

.1uf

Zo = 50 ohms

R1

50

R2

50

LVPECL Driver

R3

50

Figure 3B. General Diagram for LVPECL Driver to XTAL Input Interface

20

May 19, 2016

8T39S08A Datasheet

Wiring the Differential Input to Accept Single-Ended Levels

Figure 4 shows how a differential input can be wired to accept single

ended levels. The reference voltage V₁= V_DD/2 is generated by the

bias resistors R1 and R2. The bypass capacitor (C1) is used to help

filter noise on the DC bias. This bias circuit should be located as close

to the input pin as possible. The ratio of R1 and R2 might need to be

adjusted to position the V₁in the center of the input voltage swing. For

example, if the input clock swing is 2.5V and V_DD= 3.3V, R1 and R2

value should be adjusted to set V₁at 1.25V. The values below are for

when both the single ended swing and V_DDare at the same voltage.

This configuration requires that the sum of the output impedance of

the driver (Ro) and the series resistance (Rs) equals the transmission

line impedance. In addition, matched termination at the input will

attenuate the signal in half. This can be done in one of two ways.

First, R3 and R4 in parallel should equal the transmission line

impedance. For most 50 applications, R3 and R4 can be 100. The

values of the resistors can be increased to reduce the loading for

slower and weaker LVCMOS driver. When using single-ended

signaling, the noise rejection benefits of differential signaling are

reduced. Even though the differential input can handle full rail

LVCMOS signaling, it is recommended that the amplitude be

reduced. The datasheet specifies a lower differential amplitude,

however this only applies to differential signals. For single-ended

applications, the swing can be larger, however V_ILcannot be less

than -0.3V and V_IHcannot be more than V_DD+ 0.3V. Though some

of the recommended components might not be used, the pads

should be placed in the layout. They can be utilized for debugging

purposes. The datasheet specifications are characterized and

guaranteed by using a differential signal.

Figure 4. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels

21

May 19, 2016

8T39S08A Datasheet

3.3V Differential Clock Input Interface

The CLK /nCLK accepts LVDS, LVPECL, HSTL and other differential

signals. Both differential inputs must meet the V_PPand V_CMRinput

requirements. Figures 5A to 5E show interface examples for the

CLK/nCLK input driven by the most common driver types. The input

interfaces suggested here are examples only. Please consult with the

vendor of the driver component to confirm the driver termination

requirements. For example, in Figure 5A, the input termination

applies for IDT open emitter HSTL drivers. If you are using an HSTL

driver from another vendor, use their termination recommendation.

3.3V

1.8V

Zo = 50Ω

CLK

Zo = 50Ω

nCLK

Differential

Input

HSTL

R1

50Ω

R2

50Ω

IDT

HSTL Driver

Figure 5A. CLK/nCLK Input Driven by an

IDT Open Emitter HSTL Driver

Figure 5B. CLK/nCLK Input Driven by a

3.3V LVPECL Driver

Figure 5C. CLK/nCLK Input Driven by a

3.3V LVPECL Driver

Figure 5D. CLK/nCLK Input Driven by a

3.3V LVDS Driver

Figure 5E. CLK/nCLK Input Driven by an

IDT Open Collector CML Driver

22

May 19, 2016

8T39S08A Datasheet

2.5V Differential Clock Input Interface

The CLK /nCLK accepts LVDS, LVPECL, HSTL, HCSL and other

differential signals. Both V_SWINGand V_OHmust meet the V_PPand

V_CMRinput requirements. Figures 6A to 6E show interface examples

for the CLK/nCLK input driven by the most common driver types. The

input interfaces suggested here are examples only. Please consult

with the vendor of the driver component to confirm the driver

termination requirements. For example, in Figure 6A, the input

termination applies for IDT open emitter HSTL drivers. If you are

using an HSTL driver from another vendor, use their termination

recommendation.

2.5V

1.8V

Zo = 50Ω

CLK

Zo = 50Ω

nCLK

Differential

Input

HSTL

R1

50Ω

R2

50Ω

IDT Open Emitter

HSTL Driver

Figure 6A. CLK/nCLK Input Driven by an

IDT Open Emitter HSTL Driver

Figure 6B. CLK/nCLK Input Driven by a

2.5V LVPECL Driver

2.5V

Zo = 50

*R3

*R4

33

CLK

nCLK

Differential

Input

HCSL

R1

R2

50

*Optional R3 and R4 can be 0

Figure 6C. CLK/nCLK Input Driven by a

2.5V LVPECL Driver

Figure 6D. CLK/nCLK Input Driven by a

2.5V HCSL Driver

Figure 6E. CLK/nCLK Input Driven by a 2.5V LVDS Driver

23

May 19, 2016

8T39S08A Datasheet

LVDS Driver Termination

For a general LVDS interface, the recommended value for the

termination impedance (Z_T) is between 90 and 132. The actual

value should be selected to match the differential impedance (Z₀) of

your transmission line. A typical point-to-point LVDS design uses a

100 parallel resistor at the receiver and a 100 differential

transmission-line environment. In order to avoid any

transmission-line reflection issues, the components should be

surface mounted and must be placed as close to the receiver as

possible. IDT offers a full line of LVDS compliant devices with two

types of output structures: current source and voltage source. The

standard termination schematic as shown in Figure 7A can be used

with either type of output structure. Figure 7B, which can also be

used with both output types, is an optional termination with center tap

capacitance to help filter common mode noise. The capacitor value

should be approximately 50pF. If using a non-standard termination, it

is recommended to contact IDT and confirm if the output structure is

current source or voltage source type. In addition, since these

outputs are LVDS compatible, the input receiver’s amplitude and

common-mode input range should be verified for compatibility with

the output.

Z_O Z_T

LVDS

Receiver

LVDS

Driver

Z_T

Figure 7A. Standard Termination

Z_T

Z_O Z_T

LVDS

Driver

2

Z_T

2

LVDS

Receiver

C

Figure 7B. Optional Termination

LVDS Termination

24

May 19, 2016

8T39S08A Datasheet

Termination for 3.3V LVPECL Outputs

The clock topology shown below is a typical termination for LVPECL

outputs. The two different terminations mentioned are recommended

only as guidelines.

The differential outputs are low impedance follower outputs that

generate ECL/LVPECL compatible outputs. Therefore, terminating

resistors (DC current path to ground) or current sources must be

used for functionality. These outputs are designed to drive 50

transmission lines. Matched impedance techniques should be used

to maximize operating frequency and minimize signal distortion.

3.3V

R3

R4

125

3.3V

Z_o= 50

+

_

Input

Z_o= 50

R1

84

R2

84

Figure 8A. 3.3V LVPECL Output Termination

Figure 8B. 3.3V LVPECL Output Termination

25

May 19, 2016

8T39S08A Datasheet

Termination for 2.5V LVPECL Outputs

Figure 9A and Figure 9B show examples of termination for 2.5V

LVPECL driver. These terminations areequivalent to terminating 50

to V_DDO– 2V. For V_DDO= 2.5V, the V_DDO– 2V is very close to ground

level. The R3 in Figure 9B can be eliminated and the termination is

shown in Figure 9C.

2.5V

V_DDO= 2.5V

2.5V

V_DDO= 2.5V

R1

R3

50Ω

250

+

50Ω

+

–

50Ω

–

2.5V LVPECL Driver

R1

50

R2

50

2.5V LVPECL Driver

R2

62.5

R4

62.5

R3

18

Figure 9A. 2.5V LVPECL Driver Termination Example

Figure 9B. 2.5V LVPECL Driver Termination Example

2.5V

V_DDO= 2.5V

50Ω

+

50Ω

–

2.5V LVPECL Driver

R1

50

R2

50

Figure 9C. 2.5V LVPECL Driver Termination Example

26

May 19, 2016

8T39S08A Datasheet

Recommended Termination

Figure 10A is the recommended source termination for applications

where the driver and receiver will be on a separate PCBs. This

termination is the standard for PCI Express™and HCSL output types.

All traces should be 50 impedance single-ended or 100

differential.

Rs

0.5" Max

L1

0-0.2"

L2

1-14"

L4

0.5 - 3.5"

L5

22 to 33 +/-5%

L1

L2

L4

L5

PCI Express

Connector

PCI Express

Driver

PCI Express

Add-in Card

0-0.2" L3

L3

49.9 +/- 5%

Rt

Figure 10A. Recommended Source Termination (where the driver and receiver will be on separate PCBs)

Figure 10B is the recommended termination for applications where a

point-to-point connection can be used. A point-to-point connection

contains both the driver and the receiver on the same PCB. With a

matched termination at the receiver, transmission-line reflections will

be minimized. In addition, a series resistor (Rs) at the driver offers

flexibility and can help dampen unwanted reflections. The optional

resistor can range from 0 to 33. All traces should be 50

impedance single-ended or 100 differential.

Rs

0.5" Max

L1

0-18"

L2

0-0.2"

L3

0 to 33

L1

L2

L3

PCI Express

Driver

49.9 +/- 5%

Rt

Figure 10B. Recommended Termination (where a point-to-point connection can be used)

27

May 19, 2016

8T39S08A Datasheet

VFQFN EPAD Thermal Release Path

In order to maximize both the removal of heat from the package and

the electrical performance, a land pattern must be incorporated on

the Printed Circuit Board (PCB) within the footprint of the package

corresponding to the exposed metal pad or exposed heat slug on the

package, as shown in Figure 11. The solderable area on the PCB, as

defined by the solder mask, should be at least the same size/shape

as the exposed pad/slug area on the package to maximize the

thermal/electrical performance. Sufficient clearance should be

designed on the PCB between the outer edges of the land pattern

and the inner edges of pad pattern for the leads to avoid any shorts.

and dependent upon the package power dissipation as well as

electrical conductivity requirements. Thus, thermal and electrical

analysis and/or testing are recommended to determine the minimum

number needed. Maximum thermal and electrical performance is

achieved when an array of vias is incorporated in the land pattern. It

is recommended to use as many vias connected to ground as

possible. It is also recommended that the via diameter should be 12

to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is

desirable to avoid any solder wicking inside the via during the

soldering process which may result in voids in solder between the

exposed pad/slug and the thermal land. Precautions should be taken

to eliminate any solder voids between the exposed heat slug and the

land pattern. Note: These recommendations are to be used as a

guideline only. For further information, please refer to the Application

Note on the Surface Mount Assembly of Amkor’s Thermally/

Electrically Enhance Lead frame Base Package, Amkor Technology.

While the land pattern on the PCB provides a means of heat transfer

and electrical grounding from the package to the board through a

solder joint, thermal vias are necessary to effectively conduct from

the surface of the PCB to the ground plane(s). The land pattern must

be connected to ground through these vias. The vias act as “heat

pipes”. The number of vias (i.e. “heat pipes”) are application specific

SOLDER

EXPOSED HEAT SLUG

PIN PAD

GROUND PLANE

LAND PATTERN

(GROUND PAD)

PIN PAD

THERMAL VIA

Figure 11. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)

28

May 19, 2016

8T39S08A Datasheet

Power Considerations

This section provides information on power dissipation and junction temperature for the 8T39S08A.

Equations and example calculations are also provided.

LVPECL Power Considerations

1. Power Dissipation.

The total power dissipation for the 8T39S08A is the sum of the core power plus the power dissipated due to outputs switching.

The following is the power dissipation for V_DD= 3.3V +5% = 3.465V, which gives worst case results.

The Maximum current at 85°C is as follows:

I_{EE_MAX}= 175mA

•

Power (core)_MAX= I_{EE_MAX}* V_{DD_MAX}= 3.465V * 175mA = 606.375mW

Power (outputs)_MAX= 30mW/Loaded Output pair

If all outputs are loaded, the total power is 8 * 32mW = 256mW

Maximum LVPECL power dissipation = 606.375mW + 256mW = 862.375mW

LVCMOS Output Power Dissipation

•

Static Power Dissipation: Power_{_(static)MAX}= V_{DDOREF_MAX}* I_{DDREF_MAX}= 3.465V * 2mA = 6.93mW

(I_{DDREF_MAX}= 2mA)

•

Dynamic Power Dissipation at 250MHz

Power (Dynamic)_MAX= C_PD* Frequency * N * V_DDOREF²= 5.3pF * 250MHz * 1 * 3.465²= 15.9mW

LVCMOS Power Dissipation = 6.93mW + 15.9mW = 22.84mW

•

LVCMOS Power Dissipation = 6.93mW + 15.9mW = 22.84mW

Total Power Dissipation = 862.375mW + 22.84mW = 885.215mW

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The

maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond

wire and bond pad temperature remains below 125°C.

The equation for Tj is as follows: Tj = _JA* Pd_total + T_A

Tj = Junction Temperature

_JA= Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

T_A= Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance _JAmust be used. Assuming no air flow and

a multi-layer board, the appropriate value is 33°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85°C with all outputs

switching is:

85°C + 0.885W * 33.0°C/W = 114.2°C. This is below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of

board (multi-layer).

Table 7. Thermal Resistance  for 40-Lead VFQFN

JA

_JAvs. Air Flow

Meters per Second

0

1

2.5

Multi-Layer PCB, JEDEC Standard Test Boards

33.0°C/W

26.3°C/W

24.0°C/W

29

May 19, 2016

8T39S08A Datasheet

3. Calculations and Equations.

The purpose of this section is to calculate the power dissipation for the LVPECL output pairs.

LVPECL output driver circuit and termination are shown in Figure 12.

V_DDO

Q1

V_OUT

RL

50Ω

V_DDO- 2V

Figure 12. LVPECL Driver Circuit and Termination

To calculate power dissipation per output pair due to loading, use the following equations which assume a 50 load, and a termination voltage

of V_DDO– 2V.

•

For logic high, V_OUT= V_{OH_MAX}= V_{DDO_MAX}– 0.8V

(V_{DDO_MAX}– V_{OH_MAX}) = 0.8V

For logic low, V_OUT= V_{OL_MAX}= V_{DDO_MAX}– 1.6V

(V_{DDO_MAX}– V_{OL_MAX}) = 1.6V

Pd_H is power dissipation when the output drives high.

Pd_L is the power dissipation when the output drives low.

Pd_H = [(V_{OH_MAX}– (V_{DDO_MAX}– 2V))/R_L] * (V_{DDO_MAX}– V_{OH_MAX}) = [(2V – (V_{DDO_MAX}– V_{OH_MAX}))/R_L] * (V_{DDO_MAX}– V_{OH_MAX}) =

[(2V – 0.8V)/50] * 0.8V = 19.2mW

Pd_L = [(V_{OL_MAX}– (V_{DDO_MAX}– 2V))/R_L] * (V_{DDO_MAX}– V_{OL_MAX}) = [(2V – (V_{DDO_MAX}– V_{OL_MAX}))/R_L] * (V_{DDO_MAX}– V_{OL_MAX}) =

[(2V – 1.6V)/50] * 1.6V = 12.8mW

Total Power Dissipation per output pair = Pd_H + Pd_L = 32mW

30

May 19, 2016

8T39S08A Datasheet

Power Considerations

This section provides information on power dissipation and junction temperature for the 8T39S08A.

Equations and example calculations are also provided.

LVDS Power Considerations

1. Power Dissipation.

The total power dissipation for the 8T39S08A is the sum of the core power plus the power dissipated due to outputs switching.

The following is the power dissipation for V_DD= 3.3V +5% = 3.465V, which gives worst case results.

The Maximum current at 85°C is as follows:

I_{DD_MAX}= 110mA

I_{DDO_MAX}= 185mA

Maximum LVDS Power Dissipation = V_{DD_MAX}* (I_{DD_MAX}+ I_{DDO_MAX}) = 3.465V * (110mA + 185mA) = 1022.175mW

LVCMOS Output Power Dissipation

•

Static Power Dissipation: Power_{_(static)MAX}= V_{DDOREF_MAX}* I_{DDREF_MAX}= 3.465V * 2mA = 6.93mW

(I_{DDREF_MAX}= 2mA)

•

Dynamic Power Dissipation at 250MHz

Power (Dynamic)_MAX= C_PD* Frequency * N * V_DDOREF²= 5.3pF * 250MHz * 1 * 3.465²= 15.9mW

LVCMOS Power Dissipation = 6.93mW + 15.9mW = 22.84mW

Total Power Dissipation = 1022.175mW + 22.84mW = 1045.015mW

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The

maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond

wire and bond pad temperature remains below 125°C.

The equation for Tj is as follows: Tj = _JA* Pd_total + T_A

Tj = Junction Temperature

_JA= Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

T_A= Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance _JAmust be used. Assuming no air flow and

a multi-layer board, the appropriate value is 33°C/W per Table 7. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:

85°C + 1.045W * 33.0°C/W = 119.5°C. This is below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of

board (multi-layer).

31

May 19, 2016

8T39S08A Datasheet

Power Considerations

This section provides information on power dissipation and junction temperature for the 8T39S08A.

Equations and example calculations are also provided.

HCSL Power Considerations

1. Power Dissipation.

The total power dissipation for the 8T39S08A is the sum of the core power plus the power dissipated due to outputs switching.

The following is the power dissipation for V_DD= 3.3V +5% = 3.465V, which gives worst case results.

The Maximum current at 85°C is as follows:

I_{DD_MAX}= 100mA

I_{DDO_MAX}= 70mA (at Maximum Application Frequency 250MHz)

•

Power (core)_MAX= V_{DD_MAX}* (I_{DD_MAX}+ I_{DDO_MAX}) = 3.465V * (100mA + 70mA) = 589.05mW

Power (outputs)_MAX= 44.5mW/Loaded Output pair

If all outputs are loaded, the total power is 8 * 44.5mW = 356mW

Maximum HCSL power dissipation = 589.05mW + 356mW = 945.05mW

LVCMOS Output Power Dissipation

•

Static Power Dissipation: Power_{_(static)MAX}= V_{DDOREF_MAX}* I_{DDREF_MAX}= 3.465V * 2mA = 6.93mW

(I_{DDREF_MAX}= 2mA)

•

Dynamic Power Dissipation at 250MHz

Power (Dynamic)_MAX= C_PD* Frequency * N * V_DDOREF²= 5.3pF * 250MHz * 1 * 3.465²= 15.9mW

LVCMOS Power Dissipation = 6.93mW + 15.9mW = 22.84mW

Total Power Dissipation = 945.05mW + 22.84mW = 967.89mW

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The

maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond

wire and bond pad temperature remains below 125°C.

The equation for Tj is as follows: Tj = _JA* Pd_total + T_A

Tj = Junction Temperature

_JA= Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

T_A= Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance _JAmust be used. Assuming no air flow and

a multi-layer board, the appropriate value is 33°C/W per Table 7. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:

85°C + 0.968W * 33.0°C/W = 116.9°C. This is below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of

board (multi-layer).

32

May 19, 2016

8T39S08A Datasheet

3. Calculations and Equations.

The purpose of this section is to calculate power dissipation on the IC per HCSL output pair.

HCSL output driver circuit and termination are shown in Figure 13.

VDDO

I_OUT= 17mA

V_OUT

R_REF

=

⁴⁷⁵Ω 1%

R_L

50Ω

IC

Figure 13. HCSL Driver Circuit and Termination

HCSL is a current steering output which sources a maximum of 17mA of current per output. To calculate worst case on-chip power dissipation,

use the following equations which assume a 50 load to ground.

The highest power dissipation occurs when V_{DDO MAX}.

_

Power = (V_{DDO_MAX}– V_OUT) * I_OUT

,

since V_OUT– I_OUT* R_L

= (V_{DDO_MAX}– I_OUT* R_L) * I_OUT

= (3.465V – 17mA * 50) * 17mA

Total Power Dissipation per output pair = 44.5mW

33

May 19, 2016

8T39S08A Datasheet

Reliability Information

Table 8.  vs. Air Flow Table for a 40-Lead VFQFN

JA

_JAvs. Air Flow

Meters per Second

0

1

2.5

Multi-Layer PCB, JEDEC Standard Test Boards

33.0°C/W

26.3°C/W

°C/W24.0

Transistor Count

The transistor count for 8T39S08A is: 10,283

34

May 19, 2016

8T39S08A Datasheet

40-Lead VFQFN Package Outline and Package Dimensions

35

May 19, 2016

8T39S08A Datasheet

40-Lead VFQFN Package Outline and Package Dimensions, continued

36

May 19, 2016

8T39S08A Datasheet

40-Lead VFQFN Package Outline and Package Dimensions, continued

37

May 19, 2016

8T39S08A Datasheet

Ordering Information

Table 9. Ordering Information

Part/Order Number

8T39S08ANLGI

Marking

Package

Shipping Packaging

Tray

Temperature

-40°C to 85°C

IDT8T39S08ANLGI

40-Lead VFQFN, Lead-Free

8T39S08ANLGI8

Tape & Reel

38

May 19, 2016

Corporate Headquarters

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San Jose, CA 95138 USA

www.IDT.com

Sales

Tech Support

www.idt.com/go/support

1-800-345-7015 or 408-284-8200

Fax: 408-284-2775

www.IDT.com/go/sales

DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications

and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein

is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability,

or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.

IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably

expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.

Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of

IDT or their respective third party owners.

For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary.

厂商	型号	描述	页数
VISHAY	8T3002-1	[ RESISTOR, TEMPERATURE DEPENDENT, NTC, 30000 ohm, THROUGH HOLE MOUNT, RADIAL LEADED ]	5 页
VISHAY	8T3002-A3	[ RESISTOR, TEMPERATURE DEPENDENT, NTC, 30000 ohm ]	1 页
VISHAY	8T3002-A4	[ RESISTOR, TEMPERATURE DEPENDENT, NTC, 30000 ohm ]	1 页
NXP	8T32NA	[ IC PIA-GENERAL PURPOSE, PDIP24, Parallel IO Port ]	7 页
VISHAY	8T3302A5	[ RESISTOR, TEMPERATURE DEPENDENT, NTC, 33000 ohm, CHASSIS MOUNT, RADIAL LEADED ]	4 页
VISHAY	8T3302A8	[ RESISTOR, TEMPERATURE DEPENDENT, NTC, 33000 ohm, CHASSIS MOUNT, RADIAL LEADED ]	4 页
VISHAY	8T3302C3	[ RESISTOR, TEMPERATURE DEPENDENT, NTC, 33000 ohm, CHASSIS MOUNT, RADIAL LEADED ]	4 页
VISHAY	8T3302C8	[ RESISTOR, TEMPERATURE DEPENDENT, NTC, 33000 ohm, CHASSIS MOUNT, RADIAL LEADED ]	4 页
VISHAY	8T3302H	[ RESISTOR, TEMPERATURE DEPENDENT, NTC, 33000 ohm, CHASSIS MOUNT, RADIAL LEADED ]	4 页
IDT	8T349316	[ 2.5V LVDS 1:16 Clock Fanout Buffer ]	19 页