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8S58035AKILF

型号：

8S58035AKILF

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

21 页

PDF大小：

463 K

下载PDF手册
Low Skew, 2:1 LVPECL MUX with 1:6  
Fanout and Internal Termination  
8S58035I  
Data Sheet  
General Description  
Features  
The 8S58035I is a high speed 2-to-6 Differential-to-LVPECL Fanout  
Buffer. The 8S58035I is optimized for high speed and very low output  
skew, making it suitable for use in demanding applications such as  
SONET, 1 Gigabit and 10 Gigabit Ethernet, and Fiber Channel. The  
internally terminated differential inputs and VREF_AC pins allow other  
differential signal families such as LVDS, LVHSTL and CML to be  
easily interfaced to the input with minimal use of external compo-  
nents. The device also has a 2:1 MUX input, allowing for easy selec-  
tion between two clock reference sources. The 8S58035I is  
packaged in a small 5mm x 5mm 32-pin VFQFN package which  
makes it ideal for use in space-constrained applications.  
• Six LVPECL outputs  
• INx, nINx inputs can accept the following differential input levels:  
LVPECL, LVDS, CML  
• 50internal input termination to VT  
• Two selectable differential input pairs  
• Maximum output frequency: 3.2GHz  
• Output Skew: 45ps (maximum)  
• Part-to-Part Skew: 200ps (maximum)  
• Additive phase jitter, RMS: 47fs (typical),  
(fREF = 622.08MHz, 12kHz - 20MHz, VCC = 3.3V)  
• Propagation Delay: 580ps (maximum)  
• LVPECL mode operating voltage supply range:  
VCC = 2.5V 5%, 3.3V 10%, VEE = 0V  
• -40°C to 85°C ambient operating temperature  
Block Diagram  
Pin Assignment  
Q0  
32 31 30 29 28 27 26 25  
IN0  
VT0  
1
2
3
4
5
6
7
8
24 VEE  
23 VCC  
22 Q2  
21 nQ2  
20 Q3  
19 nQ3  
18 VCC  
17 VEE  
nQ0  
IN0  
VREF_AC0  
nIN0  
Q1  
50  
VT0  
0
nQ1  
IN1  
50  
nIN0  
VT1  
Q2  
VREF_AC1  
nIN1  
VREF_  
AC  
0
nQ2  
9
10 11 12 13 14 15 16  
IN1  
50  
Q3  
1
VT1  
50  
nQ3  
8S58035I  
nIN1  
32-Lead VFQFN  
Q4  
VREF_ AC1  
5mm x 5mm x 0.925mm package body  
3.15mm x 3.15mm Epad Size  
K Package  
nQ4  
Pullup  
SEL  
Top View  
Q5  
nQ5  
©2016 Integrated Device Technology, Inc  
1
Revision A February 5, 2016  
8S58035I Data Sheet  
Table 1. Pin Descriptions  
Number  
Name  
Type  
Description  
Non-inverting differential LVPECL clock inputs.  
RT = 50termination to VT.  
1, 5  
IN0, IN1  
Input  
Input  
2, 6  
VT0, VT1  
Termination inputs.  
VREF_AC0  
VREF_AC1  
,
3, 7  
4, 8  
Output  
Reference voltage for AC-coupled applications.  
Inverting differential LVPECL clock inputs.  
RT = 50termination to VT.  
Input  
nIN0, nIN1  
9, 17, 24, 32  
VEE  
nc  
Power  
Negative supply pins.  
No connect pin.  
10  
11, 16, 18, 23,  
25, 30  
VCC  
Power  
Positive supply pins.  
12, 13  
14, 15  
19, 20  
21, 22  
26, 27  
28, 29  
31  
nQ5, Q5  
Output  
Output  
Output  
Output  
Output  
Output  
Input  
Differential output pair. LVPECL interface levels.  
Differential output pair. LVPECL interface levels.  
Differential output pair. LVPECL interface levels.  
Differential output pair. LVPECL interface levels.  
Differential output pair. LVPECL interface levels.  
Differential output pair. LVPECL interface levels.  
Input select pin. LVCMOS/LVTTL interface levels.  
nQ4, Q4  
nQ3, Q3  
nQ2, Q2  
nQ1, Q1  
nQ0, Q0  
SEL  
Pullup  
NOTE: Pullup refers to an internal input resistor. See Table 2, Pin Characteristics, for typical values.  
Table 2. Pin Characteristics  
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
RPULLUP  
Input Pullup Resistor  
51  
k  
Function Tables  
Table 3. SEL Function Table  
SEL  
0
Function  
IN0, nIN0 input selected  
IN, nIN1 input selected (default)  
1
©2016 Integrated Device Technology, Inc  
2
Revision A February 5, 2016  
8S58035I Data Sheet  
Absolute Maximum Ratings  
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are  
stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC  
Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect  
product reliability.  
Item  
Rating  
Supply Voltage, VCC  
Inputs, VI  
4.6V  
-0.5V to VCC + 0.5V  
Outputs, IO (LVPECL)  
Continuous Current  
Surge Current  
50mA  
100mA  
Input Current, IIN (IN0, nIN0, IN1, nIN1)  
VT Current, IVT  
VREF_AC Input Sink/Source, IREF_AC  
50mA  
100mA  
2mA  
Package Thermal Impedance, JA  
42.7C/W (0 mps)  
-65C to 150C  
Storage Temperature, TSTG  
DC Electrical Characteristics  
Table 4A. Power Supply DC Characteristics, VCC = 2.375V to 3.6V, VEE = 0V, TA = -40°C to 85°C  
Symbol Parameter  
VCC Positive Supply Voltage  
IEE Power Supply Current  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
V
2.375  
3.3  
3.6  
90  
mA  
Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = 2.375V to 3.6V, VEE = 0V, TA = -40°C to 85°C  
Symbol Parameter  
Test Conditions  
VCC = 3.6V  
Minimum  
2.2  
Typical  
Maximum  
VCC + 0.3  
0.8  
Units  
V
VIH  
VIL  
IIH  
Input High Voltage  
Input Low Voltage  
Input High Current  
Input Low Current  
VCC = 3.6V  
-0.3  
V
VCC = VIN = 3.6V  
VCC = 3.6V, VIN = 0V  
10  
µA  
uA  
IIL  
-150  
©2016 Integrated Device Technology, Inc  
3
Revision A February 5, 2016  
8S58035I Data Sheet  
Table 4C. Differential DC Characteristics, VCC = 2.375V to 3.6V, VEE = 0V, TA = -40°C to 85°C  
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
IN0-to-nIN0  
or  
IN1-to-nIN1  
Differential  
Input Resistance  
RDIFF_IN  
80  
100  
120  
INx-to-VTX  
or  
RIN  
Input Resistance  
40  
50  
60  
nINx-to-VTX  
Input High  
Voltage  
IN0, nIN0,  
IN1, nIN1  
VIH  
VIL  
1.2  
0
VCC  
V
V
IN0, nIN0,  
IN1, nIN1  
Input Low Voltage  
V
IH – 0.15  
VIN  
Input Voltage Swing; NOTE 1  
Differential Input Voltage Swing  
0.15  
0.3  
1.4  
2.8  
V
V
VDIFF_IN  
Input Current;  
NOTE 2, 3  
IN0, nIN0,  
IN1, nIN1  
IIN  
45  
mA  
V
VREF_AC0  
or  
VREF_AC  
Bias Voltage  
VCC - 1.4  
VCC – 1.3  
VCC – 1.2  
VREF_AC1  
NOTE 1: Refer to Parameter Measurement Information, Input Voltage Swing diagram.  
NOTE 2: Guaranteed by design.  
NOTE 3: Because of the internal termination RIN, the input current IIN will be determined by the voltages applied at INx, nINx and VTx  
.
Observe the voltages applied to those pins so the input current does not exceed the maximum limit.  
Table 4D. LVPECL DC Characteristics, VCC = 2.375V to 3.6V, VEE = 0V, TA = -40°C to 85°C  
Symbol  
VOH  
Parameter  
Test Conditions  
Minimum  
VCC - 1.05  
VCC - 1.9  
0.55  
Typical  
Maximum  
VCC - 0.85  
VCC - 1.6  
1.0  
Units  
V
Output High Voltage; NOTE1  
Output Low Voltage; NOTE 1  
Output Voltage Swing  
VOL  
V
VOUT  
mV  
V
VDIFF_OUT  
Differential Output Voltage Swing  
1.1  
2.0  
NOTE: Output parameters vary 1:1 with VCC  
.
NOTE 1: Outputs terminated with 50to VCC – 2V  
©2016 Integrated Device Technology, Inc  
4
Revision A February 5, 2016  
8S58035I Data Sheet  
AC Electrical Characteristics  
Table 5. AC Characteristics, VCC = 2.375V to 3.6V, VEE = 0V, TA = -40°C to 85°C  
Parameter  
Symbol  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
fOUT  
Output Frequency  
3.2  
GHz  
Propagation Delay;  
NOTE 1  
tPD  
INx to Qx  
390  
480  
580  
ps  
tsk(o)  
Output Skew; NOTE 2, 4  
45  
ps  
ps  
tsk(pp)  
Part-to-Part Skew; NOTE 3, 4  
200  
Buffer Additive Phase Jitter, RMS;  
refer to Additive Phase Jitter  
section  
622.08MHz,  
Integration Range:  
12kHz to 20MHz  
tjit  
47  
fs  
tR / tF  
Output Rise/Fall Time  
20% - 80%  
40  
160  
ps  
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the  
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after  
thermal equilibrium has been reached under these conditions.  
NOTE: All parameters characterized at fOUT 3.2GHz input signal, unless otherwise noted.  
NOTE 1: Measured from the differential input crosspoint to the differential output crosspoint.  
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output  
differential crosspoints.  
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions.  
Using the same type of inputs on each device, the outputs are measured at the differential crosspoints.  
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.  
©2016 Integrated Device Technology, Inc  
5
Revision A February 5, 2016  
8S58035I Data Sheet  
Additive Phase Jitter  
The spectral purity in a band at a specific offset from the  
fundamental compared to the power of the fundamental is called  
the dBc Phase Noise. This value is normally expressed using a  
Phase noise plot and is most often the specified plot in many  
applications. Phase noise is defined as the ratio of the noise  
power present in a 1Hz band at a specified offset from the  
fundamental frequency to the power value of the fundamental.  
This ratio is expressed in decibels (dBm) or a ratio of the power in  
the 1Hz band to the power in the fundamental. When the required  
offset is specified, the phase noise is called a dBc value, which  
simply means dBm at a specified offset from the fundamental. By  
investigating jitter in the frequency domain, we get a better  
understanding of its effects on the desired application over the  
entire time record of the signal. It is mathematically possible to  
calculate an expected bit error rate given a phase noise plot.  
Additive Phase Jitter @ 622.08MHz  
12kHz to 20MHz = 47fs (typical)  
Offset from Carrier Frequency (Hz)  
As with most timing specifications, phase noise measurements  
have issues relating to the limitations of the equipment. Often the  
noise floor of the equipment is higher than the noise floor of the  
device. This is illustrated above. The device meets the noise floor  
of what is shown, but can actually be lower. The phase noise is  
dependent on the input source and measurement equipment.  
Measured using a Rohde & Schwarz SMA100A as the input  
source.  
©2016 Integrated Device Technology, Inc  
6
Revision A February 5, 2016  
8S58035I Data Sheet  
Parameter Measurement Information  
2V  
SCOPE  
V
Qx  
CC  
VDIFF_IN, VDIFF_OUT  
VIN, VOUT  
nQx  
VEE  
-0.375V to -1.6V  
Output Load Test Circuit  
Single-ended & Differential Input/Output Swing  
nQx  
Qx  
nIN[0:1]  
IN[0:1]  
nQ[0:5]  
nQy  
Qy  
Q[0:5]  
tPD  
Propagation Delay  
Output Skew  
Part 1  
nQx  
nQ[0:5]  
Q[0:5]  
Qx  
Part 2  
nQy  
Qy  
tsk(pp)  
Part-to-Part Skew  
Output Rise/Fall Time  
©2016 Integrated Device Technology, Inc  
7
Revision A February 5, 2016  
8S58035I Data Sheet  
Application Information  
Wiring the Differential Input to Accept Single-Ended Levels  
Figure 1 shows how a differential input can be wired to accept  
single ended levels. The reference voltage V1= VCC/2 is  
impedance. For most 50applications, R3 and R4 can be 100.  
The values of the resistors can be increased to reduce the loading  
for slower and weaker LVCMOS driver. When using single-ended  
signaling, the noise rejection benefits of differential signaling are  
reduced. Even though the differential input can handle full rail  
LVCMOS signaling, it is recommended that the amplitude be  
reduced. The datasheet specifies a lower differential amplitude,  
however this only applies to differential signals. For single-ended  
applications, the swing can be larger, however VIL cannot be less  
than -0.3V and VIH cannot be more than VCC + 0.3V. Though  
some of the recommended components might not be used, the  
pads should be placed in the layout. They can be utilized for  
debugging purposes. The datasheet specifications are  
generated by the bias resistors R1 and R2. The bypass capacitor  
(C1) is used to help filter noise on the DC bias. This bias circuit  
should be located as close to the input pin as possible. The ratio  
of R1 and R2 might need to be adjusted to position the V1in the  
center of the input voltage swing. For example, if the input clock  
swing is 2.5V and VCC = 3.3V, R1 and R2 value should be  
adjusted to set V1 at 1.25V. The values below are for when both  
the single ended swing and VCC are at the same voltage. This  
configuration requires that the sum of the output impedance of the  
driver (Ro) and the series resistance (Rs) equals the transmission  
line impedance. In addition, matched termination at the input will  
attenuate the signal in half. This can be done in one of two ways.  
First, R3 and R4 in parallel should equal the transmission line  
characterized and guaranteed by using a differential signal.  
Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels  
©2016 Integrated Device Technology, Inc  
8
Revision A February 5, 2016  
8S58035I Data Sheet  
3.3V Differential Input with Built-In 50Termination Interface  
The IN /nIN with built-in 50terminations accept LVDS, LVPECL,  
CML and other differential signals. Both signals must meet the VIN  
and VIH input requirements. Figures 2A to 2D show interface  
examples for the IN/nIN input with built-in 50terminations driven  
by the most common driver types. The input interfaces suggested  
here are examples only. If the driver is from another vendor, use  
their termination recommendation. Please consult with the vendor  
of the driver component to confirm the driver termination  
requirements.  
Figure 2A. IN/nIN Input with Built-In 50  
Figure 2B. IN/nIN Input with Built-In 50  
Driven by an LVDS Driver  
Driven by an LVPECL Driver  
3.3V  
3.3V  
3.3V CML with  
Built-In Pullup  
Zo = 50Ω  
Zo = 50Ω  
C1  
C2  
IN  
50Ω  
50Ω  
VT  
nIN  
V_REF_AC  
Receiver with  
Built-In 50Ω  
Figure 2C. IN/nIN Input with Built-In 50  
Figure 2D. IN/nIN Input with Built-In 50  
Driven by a CML Driver with Open Collector  
Driven by a CML Driver with Built-In 50  
Pullup  
©2016 Integrated Device Technology, Inc  
9
Revision A February 5, 2016  
8S58035I Data Sheet  
2.5V LVPECL Input with Built-In 50Termination Interface  
The IN /nIN with built-in 50terminations accept LVDS, LVPECL,  
CML and other differential signals. Both signals must meet the VIN  
and VIH input requirements. Figures 3A to 3D show interface  
examples for the IN/nIN with built-in 50termination input driven  
by the most common driver types. The input interfaces suggested  
here are examples only. If the driver is from another vendor, use  
their termination recommendation. Please consult with the vendor  
of the driver component to confirm the driver termination  
requirements.  
Figure 3A. IN/nIN Input with Built-In 50  
Figure 3B. IN/nIN Input with Built-In 50  
Driven by an LVDS Driver  
Driven by an LVPECL Driver  
Figure 3C. IN/nIN Input with Built-In 50  
Figure 3D. IN/nIN Input with Built-In 50  
Driven by a CML Driver with Built-In 50  
Pullup  
Driven by a CML Driver with Open Collector  
©2016 Integrated Device Technology, Inc  
10  
Revision A February 5, 2016  
8S58035I Data Sheet  
Recommendations for Unused Output Pins  
Outputs:  
LVPECL Outputs  
All unused LVPECL output pairs can be left floating. We  
recommend that there is no trace attached. Both sides of the  
differential output pair should either be left floating or terminated.  
2.5V Differential Input with Built-In 50Termination Unused Input Handling  
To prevent oscillation and to reduce noise, it is recommended to  
have pullup and pulldown connect to true and complement of the  
unused input as shown in Figure 4A.  
2.5V  
2.5V  
R1  
680  
IN  
VT  
nIN  
Receiver  
With  
Built-In  
R2  
50Ω  
680  
Figure 4A. Unused Input Handling  
3.3V Differential Input with Built-In 50Termination Unused Input Handling  
To prevent oscillation and to reduce noise, it is recommended to  
have pullup and pulldown connect to true and complement of the  
unused input as shown in Figure 4B.  
3.3V  
3.3V  
R1  
1k  
IN  
VT  
nIN  
Receiver  
With  
Built-In  
R2  
50Ω  
1k  
Figure 4B. Unused Input Handling  
©2016 Integrated Device Technology, Inc  
11  
Revision A February 5, 2016  
8S58035I Data Sheet  
Termination for 3.3V LVPECL Outputs  
The clock layout topology shown below is a typical termination for  
LVPECL outputs. The two different layouts mentioned are  
recommended only as guidelines.  
transmission lines. Matched impedance techniques should be  
used to maximize operating frequency and minimize signal  
distortion. Figures 5A and 5B show two different layouts which are  
recommended only as guidelines. Other suitable clock layouts  
may exist and it would be recommended that the board designers  
simulate to guarantee compatibility across all printed circuit and  
clock component process variations.  
The differential outputs are low impedance follower outputs that  
generate ECL/LVPECL compatible outputs. Therefore, terminating  
resistors (DC current path to ground) or current sources must be  
used for functionality. These outputs are designed to drive 50  
3.3V  
R3  
R4  
125  
125  
3.3V  
3.3V  
Zo = 50  
+
_
Input  
Zo = 50  
R1  
84  
R2  
84  
Figure 5A. 3.3V LVPECL Output Termination  
Figure 5B. 3.3V LVPECL Output Termination  
©2016 Integrated Device Technology, Inc  
12  
Revision A February 5, 2016  
8S58035I Data Sheet  
Termination for 2.5V LVPECL Outputs  
Figure 6A and Figure 6B show examples of termination for 2.5V  
LVPECL driver. These terminations are equivalent to terminating  
50to VCC – 2V. For VCC = 2.5V, the VCC – 2V is very close to  
ground level. The R3 in Figure 6B can be eliminated and the  
termination is shown in Figure 6C.  
2.5V  
VCC = 2.5V  
2.5V  
2.5V  
VCC = 2.5V  
50Ω  
R1  
R3  
250Ω  
250Ω  
+
–
50Ω  
50Ω  
+
–
50Ω  
2.5V LVPECL Driver  
R1  
R2  
50Ω  
50Ω  
2.5V LVPECL Driver  
R2  
R4  
62.5Ω  
62.5Ω  
R3  
18Ω  
Figure 6A. 2.5V LVPECL Driver Termination Example  
Figure 6B. 2.5V LVPECL Driver Termination Example  
2.5V  
VCC = 2.5V  
50Ω  
+
50Ω  
–
2.5V LVPECL Driver  
R1  
R2  
50Ω  
50Ω  
Figure 6C. 2.5V LVPECL Driver Termination Example  
©2016 Integrated Device Technology, Inc  
13  
Revision A February 5, 2016  
8S58035I Data Sheet  
VFQFN EPAD Thermal Release Path  
In order to maximize both the removal of heat from the package  
and the electrical performance, a land pattern must be  
dissipation as well as electrical conductivity requirements. Thus,  
thermal and electrical analysis and/or testing are recommended to  
determine the minimum number needed. Maximum thermal and  
electrical performance is achieved when an array of vias is  
incorporated in the land pattern. It is recommended to use as  
many vias connected to ground as possible. It is also  
recommended that the via diameter should be 12 to 13mils (0.30  
to 0.33mm) with 1oz copper via barrel plating. This is desirable to  
avoid any solder wicking inside the via during the soldering  
process which may result in voids in solder between the exposed  
pad/slug and the thermal land. Precautions should be taken to  
eliminate any solder voids between the exposed heat slug and the  
land pattern. Note: These recommendations are to be used as a  
guideline only. For further information, please refer to the  
Application Note on the Surface Mount Assembly of Amkor’s  
Thermally/ Electrically Enhance Leadframe Base Package, Amkor  
Technology.  
incorporated on the Printed Circuit Board (PCB) within the  
footprint of the package corresponding to the exposed metal pad  
or exposed heat slug on the package, as shown in Figure 7. The  
solderable area on the PCB, as defined by the solder mask,  
should be at least the same size/shape as the exposed pad/slug  
area on the package to maximize the thermal/electrical  
performance. Sufficient clearance should be designed on the PCB  
between the outer edges of the land pattern and the inner edges  
of pad pattern for the leads to avoid any shorts.  
While the land pattern on the PCB provides a means of heat  
transfer and electrical grounding from the package to the board  
through a solder joint, thermal vias are necessary to effectively  
conduct from the surface of the PCB to the ground plane(s). The  
land pattern must be connected to ground through these vias. The  
vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are  
application specific and dependent upon the package power  
SOLDER  
PIN  
SOLDER  
EXPOSED HEAT SLUG  
PIN  
PIN PAD  
GROUND PLANE  
LAND PATTERN  
(GROUND PAD)  
PIN PAD  
THERMAL VIA  
Figure 7. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)  
©2016 Integrated Device Technology, Inc  
14  
Revision A February 5, 2016  
8S58035I Data Sheet  
Power Considerations  
This section provides information on power dissipation and junction temperature for the 8S58035I.  
Equations and example calculations are also provided.  
1. Power Dissipation.  
The total power dissipation for the 8S58035I is the sum of the core power plus the output power dissipated due to loading.  
The following is the power dissipation for VCC = 3.6V, which gives worst case results.  
NOTE: Please refer to Section 3 for details on calculating output power dissipated due to loading.  
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.6V * 90mA = 324mW  
Power (outputs)MAX = 32.35mW/Loaded Output pair  
If all outputs are loaded, the total power is 6 * 32.35mW = 194.1mW  
•
Power Dissipation for internal termination RT  
Power (RT)MAX = 2 * [(VIN_MAX)2 / (2 * RT_MIN)] = 2 * [(1.4V)2 / (2 * 40)] = 49mW  
Total Power_MAX (3.6V, with all outputs switching) = 324mW + 194.1mW + 49mW= 567.1mW  
2. Junction Temperature.  
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device.  
The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that  
the bond wire and bond pad temperature remains below 125°C.  
The equation for Tj is as follows: Tj = JA * Pd_total + TA  
Tj = Junction Temperature  
JA = Junction-to-Ambient Thermal Resistance  
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)  
TA = Ambient Temperature  
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow  
and a multi-layer board, the appropriate value is 42.7°C/W per Table 6 below.  
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:  
85°C + 0.567W * 42.7°C/W = 109°C. This is well below the limit of 125°C.  
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type  
of board.  
Table 6. Thermal Resistance JA for 32 Lead VFQFN, Forced Convection  
JA vs. Air Flow  
Meters per Second  
0
1
2.5  
Multi-Layer PCB, JEDEC Standard Test Boards  
42.7°C/W  
37.3°C/W  
33.5°C/W  
©2016 Integrated Device Technology, Inc  
15  
Revision A February 5, 2016  
8S58035I Data Sheet  
3. Calculations and Equations.  
The purpose of this section is to calculate the power dissipation for the LVPECL output pairs.  
LVPECL output driver circuit and termination are shown in Figure 7.  
VCC  
Q1  
VOUT  
RL  
VCC - 2V  
Figure 7. LVPECL Driver Circuit and Termination  
To calculate power dissipation per output pair due to loading, use the following equations which assume a 50load, and a termination  
voltage  
of VCC – 2V.  
•
•
For logic high, VOUT = VOH_MAX = VCC_MAX – 0.85V  
(VCC_MAX – VOH_MAX) = 0.85V  
For logic low, VOUT = VOL_MAX = VCC_MAX – 1.6V  
(VCC_MAX – VOL_MAX) = 1.6V  
Pd_H is the power dissipation when the output drives high.  
Pd_L is the power dissipation when the output drives low.  
Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) =  
[(2V – 0.85V)/50] * 0.85V = 19.55mW  
Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX) =  
[(2V – 1.6V)/50] * 1.6V = 12.8mW  
Total Power Dissipation per output pair = Pd_H + Pd_L = 32.35mW  
©2016 Integrated Device Technology, Inc  
16  
Revision A February 5, 2016  
8S58035I Data Sheet  
Reliability Information  
Table 7. JA vs. Air Flow Table for a 32 Lead VFQFN  
JA vs. Air Flow  
Meters per Second  
0
1
2.5  
Multi-Layer PCB, JEDEC Standard Test Boards  
42.7°C/W  
37.3°C/W  
33.5°C/W  
Transistor Count  
The transistor count for 8S58035I: 348  
©2016 Integrated Device Technology, Inc  
17  
Revision A February 5, 2016  
8S58035I Data Sheet  
32 Lead VFQFN Package Outline and Package Dimensions  
Package Outline - K Suffix for 32 Lead VFQFN  
(Ref.)  
N & N  
Even  
Seating Plane  
(N -1)x e  
(Ref.)  
A1  
IndexArea  
L
A3  
E2  
e
2
N
N
(Ty p.)  
If N & N  
are Even  
Anvil  
1
Singulation  
2
(N -1)x e  
(Re f.)  
E2  
2
TopView  
D
b
e
Thermal  
Base  
A
(Ref.)  
D2  
2
N & N  
Odd  
0. 08  
C
Chamfer 4x  
0.6 x 0.6 max  
OPTIONAL  
D2  
C
Bottom View w/Type A ID  
Bottom View w/Type C ID  
2
1
2
1
CHAMFER  
RADIUS  
N N-1  
N N-1  
4
4
There are 2 methods of indicating pin 1 corner at the back of the VFQFN package:  
1. Type A: Chamfer on the paddle (near pin 1)  
2. Type C: Mouse bite on the paddle (near pin 1)  
NOTE: This package mechanical drawing is a generic drawing that  
applies to any pin count VFQFN package. This drawing is not  
intended to convey the actual pin count or pin layout of this device.  
The pin count and pinout are shown on the front page. The  
package dimensions are in Table 8.  
Table 8. Package Dimensions  
JEDEC Variation: VHHD-2/-4  
All Dimensions in Millimeters  
Symbol  
Minimum  
Nominal  
Maximum  
N
32  
A
0.80  
0
1.00  
0.05  
A1  
A3  
0.25 Ref.  
0.25  
b
ND & NE  
D & E  
D2 & E2  
e
0.18  
0.30  
8
5.00 Basic  
3.0  
3.3  
0.50 Basic  
0.40  
L
0.30  
0.50  
Reference Document: JEDEC Publication 95, MO-220  
©2016 Integrated Device Technology, Inc  
18  
Revision A February 5, 2016  
8S58035I Data Sheet  
Ordering Information  
Table 9. Ordering Information  
Part/Order Number  
8S58035AKILF  
8S58035AKILFT  
Marking  
ICS58035AIL  
ICS58035AIL  
Package  
“Lead-Free” 32 Lead VFQFN  
“Lead-Free” 32 Lead VFQFN  
Shipping Packaging  
Tray  
Temperature  
-40C to 85C  
-40C to 85C  
Tape & Reel  
©2016 Integrated Device Technology, Inc  
19  
Revision A February 5, 2016  
8S58035I Data Sheet  
Revision History  
Revision Date  
Description of Change  
▪ Removed ICS from the part number where needed.  
▪ Updated header and footer.  
February 5, 2016  
©2016 Integrated Device Technology, Inc  
20  
Revision A February 5, 2016  
8S58035I Data Sheet  
Corporate Headquarters  
6024 Silver Creek Valley Road  
San Jose, CA 95138 USA  
www.IDT.com  
Sales  
Tech Support  
www.idt.com/go/support  
1-800-345-7015 or 408-284-8200  
Fax: 408-284-2775  
www.IDT.com/go/sales  
DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications  
and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein  
is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability,  
or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.  
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably  
expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.  
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of  
IDT or their respective third party owners.  
For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary.  
Copyright ©2016 Integrated Device Technology, Inc. All rights reserved.  
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