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8T349316NLGI

型号：

8T349316NLGI

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

19 页

PDF大小：

359 K

下载PDF手册
2.5V LVDS 1:16 Clock Fanout Buffer  
8T349316  
DATASHEET  
General Description  
Features  
The 8T349316 is a 2.5V differential clock buffer with sixteen LVDS  
outputs. The fanout from a differential input to the sixteen LVDS  
outputs reduces loading on the preceding driver and provides an  
efficient clock distribution network. The 8T349316 can act as a  
translator from a differential HSTL, LVPECL, CML or LVDS input to  
LVDS output signals. A single-ended 3.3V, 2.5V LVCMOS/LVTTL  
input can also be used to translate to LVDS outputs. The redundant  
input capability allows for an asynchronous change-over from a  
primary clock source to a secondary clock source. Selectable  
reference inputs are controlled by SEL. The 8T349316 outputs can  
be asynchronously enabled/disabled. When disabled, the outputs  
will drive to the value selected by the GL pin. Multiple power and  
grounds reduce noise.The extended temperature range supports  
wireless infrastructure, telecommunication and networking end  
equipment requirements. The device is a member of the  
• Clock signal selection and fanout to 16 LVDS outputs  
• Guaranteed Low Skew < 50ps (max)  
• Low output pulse skew < 125ps (max)  
• Propagation delay < 1.75ns (max)  
• Up to 1GHz clock signal operation  
• Support the following input types: HSTL, LVPECL, HCSL, LVTTL  
• Selectable differential input  
• Power-down mode  
• Full 2.5V power supply  
• -40°C to +85°C ambient operating temperature  
• Lead-free (RoHS 6) 52-lead VFQFN-P packaging  
• Replacement device for the 5T9316  
high-performance clock family from IDT.  
Block Diagram  
A1  
Pin Assignment  
Q1  
OUT  
CTRL  
1
nA1  
nQ1  
Q2  
OUT  
CTRL  
A2  
0
52 51 50 49 48 47 46 45 44 43 42 41 40  
nQ2  
Q3  
nA2  
1
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
nG1  
VDD  
Q1  
nG2  
VDD  
OUT  
CTRL  
nQ3  
Q4  
SEL  
GL  
2
OUT  
CTRL  
3
Q12  
nQ12  
Q11  
nQ11  
Q10  
nQ10  
Q9  
nQ4  
Q5  
OUT  
CTRL  
4
nQ1  
Q2  
nQ5  
Q6  
5
OUT  
CTRL  
nQ6  
Q7  
6
nQ2  
Q3  
OUT  
CTRL  
7
8T349316  
nQ7  
Q8  
8
OUT  
CTRL  
nQ3  
Q4  
nQ8  
nG1  
nG2  
9
Q9  
10  
11  
12  
13  
nQ4  
VDD  
A1  
nQ9  
VDD  
OUT  
CTRL  
nQ9  
Q10  
OUT  
CTRL  
A2  
nQ10  
Q11  
OUT  
CTRL  
nA1  
nA2  
nQ11  
Q12  
14 15 16 17 17 19 20 21 22 23 24 25 26  
OUT  
CTRL  
nQ12  
Q13  
OUT  
CTRL  
nQ14  
Q15  
52-lead VFQFN-P, EPad  
8mm x 8mm x 0.9mm Package body  
NL package  
OUT  
CTRL  
POWER DOWN  
CTRL  
nQ15  
Q16  
nPD  
OUT  
CTRL  
nQ16  
Top View  
8T349316 REVISION 2 11/2/14  
1
©2014 Integrated Device Technology, Inc.  
8T349316 DATASHEET  
Pin Description and Pin Characteristic Tables  
Table 1: Pin Descriptions  
Number  
Name  
Type  
Description  
Output enable control input for the Q[1:8] differential outputs.  
See Table 3C. LVCMOS/LVTTL interface levels.  
1
Input  
-
nG1  
2
3
Power  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Power  
Input  
Positive power supply voltage.  
VDD  
Q1  
Differential clock output Q1. LVDS interface signals.  
Differential clock output Q1. LVDS interface signals.  
Differential clock output Q2. LVDS interface signals.  
Differential clock output Q2. LVDS interface signals.  
Differential clock output Q3. LVDS interface signals.  
Differential clock output Q3. LVDS interface signals.  
Differential clock output Q4. LVDS interface signals.  
Differential clock output Q4. LVDS interface signals.  
Positive power supply voltage.  
4
nQ1  
Q2  
5
6
nQ2  
Q3  
7
8
nQ3  
Q4  
9
10  
11  
12  
13  
nQ4  
VDD  
A1  
-
-
Differential clock signal input 1.  
Input  
Differential clock signal input 1.  
nA1  
Control input for the output level for outputs in disable state.   
See Table 3C and Table 3D. LVCMOS/LVTTL interface levels.  
14  
Input  
-
GL  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
Power  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Power  
Power  
-
Positive power supply voltage.  
VDD  
Q5  
Differential clock output Q5. LVDS interface signals.  
Differential clock output Q5. LVDS interface signals.  
Differential clock output Q6. LVDS interface signals.  
Differential clock output Q6. LVDS interface signals.  
Differential clock output Q7. LVDS interface signals.  
Differential clock output Q7. LVDS interface signals.  
Differential clock output Q8. LVDS interface signals.  
Differential clock output Q8. LVDS interface signals.  
Positive power supply voltage.  
nQ5  
Q6  
nQ6  
Q7  
nQ7  
Q8  
nQ8  
VDD  
GND  
nc  
Power Supply Ground.  
-
-
-
Not connected. It is recommended to connect this pin to board GND (0V).  
Differential clock signal input 2.  
Input  
nA2  
A2  
Input  
Differential clock signal input 2.  
Power  
Output  
Output  
Output  
Output  
Output  
Positive power supply voltage.  
VDD  
nQ9  
Q9  
Differential clock output Q9. LVDS interface signals.  
Differential clock output Q9. LVDS interface signals.  
Differential clock output Q10. LVDS interface signals.  
Differential clock output Q10. LVDS interface signals.  
Differential clock output Q11. LVDS interface signals.  
nQ10  
Q10  
nQ11  
2.5V LVDS 1:16 CLOCK FANOUT BUFFER  
2
REVISION 2 11/2/14  
8T349316 DATASHEET  
Table 1: Pin Descriptions  
Number  
35  
Name  
Q11  
Type  
Description  
Output  
Output  
Output  
Power  
Differential clock output Q11. LVDS interface signals.  
Differential clock output Q12. LVDS interface signals.  
Differential clock output Q12. LVDS interface signals.  
Positive power supply voltage.  
36  
nQ12  
Q12  
37  
38  
VDD  
Output enable control input for the Q[9:16] differential outputs.   
See Table 3D. LVCMOS/LVTTL interface levels.  
39  
40  
41  
Input  
-
-
-
-
nG2  
nc  
Not connected. It is recommended to connect this pin to board GND (0V).  
Device power-down control input.   
See Table 3B. LVCMOS/LVTTL interface levels.  
Input  
nPD  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
Power  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Power  
Positive power supply voltage.  
VDD  
nQ13  
Q13  
Differential clock output Q13. LVDS interface signals.  
Differential clock output Q13. LVDS interface signals.  
Differential clock output Q14. LVDS interface signals.  
Differential clock output Q14. LVDS interface signals.  
Differential clock output Q15. LVDS interface signals.  
Differential clock output Q15. LVDS interface signals.  
Differential clock output Q16. LVDS interface signals.  
Differential clock output Q16. LVDS interface signals.  
Positive power supply voltage.  
nQ14  
Q14  
nQ15  
Q15  
nQ16  
Q16  
VDD  
Reference input signal select control pin.   
See Table 3A. LVCMOS/LVTTL interface levels.  
52  
—
Input  
SEL  
Power  
Exposed package ground supply voltage (GND). Connect to board GND.  
GND  
Table 2. Pin Characteristics  
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
CIN  
Input Capacitance  
GL, nG1, nG2, nPD, SEL  
3
pF  
REVISION 2 11/2/14  
3
2.5V LVDS 1:16 CLOCK FANOUT BUFFER  
8T349316 DATASHEET  
Logic Truth Tables  
1
Table 3A: Input Signal Source Select  
SEL  
0
Input Selection  
A2  
A1  
1
1. Asynchronous control.  
Table 3B. Device Power-down control  
1
nPD  
Power-down Operation  
Power-down mode of the entire device. Input and outputs disable and the output  
voltage is VDD (for each Q1, nQ1 to Q16, nQ16 pair)2  
0
1
Normal 0peration  
1. Asynchronous control.  
2. Disable outputs by setting nG1 = nG2 = 1 before entering power-down mode and while in  
power-down mode. To enter normal device operation, first enable the outputs by setting   
nG1 = nG2 = 0 before setting nPD = 1.  
1
Table 3C. Output Q[1:8] Enable Control  
GL  
X
nG1  
Q1 to Q8 Output State  
0
1
1
Enabled (active)  
0
Disabled, output state is logic low (Q[1:8] = L, nQ[1:8] = H)  
Disabled, output state is logic high (Q[1:8] = H, nQ[1:8] = L)  
1
1. Asynchronous controls.  
Table 3D. Output Q[9:16] Enable Control  
1
GL  
X
nG2  
Q9 to Q16 Output State  
0
1
1
Enabled (active)  
0
Disabled, output state is logic low (Q[9:16] = L, nQ[9:16] = H)  
Disabled, output state is logic high (Q[9:16] = H, nQ[9:16] = L)  
1
1. Asynchronous controls.  
2.5V LVDS 1:16 CLOCK FANOUT BUFFER  
4
REVISION 2 11/2/14  
8T349316 DATASHEET  
Absolute Maximum Ratings  
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress  
specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the DC Characteristics or  
AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.  
Table 4. Absolute Maximum Ratings  
Item  
Rating  
Supply Voltage, VDD  
Input Voltage  
Output Voltage  
-0.5V to 3.6V  
-0.5V to 3.6V  
-0.5V to VDD + 0.5V and <3.6V  
Outputs, IO (LVDS)  
Continuous Current  
Surge Current  
10mA  
15mA  
Storage Temperature  
-65°C to 150°C  
Thermal Junction Temperature, TJ  
125C  
Table 5. Recommended Operating Range  
Item  
Minimum  
2.3  
Typical  
Maximum  
2.7  
Units  
V
Supply Voltage, VDD  
Ambient Temperature  
2.5  
-40  
+85  
°C  
REVISION 2 11/2/14  
5
2.5V LVDS 1:16 CLOCK FANOUT BUFFER  
8T349316 DATASHEET  
DC Electrical Characteristics  
Table 6A. Power Supply DC Characteristics, V = 2.5V 10%, T = -40°C to +85°C  
DD A  
Symbol Parameter  
VDD Core Supply Voltage  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
2.3  
2.5  
2.7  
V
Core and Output   
Power Supply Current  
IDD  
VDD = 2.7V, fREF = 1GHz  
360  
350  
5
mA  
mA  
mA  
Core and Output   
Power Supply Current  
VDD = Maximum, A1, nA1 and A2, nA2 at  
Logic Low Level, Q[1:16] outputs Enabled  
IDDQ  
Power-down Core and Output  
Power Supply Current  
IDD, PD  
nPD = 0  
Table 6B. LVCMOS/LVTTL DC Characteristics, V = 2.5V 10%, T = -40°C to +85°C  
DD A  
Symbol Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
Input  
IIH  
nPD, nG1, nG2, GL  
nPD, nG1, nG2, GL  
nPD, nG1, nG2, GL  
VDD = 2.7V  
VDD = 2.7V  
150  
µA  
High Voltage  
Input   
IIL  
-10  
µA  
Low Voltage  
DC Input  
High  
VIH  
1.7  
3.6  
0.7  
V
V
VIL  
DC Input Low nPD, nG1, nG2, GL  
-0.3  
1
Table 6C. Differential Input DC Characteristics, V = 2.5V 10%, T = -40°C to +85°C  
DD A  
Symbol Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
Input  
IIH  
A1, nA1, A2, nA2  
A1, nA1, A2, nA2  
V
DD = 2.7V  
DD = 2.7V  
150  
µA  
High Voltage  
Input  
IIL  
V
-10  
µA  
Low Voltage  
VPP  
Peak-to-Peak Voltage1  
0.15  
0.5  
3.6  
V
V
VCMR  
Common Mode Input Voltage1, 2  
VDD  
1. VIL should not be less than -0.3V.  
2. Common mode input voltage is defined at the crosspoint.  
Table 6D. LVDS DC Characteristics, V = 2.5V 10%, T = -40°C to +85°C  
DD A  
Symbol Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
454  
Units  
mV  
mV  
V
VOD  
Differential Output Voltage  
247  
VOD  
VOS  
VOD Magnitude Change  
Offset Voltage  
50  
1.125  
1.2  
1.375  
50  
VOS  
IOS  
VOS Magnitude Change  
Outputs Short Circuit Current  
mV  
mA  
QX and nQX = 0V  
QX = nQX  
12  
6
24  
Differential Outputs   
Short Circuit Current  
IOSD  
12  
mA  
2.5V LVDS 1:16 CLOCK FANOUT BUFFER  
6
REVISION 2 11/2/14  
8T349316 DATASHEET  
AC Electrical Characteristics  
1
Table 7. AC Characteristics, V = 2.5V 10%, T = -40°C to +85°C  
DD A  
Symbol Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
Output  
fOUT  
Q[1:16]  
1
GHz  
Frequency  
LH and HL  
A1, A2 to Q[1:16]  
1.4  
1.75  
3.5  
ns  
ns  
ns  
µs  
Output Enable  
Output Disable  
Powered-down  
nG1, nG2 to Q[1:16]  
nG1, nG2 to Q[1:16]  
nPD to Q, nQ = VDD  
Propagation  
Delay  
3.5  
tPD  
100  
nPD to Q, nQ = Logic Level  
defined by the Selected Input  
Powered-down  
100  
50  
µs  
ps  
ps  
tsk(o)  
tsk(p)  
Output Skew2 3 Q[1:16]  
12  
20  
Output Pulse  
Skew  
Q[1:16]  
Q[1:16]  
125  
Part-to-Part  
Skew4  
tsk(pp)  
300  
ps  
1. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is  
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal  
equilibrium has been reached under these conditions.  
2. This parameter is defined in accordance with JEDEC standard 65.  
3. Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross point.  
4. Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and with  
equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross point.  
REVISION 2 11/2/14  
7
2.5V LVDS 1:16 CLOCK FANOUT BUFFER  
8T349316 DATASHEET  
Parameter Measurement Information  
V
DD  
V
nA1, nA2  
A1, A2  
GND  
DD  
2.5V 10%  
POWER SUPPLY  
V
Cross Points  
+
Float GND –  
PP  
V
CMR  
2.5V LVDS Output Load Test Circuit  
Differential Input Level  
nQx  
Qx  
nA1, nA2  
A1, A2  
nQ{1:16]  
nQy  
Qy  
Q{1:16]  
tPD  
Propagation Delay  
Output Skew  
nA1, nA2  
A1, A2  
Part 1  
nQx  
Qx  
nQy  
Qy  
Part 2  
nQx  
tPLH  
tPHL  
Qx  
tsk(pp)  
tsk(p)= |tPHL - tPLH  
|
Part-to-Part Skew  
Pulse Skew  
V
DD  
out  
out  
DC Input  
LVDS  
Offset Voltage Setup  
Differential Output Voltage Setup  
2.5V LVDS 1:16 CLOCK FANOUT BUFFER  
8
REVISION 2 11/2/14  
8T349316 DATASHEET  
Applications Information  
Recommendations for Unused Input and Output Pins  
Inputs:  
Outputs:  
Ax/nAx Clock Inputs  
LVDS Outputs  
For applications not requiring the use of the differential input, Ax  
should be pulled up with a 10kresistor and nAx pulled down with a  
10kresistor.  
All unused LVDS output pairs can be either left floating or terminated  
with 100across. If they are left floating, there should be no trace  
attached.  
LVCMOS Control Pins  
All control pins have internal pullup or pulldown resistors; additional  
resistance is not required but can be added for additional protection.  
A 1kresistor can be used.  
REVISION 2 11/2/14  
9
2.5V LVDS 1:16 CLOCK FANOUT BUFFER  
8T349316 DATASHEET  
Wiring the Differential Input to Accept Single-Ended Levels  
Figure 1 shows how a differential input can be wired to accept single  
ended levels. The reference voltage V1= VDD/2 is generated by the  
bias resistors R1 and R2. The bypass capacitor (C1) is used to help  
filter noise on the DC bias. This bias circuit should be located as close  
to the input pin as possible. The ratio of R1 and R2 might need to be  
adjusted to position the V1in the center of the input voltage swing. For  
example, if the input clock swing is 2.5V and VDD = 3.3V, R1 and R2  
value should be adjusted to set V1 at 1.25V. The values below are for  
when both the single ended swing and VDD are at the same voltage.  
This configuration requires that the sum of the output impedance of  
the driver (Ro) and the series resistance (Rs) equals the transmission  
line impedance. In addition, matched termination at the input will  
attenuate the signal in half. This can be done in one of two ways.  
First, R3 and R4 in parallel should equal the transmission line  
impedance. For most 50applications, R3 and R4 can be 100. The  
values of the resistors can be increased to reduce the loading for  
slower and weaker LVCMOS driver. When using single-ended  
signaling, the noise rejection benefits of differential signaling are  
reduced. Even though the differential input can handle full rail  
LVCMOS signaling, it is recommended that the amplitude be  
reduced. The datasheet specifies a lower differential amplitude,  
however this only applies to differential signals. For single-ended  
applications, the swing can be larger, however VIL cannot be less  
than -0.3V and VIH cannot be more than VDD + 0.3V. Though some  
of the recommended components might not be used, the pads  
should be placed in the layout. They can be utilized for debugging  
purposes. The datasheet specifications are characterized and  
guaranteed by using a differential signal.  
Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels.  
2.5V LVDS 1:16 CLOCK FANOUT BUFFER  
10  
REVISION 2 11/2/14  
 
8T349316 DATASHEET  
LVDS Driver Termination  
For a general LVDS interface, the recommended value for the  
termination impedance (ZT) is between 90and 132. The actual  
value should be selected to match the differential impedance (Z0) of  
your transmission line. A typical point-to-point LVDS design uses a  
100parallel resistor at the receiver and a 100differential  
transmission-line environment. In order to avoid any  
with either type of output structure. Figure 2B, which can also be  
used with both output types, is an optional termination with center tap  
capacitance to help filter common mode noise. The capacitor value  
should be approximately 50pF. If using a non-standard termination, it  
is recommended to contact IDT and confirm if the output structure is  
current source or voltage source type. In addition, since these  
outputs are LVDS compatible, the input receiver’s amplitude and  
common-mode input range should be verified for compatibility with  
the output.  
transmission-line reflection issues, the components should be  
surface mounted and must be placed as close to the receiver as  
possible. IDT offers a full line of LVDS compliant devices with two  
types of output structures: current source and voltage source. The  
standard termination schematic as shown in Figure 2A can be used  
ZO ZT  
LVDS  
Driver  
LVDS  
ZT  
Receiver  
Figure 2A. Standard LVDS Termination  
ZT  
2
ZO ZT  
LVDS  
Driver  
LVDS  
Receiver  
C
ZT  
2
Figure 2B. Optional LVDS Termination  
REVISION 2 11/2/14  
11  
2.5V LVDS 1:16 CLOCK FANOUT BUFFER  
 
 
8T349316 DATASHEET  
VFQFN EPAD Thermal Release Path  
In order to maximize both the removal of heat from the package and  
the electrical performance, a land pattern must be incorporated on  
the Printed Circuit Board (PCB) within the footprint of the package  
corresponding to the exposed metal pad or exposed heat slug on the  
package, as shown in Figure 3. The solderable area on the PCB, as  
defined by the solder mask, should be at least the same size/shape  
as the exposed pad/slug area on the package to maximize the  
thermal/electrical performance. Sufficient clearance should be  
designed on the PCB between the outer edges of the land pattern  
and the inner edges of pad pattern for the leads to avoid any shorts.  
and dependent upon the package power dissipation as well as  
electrical conductivity requirements. Thus, thermal and electrical  
analysis and/or testing are recommended to determine the minimum  
number needed. Maximum thermal and electrical performance is  
achieved when an array of vias is incorporated in the land pattern. It  
is recommended to use as many vias connected to ground as  
possible. It is also recommended that the via diameter should be 12  
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is  
desirable to avoid any solder wicking inside the via during the  
soldering process which may result in voids in solder between the  
exposed pad/slug and the thermal land. Precautions should be taken  
to eliminate any solder voids between the exposed heat slug and the  
land pattern. Note: These recommendations are to be used as a  
guideline only. For further information, please refer to the Application  
Note on the Surface Mount Assembly of Amkor’s Thermally/  
Electrically Enhance Leadframe Base Package, Amkor Technology.  
While the land pattern on the PCB provides a means of heat transfer  
and electrical grounding from the package to the board through a  
solder joint, thermal vias are necessary to effectively conduct from  
the surface of the PCB to the ground plane(s). The land pattern must  
be connected to ground through these vias. The vias act as “heat  
pipes”. The number of vias (i.e. “heat pipes”) are application specific  
SOLDER  
SOLDER  
PIN  
PIN  
EXPOSED HEAT SLUG  
PIN PAD  
GROUND PLANE  
LAND PATTERN  
(GROUND PAD)  
PIN PAD  
THERMAL VIA  
Figure 3. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale).  
2.5V LVDS 1:16 CLOCK FANOUT BUFFER  
12  
REVISION 2 11/2/14  
 
8T349316 DATASHEET  
Power Considerations  
This section provides information on power dissipation and junction temperature for the 8T349316. Equations and example calculations are  
also provided.  
1. Power Dissipation.  
The total power dissipation for the 8T349316 is the sum of the core power plus the output power dissipation due to the load. The following is  
the power dissipation for VDD = 2.5V + 10% = 2.700V, which gives worst case results.  
The maximum current at 85°C is as follows:  
IDD_MAX = 360mA  
•
Power (core)MAX = VDD_MAX * IDD_MAX = 2.7V * 360mA = 972mW  
Total Power_MAX = 972mW  
2. Junction Temperature.  
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The  
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond  
wire and bond pad temperature remains below 125°C.  
The equation for Tj is as follows: Tj = JA * Pd_total + TA  
Tj = Junction Temperature  
JA = Junction-to-Ambient Thermal Resistance  
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)  
TA = Ambient Temperature  
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and  
a multi-layer board, the appropriate value is 33°C/W per Table 6 below.  
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:  
85°C + 0.972W * 33°C/W = 117.1°C. This is below the limit of 125°C.  
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of  
board (multi-layer).  
Table 6. Thermal Resistance JA for 52-Lead VFQFN, Forced Convection  
JA at 0 Air Flow  
Meters per Second  
0
1
2
Multi-Layer PCB, JEDEC Standard Test Boards  
33.0°C/W  
29.76°C/W  
28.27°C/W  
REVISION 2 11/2/14  
13  
2.5V LVDS 1:16 CLOCK FANOUT BUFFER  
8T349316 DATASHEET  
Reliability Information  
Table 8. JA vs. Air Flow Table for a 52-lead VFQFN Package  
JA vs. Air Flow  
Meters per Second  
0
1
2
Multi-Layer PCB, JEDEC Standard Test Boards  
33.0°C/W  
29.76°C/W  
28.27°C/W  
Transistor Count  
The transistor count for 8T349316 is: 1821  
2.5V LVDS 1:16 CLOCK FANOUT BUFFER  
14  
REVISION 2 11/2/14  
8T349316 DATASHEET  
52-Lead VFQFN Package Outline  
REVISION 2 11/2/14  
15  
2.5V LVDS 1:16 CLOCK FANOUT BUFFER  
8T349316 DATASHEET  
52-Lead VFQFN Package Outline, (continued)  
2.5V LVDS 1:16 CLOCK FANOUT BUFFER  
16  
REVISION 2 11/2/14  
8T349316 DATASHEET  
52-Lead VFQFN Package Outline, (continued)  
REVISION 2 11/2/14  
17  
2.5V LVDS 1:16 CLOCK FANOUT BUFFER  
8T349316 DATASHEET  
Ordering Information  
Table 9. Ordering Information  
Part/Order Number  
Marking  
Package  
Shipping Packaging  
Tray  
Temperature  
-40°C to +85°C  
-40°C to +85°C  
8T349316NLGI  
8T349316NLGI8  
IDT8T349316NLGI  
IDT8T349316NLGI  
“Lead-free” 52-lead VFQFN-P  
“Lead-free” 52-lead VFQFN-P  
Tape & Reel  
2.5V LVDS 1:16 CLOCK FANOUT BUFFER  
18  
REVISION 2 11/2/14  
Corporate Headquarters  
6024 Silver Creek Valley Road  
San Jose, CA 95138 USA  
Sales  
Tech Support  
email: clocks@idt.com  
1-800-345-7015 or 408-284-8200  
Fax: 408-284-2775  
www.IDT.com  
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in  
this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined  
in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether  
express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This  
document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.  
IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably  
expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.  
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or  
other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications, such as  
those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any  
circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.  
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Product specification subject to change without notice. Other trademarks and service marks used herein, including protected  
names, logos and designs, are the property of IDT or their respective third party owners.  
Copyright ©2014 Integrated Device Technology, Inc.. All rights reserved.  
厂商 型号 描述 页数 下载

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