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8V54816A

型号：

8V54816A

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

27 页

PDF大小：

735 K

下载PDF手册
16-Port, Bi-directional M-LVDS Clock  
Cross-Point Sw itch  
8V54816A  
Datasheet  
General Description  
Features  
▪ Sixteen bi-directional M-LVDS ports  
The 8V54816A is a 16-port, bi-directional cross-point clock switch  
designed for clock distribution in MicroTCA.4 systems. It features 16  
bi-directional M-LVDS ports. Each port can be individually set as  
input or output. Each output port can be connected to any port  
defined as input. Each port features switchable termination (ON:  
100, OFF: High impedance). Output ports can drive up to 19-inch  
PCB tracks with M-LVDS levels. The device is optimized for very low  
additive phase noise. Configuration of the device is achieved by I2C.  
At startup, a default configuration is set where all ports are in  
High-Impedance mode with outputs disabled.  
▪ Operating frequency: up to 350MHz (maximum)  
▪ Switchable termination resistors  
▪ I2C support with read-back capabilities up to 400kHz  
▪ PCI Express (2.5Gb/S), Gen 2 (5Gb/s) and Gen 3 (8Gb/s) jitter  
compliant  
▪ Architecturally compliant with MicroTCA.4 specification  
▪ Output polarity inversion  
▪ Support for 1PPS signals  
▪ Full 3.3V supply voltage  
▪ 12mm x 12mm, 100-lead VFQFN  
▪ E-Pad size: 6.9mm x 6.9mm  
▪ 0°C to +70°C ambient operating temperature  
▪ Lead-free (RoHS 6) packaging  
©2015 Integrated Device Technology, Inc.  
1
December 18, 2015  
8V54816A Datasheet  
Block Diagram  
Figure 1: Block Diagram  
Termination  
Enable  
RT  
16:1  
Mux  
CLK0  
nCLK0  
I/O Port  
Select 0  
Termination  
Enable  
RT  
16:1  
Mux  
CLK1  
nCLK1  
I/O Port  
Select 1  
Termination  
Enable  
RT  
16:1  
Mux  
CLK15  
nCLK15  
VDD VDD  
VDD  
I/O Port  
Select 15  
I/O Port  
Select  
SDATA  
SCLK  
S_A1  
S_A0  
nMR  
Termination  
Enable  
I2C Controller  
GNDGND  
©2015 Integrated Device Technology, Inc  
2
December 18, 2015  
8V54816A Datasheet  
Pin Assignment  
Figure 2: Pin Assignment for 12mm x 12mm, 100-Pin VFQFN Package (Top View )  
VDD  
GND  
1
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
VDD  
2
VDD  
GND  
3
GND  
VDD  
4
GND_S  
VDDO_CLK0  
CLK0  
5
GNDO_CLK11  
nCLK11  
6
nCLK0  
7
CLK11  
GNDO_CLK0  
VDDO_CLK1  
CLK1  
8
VDDO_CLK11  
GNDO_CLK10  
nCLK10  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
nCLK1  
CLK10  
GNDO_CLK1  
nc  
VDDO_CLK10  
nc  
8V54816A  
VDDO_CLK2  
CLK2  
GNDO_CLK9  
nCLK9  
nCLK2  
CLK9  
GNDO_CLK2  
VDDO_CLK3  
CLK3  
VDDO_CLK9  
GNDO_CLK8  
nCLK8  
nCLK3  
CLK8  
GNDO_CLK3  
nMR  
VDDO_CLK8  
GND_DIGITAL  
VDD_DIGITAL  
S_A1  
VDD_DIGITAL  
GND  
SCLK  
S_A0  
©2015 Integrated Device Technology, Inc  
3
December 18, 2015  
8V54816A Datasheet  
Pin Descriptions & Characteristics  
Table 1: Pin Description Tablea  
Number  
Name  
VDD  
Type  
Description  
1, 4, 50, 74, 75, 76, 98, 100  
Power  
Power  
Power  
I/O  
Power supply pins.  
2, 3, 24, 48, 73, 77  
GND  
Power supply ground.  
5
6, 7  
8
VDDO_CLK0  
CLK0, nCLK0  
GNDO_CLK0  
VDDO_CLK1  
CLK1, nCLK1  
GNDO_CLK1  
Port 0 output power supply.  
Bi-directional clock port 0.  
Port 0 power supply ground.  
Port 1 output power supply.  
Bi-directional clock port 1.  
Port 1 power supply ground.  
Power  
Power  
I/O  
9
10, 11  
12  
Power  
13, 27, 38, 49,  
63, 79, 88, 97  
nc  
Unused  
Do not connect.  
14  
15, 16  
17  
VDDO_CLK2  
CLK2, nCLK2  
GNDO_CLK2  
VDDO_CLK3  
CLK3, nCLK3  
GNDO_CLK3  
nMR  
Power  
I/O  
Port 2 output power supply.  
Bi-directional clock port 2.  
Port 2 power supply ground.  
Port 3 output power supply.  
Bi-directional clock port 3.  
Port 3 power supply ground.  
Power  
Power  
I/O  
18  
19, 20  
21  
Power  
Input  
Power  
22  
Pullup  
Master reset. Active Low. LVCMOS/LVTTL interface levels.  
Digital power supply pins.  
23, 28, 53  
VDD_DIGITAL  
I2C compatible SCLK. This pin has an internal pullup resistor.  
LVCMOS/LVTTL interface levels.  
25  
26  
SCLK  
Input  
I/O  
Pullup  
Pullup  
I2C compatible SDATA. This pin has an internal pullup resistor.  
LVCMOS/LVTTL interface levels.  
SDATA  
29, 54  
GND_DIGITAL  
VDDO_CLK4  
CLK4, nCLK4  
GNDO_CLK4  
VDDO_CLK5  
CLK5, nCLK5  
GNDO_CLK5  
VDDO_CLK6  
CLK6, nCLK6  
GNDO_CLK6  
VDDO_CLK7  
CLK7, nCLK7  
GNDO_CLK7  
GND_S  
Power  
Power  
I/O  
Digital power supply ground.  
Port 4 output power supply.  
Bi-directional clock port 4.  
Port 4 power supply ground.  
Port 5 output power supply.  
Bi-directional clock port 5.  
Port 5 power supply ground.  
Port 6 output power supply.  
Bi-directional clock port 6.  
Port 6 power supply ground.  
Port 7 output power supply.  
Bi-directional clock port 7.  
Port 7 power supply ground.  
Power supply ground.  
30  
31, 32  
33  
Power  
Power  
I/O  
34  
35, 36  
37  
Power  
Power  
I/O  
39  
40, 41  
42  
Power  
Power  
I/O  
43  
44, 45  
46  
Power  
Power  
Input  
47, 72, 78, 99  
51  
S_A0  
Pulldown I2C address bit 0. LVCMOS/LVTTL interface levels.  
©2015 Integrated Device Technology, Inc  
4
December 18, 2015  
8V54816A Datasheet  
Table 1: Pin Description Tablea  
Number  
52  
Name  
Type  
Description  
S_A1  
Input  
Power  
I/O  
Pulldown I2C address bit 1. LVCMOS/LVTTL interface levels.  
Port 8 output power supply.  
55  
VDDO_CLK8  
CLK8, nCLK8  
GNDO_CLK8  
VDDO_CLK9  
CLK9, nCLK9  
GNDO_CLK9  
VDDO_CLK10  
56, 57  
58  
Bi-directional clock port 8.  
Power  
Power  
I/O  
Port 8 power supply ground.  
59  
Port 9 output power supply.  
60, 61  
62  
Bi-directional clock port 9.  
Power  
Power  
Port 9 power supply ground.  
64  
Port 10 output power supply.  
CLK10,  
nCLK10  
65, 66  
I/O  
Bi-directional clock port 10.  
67  
68  
GNDO_CLK10  
VDDO_CLK11  
Power  
Power  
Port 10 power supply ground.  
Port 11 output power supply.  
CLK11,  
nCLK11  
69, 70  
I/O  
Bi-directional clock port 11.  
71  
80  
GNDO_CLK11  
VDDO_CLK12  
Power  
Power  
Port 11 power supply ground.  
Port 12 output power supply.  
CLK12,  
nCLK12  
81, 82  
I/O  
Bi-directional clock port 12.  
83  
84  
GNDO_CLK12  
VDDO_CLK13  
Power  
Power  
Port 12 power supply ground.  
Port 13 output power supply.  
CLK13,  
nCLK13  
85, 86  
I/O  
Bi-directional clock port 13.  
87  
89  
GNDO_CLK13  
VDDO_CLK14  
Power  
Power  
Port 13 power supply ground.  
Port 14 output power supply.  
CLK14,  
nCLK14  
90, 91  
I/O  
Bi-directional clock port 14.  
92  
93  
GNDO_CLK14  
VDDO_CLK15  
Power  
Power  
Port 14 power supply ground.  
Port 15 output power supply.  
CLK15,  
nCLK15  
94, 95  
I/O  
Bi-directional clock port 15.  
Port 15 power supply ground.  
96  
GNDO_CLK15  
Power  
a.  
Pullup, Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.  
Table 2: Pin Characteristics Table  
Symbol  
CIN  
Parameter  
Test Conditions  
Minimum  
Typical  
4
Maximum  
Units  
pF  
Input Capacitance  
Input Pullup Resistor  
Input Pulldown Resistor  
Output Termination  
RPULLUP  
RPULLDOWN  
RT  
51  
k  
k  
51  
100  
©2015 Integrated Device Technology, Inc  
5
December 18, 2015  
 
8V54816A Datasheet  
Serial Interface Configuration Description  
The 8V54816A has an I2C-compatible configuration interface to access any of the internal registers (Table 3) for frequency and PLL parameter  
programming. The 8V54816A acts as a slave device on the I2C bus and has the address 0b10110xx, where xx is set by the values on the  
S_A0 & S_A1 pins (see Table 3 for details). Data bytes (registers) are accessed in sequential order from the lowest to the highest byte (most  
significant bit first). Read and write block transfers are not supported. It is recommended to terminate I2C read or write transfer after accessing  
byte #15.  
For full electrical I2C compliance, it is recommended to use external pull-up resistors for SDATA and SCLK. The internal pull-up resistors have  
a size of 51ktypical.  
Table 3: I2C Address  
1
0
1
1
0
S_A1  
S_A0  
R/W  
Table 4: I2C Register Map  
Binary Register  
Register  
Address  
0x00  
0x01  
0x02  
0x03  
0x04  
0x05  
0x06  
0x07  
0x08  
0x09  
0x0A  
0x0B  
0x0C  
0x0D  
0x0E  
0x0F  
Function  
0
1
Port 0 configuration  
Port 1 configuration  
Port 2 configuration  
Port 3 configuration  
Port 4 configuration  
Port 5 configuration  
Port 6 configuration  
Port 7 configuration  
Port 8 configuration  
Port 9 configuration  
Port 10 configuration  
Port 11 configuration  
Port 12 configuration  
Port 13 configuration  
Port 14 configuration  
Port 15 configuration  
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Table 5: Port Configuration Bit Allocation Table  
Bit  
Description  
Default  
Function  
0 = Port is input  
1 = Port is output  
7
Port I/O  
0
0 = Internal termination is off (high-impedance)  
1 = Internal termination is on (100)  
6
Termination On/Off  
0
0 = Inverted  
1 = Non-inverted  
5
4
Polarity  
0
0
Reserved  
Reserved  
If port is an output (Port I/O = 1):  
Bit[3:0] specifies the input port that is used as a signal source for this output  
[3:0]  
Output Port Signal Source [3:0]  
0000  
If port is an input (Port I/O = 0):  
Bit[3:0] has no meaning  
©2015 Integrated Device Technology, Inc  
6
December 18, 2015  
8V54816A Datasheet  
Absolute Maximum Ratings  
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress  
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC  
Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.  
Table 6: Absolute Maximum Ratings Table  
Item  
Rating  
Supply Voltage, VDD  
Inputs, VI  
3.63V  
-0.5V to VDD + 0.5V  
Outputs, IO  
Continuous Current  
Surge Current  
10mA  
15mA  
Junction Temperature, TJ  
Storage Temperature, TSTG  
125°C  
-65C to 150C  
DC Electrical Characteristics  
Table 7: Pow er Supply DC Characteristics, VDD = VDD_DIGITAL = VDDO_X = 3.3V ± 5%, TA = 0°C to 70°C  
a
Symbol  
Parameter  
Test Conditions  
Minimum  
3.135  
Typical  
3.3  
Maximum  
3.465  
3.465  
3.465  
295  
Units  
V
VDD  
Power Supply Voltage  
VDD_DIGITAL Digital Supply Voltage  
3.135  
3.3  
V
VDDO_X  
IDD  
Output Supply Voltage  
Power Supply Current  
Digital Supply Current  
3.135  
3.3  
V
258  
6
mA  
mA  
mA  
IDD_DIGITAL  
7
0 Ports Configured as Outputs  
63  
b
IDDO  
Total Output Supply Current  
15 Ports Configured as  
Outputs  
258  
13  
295  
mA  
mA  
Output Current Contribution, per  
output port  
b, c  
IDDO_inc  
a.  
b.  
c.  
VDDO_X denotes VDDO_[0:15].  
Output ports are terminated internally and externally with 100across CLK and nCLK.  
This is the increase in IDDO when the number of output ports is increased by one.  
a
Table 8: LVCMOS/LVTTL DC Characteristics, VDD = VDD_DIGITAL = VDDO_X = 3.3V ± 5%, TA = 0°C to 70°C  
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
Input  
High Voltage  
SDATA, SCLK,  
S_A0, S_A1, nMR  
VIH  
2.2  
VDD + 0.3  
V
Input  
Low Voltage  
SDATA, SCLK,  
S_A0, S_A1, nMR  
VIL  
-0.3  
0.8  
150  
5
V
S_A0, S_A1  
VDD = VIN = 3.465V  
VDD = VIN = 3.465V  
µA  
µA  
µA  
µA  
Input High  
Current  
IIH  
nMR, SCLK,  
SDATA  
S_A0, S_A1  
VDD = 3.465V, VIN = 0V  
VDD = 3.465V, VIN = 0V  
-5  
Input Low  
Current  
IIL  
nMR, SCLK,  
SDATA  
-150  
a.  
VDDO_X denotes VDDO_[0:15].  
©2015 Integrated Device Technology, Inc  
7
December 18, 2015  
 
8V54816A Datasheet  
a
Table 9: Differential Input DC Characteristics, VDD = VDD_DIGITAL = VDDO_X = 3.3V ± 5%, TA = 0°C to 70°C  
Symbol Parameter  
Test Conditions  
Minimum  
0.15  
Typical  
Maximum  
1.3  
Units  
VPP  
Peak-to-Peak Voltageb  
Common Mode Rangeb, c  
V
V
VCMR  
0.5  
VDD – 1  
a.  
b.  
c.  
VDDO_X denotes VDDO_[0:15].  
Common mode input is defined at the differential crosspoint.  
VIL must not be less than -0.3V. VIH must be less than VDD.  
a
Table 10: M-LVDS DC Characteristics, VDD = VDD_DIGITAL = VDDO_X = 3.3V ± 5%, TA = 0°C to 70°C  
Symbol Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
mV  
mV  
V
VOD  
Differential Output Voltage  
400  
850  
50  
VOD  
VOS  
VOD Magnitude Change  
Offset Voltage  
0.3  
2.1  
50  
VOS  
VOS Magnitude Change  
mV  
a.  
VDDO_X denotes VDDO_[0:15].  
AC Electrical Characteristics  
a
Table 11: AC Characteristics, VDD = VDD_DIGITAL = VDDO_X = 3.3V ± 5%, TA = 0°C to 70°Cb  
Symbol Parameter  
fOUT Output Frequency  
tPD  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
MHz  
ns  
350  
6
Propagation Delayc  
Output Slew Rate  
AC Swing  
2
3.8  
2.4  
Measured at the Differential Waveform,  
200mV from the Center  
tsl(o)  
VAC  
tjit  
0.9  
400  
4
V/ns  
mV  
ps  
674  
0.32  
850  
0.5  
Buffer Additive Phase Jitter,  
RMSd  
fOUT = 125MHz,  
Integration Range 12kHz – 20MHz  
tjit(TJ)  
odc  
Total Time Domain Jittere, f  
Output Duty Cycleg  
fOUT = 100MHz  
fIN 200MHz  
20% to 80%  
60  
50  
94  
55  
ps  
%
45  
tR / tF  
Output Rise/Fall Time  
380  
741  
ps  
a.  
b.  
VDDO_X denotes VDDO_[0:15].  
Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is  
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium  
has been reached under these conditions.  
c.  
d.  
e.  
f.  
Measured from the differential input crosspoint to the differential output crosspoint.  
SMA-100 as the signal source. With CLK6 as the input port and CLK4 as the output port for measurement (internal termination enabled.)  
Total Jitter (Peak-to-Peak) = [RMS Multiplier * Random Jitter (RJ)] + Deterministic Jitter (DJ), RMS Multiplier = 14.26 (BER = 1E-12).  
Device configured for 15 inputs and 1 output. Input source is an IDT clock generator 8714008D driven by an SRS CG635 signal  
generator.  
g.  
Input Duty Cycle must be 50%.  
©2015 Integrated Device Technology, Inc  
8
December 18, 2015  
 
8V54816A Datasheet  
a
Table 12: Serial Rapid IO Sw itch Jitter Specification, VDD = VDD_DIGITAL = VDDO_X = 3.3V ± 5%,  
TA = 0°C to 70°Cb  
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
JCLK_REF  
Total Phase Jitter, RMSc, d, e, f  
fOUT = 156.25MHz  
0.247  
0.5  
ps  
a.  
b.  
VDDO_X denotes VDDO_[0:15].  
Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is  
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium  
has been reached under these conditions.  
c.  
d.  
e.  
f.  
Evaluation band with sRIO mask applied: 10Hz - 40MHz.  
Total phase jitter includes random and deterministic jitter.  
Jitter data is measured using a Rohde & Schwarz SMA 100 input source and an Agilent E5052 phase noise analyzer.  
CLK0 is the input port. All other CLKs are programmed as output ports.  
a
Table 13: PCI Express Jitter Specifications, VDD = VDD_DIGITAL = VDDO_X = 3.3V ± 5%, TA = 0°C to 70°Cb  
PCIe Industry  
Specification Units  
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Phase Jitter,  
Peak-to-Peakc, d, e, f  
ƒ= 100MHz,  
Evaluation Band: 0Hz - Nyquist  
(clock frequency/2)  
tj  
11.2  
20  
86  
ps  
(PCIe Gen 1)  
ƒ= 100MHz,  
High Band: 1.5MHz - Nyquist  
(clock frequency/2)  
tREFCLK_HF_RMS  
(PCIe Gen 2)  
Phase Jitter,  
RMSc, d, f, g  
1
2
3.1  
3.0  
0.8  
ps  
ps  
ps  
tREFCLK_LF_RMS  
(PCIe Gen 2)  
Phase Jitter,  
RMSc, d, f, g  
ƒ= 100MHz  
Low Band: 10kHz - 1.5MHz  
0.06  
0.15  
0.5  
0.5  
ƒ= 100MHz  
Evaluation Band: 0Hz - Nyquist  
(clock frequency/2)  
tREFCLK_RMS  
(PCIe Gen 3)  
Phase Jitter,  
RMSc, d, f, h  
a.  
b.  
VDDO_X denotes VDDO_[0:15].  
Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is  
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium  
has been reached under these conditions. For additional information, refer to the PCI Express Application Note section in the datasheet.  
c.  
d.  
e.  
This parameter is guaranteed by characterization. Not tested in production.  
Parameter measured with an SRS CG635 as the input source.  
Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1 is  
86ps peak-to-peak for a sample size of 106 clock periods.  
f.  
CLK0 is the input port. All other CLKs are programmed as output ports. CLK4 and CLK12 are output ports for measurement.  
RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and reporting  
g.  
the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for tREFCLK_HF_RMS (High Band)  
and 3.0ps RMS for tREFCLK_LF_RMS (Low Band).  
h. RMS jitter after applying system transfer function for the common clock architecture. This specification is based on the PCI Express Base  
Specification Revision 0.7, October 2009 and is subject to change pending the final release version of the specification.  
©2015 Integrated Device Technology, Inc  
9
December 18, 2015  
 
 
 
8V54816A Datasheet  
Parameter Measurement Information  
nCLKx  
CLKx  
INTE R NAL 100Ω  
TE R MINATION  
S C OP E  
Qx  
V
DD,  
VDD_DIGITAL,  
3.3V 5%  
P OWE R S UP P LY  
+ Float G ND –  
V
DDO_X  
nCLKx  
CLKx  
nQx  
tPD  
Figure 3: 3.3V M-LVDS Output Load AC Test Circuit  
Figure 7: Propagation Delay  
nCLK[0:15]  
nCLK[0:15]  
80%  
80%  
+200mV  
VOD, VAC  
VCROSS  
-200mV  
VR  
VF  
20%  
20%  
CLK[0:15]  
CLK[0:15]  
tF  
tR  
tR  
tF  
Figure 4: Output Slew Rate  
Figure 8: Output Rise/Fall Time, VOD, VAC  
VDD  
nCLK[0:15]  
CLK[0:15]  
out  
➤
DC Input  
M-LVDS  
out  
VOS/∆ VOS  
➤
Figure 5: Output Duty Cycle/Pulse Width/tPeriod  
Figure 9: M-LVDS Offset Voltage Setup  
VDD  
➤
out  
M-LVDS  
DC Input  
100  
100  
VOD/∆ VOD  
➤
out  
Figure 6: M-LVDS Differential Output Voltage Setup  
©2015 Integrated Device Technology, Inc  
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December 18, 2015  
8V54816A Datasheet  
Applications Information  
The 8V54816A is a clock crosspoint switch designed to distribute clocks in MicroTCA.4 systems. The 8V54816A distributes clock coming from  
an AMC Timing card to other AMC cards.  
MCH  
IDT 8V54816A – Clock 1 Crosspoint switch  
IDT 8V54816A – Clock 2 Crosspoint switch  
Backplane  
Clock 2  
Clock 1  
Clock 2  
Clock 1  
AMC  
AMC  
AMC  
Timing  
Figure 10: 8V54816A Application Drawing  
Port Termination  
All 16 bi-directional clock ports (CLKx, nCLKx) feature a switchable, 100termination. External 100termination may be used. In that case  
the internal termination shall be turned off.  
Internal termination is turned on by setting Bit 6 of the configuration register corresponding to the considered I/O port to 1.  
Case 1: Terminations present on the backplane  
In case 100terminations are present on the backplane, terminations of the corresponding ports of the 8V54816A shall be turned off. No  
termination shall be present on AMC cards. See Figure 11.  
Figure 11: Termination on Blackplane  
©2015 Integrated Device Technology, Inc  
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December 18, 2015  
 
8V54816A Datasheet  
Case 2: No terminations present on the backplane  
When no terminations are present on the backplane, two terminations shall be turned on in order to realize a multi-point M-LVDS configuration.  
See Figure 12.  
Figure 12: No Termination on Backplane  
Polarity Inversion  
Polarity inversion of each port can be used in order to facilitate board layout. Polarity inversion is enabled by setting Bit 5 of the register  
corresponding to the considered port to 1. If polarity inversion is enabled,  
▪ CLKx becomes the negative input or output of port x  
▪ nCLKx becomes the positive input or output of port x  
©2015 Integrated Device Technology, Inc  
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8V54816A Datasheet  
Port Configuration Example  
Any CLKx, nCLKx port of the 8V54816A can be configured as either input or output. Let’s consider the following examples:  
▪ 100MHz clock source routed to port 2  
▪ 100MHz clock to be distributed to ports 3, 5, 8 and 9  
▪ 25MHz clock source routed to port 6  
▪ 25MHz clock to be distributed to ports 1, 11 and 12  
▪ Ports 13, 14 and 15 are not used  
Table 14: Port Configuration Table  
I2C Register  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Output  
PortSelect  
[3]  
Output  
Port  
Select[2]  
Output Output  
Port Select PortSelect  
Bit  
Description  
Termination  
On/Off  
Port I/O  
Polarity  
Reserved  
[1]  
[0]  
0
n/a  
1
n/a  
1
0
X
0
1
X
0
1
X
1
0
X
0
2
0
3
1
4
n/a  
1
n/a  
n/a  
n/a  
5
0
0
1
0
6
0
According to Backplane  
X
X
X
X
7
n/a  
1
Reserved  
8
0
0
0
0
1
1
0
0
9
1
10  
11  
12  
13  
14  
15  
n/a  
1
0
0
1
1
1
1
0
0
1
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
©2015 Integrated Device Technology, Inc  
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December 18, 2015  
8V54816A Datasheet  
Recommendations for Unused Input Pins  
Inputs:  
LVCMOS Control Pins  
All control pins have internal pullup or pulldown resistors; additional resistance is not required but can be added for additional protection. A  
1kresistor can be used.  
Bi-directional CLK/nCLK Ports  
The bi-directional input/output ports do not feature pull-up or pull-down resistors. Ports configured as inputs and left floating might toggle due  
to noise. This noise can propagate into the device’s core and increase the noise of the valid clocks due to internal crosstalk.  
Therefore, it is recommended to connect external biasing resistors to unused ports:  
▪
▪
Resistor to GND on the CLKx pin (e.g. 1 kto GND)  
Resistor network to GND and VDD on the nCLKx pin (e.g. 1.2kto GND and 2.7 kto VDD) and configure the port as an input. The internal  
termination can be disabled or enabled.  
If using external biasing resistors to unused ports cannot be realized, the recommended operation of an unused port is to:  
▪
▪
▪
▪
leave the port unconnected  
configure the port as an output  
disable the internal termination (to save power)  
select a valid clock input as clock source for this port.  
©2015 Integrated Device Technology, Inc  
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December 18, 2015  
8V54816A Datasheet  
Differential Clock Input Interface  
The CLKx /nCLKx accepts LVDS and other differential signals. Both differential signals must meet the VPP and VCMR input requirements.  
Figure 13 shows an interface example for the CLKx/nCLKx input driven by the most common driver types. The input interfaces suggested here  
are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. If the driver is from  
another vendor, use their termination recommendation.  
Figure 13: CLK/nCLK Input Driven by a 3.3V LVDS Driver  
3.3V M-LVDS Driver Termination  
A general M-LVDS interface is shown in Figure 14 In a 100differential transmission line environment, M-LVDS drivers require a matched  
load termination of 100across near the receiver input. For a multiple M-LVDS outputs buffer, if only partial outputs are used, it is  
recommended to terminate the unused outputs.  
3.3V  
3.3V  
50  
Internal 100Termination  
M-LVDS Driver  
+
–
R2  
100  
R1  
100  
50  
100Differential Transmission Line  
Figure 14: Typical M-LVDS Driver Termination  
©2015 Integrated Device Technology, Inc  
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December 18, 2015  
 
 
8V54816A Datasheet  
VFQFN EPAD Thermal Release Path  
In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the  
Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package,  
as shown in Figure 15. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the  
exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB  
between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts.  
While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder  
joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be  
connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are application specific and  
dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or  
testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array  
of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended  
that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking  
inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land.  
Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations  
are to be used as a guideline only. For further information, please refer to the Application Note on the Surface Mount Assembly of Amkor’s  
Thermally/ Electrically Enhance Leadframe Base Package, Amkor Technology.  
SOLDER  
SOLDER  
PIN  
EXPOSED HEAT SLUG  
PIN  
PIN PAD  
GROUND PLANE  
LAND PATTERN  
(GROUND PAD)  
PIN PAD  
THERMAL VIA  
Figure 15: P.C. Assembly for Exposed Pad Thermal Release Path – Side View (draw ing not to scale)  
©2015 Integrated Device Technology, Inc  
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December 18, 2015  
 
8V54816A Datasheet  
PCI Express Application Note  
PCI Express jitter analysis methodology models the system response to reference clock jitter. The block diagram below shows the most  
frequently used Common Clock Architecture in which a copy of the reference clock is provided to both ends of the PCI Express Link.  
In the jitter analysis, the transmit (Tx) and receive (Rx) serdes PLLs are modeled as well as the phase interpolator in the receiver. These  
transfer functions are called H1, H2, and H3 respectively. The overall system transfer function at the receiver is:  
Hts= H3s  H1s– H2s  
The jitter spectrum seen by the receiver is the result of applying this system transfer function to the clock spectrum X(s) and is:  
Ys= Xs  H3s  H1s– H2s  
In order to generate time domain jitter numbers, an inverse Fourier Transform is performed on X(s)*H3(s) * [H1(s) - H2(s)].  
Figure 16: PCI Express Common Clock Architecture  
For PCI Express Gen 1, one transfer function is defined and the evaluation is performed over the entire spectrum: DC to Nyquist (e.g for a  
100MHz reference clock: 0Hz – 50MHz) and the jitter result is reported in peak-peak.  
Figure 17: PCIe Gen 1 Magnitude of Transfer Function  
©2015 Integrated Device Technology, Inc  
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December 18, 2015  
8V54816A Datasheet  
For PCI Express Gen 2, two transfer functions are defined with 2 evaluation ranges and the final jitter number is reported in rms. The two  
evaluation ranges for PCI Express Gen 2 are 10kHz – 1.5MHz (Low Band) and 1.5MHz – Nyquist (High Band). The plots show the individual  
transfer functions as well as the overall transfer function Ht.  
Figure 18: PCIe Gen 2A Magnitude of Transfer Function  
Figure 19: PCIe Gen 2B Magnitude of Transfer Function  
For PCI Express Gen 3, one transfer function is defined and the evaluation is performed over the entire spectrum. The transfer function  
parameters are different from Gen 1 and the jitter result is reported in RMS.  
Figure 20: PCIe Gen 3 Magnitude of Transfer Function  
For a more thorough overview of PCI Express jitter analysis methodology, please refer to IDT Application Note PCI Express Reference Clock  
Requirements.  
©2015 Integrated Device Technology, Inc  
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December 18, 2015  
8V54816A Datasheet  
Power Considerations  
This section provides information on power dissipation and junction temperature for the 8V54816A.  
Equations and example calculations are also provided.  
The following calculation is for maximum current at 70°C.  
1. Power Dissipation.  
The total power dissipation for the 8V54816A is the sum of the core power plus the power dissipated due to into the load.  
The following is the power dissipation for VDD= 3.3V + 5% = 3.465V, which gives worst case results.  
The maximum current at 70°C is as below:  
IDD_MAX = 293mA  
IDD_DIGITAL_MAX = 7mA  
IDDO_MAX = 295mA  
▪ Power (core)MAX = VDD_MAX * (IDD_MAX + IDD_DIGITAL_MAX)= 3.465V * (293mA + 7mA) = 1040mW  
▪ Power (outputs)MAX = VDDO_MAX * IDDO_MAX = 3.465V * 295mA = 1022.2mW  
Total Power_MAX = 1040mW + 1022.2mW = 2062.2mW  
2. Junction Temperature.  
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The  
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the  
bond wire and bond pad temperature remains below 125°C.  
The equation for Tj is as follows: Tj = JA * Pd_total + TA  
Tj = Junction Temperature  
JA = Junction-to-Ambient Thermal Resistance  
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)  
TA = Ambient Temperature  
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and  
a multi-layer board, the appropriate value is 22.9°C/W per Table 15 below.  
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:  
70°C + 2.06W * 22.9°C/W = 117.2°C. This is below the limit of 125°C.  
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of  
board (multi-layer).  
Table 15: Thermal Resistance JA for 100-Lead VFQFN, Forced Convection  
JA by Velocity  
Meters per Second  
0
1
2.5  
Multi-Layer PCB, JEDEC Standard  
22.9°C/W  
18.0°C/W  
16.0°C/W  
©2015 Integrated Device Technology, Inc  
19  
December 18, 2015  
 
8V54816A Datasheet  
Reliability Information  
Table 16: JA vs. Air Flow Table for a 100-Lead VFQFN Package  
JA vs. Air Flow  
Meters per Second  
0
1
2.5  
Multi-Layer PCB, JEDEC Standard Test Boards  
22.9°C/W  
18.0°C/W  
16.0°C/W  
Transistor Count  
The transistor count for 8V54816A is: 195,306  
©2015 Integrated Device Technology, Inc  
20  
December 18, 2015  
8V54816A Datasheet  
VFQFN Package Outline and Package Dimensions  
©2015 Integrated Device Technology, Inc  
21  
December 18, 2015  
8V54816A Datasheet  
VFQFN Package Outline and Package Dimensions, continued  
©2015 Integrated Device Technology, Inc  
22  
December 18, 2015  
8V54816A Datasheet  
VFQFN Package Outline and Package Dimensions, continued  
©2015 Integrated Device Technology, Inc  
23  
December 18, 2015  
8V54816A Datasheet  
VFQFN Package Outline and Package Dimensions, continued  
©2015 Integrated Device Technology, Inc  
24  
December 18, 2015  
8V54816A Datasheet  
VFQFN Package Outline and Package Dimensions, continued  
©2015 Integrated Device Technology, Inc  
25  
December 18, 2015  
8V54816A Datasheet  
Ordering Information  
Part/Order Number  
8V54816ANLG  
Marking  
Package  
Shipping Packaging  
Tray  
Temperature  
0°C to 70°C  
0°C to 70°C  
IDT8V54816ANLG  
IDT8V54816ANLG  
100-lead VFQFN, Lead-Free  
100-lead VFQFN, Lead-Free  
8V54816ANLG8  
Tape & Reel  
©2015 Integrated Device Technology, Inc  
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December 18, 2015  
8V54816A Datasheet  
Corporate Headquarters  
6024 Silver Creek Valley Road  
San Jose, CA 95138 USA  
www.IDT.com  
Sales  
Tech Support  
1-800-345-7015 or 408-284-8200  
Fax: 408-284-2775  
www.IDT.com/go/sales  
www.idt.com/go/support  
DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications  
and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein  
is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability,  
or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.  
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably  
expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.  
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of  
IDT or their respective third party owners.  
For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary.  
Copyright ©2015 Integrated Device Technology, Inc. All rights reserved.  
厂商 型号 描述 页数 下载

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 		8V54816ANLG [ 16-Por t , Bi-direct ional M-LVDS Clock Cross-Point Switch ] 27 页

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 		8V54816ANLG8 [ 16-Por t , Bi-direct ional M-LVDS Clock Cross-Point Switch ] 27 页

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