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9ZX21901DKLF

型号：

9ZX21901DKLF

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

20 页

PDF大小：

341 K

下载PDF手册
19-Output DB1900Z for PCIe Gen1-4 and  
QPI/UPI  
9ZX21901D  
DATASHEET  
Description  
Features  
The 9ZX21901D is a second generation DB1900Z differential  
buffer for Intel Purley and newer platforms. The part is  
backwards compatible to the 9ZX21901C while offering much  
improved phase jitter performance. A fixed external feedback  
maintains low drift for critical QPI/UPI applications. In bypass  
mode, the 9ZX21901D can provide outputs up to 400MHz.  
• Fixed feedback path; 0ps input-to-output delay  
• 9 Selectable SMBus addresses; multiple devices can share  
same SMBus segment  
• 8 dedicated OE# pins; hardware control of outputs  
• PLL or bypass mode; PLL can dejitter incoming clock  
• Selectable PLL BW; minimizes jitter peaking in downstream  
PLL's  
PCIe Clocking Architectures Supported  
• Common Clocked (CC)  
• Separate Reference No Spread (SRNS)  
• Separate Reference Independent Spread (SRIS)  
• Hardware or software control of PLL operating mode;  
change mode with software mode does not need power  
cycle  
• Spread spectrum compatible; tracks spreading input clock  
for EMI reduction  
Typical Applications  
• Servers, Storage, Networking  
• SMBus Interface; unused outputs can be disabled  
• 100MHz and 133.33MHz PLL mode; legacy QPI support  
• 72-QFN 10 x 10 mm package; small board footprint  
Output Features  
• 19 HCSL output pairs  
Key Specifications  
• Cycle-to-cycle jitter: < 50ps  
• Output-to-output skew: < 50ps  
• Input-to-output delay: Fixed at 0 ps  
• Input-to-output delay variation: < 50ps  
• Phase jitter: PCIe Gen4 < 0.5ps rms  
• Phase jitter: UPI 9.6GB/s < 0.1ps rms  
Functional Block Diagram  
Low Phase  
Noise Z-PLL  
(SS-  
DFB_OUT  
DIF[18]  
DIF_IN  
Compatible)  
OE(12:5)#  
Bypass path  
HIBW_BYPM_LOBW#  
100M_133M#  
19 outputs  
CKPWRGD/PD#  
SMB_A0_tri  
SMB_A1_tri  
SMBDAT  
SMBCLK  
DIF[0]  
IREF  
9ZX21901D APRIL 17, 2018  
1
©2018 Integrated Device Technology, Inc.  
9ZX21901D DATASHEET  
Pin Configuration  
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55  
VDDA  
GNDA  
1
2
3
4
5
6
7
8
9
54 OE11#  
53 DIF_11#  
52 DIF_11  
51 OE10#  
50 DIF_10#  
49 DIF_10  
48 OE9#  
47 DIF_9#  
46 DIF_9  
45 VDD  
IREF  
100M_133M#  
HIBW_BYPM_LOBW#  
CKPWRGD_PD#  
GND  
9ZX21901D  
connect ePad to Ground  
NOTE: DFB_OUT pins must be  
terminated identically to the regular DIF  
outputs  
VDDR  
DIF_IN  
DIF_IN# 10  
SMB_A0_tri 11  
SMBDAT 12  
SMBCLK 13  
SMB_A1_tri 14  
NC 15  
44 GND  
43 OE8#  
42 DIF_8#  
41 DIF_8  
40 OE7#  
39 DIF_7#  
38 DIF_7  
37 OE6#  
NC 16  
DFB_OUT# 17  
DFB_OUT 18  
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36  
72-pin VFQFPN (10mm x10 mm, 0.5mm pad pitch)  
Power Connections  
Functionality at Power Up (PLL Mode)  
DIF_IN  
(MHz)  
100.00  
133.33  
DIF_x  
(MHz)  
Pin Number  
100M_133M#  
Description  
VDD  
GND  
1
0
DIF_IN  
DIF_IN  
1
8
2
7
Analog PLL  
Analog Input  
21, 31, 45,  
58, 68  
26, 44, 63  
DIF clocks  
PLL Operating Mode Readback Table  
HiBW_BypM_LoBW#  
Low (Low BW)  
Byte0, bit 7  
Byte 0, bit 6  
0
0
1
0
1
1
9ZX21901 SMBus Addressing  
Mid (Bypass)  
Pin  
SMBus Address  
(Rd/Wrt bit = 0)  
D8  
High (High BW)  
SMB_A1_tri SMB_A0_tri  
0
0
M
1
0
DA  
PLL Operating Mode  
HiBW_BypM_LoBW#  
Low  
0
DE  
C2  
C4  
MODE  
M
M
0
PLL Lo BW  
M
1
Mid  
Bypass  
M
1
C6  
CA  
CC  
CE  
High  
PLL Hi BW  
0
NOTE: PLL is OFF in Bypass Mode  
M
1
1
1
Tri-level Input Thresholds  
Level  
Low  
Voltage  
<0.8V  
Mid  
1.2<Vin<1.8V  
Vin > 2.2V  
High  
19-OUTPUT DB1900Z FOR PCIE GEN1-4 AND QPI/UPI  
2
APRIL 17, 2018  
9ZX21901D DATASHEET  
Pin Descriptions  
PIN #  
PIN NAME  
VDDA  
PIN TYPE  
PWR  
DESCRIPTION  
1
2
Power supply for PLL core.  
Ground pin for the PLL core.  
GNDA  
IREF  
GND  
This pin establishes the reference for the differential current-mode output pairs.  
It requires a fixed precision resistor to ground. 475ohm is the standard value  
for 100ohm differential impedance. Other impedances require different values.  
See data sheet.  
3
OUT  
Input to select operating frequency  
4
5
100M_133M#  
IN  
IN  
1 = 100MHz, 0 = 133.33MHz  
Tri-level input to select High BW, Bypass or Low BW mode.  
See PLL Operating Mode Table for Details.  
HIBW_BYPM_LOBW#  
3.3V input notifies device to sample latched inputs and start up on first high  
assertion, or exit Power Down Mode on subsequent assertions. Low enters  
Power Down Mode.  
6
CKPWRGD_PD#  
IN  
7
8
GND  
GND  
PWR  
Ground pin.  
Power supply for differential input clock (receiver). This VDD should be treated  
as an analog power rail and filtered appropriately. Nominally 3.3V.  
HCSL true input.  
VDDR  
9
DIF_IN  
IN  
IN  
10  
DIF_IN#  
HCSL complementary input.  
SMBus address pin. This is a tri-level input that works in conjunction with other  
SMBus address pins to decode 3^n SMBus addresses, where n is the number  
Data pin of SMBUS circuitry  
11  
SMB_A0_tri  
IN  
12  
13  
SMBDAT  
SMBCLK  
I/O  
IN  
Clock pin of SMBUS circuitry  
SMBus address pin. This is a tri-level input that works in conjunction with other  
SMBus address pins to decode 3^n SMBus addresses, where n is the number  
No connection.  
14  
SMB_A1_tri  
IN  
15  
16  
NC  
NC  
N/A  
N/A  
No connection.  
Complementary half of differential feedback output, provides feedback signal  
to the PLL for synchronization with input clock to eliminate phase error.  
17  
DFB_OUT#  
OUT  
True half of differential feedback output, provides feedback signal to the PLL  
for synchronization with the input clock to eliminate phase error.  
HCSL true clock output.  
18  
DFB_OUT  
OUT  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
DIF_0  
DIF_0#  
VDD  
OUT  
OUT  
PWR  
OUT  
OUT  
OUT  
OUT  
GND  
OUT  
OUT  
OUT  
OUT  
PWR  
OUT  
OUT  
HCSL complementary clock output.  
Power supply, nominally 3.3V.  
DIF_1  
DIF_1#  
DIF_2  
DIF_2#  
GND  
HCSL true clock output.  
HCSL complementary clock output.  
HCSL true clock output.  
HCSL complementary clock output.  
Ground pin.  
DIF_3  
DIF_3#  
DIF_4  
DIF_4#  
VDD  
HCSL true clock output.  
HCSL complementary clock output.  
HCSL true clock output.  
HCSL complementary clock output.  
Power supply, nominally 3.3V.  
DIF_5  
DIF_5#  
HCSL true clock output.  
HCSL complementary clock output.  
Active low input for enabling output 5.  
1 = disable outputs, 0 = enable outputs.  
HCSL true clock output.  
34  
OE5#  
IN  
35  
36  
DIF_6  
OUT  
OUT  
DIF_6#  
HCSL complementary clock output.  
APRIL 17, 2018  
3
19-OUTPUT DB1900Z FOR PCIE GEN1-4 AND QPI/UPI  
9ZX21901D DATASHEET  
Pin Descriptions (cont.)  
PIN #  
PIN NAME  
PIN TYPE  
DESCRIPTION  
Active low input for enabling DIF pair 6.  
37  
OE6#  
DIF_7  
IN  
1 =disable outputs, 0 = enable outputs  
HCSL true clock output  
38  
39  
OUT  
OUT  
DIF_7#  
HCSL Complementary clock output  
Active low input for enabling DIF pair 7.  
1 =disable outputs, 0 = enable outputs  
HCSL true clock output  
40  
OE7#  
IN  
41  
42  
DIF_8  
OUT  
OUT  
DIF_8#  
HCSL Complementary clock output  
Active low input for enabling DIF pair 8.  
1 =disable outputs, 0 = enable outputs  
Ground pin.  
43  
OE8#  
IN  
44  
45  
46  
47  
GND  
GND  
PWR  
OUT  
OUT  
VDD  
Power supply, nominal 3.3V  
DIF_9  
DIF_9#  
HCSL true clock output  
HCSL Complementary clock output  
Active low input for enabling DIF pair 9.  
1 =disable outputs, 0 = enable outputs  
HCSL true clock output  
48  
OE9#  
IN  
49  
50  
DIF_10  
OUT  
OUT  
DIF_10#  
HCSL Complementary clock output  
Active low input for enabling DIF pair 10.  
1 =disable outputs, 0 = enable outputs  
HCSL true clock output  
51  
OE10#  
IN  
52  
53  
DIF_11  
OUT  
OUT  
DIF_11#  
HCSL Complementary clock output  
Active low input for enabling DIF pair 11.  
1 =disable outputs, 0 = enable outputs  
HCSL true clock output  
54  
OE11#  
IN  
55  
56  
DIF_12  
OUT  
OUT  
DIF_12#  
HCSL Complementary clock output  
Active low input for enabling DIF pair 12.  
1 =disable outputs, 0 = enable outputs  
Power supply, nominal 3.3V  
57  
OE12#  
IN  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
VDD  
PWR  
OUT  
OUT  
OUT  
OUT  
GND  
OUT  
OUT  
OUT  
OUT  
PWR  
OUT  
OUT  
OUT  
OUT  
DIF_13  
DIF_13#  
DIF_14  
DIF_14#  
GND  
HCSL true clock output  
HCSL Complementary clock output  
HCSL true clock output  
HCSL Complementary clock output  
Ground pin.  
DIF_15  
DIF_15#  
DIF_16  
DIF_16#  
VDD  
HCSL true clock output  
HCSL Complementary clock output  
HCSL true clock output  
HCSL Complementary clock output  
Power supply, nominal 3.3V  
DIF_17  
DIF_17#  
DIF_18  
DIF_18#  
HCSL true clock output  
HCSL Complementary clock output  
HCSL true clock output  
HCSL Complementary clock output  
19-OUTPUT DB1900Z FOR PCIE GEN1-4 AND QPI/UPI  
4
APRIL 17, 2018  
9ZX21901D DATASHEET  
Electrical Characteristics – Absolute Maximum Ratings  
PARAMETER  
SYMBOL  
CONDITIONS  
UNITS NOTES  
MIN  
TYP  
MAX  
Supply Voltage  
Input Low Voltage  
Input High Voltage  
Input High Voltage  
VDDx  
VIL  
3.9  
V
V
V
V
1,2  
1
GND-0.5  
VIH  
Except for SMBus interface  
SMBus clock and data pins  
VDD+0.5  
3.9  
1,3  
1
VIHSMB  
1
Storage Temperature  
Junction Temperature  
Ts  
Tj  
-65  
150  
125  
°C  
°C  
1
1
Input ESD protection  
ESD prot  
Human Body Model  
2000  
V
1Guaranteed by design and characterization, not 100% tested in production.  
2 Operation under these conditions is neither implied nor guaranteed.  
3 Not to exceed 3.9V.  
Electrical Characteristics – DIF_IN Clock Input Parameters  
Over specified temperature and voltage ranges unless otherwise indicated. See Test Loads for loading conditions.  
PARAMETER  
SYMBOL  
VCROSS  
CONDITIONS  
MIN  
150  
TYP  
MAX  
900  
UNITS NOTES  
Input Crossover Voltage  
Crossover voltage  
mV  
1
Input Swing - DIF_IN  
Input Slew Rate - DIF_IN  
Input Leakage Current  
Input Duty Cycle  
VSWING  
dv/dt  
IIN  
Differential value  
Measured differentially  
300  
0.35  
-5  
mV  
V/ns  
uA  
1
8
5
1,2  
VIN = VDD , VIN = GND  
dtin  
Measurement from differential waveform  
45  
55  
%
1
1
Input Jitter - Cycle to Cycle  
JDIFIn  
Differential measurement  
0
125  
ps  
1 Guaranteed by design and characterization, not 100% tested in production.  
2Slew rate measured through +/-75mV window centered around differential zero.  
Electrical Characteristics – SMBus  
Over specified temperature and voltage ranges unless otherwise indicated. See Test Loads for Loading Conditions  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS NOTES  
SMBus Input Low Voltage  
SMBus Input High Voltage  
VILSMB  
VIHSMB  
0.8  
VDDSMB  
0.4  
V
V
2.1  
SMBus Output Low Voltage VOLSMB  
@ IPULLUP  
@ VOL  
V
SMBus Sink Current  
Nominal Bus Voltage  
SCLK/SDATA Rise Time  
IPULLUP  
VDDSMB  
tRSMB  
4
mA  
2.7  
3.6  
1000  
300  
V
1
1
1
(Max VIL - 0.15) to (Min VIH + 0.15)  
(Min VIH + 0.15) to (Max VIL - 0.15)  
ns  
ns  
SCLK/SDATA Fall Time  
SMBus Operating  
Frequency  
tFSMB  
fMAXSMB  
Maximum SMBus operating frequency  
400  
kHz  
5
1Guaranteed by design and characterization, not 100% tested in production.  
2Control input must be monotonic from 20% to 80% of input swing.  
3Time from deassertion until outputs are >200 mV  
4DIF_IN input  
5The differential input clock must be running for the SMBus to be active  
APRIL 17, 2018  
5
19-OUTPUT DB1900Z FOR PCIE GEN1-4 AND QPI/UPI  
9ZX21901D DATASHEET  
Electrical Characteristics – Current Consumption  
Over specified temperature and voltage ranges unless otherwise indicated. See Test Loads for Loading Conditions  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX UNITS NOTES  
Operating Supply Current  
Operating Supply Current  
Powerdown Current  
IDDA  
IDD  
VDDA, PLL Mode@100MHz  
All other VDD pins  
42  
466  
4
45  
490  
5
mA  
mA  
mA  
1
IDDPD  
All DIF pairs Hi-Z  
1.  
Includes VDDR if applicable  
Electrical Characteristics – Input/Supply/Common Parameters  
Over specified temperature and voltage ranges unless otherwise indicated. See Test Loads for Loading Conditions  
PARAMETER  
SYMBOL  
VDDx  
CONDITIONS  
MIN  
TYP  
3.3  
MAX  
UNITS NOTES  
V
Supply Voltage  
Ambient Operating  
Temperature  
Supply voltage for core and analog  
3.135  
3.465  
70  
TAMB  
VIH  
Commercial range (TCOM  
)
0
2
°C  
V
Single-ended inputs, except SMBus, tri-level  
Input High Voltage  
VDD + 0.3  
0.8  
inputs  
Single-ended inputs, except SMBus, tri-level  
inputs  
Input Low Voltage  
VIL  
GND - 0.3  
V
Input High Voltage  
Input Mid Voltage  
Input Low Voltage  
VIH  
VIL  
VIL  
IIN  
Tri-Level Inputs  
2.2  
1.2  
VDD + 0.3  
V
V
Tri-Level Inputs  
Tri-Level Inputs  
VDD/2  
1.8  
0.8  
5
GND - 0.3  
-5  
V
Single-ended inputs, VIN = GND, VIN = VDD  
µA  
Single-ended inputs  
Input Current  
VIN = 0 V; Inputs with internal pull-up resistors  
IN = VDD; Inputs with internal pull-down resistors  
IINP  
-200  
200  
µA  
V
Fibyp  
Fipll  
VDD = 3.3 V, Bypass mode  
VDD = 3.3 V, 100MHz PLL mode  
VDD = 3.3 V, 133.33MHz PLL mode  
33  
400  
102  
135  
7
MHz  
MHz  
MHz  
Input Frequency  
Pin Inductance  
Capacitance  
98.5  
125  
100.00  
130.50  
Fipll  
Lpin  
nH  
pF  
pF  
pF  
1
1
CIN  
Logic Inputs, except DIF_IN  
DIF_IN differential clock inputs  
Output pin capacitance  
1.5  
1.5  
5
CINDIF_IN  
COUT  
2.7  
6
1,4  
1
From VDD Power-Up and after input clock  
Clk Stabilization  
TSTAB  
1.4  
1.8  
ms  
1,2  
stabilization or de-assertion of PD# to 1st clock  
Input SS Modulation  
Frequency PCIe  
Allowable Frequency for PCIe Applications  
(Triangular Modulation)  
fMODINPCIe  
tLATOE#  
tDRVPD  
30  
4
33  
10  
kHz  
DIF start after OE# assertion  
DIF stop after OE# deassertion  
DIF output enable after  
OE# Latency  
Tdrive_PD#  
6
clocks 1,2,3  
85  
300  
µs  
1,3  
PD# de-assertion  
Tfall  
tF  
Fall time of control inputs  
Rise time of control inputs  
5
5
ns  
ns  
2
2
Trise  
tR  
1 Guaranteed by design and characterization, not 100% tested in production.  
2 Control input must be monotonic from 20% to 80% of input swing.  
3 Time from deassertion until outputs are > 200 mV.  
4 DIF_IN input.  
19-OUTPUT DB1900Z FOR PCIE GEN1-4 AND QPI/UPI  
6
APRIL 17, 2018  
9ZX21901D DATASHEET  
Electrical Characteristics – DIF HCSL/LP-HCSL Outputs  
Over specified temperature and voltage ranges unless otherwise indicated. See Test Loads for Loading Conditions  
INDUSTRY  
PARAMETER  
SYMBOL  
dV/dt  
CONDITIONS  
MIN  
1.5  
TYP MAX  
UNITS NOTES  
LIMIT  
0.6 - 4  
20  
V/ns  
%
Slew rate  
Slew rate matching  
Max Voltage  
Scope averaging on  
2.2  
7.3  
772  
11  
3.0  
18  
1,2,3  
1,2,4,7  
7,8  
dV/dt  
Δ
Slew rate matching, Scope averaging on  
Measurement on single ended signal using  
absolute value. (Scope averaging off)  
Vmax  
Vmin  
719  
310  
842  
50  
1150  
-300  
mV  
Min Voltage  
7,8  
Crossing Voltage (abs)  
Vcross_abs  
Scope averaging off  
367  
14  
400  
30  
250 - 550  
140  
mV  
mV  
1,5,7  
1,6,7  
Crossing Voltage (var)  
-Vcross  
Δ
Scope averaging off  
1Guaranteed by design and characterization, not 100% tested in production.  
2 Measured from differential waveform  
3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around  
differential 0V.  
4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the  
average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the  
oscilloscope is to use for the edge rate calculations.  
5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e.  
Clock rising and Clock# falling).  
6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross absolute)  
allowed. The intent is to limit Vcross induced modulation by setting ꢀ-Vcross to be smaller than Vcross absolute.  
7 At default SMBus settings.  
8 If driving a receiver with input terminations, the Vmax and Vmin values will be halved.  
APRIL 17, 2018  
7
19-OUTPUT DB1900Z FOR PCIE GEN1-4 AND QPI/UPI  
9ZX21901D DATASHEET  
Electrical Characteristics – Skew and Differential Jitter Parameters  
Over specified temperature and voltage ranges unless otherwise indicated. See Test Loads for Loading Conditions  
PARAMETER  
CLK_IN, DIF[x:0]  
CLK_IN, DIF[x:0]  
CLK_IN, DIF[x:0]  
SYMBOL  
tSPO_PLL  
tPD_BYP  
CONDITIONS  
MIN  
-100  
1.9  
TYP  
54  
MAX UNITS NOTES  
Input-to-Output Skew in PLL mode  
at 100MHz, nominal temperature and voltage  
Input-to-Output Skew in Bypass mode  
at 100MHz, nominal temperature and voltage  
Input-to-Output Skew Variation in PLL mode  
at 100MHz, across voltage and temperature  
Input-to-Output Skew Variation in Bypass  
mode  
100  
3
ps  
ns  
ps  
1,2,4,5,8  
1,2,3,5,8  
1,2,3,5,8  
2.6  
0.0  
tDSPO_PLL  
-50  
50  
CLK_IN, DIF[x:0]  
tDSPO_BYP  
-250  
0.0  
250  
ps  
1,2,3,5,8  
at 100MHz, across voltage and temperature,  
T
AMB = TCOM  
Output-to-Output Skew across all outputs,  
DIF[x:0]  
tSKEW_ALL  
32  
50  
ps  
1,2,3,8  
common to PLL and Bypass mode, at 100MHz  
PLL Jitter Peaking  
PLL Jitter Peaking  
PLL Bandwidth  
PLL Bandwidth  
Duty Cycle  
jpeak-hibw  
jpeak-lobw  
pllHIBW  
pllLOBW  
tDC  
LOBW#_BYPASS_HIBW = 1  
LOBW#_BYPASS_HIBW = 0  
LOBW#_BYPASS_HIBW = 1  
LOBW#_BYPASS_HIBW = 0  
0
0
1.4  
1.2  
2.8  
1.1  
50  
2.5  
2
dB  
dB  
7,8  
7,8  
8,9  
8,9  
1
2
4
MHz  
MHz  
%
0.7  
45  
1.4  
55  
Measured differentially, PLL Mode  
Measured differentially, Bypass Mode at  
100MHz  
Duty Cycle Distortion  
Jitter, Cycle to Cycle  
tDCD  
-1  
-0.5  
0
%
1,10  
PLL mode  
17  
50  
5
ps  
ps  
1,11  
1,11  
tjcyc-cyc  
Additive Jitter in Bypass Mode  
0.1  
1
2
3
Measured into fixed 2 pF load cap. Input to output skew is measured at the first output edge following the corresponding input.  
Measured from differential cross-point to differential cross-point. This parameter can be tuned with external feedback path, if present.  
All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it.  
4 This parameter is deterministic for a given device.  
5
Measured with scope averaging on to find mean value.  
6 t is the period of the input clock.  
7 Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL jitter peaking.  
8.  
Guaranteed by design and characterization, not 100% tested in production.  
9
Measured at 3 db down or half power point.  
10 Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.  
11 Measured from differential waveform.  
19-OUTPUT DB1900Z FOR PCIE GEN1-4 AND QPI/UPI  
8
APRIL 17, 2018  
9ZX21901D DATASHEET  
Electrical Characteristics – Filtered Phase Jitter Parameters - PCIe Common Clocked  
(CC) Architectures  
Over specified temperature and voltage ranges unless otherwise indicated. See Test Loads for Loading Conditions  
INDUSTRY  
PARAMETER  
SYMBOL  
CONDITIONS  
PCIe Gen 1  
MIN  
TYP  
18  
MAX  
30  
UNITS  
Notes  
1,2,3  
LIMIT  
86  
tjphPCIeG1-CC  
ps (p-p)  
PCIe Gen 2 Lo Band  
10kHz < f < 1.5MHz  
ps  
0.4  
0.8  
3
1,2  
(rms)  
(PLL BW of 5-16MHz or 8-5MHz, CDR = 5MHz)  
tjphPCIeG2-CC  
PCIe Gen 2 High Band  
1.5MHz < f < Nyquist (50MHz)  
ps  
1.6  
3.1  
Phase Jitter,  
PLL Mode  
1.1  
1,2  
1,2  
(rms)  
(PLL BW of 5-16MHz or 8-5MHz, CDR = 5MHz)  
PCIe Gen 3  
ps  
0.40  
1
tjphPCIeG3-CC  
0.28  
(PLL BW of 2-4MHz or 2-5MHz, CDR = 10MHz)  
(rms)  
PCIe Gen 4  
ps  
0.40  
0.5  
tjphPCIeG4-CC  
0.28  
0.1  
1,2  
1,2  
(PLL BW of 2-4MHz or 2-5MHz, CDR = 10MHz)  
(rms)  
tjphPCIeG1-CC  
PCIe Gen 1  
0.1  
ps (p-p)  
PCIe Gen 2 Lo Band  
10kHz < f < 1.5MHz  
ps  
0.1  
0.1  
1,2,4  
1,2,4  
(rms)  
(PLL BW of 5-16MHz or 8-5MHz, CDR = 5MHz)  
tjphPCIeG2-CC  
Additive Phase Jitter,  
Bypass mode  
PCIe Gen 2 High Band  
1.5MHz < f < Nyquist (50MHz)  
n/a  
ps  
0.105  
0.13  
(rms)  
(PLL BW of 5-16MHz or 8-5MHz, CDR = 5MHz)  
PCIe Gen 3  
ps  
tjphPCIeG3-CC  
0.1  
0.1  
0.1  
0.1  
1,2,4  
1,2,4  
(PLL BW of 2-4MHz or 2-5MHz, CDR = 10MHz)  
(rms)  
PCIe Gen 4  
ps  
tjphPCIeG4-CC  
(PLL BW of 2-4MHz or 2-5MHz, CDR = 10MHz)  
(rms)  
1 Applies to all outputs,, when driven by 9SQL4958 or equivalent  
2 Based on PCIe Base Specification Rev4.0 version 0.7 draft. See http://www.pcisig.com for latest specifications.  
3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.  
4 For RMS values additive jitter is calculated by solving the following equation for b [a^2+b^2=c^2] where a is rms input jitter and c is rms total jitter.  
APRIL 17, 2018  
9
19-OUTPUT DB1900Z FOR PCIE GEN1-4 AND QPI/UPI  
9ZX21901D DATASHEET  
Electrical Characteristics – Filtered Phase Jitter Parameters - PCIe Separate  
Reference Independent Spread (SRIS) Architectures  
Over specified temperature and voltage ranges unless otherwise indicated. See Test Loads for Loading Conditions  
INDUSTRY  
PARAMETER  
SYMBOL  
tjphPCIeG1-  
CONDITIONS  
PCIe Gen 1  
MIN  
TYP  
n/a  
MAX  
UNITS  
Notes  
1,2,3  
1,2  
LIMIT  
n/a  
ps (p-p)  
SRIS  
tjphPCIeG2-  
PCIe Gen 2  
ps  
0.8  
1.1  
2
(PLL BW of 16MHz , CDR = 5MHz)  
(rms)  
Phase Jitter, PLL  
Mode  
SRIS  
tjphPCIeG3-  
PCIe Gen 3  
ps  
0.7  
TBD  
n/a  
0.6  
1,2  
(PLL BW of 2-4MHz or 2-5MHz, CDR = 10MHz)  
(rms)  
SRIS  
tjphPCIeG4-  
PCIe Gen 4  
ps  
n/a  
n/a  
0.0  
0.0  
n/a  
1,2  
(PLL BW of 2-4MHz or 2-5MHz, CDR = 10MHz)  
(rms)  
SRIS  
tjphPCIeG1-  
PCIe Gen 1  
ps (p-p)  
1,2  
SRIS  
tjphPCIeG2-  
PCIe Gen 2  
ps  
0.01  
1,2,4  
1,2,4  
1,2,4  
(PLL BW of 16MHz , CDR = 5MHz)  
(rms)  
AdditivePhase Jitter,  
Bypass mode  
SRIS  
n/a  
tjphPCIeG3-  
PCIe Gen 3  
ps  
0.01  
(PLL BW of 2-4MHz or 2-5MHz, CDR = 10MHz)  
(rms)  
SRIS  
tjphPCIeG4-  
PCIe Gen 4  
ps  
(PLL BW of 2-4MHz or 2-5MHz, CDR = 10MHz)  
(rms)  
SRIS  
1 Applies to all outputs, when driven by 9SQL4958 or equivalent  
2 Preliminary based on PCIe Base Specification Rev3.1a. PCIe Gen4 is expected to remove the SRIS specifications. These filters are different than  
Common Clock filters. See http://www.pcisig.com for latest specifications.  
3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.  
4 For RMS values, additive jitter is calculated by solving the following equation for b [a^2+b^2=c^2] where a is rms input jitter and c is rms total  
Electrical Characteristics – Filtered Phase Jitter Parameters - QPI/UPI  
Over specified temperature and voltage ranges unless otherwise indicated. See Test Loads for Loading Conditions  
PARAMETER  
SYMBOL  
CONDITIONS  
QPI & SMI  
MIN  
TYP  
0.15  
MAX  
0.3  
IND.LIMIT  
0.5  
UNITS  
ps  
Notes  
1,2  
(100MHz or 133MHz, 4.8Gb/s, 6.4Gb/s 12UI)  
QPI & SMI  
(rms)  
ps  
Phase Jitter, PLL  
Mode  
tjphQPI_UPI  
0.08  
0.07  
0.12  
0.1  
0.3  
0.2  
1,2  
(100MHz, 8.0Gb/s, 12UI)  
QPI & SMI  
(rms)  
ps  
1,2  
(100MHz, 9.6Gb/s, 12UI)  
QPI & SMI  
(rms)  
ps  
0.009  
0.020  
0.016  
0.12  
0.07  
0.06  
1,2,3  
1,2,3  
1,2,3  
(100MHz or 133MHz, 4.8Gb/s, 6.4Gb/s 12UI)  
QPI & SMI  
(rms)  
ps  
AdditivePhase Jitter,  
tjphQPI_UPI  
n/a  
Bypass mode  
(100MHz, 8.0Gb/s, 12UI)  
QPI & SMI  
(rms)  
ps  
(100MHz, 9.6Gb/s, 12UI)  
(rms)  
1 Applies to all outputs, when driven by 9SQL4958 or equivalent  
2 Calculated from Intel-supplied Clock Jitter Tool v 1.6.6  
3 For RMS values additive jitter is calculated by solving the following equation for b [a^2+b^2=c^2] where a is rms input jitter and c is rms total jitter.  
19-OUTPUT DB1900Z FOR PCIE GEN1-4 AND QPI/UPI  
10  
APRIL 17, 2018  
9ZX21901D DATASHEET  
Electrical Characteristics – Unfiltered Phase Jitter Parameters - 12kHz to 20MHz  
Over specified temperature and voltage ranges unless otherwise indicated. See Test Loads for Loading Conditions  
PARAMETER  
Phase Jitter, PLL  
Mode  
SYMBOL  
tjph12k-20MHi  
CONDITIONS  
MIN  
161  
TYP  
178  
MAX  
198  
IND.LIMIT  
n/a  
UNITS  
fs  
Notes  
1,2  
PLL High BW, SSC OFF, 100MHz  
(rms)  
fs  
Phase Jitter, PLL  
Mode  
tjph12k-20MLo  
PLL Low BW, SSC OFF, 100MHz  
Bypass Mode, SSC OFF, 100MHz  
175  
104  
193  
104  
207  
110  
n/a  
n/a  
1,2  
(rms)  
fs  
AdditivePhase Jitter,  
Bypass mode  
tjph12k-20MByp  
1,2,3  
(rms)  
1 Applies to all outputs.  
2 12kHz to 20MHz brick wall filter.  
3 For RMS values additive jitter is calculated by solving the following equation for b [a^2+b^2=c^2] where a is rms input jitter and c is rms total jitter.  
Power Management Table  
Inputs  
Control Bits/Pins  
SMBus  
Outputs  
PLL  
DIF_IN/  
DIF_IN#  
State  
CKPWRGD_PD#  
EN bit  
OE# Pin  
DIF(5:12)  
Hi-Z1  
Hi-Z1  
Running  
Other DIF  
Hi-Z1  
Hi-Z1  
Running  
Running  
DFB_OUT  
Hi-Z1  
0
X
X
0
1
1
X
X
0
1
OFF  
ON  
ON  
ON  
Running  
Running  
Running  
1
Running  
Hi-Z1  
Due to external pull down resistors, HI-Z results in Low/Low on the True/Complement outputs  
NOTE: 1.  
Clock Periods – Differential Outputs with Spread Spectrum Disabled  
Measurement Window  
1 Clock  
1us  
0.1s  
0.1s  
0.1s  
1us  
1 Clock  
Center  
Freq.  
MHz  
-SSC  
- ppm  
+ ppm  
+SSC  
SSC OFF  
-c2c jitter  
AbsPer  
Min  
0 ppm  
Period  
+c2c jitter Units Notes  
Short-Term Long-Term  
Long-Term Short-Term  
AbsPer  
Max  
Average  
Min  
Average  
Min  
Average  
Max  
Average  
Max  
Nominal  
100.00  
133.33  
9.94900  
7.44925  
9.99900  
7.49925  
10.00000  
7.50000  
10.00100  
7.50075  
10.05100  
7.55075  
ns  
ns  
1,2,3  
1,2,4  
DIF  
Clock Periods – Differential Outputs with Spread Spectrum Enabled  
Measurement Window  
1 Clock  
1us  
0.1s  
0.1s  
0.1s  
1us  
1 Clock  
Center  
Freq.  
MHz  
-SSC  
- ppm  
+ ppm  
+SSC  
SSC ON  
-c2c jitter  
AbsPer  
Min  
0 ppm  
Period  
+c2c jitter Units Notes  
Short-Term Long-Term  
Long-Term Short-Term  
AbsPer  
Max  
Average  
Min  
Average  
Min  
Average  
Max  
Average  
Max  
Nominal  
99.75  
9.94906  
7.44930  
9.99906  
7.49930  
10.02406  
7.51805  
10.02506  
7.51880  
10.02607  
7.51955  
10.05107  
7.53830  
10.10107  
7.58830  
ns  
ns  
1,2,3  
1,2,4  
DIF  
133.00  
Notes:  
1Guaranteed by design and characterization, not 100% tested in production.  
2 All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with CK420BQ accuracy  
requirements (+/-100ppm). The device itself does not contribute to ppm error.  
3
Driven by SRC output of main clock, 100 MHz PLL Mode or Bypass mode  
4
Driven by CPU output of main clock, 133 MHz PLL Mode or Bypass mode  
APRIL 17, 2018  
11  
19-OUTPUT DB1900Z FOR PCIE GEN1-4 AND QPI/UPI  
9ZX21901D DATASHEET  
Test Loads  
9ZX21901D Characterization Test Loads  
10 inches  
Rs  
Differential Zo  
2pF  
2pF  
Rp  
Rp  
Rs  
HCSL Output  
Buffer  
Differential Output Termination Table  
Ω
Ω
Ω
DIF Zo ( ) Iref ( ) Rs ( )  
Ω
Rp ( )  
100  
85  
475  
412  
33  
27  
50  
42.2 or 43.2  
Alternate Terminations  
The 9ZX21901D can easily drive LVPECL, LVDS, CML, and SSTL logic. See “AN-891 Driving LVPECL, LVDS, CML, and SSTL  
Logic with IDT's "Universal" Low-Power HCSL Outputs” for details.  
19-OUTPUT DB1900Z FOR PCIE GEN1-4 AND QPI/UPI  
12  
APRIL 17, 2018  
9ZX21901D DATASHEET  
General SMBus Serial Interface Information  
(see also 9ZX21901 SMBus Addressing on page 2)  
How to Write  
How to Read  
• Controller (host) sends a start bit  
• Controller (host) will send a start bit  
• Controller (host) sends the write address XX(H)  
• IDT clock will acknowledge  
• Controller (host) sends the write address XX(H)  
• IDT clock will acknowledge  
• Controller (host) sends the beginning byte location = N  
• IDT clock will acknowledge  
• Controller (host) sends the beginning byte location = N  
• IDT clock will acknowledge  
• Controller (host) sends the byte count = X  
• IDT clock will acknowledge  
• Controller (host) will send a separate start bit  
• Controller (host) sends the read address YY(H)  
• IDT clock will acknowledge  
• Controller (host) starts sending Byte N through Byte  
N+X-1  
• IDT clock will send the data byte count = X  
• IDT clock sends Byte N+X-1  
• IDT clock will acknowledge each byte one at a time  
• Controller (host) sends a Stop bit  
• IDT clock sends Byte 0 through Byte X (if X was  
(H)  
written to Byte 8)  
• Controller (host) will need to acknowledge each byte  
• Controller (host) will send a not acknowledge bit  
• Controller (host) will send a stop bit  
Index Block Write Operation  
Index Block Read Operation  
Controller (Host)  
starT bit  
Slave Address  
IDT (Slave/Receiver)  
Controller (Host)  
starT bit  
IDT (Slave/Receiver)  
T
T
Slave Address  
WR  
WRite  
WR  
WRite  
ACK  
ACK  
ACK  
ACK  
ACK  
ACK  
Beginning Byte = N  
Data Byte Count = X  
Beginning Byte N  
Beginning Byte = N  
RT  
Repeat starT  
Slave Address  
ReaD  
RD  
ACK  
O
O
O
O
O
O
Data Byte Count=X  
Beginning Byte N  
ACK  
ACK  
Byte N + X - 1  
ACK  
O
O
O
P
stoP bit  
O
O
O
Note: XX is defined by SMBus Address select pins.  
Byte N + X - 1  
(H)  
N
P
Not acknowledge  
stoP bit  
APRIL 17, 2018  
13  
19-OUTPUT DB1900Z FOR PCIE GEN1-4 AND QPI/UPI  
9ZX21901D DATASHEET  
SMBusTable: PLL Mode, and Frequency Select Register  
Byte 0  
Bit 7  
Pin  
Name  
Control Function  
PLL Operating Mode Rd back 1  
PLL Operating Mode Rd back 0  
Output Enable  
Type  
R
0
See PLL Operating Mode  
1
Default  
Latch  
5
5
PLL Mode 1  
PLL Mode 0  
DIF_18_En  
DIF_17_En  
DIF_16_En  
Readback Table  
Latch  
1
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
R
72/71  
70/69  
67/66  
RW  
RW  
RW  
Hi-Z  
Hi-Z  
Hi-Z  
Enable  
Enable  
Enable  
Output Enable  
Output Enable  
1
1
0
Reserved  
Reserved  
0
Latch  
133MHz  
100MHz  
4
100M_133M#  
Frequency Select Readback  
R
SMBusTable: Output Control Register  
Byte 1  
Pin  
39/38  
Name  
Control Function  
Output Enable  
Output Enable  
Output Enable  
Output Enable  
Output Enable  
Output Enable  
Output Enable  
Output Enable  
Type  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
0
1
Default  
DIF_7_En  
DIF_6_En  
DIF_5_En  
DIF_4_En  
DIF_3_En  
DIF_2_En  
DIF_1_En  
DIF_0_En  
1
1
1
1
1
1
1
1
Bit 7  
OE# pin  
35/36  
32/33  
29/30  
27/28  
24/25  
22/23  
19/20  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
controlled  
Hi-Z  
Enable  
SMBusTable: Output Control Register  
Byte 2  
Pin  
65/64  
Name  
Control Function  
Output Enable  
Output Enable  
Output Enable  
Output Enable  
Output Enable  
Output Enable  
Output Enable  
Output Enable  
Type  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
0
1
Default  
DIF_15_En  
DIF_14_En  
DIF_13_En  
DIF_12_En  
DIF_11_En  
DIF_10_En  
DIF_9_En  
DIF_8_En  
1
1
1
1
1
1
1
1
Bit 7  
62/61  
60/59  
56/55  
53/52  
50/49  
47/46  
42/41  
Enable  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Hi-Z  
OE# pin  
controlled  
SMBusTable: Output Enable Pin Status Readback Register  
Byte 3  
Bit 7  
Pin  
57  
Name  
Control Function  
Type  
R
0
1
Default  
OE_RB12  
OE_RB11  
OE_RB10  
OE_RB9  
OE_RB8  
OE_RB7  
OE_RB6  
OE_RB5  
Real Time readback of OE#12  
Real Time readback of OE#11  
Real Time readback of OE#10  
Real Time readback of OE#9  
Real Time readback of OE#8  
Real Time readback of OE#7  
Real Time readback of OE#6  
Real Time readback of OE#5  
Real time  
Real time  
Real time  
Real time  
Real time  
Real time  
Real time  
Real time  
54  
51  
48  
43  
40  
37  
34  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
R
R
R
OE# pin Low OE# Pin High  
R
R
R
R
SMBusTable: PLL SW Override Control Register  
Byte 4  
Bit 7  
Pin  
Name  
Control Function  
Reserved  
Type  
0
1
Default  
0
0
0
0
0
0
0
0
Reserved  
Reserved  
Reserved  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Note:  
PLL_SW_EN  
PLL Mode 1  
PLL Mode 0  
Enable S/W control of PLL BW  
PLL Operating Mode 1  
PLL Operating Mode 1  
Reserved  
RW  
RW  
RW  
HW Latch  
See PLL Operating Mode  
Readback Table  
SMBus Control  
Setting bit 3 to '1' allows the user to override the Latch value from pin 4 via use of bits 2 and 1. Use the values from the  
PLL Operating Mode Readback Table. Note that Byte 0, Bits 7:6 will keep the value originally latched on pin 4. A warm reset of  
the system will have to be completed if the user changes these bits.  
19-OUTPUT DB1900Z FOR PCIE GEN1-4 AND QPI/UPI  
14  
APRIL 17, 2018  
9ZX21901D DATASHEET  
SMBusTable: Vendor & Revision ID Register  
Byte 5  
Bit 7  
Pin  
Name  
RID3  
RID2  
RID1  
RID0  
VID3  
VID2  
VID1  
VID0  
Control Function  
Type  
R
0
1
Default  
-
-
-
-
-
-
-
-
0
0
1
1
0
0
0
1
R
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
REVISION ID  
D rev = 0011  
R
R
R
-
-
-
-
-
-
-
-
R
VENDOR ID  
R
R
SMBusTable: DEVICE ID  
Byte 6 Pin  
Bit 7  
Name  
Control Function  
Device ID 7 (MSB)  
Type  
R
0
1
Default  
-
-
-
-
-
-
-
-
1
1
0
1
1
0
1
1
Device ID 6  
Device ID 5  
Device ID 4  
Device ID 3  
Device ID 2  
Device ID 1  
Device ID 0  
R
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
R
Device ID is 219 decimal or  
DB hex.  
R
R
R
R
R
SMBusTable: Byte Count Register  
Byte 7  
Bit 7  
Pin  
Name  
Control Function  
Reserved  
Type  
0
1
Default  
0
0
0
0
1
0
0
0
Reserved  
Reserved  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
-
-
-
-
-
BC4  
BC3  
BC2  
BC1  
BC0  
RW  
RW  
RW  
RW  
RW  
Default value is 8 hex, so 9  
bytes (0 to 8) will be read back  
by default.  
Writing to this register configures how  
many bytes will be read back.  
SMBusTable: Reserved Register  
Byte 8 Pin Name  
Bit 7  
Control Function  
Reserved  
Reserved  
Type  
0
1
Default  
0
0
0
0
0
0
0
0
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
APRIL 17, 2018  
15  
19-OUTPUT DB1900Z FOR PCIE GEN1-4 AND QPI/UPI  
9ZX21901D DATASHEET  
Package Outline Drawings  
The package outline drawings are appended at the end of this document and are accessible from the link below. The package  
information is the most current data available.  
www.idt.com/document/psc/nlnlg72-package-outline-100-x-100-mm-body-epad-59-mm-sq-050-mm-pitch-vfqfpn-sawn  
Thermal Characteristics  
Parameter  
Symbol Conditions Min. Typ. Max. Units  
θJA Still air  
θJA 1 m/s air flow  
θJA 3 m/s air flow  
θJC  
28.2  
21.6  
17.9  
14.4  
0.61  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
Thermal Resistance Junction to Ambient  
Thermal Resistance Junction to Case  
Thermal Resistance Junction to Board  
θJB  
Marking Diagram  
ICS  
9ZX21901DKLF  
LOT  
COO YYWW  
Notes:  
1. “LOT” is the lot sequence number.  
2. “COO” denotes country of origin.  
3. “YYWW” is the last two digits of the year and week that the part was assembled.  
4. “LF” denotes RoHS compliant package.  
Ordering Information  
Part / Order Number Shipping Package  
Package  
72-pin VFQFPN  
72-pin VFQFPN  
Temperature  
0 to +70°C  
0 to +70°C  
9ZX21901DKLF  
9ZX21901DKLFT  
Trays  
Tape and Reel  
"LF" designates PB-free configuration, RoHS compliant.  
"D" designates die revision and does not correlate to data sheet revision.  
19-OUTPUT DB1900Z FOR PCIE GEN1-4 AND QPI/UPI  
16  
APRIL 17, 2018  
Revision History  
Issue Date Description  
1. Updated electrical tables  
9/16/2016  
2. Move to Final  
10/5/2016 Changed IDD maximum value from 450 to 490mA  
1. Features change: "Hardware or software control of PLL operating mode; change mode with software mode does not need  
power cycle."  
2. Change Max of Powerdown Current IDDPD to 5mA.  
3. Input frequency of PLL mode:  
(1). Change Min of 100MHz to 98.5HMz and Max of 100MHz to 102MHz.  
(2). Change Max of 133.33MHz to 130.5MHz and Max of 133.33MHz to 135MHz.  
4. DIF HCSL/LP-HCSL Outputs:  
(1). Change Min of Max Voltage to 719mV and Max of Max Voltage to 842mV.  
(2). Change Min of (Crossing Voltage (abs)) to 310mV and Max of (Crossing Voltage (abs)) to 400mV.  
5. Change Typ of Cycle to cycle jitter of PLL mode to 17ps.  
2/15/2017  
6.Filtered Phase Jitter Parameters - PCIe Common Clocked  
(CC) Architectures"  
(1).Change Typ of additive phase jitter of bypass mode of PCIe Gen1 to 0.1.  
(2). Change Typ and max of additive phase jitter of bypass mode of PCIe Gen2 Lo Band to 0.1.  
(3). Change Typ and max of additive phase jitter of bypass mode of PCIe Gen3 to 0.1.  
(4). Change Typ and max of additive phase jitter of bypass mode of PCIe Gen4 to 0.1.  
7.Unfiltered Phase Jitter Parameters - 12kHz to 20MHz  
(1). Change Min,TYP and Max of PLLmode High BW to 161, 178, 198ps.  
(2). Change Min,TYP and Max of PLLmode Low BW to 175, 193, 207ps.  
(3). Change Min,TYP and Max of Bpmode to 104, 104, 110ps.  
12/1/2017 Removed “5V tolerant” reference in pins 12 and 13 descriptions.  
4/17/2018 Updated absolute maximum supply voltage rating and VIHSMB to 3.9V.  
Corporate Headquarters  
6024 Silver Creek Valley Road  
San Jose, CA 95138 USA  
www.IDT.com  
Sales  
Tech Support  
www.idt.com/go/support  
1-800-345-7015 or 408-284-8200  
Fax: 408-284-2775  
www.IDT.com/go/sales  
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications described herein at any time, without  
notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed  
in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any  
particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intel-  
lectual property rights of IDT or any third parties.  
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably  
expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.  
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of  
IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Integrated Device Technology, Inc. All rights reserved.  
9ZX21901D APRIL 17, 2018  
17  
©2018 Integrated Device Technology, Inc.  
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