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9ZXL1252EKILF

型号：

9ZXL1252EKILF

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

21 页

PDF大小：

254 K

下载PDF手册
12-Output DB1200ZL Derivative  
for PCIe Gen1–4 and UPI with  
Write Lock  
9ZXL1232E / 9ZXL1252E  
Datasheet  
Description  
Features  
▪ SMBus write lock feature; increases system security  
▪ LP-HCSL outputs; eliminate 24 resistors, save 41mm2 of area  
The 9ZXL1232E / 9ZXL1252E are second-generation,  
enhanced-performance DB1200ZL differential buffers. The parts  
are pin-compatible upgrades to the 9ZXL1232A and 9ZLX1252A,  
while offering a much improved phase jitter performance and an  
SMBus Write Lock feature for increased system security. A fixed  
external feedback maintains low drift for critical QPI/UPI  
applications. The 9ZXL1232E and 9ZXL1252E have an SMBus  
Write Lockout pin for increased device and system security.  
(1232E)  
▪ LP-HCSL outputs with 85Ω Zout; eliminate 48 resistors, save  
82mm2 of area (1252E)  
▪ 12 OE# pins; hardware control of each output  
▪ 9 selectable SMBus addresses; multiple devices can share the  
same SMBus segment  
▪ Selectable PLL BW; minimizes jitter peaking in cascaded PLL  
PCIe Clocking Architectures  
Supported  
topologies  
▪ Hardware/SMBus control of PLL bandwidth and bypass;  
▪ Common Clocked (CC)  
change mode without power cycle  
▪ Independent Reference (IR) with and without spread spectrum  
▪ Spread spectrum compatible; tracks spreading input clock for  
EMI reduction  
▪ 100MHz & 133.33MHz PLL mode; UPI and legacy QPI support  
▪ 9 x 9 mm 64-QFN package; small board footprint  
Typical Applications  
▪ Servers  
▪ Storage  
▪ Networking  
▪ SSDs  
Key Specifications  
▪ Cycle-to-cycle jitter < 50ps  
▪ Output-to-output skew < 50ps  
▪ Input-to-output delay: Fixed at 0ps  
▪ Input-to-output delay variation < 50ps  
▪ Phase jitter: PCIe Gen4 < 0.5ps rms  
▪ Phase jitter: QPI/UPI > = 9.6GB/s < 0.2ps rms  
▪ Phase jitter: IF-UPI < 1.0ps rms  
Output Features  
▪ 12 Low-Power (LP) HCSL output pairs (1232E)  
▪ 12 Low-Power (LP) HCSL output pairs with 85Ω Zout (1252E)  
Block Diagram  
VDDR  
VDDA  
VDD x3  
VDDIO x4  
FBOUT_NC#  
FBOUT_NC  
PLL  
DIF_IN#  
DIF_IN  
DIF11#  
DIF11  
^100M_133M#  
vSADR[1:0]_tri  
SMBCLK  
12  
outputs  
SMBus  
Engine Configuration  
Factory  
SMBDAT  
vSMB_WRTLOCK  
DIF0#  
DIF0  
^vHIBW_BYPM-LOBW#  
^CKPWRGD_PD#  
vOE[11:0]#  
Control Logic  
Resistors are integrated on 9ZXL125x devices and  
external on 9ZXL123x devices  
GNDA  
GND x7  
©2018 Integrated Device Technology, Inc  
1
August 14, 2018  
 
 
 
 
 
 
 
9ZXL1232E / 9ZXL1252E Datasheet  
Contents  
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
PCIe Clocking Architectures Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Output Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Key Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
Clock Periods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Power Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Functionality at Power-Up (PLL Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
PLL Operating Mode Readback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
PLL Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
SMBus Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Test Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Alternate Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
General SMBus Serial Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
How to Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
How to Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Package Outline Drawings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
Marking Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
©2018 Integrated Device Technology, Inc  
2
August 14, 2018  
9ZXL1232E / 9ZXL1252E Datasheet  
Pin Configuration  
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49  
VDDA 1  
GNDA 2  
48 GND  
47 DIF7#  
46 DIF7  
45 vOE7#  
44 vOE6#  
43 DIF6#  
42 DIF6  
41 GND  
40 VDD  
vSMB_WRTLOCK 3  
^100M_133M# 4  
^HIBW_BYPM_LOBW# 5  
^CKPWRGD_PD# 6  
GND 7  
9ZXL1232  
9ZXL1252  
VDDR 8  
DIF_IN 9  
connect EPAD to ground  
DIF_IN# 10  
39 DIF5#  
38 DIF5  
37 vOE5#  
36 vOE4#  
35 DIF4#  
34 DIF4  
33 GND  
vSADR0_tri 11  
SMBDAT 12  
SMBCLK 13  
vSADR1_tri 14  
FBOUT_NC# 15  
FBOUT_NC 16  
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32  
9 x 9 mm 64-VFQFPN  
Note: Pins with ^ prefix have internal 120kohm pull-up  
Pins with v prefix have internal 120kohm pull-down  
Pin Descriptions  
Table 1. Pin Descriptions  
Number  
Name  
Type  
Description  
1
2
VDDA  
GNDA  
Power  
GND  
Power supply for PLL core.  
Ground pin for the PLL core.  
This pin prevents SMBus writes when asserted. SMBus reads are not affected. This pin  
has an internal 120kΩ pull-down.  
3
vSMB_WRTLOCK  
Input  
0 = SMBus writes allows, 1 = SMBus writes blocked.  
3.3V input to select operating frequency. This pin has an internal 120kΩ pull-up  
resistor. See Functionality at Power-Up table for definition.  
4
5
^100M_133M#  
Latched In  
Latched In  
Tri-level input to select High BW, Bypass or Low BW Mode. Has an internal 120kΩ  
pull-up resistor. See PLL Operating Mode table for details.  
^HIBW_BYPM_LOBW#  
Input notifies device to sample latched inputs and start up on first high assertion. Low  
enters Power Down Mode, subsequent high assertions exit Power Down Mode. This  
pin has internal 120kΩ pull-up resistor.  
6
^CKPWRGD_PD#  
Input  
7
8
GND  
GND  
Ground pin.  
Power supply for differential input clock (receiver). This V should be treated as an  
analog power rail and filtered appropriately. Nominally 3.3V.  
DD  
VDDR  
Power  
9
DIF_IN  
Input  
Input  
HCSL true input.  
10  
DIF_IN#  
HCSL complementary input.  
©2018 Integrated Device Technology, Inc  
3
August 14, 2018  
9ZXL1232E / 9ZXL1252E Datasheet  
Table 1. Pin Descriptions (Cont.)  
Number  
Name  
Type  
Description  
SMBus address bit. This is a tri-level input that works in conjunction with other SADR  
pins, if present, to decode SMBus addresses. It has an internal 120kΩ pull-down  
resistor. See the SMBus Addressing table.  
11  
vSADR0_tri  
Input  
12  
13  
SMBDAT  
SMBCLK  
I/O  
Data pin of SMBUS circuitry.  
Clock pin of SMBUS circuitry.  
Input  
SMBus address bit. This is a tri-level input that works in conjunction with other SADR  
pins, if present, to decode SMBus addresses. It has an internal 120kΩ pull-down  
resistor. See the SMBus Addressing table.  
14  
vSADR1_tri  
Input  
Complementary half of differential feedback output. This pin should NOT be connected  
to anything outside the chip. It exists to provide delay path matching to get 0  
propagation delay.  
15  
16  
FBOUT_NC#  
FBOUT_NC  
Output  
Output  
True half of differential feedback output. This pin should NOT be connected to anything  
outside the chip. It exists to provide delay path matching to get 0 propagation delay.  
17  
18  
DIF0  
Output  
Output  
Differential true clock output.  
DIF0#  
Differential complementary clock output.  
Active low input for enabling output 0. This pin has an internal 120kΩ pull-down.  
19  
20  
vOE0#  
vOE1#  
Input  
Input  
1 = disable outputs, 0 = enable outputs.  
Active low input for enabling output 1. This pin has an internal 120kΩ pull-down.  
1 = disable outputs, 0 = enable outputs.  
21  
22  
23  
24  
25  
26  
27  
DIF1  
DIF1#  
GND  
Output  
Output  
GND  
Differential true clock output.  
Differential complementary clock output.  
Ground pin.  
VDD  
Power  
Power  
Output  
Output  
Power supply, nominally 3.3V.  
Power supply for differential outputs.  
Differential true clock output.  
Differential complementary clock output.  
VDDIO  
DIF2  
DIF2#  
Active low input for enabling output 2. This pin has an internal 120kΩ pull-down.  
28  
29  
vOE2#  
vOE3#  
Input  
Input  
1 = disable outputs, 0 = enable outputs.  
Active low input for enabling output 3. This pin has an internal 120kΩ pull-down.  
1 = disable outputs, 0 = enable outputs.  
30  
31  
32  
33  
34  
35  
DIF3  
DIF3#  
VDDIO  
GND  
Output  
Output  
Power  
GND  
Differential true clock output.  
Differential complementary clock output.  
Power supply for differential outputs.  
Ground pin.  
DIF4  
Output  
Output  
Differential true clock output.  
Differential complementary clock output.  
DIF4#  
Active low input for enabling output 4. This pin has an internal 120kΩ pull-down.  
36  
vOE4#  
Input  
1 = disable outputs, 0 = enable outputs.  
©2018 Integrated Device Technology, Inc  
4
August 14, 2018  
9ZXL1232E / 9ZXL1252E Datasheet  
Table 1. Pin Descriptions (Cont.)  
Number  
Name  
Type  
Description  
Active low input for enabling output 5. This pin has an internal 120kΩ pull-down.  
37  
vOE5#  
Input  
1 = disable outputs, 0 = enable outputs.  
38  
39  
40  
41  
42  
43  
DIF5  
DIF5#  
VDD  
Output  
Output  
Power  
GND  
Differential true clock output.  
Differential complementary clock output.  
Power supply, nominally 3.3V.  
Ground pin.  
GND  
DIF6  
Output  
Output  
Differential true clock output.  
Differential complementary clock output.  
DIF6#  
Active low input for enabling output 6. This pin has an internal 120kΩ pull-down.  
44  
45  
vOE6#  
vOE7#  
Input  
Input  
1 = disable outputs, 0 = enable outputs.  
Active low input for enabling output 7. This pin has an internal 120kΩ pull-down.  
1 = disable outputs, 0 = enable outputs.  
46  
47  
48  
49  
50  
51  
DIF7  
DIF7#  
GND  
Output  
Output  
GND  
Differential true clock output.  
Differential complementary clock output.  
Ground pin.  
VDDIO  
DIF8  
Power  
Output  
Output  
Power supply for differential outputs.  
Differential true clock output.  
Differential complementary clock output.  
DIF8#  
Active low input for enabling output 8. This pin has an internal 120kΩ pull-down.  
52  
53  
vOE8#  
vOE9#  
Input  
Input  
1 = disable outputs, 0 = enable outputs.  
Active low input for enabling output 9. This pin has an internal 120kΩ pull-down.  
1 = disable outputs, 0 = enable outputs.  
54  
55  
56  
57  
58  
59  
60  
DIF9  
DIF9#  
VDDIO  
VDD  
Output  
Output  
Power  
Power  
GND  
Differential true clock output.  
Differential complementary clock output.  
Power supply for differential outputs.  
Power supply, nominally 3.3V.  
Ground pin.  
GND  
DIF10  
DIF10#  
Output  
Output  
Differential true clock output.  
Differential complementary clock output.  
Active low input for enabling output 10. This pin has an internal 120kΩ pull-down.  
61  
62  
vOE10#  
vOE11#  
Input  
Input  
1 = disable outputs, 0 = enable outputs.  
Active low input for enabling output 11. This pin has an internal 120kΩ pull-down.  
1 = disable outputs, 0 = enable outputs.  
63  
64  
65  
DIF11  
DIF11#  
EPAD  
Output  
Output  
GND  
Differential true clock output.  
Differential complementary clock output.  
Connect EPAD to ground.  
©2018 Integrated Device Technology, Inc  
5
August 14, 2018  
9ZXL1232E / 9ZXL1252E Datasheet  
Absolute Maximum Ratings  
Stresses above the ratings listed below can cause permanent damage to the 9ZXL1232E / 9ZXL1252E. These ratings, which are  
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other  
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating  
conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating  
temperature range.  
Table 2. Absolute Maximum Ratings  
Parameter  
Symbol  
Conditions  
Minimum  
Typical  
Maximum Units Notes  
Supply Voltage  
Input Voltage  
VDDx  
3.9  
+0.5  
V
V
1,2  
1,3  
1
V
-0.5  
-65  
V
IN  
DD  
Input High Voltage, SMBus  
Storage Temperature  
Junction Temperature  
Input ESD Protection  
V
SMBus clock and data pins.  
3.9  
150  
125  
V
IHSMB  
Ts  
°C  
°C  
V
1
Tj  
1
ESD prot Human Body Model.  
2500  
1
1 Guaranteed by design and characterization, not 100% tested in production.  
2 Operation under these conditions is neither implied nor guaranteed.  
3 Not to exceed 3.9V.  
Electrical Characteristics  
TA = TAMB. Supply voltages per normal operation conditions; see Test Loads for loading conditions.  
Table 3. SMBus Parameters  
Parameter  
Symbol  
Conditions  
Minimum Typical  
Maximum Units Notes  
SMBus Input Low Voltage  
SMBus Input High Voltage  
SMBus Output Low Voltage  
SMBus Sink Current  
V
0.8  
V
V
ILSMB  
V
2.1  
V
DDSMB  
IHSMB  
V
At I  
0.4  
V
OLSMB  
PULLUP  
PULLUP.  
I
At V  
4
mA  
V
OL.  
Nominal Bus Voltage  
V
2.7  
3.6  
1000  
300  
1
1
1
5
DDSMB  
SCLK/SDATA Rise Time  
SCLK/SDATA Fall Time  
SMBus Operating Frequency  
t
(Max V - 0.15V) to (Min V + 0.15V).  
ns  
ns  
kHz  
RSMB  
IL  
IH  
t
(Min V + 0.15V) to (Max V - 0.15V).  
IH IL  
FSMB  
f
SMBus operating frequency.  
400  
SMB  
1 Guaranteed by design and characterization, not 100% tested in production.  
2 Control input must be monotonic from 20% to 80% of input swing.  
3 Time from deassertion until outputs are > 200mV.  
4 DIF_IN input.  
5 The differential input clock must be running for the SMBus to be active.  
©2018 Integrated Device Technology, Inc  
6
August 14, 2018  
9ZXL1232E / 9ZXL1252E Datasheet  
Table 4. DIF_IN Clock Input Parameters  
Parameter  
Symbol  
Conditions  
Cross over voltage.  
Minimum Typical Maximum Units Notes  
Input Crossover Voltage – DIF_IN  
Input Swing – DIF_IN  
V
150  
300  
0.4  
-5  
900  
mV  
mV  
V/ns  
μA  
1
1
CROSS  
V
Differential value.  
SWING  
Input Slew Rate – DIF_IN  
Input Leakage Current  
Input Duty Cycle  
dv/dt  
Measured differentially.  
8
5
1,2  
I
V
= V  
V = GND.  
DD , IN  
IN  
IN  
d
Measurement from differential waveform.  
Differential measurement.  
45  
0
55  
125  
%
1
1
tin  
Input Jitter – Cycle to Cycle  
J
ps  
DIFIn  
1 Guaranteed by design and characterization, not 100% tested in production.  
2 Slew rate measured through ±75mV window centered around differential zero.  
Table 5. Input/Supply/Common Parameters  
TAMB = over the specified operating range. Supply voltages per normal operation conditions; see Test Loads for loading conditions.  
Parameter  
Symbol  
Conditions  
Minimum  
Typical Maximum Units Notes  
Supply Voltage  
V
x
Supply voltage for core and analog.  
3.135  
0.95  
0
3.3  
3.465  
3.465  
70  
V
V
DD  
Output Supply Voltage  
V
Supply voltage for DIF outputs, if present.  
1.05  
DDIO  
Commercial range (T  
).  
°C  
°C  
COM  
Ambient Operating  
Temperature  
T
AMB  
Industrial range (T ).  
-40  
25  
85  
IND  
Single-ended inputs, except SMBus, tri-level  
inputs.  
Input High Voltage  
Input Low Voltage  
V
2
V
V
+ 0.3  
DD  
V
V
IH  
Single-ended inputs, except SMBus, tri-level  
inputs.  
V
GND - 0.3  
0.8  
+ 0.3  
IL  
Input High Voltage  
Input Mid Voltage  
Input Low Voltage  
V
Tri-level inputs.  
Tri-level inputs.  
Tri-level inputs.  
2.2  
1.2  
V
V
IH  
DD  
V
V
V
/2  
1.8  
IL  
IL  
DD  
GND - 0.3  
-5  
0.8  
5
V
I
Single-ended inputs, V = GND, V = V  
DD.  
μA  
IN  
IN  
IN  
Single-ended inputs.  
Input Current  
V
= 0 V; inputs with internal pull-up resistors.  
IN  
I
-50  
50  
μA  
INP  
V
= V ; inputs with internal pull-down  
IN  
DD  
resistors.  
F
V
V
V
= 3.3V, Bypass Mode.  
1
400  
102.5  
135  
7
MHz  
MHz  
MHz  
nH  
ibyp  
DD  
DD  
DD  
Input Frequency  
Pin Inductance  
Capacitance  
F
= 3.3V, 100MHz PLL Mode.  
= 3.3V, 133.33MHz PLL Mode.  
98.5  
132  
100.00  
133.33  
ipll  
ipll  
pin  
F
L
1
1
C
Logic inputs, except DIF_IN.  
DIF_IN differential clock inputs.  
Output pin capacitance.  
1.5  
1.5  
5
pF  
IN  
INDIF_IN  
C
2.7  
6
pF  
1,4  
1
C
pF  
OUT  
©2018 Integrated Device Technology, Inc  
7
August 14, 2018  
9ZXL1232E / 9ZXL1252E Datasheet  
Table 5. Input/Supply/Common Parameters (Cont.)  
TAMB = over the specified operating range. Supply voltages per normal operation conditions; see Test Loads for loading conditions.  
Parameter  
Symbol  
Conditions  
Minimum  
Typical Maximum Units Notes  
From V power-up and after input clock  
stabilization or deassertion of PD# to 1st clock.  
DD  
Clk Stabilization  
T
1
1.8  
33  
10  
ms  
1,2  
STAB  
Input SS Modulation  
Frequency PCIe  
Allowable frequency for PCIe applications  
(Triangular modulation).  
f
30  
4
kHz  
MODINPCIe  
DIF start after OE# assertion.  
DIF stop after OE# deassertion.  
OE# Latency  
t
5
clocks 1,2,3  
LATOE#  
Tdrive_PD#  
Tfall  
t
DIF output enable after PD# deassertion.  
Fall time of control inputs.  
49  
300  
5
μs  
ns  
ns  
1,3  
2
DRVPD  
t
F
Trise  
t
Rise time of control inputs.  
5
2
R
1 Guaranteed by design and characterization, not 100% tested in production.  
2 Control input must be monotonic from 20% to 80% of input swing.  
3 Time from deassertion until outputs are > 200mV.  
4 DIF_IN input.  
Table 6. Current Consumption  
Parameter  
Symbol  
Conditions  
Minimum  
Typical  
Maximum Units Notes  
I
V
, PLL Mode at 100MHz.  
DDA  
38  
25  
46  
34  
107  
4
mA  
mA  
mA  
mA  
mA  
1
DDA  
Operating Supply  
Current  
I
All other V pins.  
DD  
DD  
I
V
V
for LP-HCSL outputs, if applicable.  
DDIO  
83  
DDOIO  
I
, CKPWRGD_PD# = 0.  
DDA  
3.3  
1.3  
1
DDAPD  
Power Down  
Current  
I
All other V pins, CKPWRGD_PD# = 0.  
2
DDPD  
DD  
1 Includes VDDR if applicable.  
Table 7. Skew and Differential Jitter Parameters  
TAMB = over the specified operating range. Supply voltages per normal operation conditions; see Test Loads for loading conditions.  
Parameter  
Symbol  
Conditions  
Minimum Typical Maximum Units Notes  
Input-to-output skew in PLL Mode at 100MHz, nominal  
temperature and voltage.  
1,2,4,5  
,8  
CLK_IN, DIF[x:0]  
t
-100  
2.5  
-21.3  
2.6  
100  
4.5  
50  
ps  
ns  
ps  
SPO_PLL  
Input-to-output skew in Bypass Mode at 100MHz,  
nominal temperature and voltage.  
1,2,3,5  
,8  
CLK_IN, DIF[x:0]  
CLK_IN, DIF[x:0]  
t
PD_BYP  
Input-to-output skew variation in PLL Mode at 100MHz,  
across voltage and temperature.  
1,2,3,5  
,8  
t
-50  
0.0  
DSPO_PLL  
©2018 Integrated Device Technology, Inc  
8
August 14, 2018  
9ZXL1232E / 9ZXL1252E Datasheet  
Table 7. Skew and Differential Jitter Parameters (Cont.)  
TAMB = over the specified operating range. Supply voltages per normal operation conditions; see Test Loads for loading conditions.  
Parameter  
Symbol  
Conditions  
Minimum Typical Maximum Units Notes  
Input-to-output skew variation in Bypass Mode at  
100MHz, across voltage and temperature,  
1,2,3,5  
,8  
-250  
-350  
250  
350  
ps  
ps  
T
= 0 to 70°C.  
AMB  
CLK_IN, DIF[x:0]  
t
DSPO_BYP  
Input-to-output skew variation in Bypass Mode at  
100MHz, across voltage and temperature,  
1,2,3,5  
,8  
T
= -40 to +85°C.  
AMB  
ps  
Random differential tracking error between two 9ZX  
devices in High BW Mode.  
1,2,3,5  
,8  
CLK_IN, DIF[x:0]  
CLK_IN, DIF[x:0]  
DIF[x:0]  
t
3
5
DTE  
(rms)  
Random differential spread spectrum tracking error  
between two 9ZX devices in High BW Mode.  
1,2,3,5  
,8  
t
23  
50  
50  
ps  
DSSTE  
Output-to-output skew across all outputs, common to  
PLL and Bypass Mode, at 100MHz.  
t
ps 1,2,3,8  
SKEW_ALL  
PLL Jitter Peaking  
PLL Jitter Peaking  
PLL Bandwidth  
j
j
LOBW#_BYPASS_HIBW = 1.  
LOBW#_BYPASS_HIBW = 0.  
LOBW#_BYPASS_HIBW = 1.  
LOBW#_BYPASS_HIBW = 0.  
Measured differentially, PLL Mode.  
Measured differentially, Bypass Mode at 100MHz.  
PLL Mode.  
0
0
1.3  
1.3  
2.6  
1.0  
50.3  
0
2.5  
2
dB  
dB  
7,8  
7,8  
peak-hibw  
peak-lobw  
pll  
2
4
MHz  
MHz  
%
8,9  
HIBW  
PLL Bandwidth  
pll  
0.7  
45  
-1  
1.4  
55  
1
8,9  
LOBW  
Duty Cycle  
t
1
DC  
Duty Cycle Distortion  
t
%
1,10  
1,11  
1,11  
DCD  
14  
50  
5
ps  
Jitter, Cycle to Cycle  
t
jcyc-cyc  
Additive jitter in Bypass Mode.  
0.1  
ps  
1 Measured into fixed 2pF load cap. Input to output skew is measured at the first output edge following the corresponding input.  
2 Measured from differential cross-point to differential cross-point. This parameter can be tuned with external feedback path, if present.  
3 All Bypass Mode input-to-output specs refer to the timing between an input edge and the specific output edge created by it.  
4 This parameter is deterministic for a given device.  
5 Measured with scope averaging on to find mean value.  
6 “t” is the period of the input clock.  
7 Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL jitter peaking.  
8 Guaranteed by design and characterization, not 100% tested in production.  
9 Measured at 3db down or half power point.  
10 Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in Bypass Mode.  
11 Measured from differential waveform.  
©2018 Integrated Device Technology, Inc  
9
August 14, 2018  
9ZXL1232E / 9ZXL1252E Datasheet  
Table 8. HCSL/LP-HCSL Outputs  
TAMB = over the specified operating range. Supply voltages per normal operation conditions; see Test Loads for loading conditions.  
Specification  
Parameter  
Symbol  
Conditions  
Minimum Typical Maximum  
Limits  
Units Notes  
Slew Rate  
dV/dt  
ΔdV/dt  
Vmax  
Scope averaging on.  
2
2.9  
7.1  
792  
4
1–4  
20  
V/ns 1,2,3  
Slew Rate Matching  
Maximum Voltage  
Single-ended measurement.  
20  
%
1,4,7  
7
Measurement on single-ended  
signal using absolute value  
(scope averaging off).  
660  
-150  
250  
850  
1150  
mV  
Minimum Voltage  
Vmin  
-35  
150  
-300  
7
Crossing Voltage (abs) Vcross_abs  
Crossing Voltage (var) Δ-Vcross  
Scope averaging off.  
Scope averaging off.  
372  
15  
550  
140  
250–550  
140  
mV  
mV  
1,5,7  
1,6,7  
1 Guaranteed by design and characterization, not 100% tested in production.  
2 Measured from differential waveform.  
3 Slew rate is measured through the Vswing voltage range centered around differential 0 V. This results in a ±150mV window around differential 0V.  
4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a ±75mV window centered on the average  
cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use  
for the edge rate calculations.  
5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e. Clock  
rising and Clock# falling).  
6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross absolute) allowed.  
The intent is to limit Vcross induced modulation by setting Δ-Vcross to be smaller than Vcross absolute.  
7 At default SMBus settings.  
Table 9. Filtered Phase Jitter Parameters - PCIe Common Clocked (CC) Architectures  
Specification  
Parameter  
Symbol  
Conditions  
Minimum Typical Maximum  
Limits  
Units Notes  
ps  
t
t
PCIe Gen 1.  
13.4  
30  
86  
1,2,3  
(p-p)  
jphPCIeG1-CC  
PCIe Gen 2 Low Band.  
10kHz < f < 1.5MHz  
ps  
1,2  
0.2  
0.7  
3
(rms)  
(PLL BW of 5–16MHz or 8–16MHz,  
CDR = 5MHz).  
jphPCIeG2-CC  
PCIe Gen 2 High Band.  
ps  
1,2  
Phase Jitter, PLL  
Mode  
1.5MHz < f < Nyquist (50MHz)  
1.0  
1.5  
3.1  
(rms)  
(PLL BW of 5–16MHz or 8–16MHz,  
CDR = 5MHz).  
PCIe Gen 3.  
ps  
1,2  
t
t
0.2  
0.2  
0.4  
0.4  
1
(PLL BW of 2–4MHz or 2–5MHz, CDR  
= 10MHz).  
jphPCIeG3-CC  
jphPCIeG4-CC  
(rms)  
PCIe Gen 4.  
ps  
1,2  
0.5  
(PLL BW of 2–4MHz or 2–5MHz, CDR  
= 10MHz).  
(rms)  
©2018 Integrated Device Technology, Inc  
10  
August 14, 2018  
9ZXL1232E / 9ZXL1252E Datasheet  
Table 9. Filtered Phase Jitter Parameters - PCIe Common Clocked (CC) Architectures (Cont.)  
Specification  
Limits  
Parameter  
Symbol  
Conditions  
Minimum Typical Maximum  
Units Notes  
ps  
t
t
PCIe Gen 1.  
0.01  
0.06  
1,2,3,4  
(p-p)  
jphPCIeG1-CC  
PCIe Gen 2 Low Band.  
10kHz < f < 1.5MHz  
ps  
0.01  
0.06  
1,2,3,4  
(rms)  
(PLL BW of 5–16MHz or 8–16MHz,  
CDR = 5MHz).  
jphPCIeG2-CC  
PCIe Gen 2 High Band.  
Additive Phase  
Jitter, Bypass  
Mode  
ps  
1.5MHz < f < Nyquist (50MHz)  
Not  
Applicable  
0.01  
0.06  
1,2,3,4  
(rms)  
(PLL BW of 5–16MHz or 8–16MHz,  
CDR = 5MHz).  
PCIe Gen 3.  
ps  
t
t
0.01  
0.01  
0.06  
0.06  
1,2,3,4  
(rms)  
(PLL BW of 2–4MHz or 2–5MHz, CDR  
= 10MHz).  
jphPCIeG3-CC  
jphPCIeG4-CC  
PCIe Gen 4.  
ps  
1,2,3,4  
(rms)  
(PLL BW of 2–4MHz or 2–5MHz, CDR  
= 10MHz).  
Table 10. Filtered Phase Jitter Parameters – PCIe Independent Reference (IR) Architectures  
Industry  
Limits  
Parameter  
Symbol  
Conditions  
Minimum Typical Maximum  
Units Notes  
PCIe Gen 2.  
ps  
t
t
t
t
0.9  
0.6  
1.1  
2
1,2,5  
(rms)  
jphPCIeG2-SRIS  
(PLL BW of 16MHz, CDR = 5MHz).  
Phase Jitter,  
PLL Mode  
PCIe Gen 3.  
ps  
0.65  
0.05  
0.05  
0.7  
1,2,5  
(rms)  
jphPCIeG3-SRIS  
jphPCIeG2-SRIS  
jphPCIeG3-SRIS  
(PLL BW of 2–4MHz, CDR = 10MHz).  
PCIe Gen 2.  
ps  
0.01  
0.01  
2,4,5  
(rms)  
Additive Phase  
Jitter, Bypass  
Mode  
(PLL BW of 16MHz, CDR = 5MHz).  
Not  
applicable  
PCIe Gen 3.  
ps  
2,4,5  
(rms)  
(PLL BW of 2–4MHz, CDR = 10MHz).  
Notes for PCIe Filtered Phase Jitter tables (CC) and (IR).  
1 Applies to all differential outputs, guaranteed by design and characterization.  
2 Calculated from Intel-supplied clock jitter tool when driven by 9SQL495x or equivalent with spread on and off.  
3 Sample size of at least 100K cycles. This figure extrapolates to 108ps pk-pk at 1M cycles for a BER of 1–12  
4 For RMS values, additive jitter is calculated by solving for b [b = sqrt(c2 - a2)] where “a” is rms input jitter and “c” is rms total jitter.  
.
5 IR is the new name for Separate Reference Independent Spread (SRIS) and Separate Reference no Spread (SRNS) PCIe clock architectures.  
According to the PCIe Base Specification Rev4.0 version 0.7 draft, the jitter transfer functions and corresponding jitter limits are not defined for the  
IR clock architecture. Widely accepted industry limits using widely accepted industry filters are used to populate this table. There are no accepted  
filters or limits for IR clock architectures at PCIe Gen1 or Gen4 data rates.  
©2018 Integrated Device Technology, Inc  
11  
August 14, 2018  
9ZXL1232E / 9ZXL1252E Datasheet  
Table 11. Filtered Phase Jitter Parameters – QPI/UPI  
Specification  
Parameter  
Symbol  
Conditions  
Minimum Typical Maximum  
Limits  
Units Notes  
QPI & UPI.  
0.14  
0.07  
0.06  
0.3  
0.13  
0.1  
0.5  
1,2  
(100MHz or 133MHz, 4.8Gb/s, 6.4Gb/s 12UI).  
QPI & UPI.  
t
0.3  
0.2  
1
1,2  
ps  
jphQPI_UPI  
(100MHz, 8.0Gb/s, 12UI).  
Phase Jitter,  
PLL Mode  
(rms)  
1,2  
QPI & UPI.  
(100MHz, > 9.6Gb/s, 12UI).  
0.1  
0.17  
0.14  
0.2  
t
IF-UPI.  
1,4,5  
1,2,3  
jphIF-UPI  
QPI & UPI.  
0.00  
0.00  
0.01  
0.01  
(100MHz or 133MHz, 4.8Gb/s, 6.4Gb/s 12UI).  
QPI & UPI.  
Additive  
Phase Jitter,  
Bypass Mode  
t
1,2,3  
ps  
jphQPI_UPI  
(100MHz, 8.0Gb/s, 12UI).  
Not applicable  
(rms)  
QPI & UPI.  
0.00  
0.06  
0.01  
0.07  
1,2,3  
1,4  
(100MHz, > 9.6Gb/s, 12UI).  
t
IF-UPI.  
jphIF-UPI  
1 Applies to all differential outputs, guaranteed by design and characterization.  
2 Calculated from Intel-supplied clock jitter tool, when driven by 9SQL495x or equivalent with spread on and off.  
3 For RMS values, additive jitter is calculated by solving for b [b = sqrt(c2 - a2)] where “a” is rms input jitter and “c” is rms total jitter.  
4 Calculated from phase noise analyzer when driven by Wenzel Associates source with Intel-specified brick-wall filter applied.  
5 Top number is when the buffer is in Low BW mode, bottom number is when the buffer is in High BW mode.  
Table 12. Unfiltered Phase Jitter Parameters – 12kHz to 20MHz  
Industry  
Limits  
Parameter  
Symbol  
Conditions  
Minimum  
Typical  
Maximum  
Units Notes  
fs  
Phase Jitter, PLL  
Mode  
PLL High BW, SSC Off,  
100MHz.  
t
171  
225  
1,2  
jph12k-20MHi  
(rms)  
fs  
Phase Jitter, PLL  
Mode  
PLL Low BW, SSC Off,  
100MHz.  
Not  
applicable  
t
184  
107  
225  
125  
1,2  
jph12k-20MLo  
(rms)  
fs  
Additive Phase Jitter,  
Bypass Mode, SSC Off,  
100MHz.  
t
1,2,3  
(rms)  
jph12k-20MByp  
Bypass Mode  
1 Applies to all outputs when driven by Wenzel clock source.  
2 12kHz to 20MHz brick wall filter.  
3 For RMS values, additive jitter is calculated by solving for b [b = sqrt(c2 - a2)] where “a” is rms input jitter and “c” is rms total jitter.  
©2018 Integrated Device Technology, Inc  
12  
August 14, 2018  
9ZXL1232E / 9ZXL1252E Datasheet  
Clock Periods  
Table 13. Clock Periods – Differential Outputs w ith Spread Spectrum Disabled  
Measurement Window  
1 Clock  
1μs  
0.1s  
0.1s  
0.1s  
1μs  
1 Clock  
- S S C  
- p p m  
+ p p m  
Long-Term  
Average  
+ S S C  
Short-Term  
Average  
Center  
Frequency  
MHz  
-c2cjitter  
AbsPer  
Minimum  
Short-Term Long-Term  
Average  
Minimum  
0 ppm  
Period  
Nominal  
+c2cjitter  
AbsPer  
Maximum Units Notes  
Average  
Minimum  
SSC On  
Maximum  
Maximum  
100.00  
133.33  
9.94900  
7.44925  
—
—
9.99900  
7.49925  
10.00000  
7.50000  
10.00100  
7.50075  
—
—
10.05100  
7.55075  
ns  
ns  
1,2,3  
1,2,4  
DIF  
Table 14. Clock Periods – Differential Outputs w ith Spread Spectrum Enabled  
Measurement Window  
1 Clock  
1μs  
0.1s  
0.1s  
0.1s  
1μs  
1 Clock  
- S S C  
- p p m  
+ p p m  
Long-Term  
Average  
+ S S C  
Center  
Frequency  
MHz  
- c 2 c j i t t e r  
AbsPer  
Minimum  
Short-Term Long-Term  
Average  
Minimum  
0 ppm  
Period  
Nominal  
Short-Term +c2cjitter  
Average  
Maximum  
Average  
Minimum  
AbsPer  
Maximum Units Notes  
SSC On  
Maximum  
99.75  
9.94906  
7.44930  
9.99906  
7.49930  
10.02406  
7.51805  
10.02506  
7.51880  
10.02607  
7.51955  
10.05107  
7.53830  
10.10107  
7.58830  
ns  
ns  
1,2,3  
1,2,4  
DIF  
133.00  
1 Guaranteed by design and characterization, not 100% tested in production.  
2 All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with CK420BQ accuracy requirements  
(±100ppm). The buffer itself does not contribute to ppm error.  
3 Driven by SRC output of main clock, 100MHz PLL Mode or Bypass Mode.  
4 Driven by CPU output of main clock, 133MHz PLL Mode or Bypass Mode.  
Pow er Management  
CKPWRGD_PD#  
DIF_IN  
SMBus EN bit  
OE[x]#  
DIF[x]  
PLL State if not in Bypass Mode  
0
X
X
0
0
1
1
X
0
1
0
1
Low/Low  
Low/Low  
Low/Low  
Running  
Low/Low  
Off  
On  
On  
On  
On  
1
Running  
©2018 Integrated Device Technology, Inc  
13  
August 14, 2018  
9ZXL1232E / 9ZXL1252E Datasheet  
Pow er Connections  
Pin Number  
V
V
GND  
Description  
DD  
DDIO  
1
8
2
Analog PLL  
Analog input  
DIF clocks  
7
24,40,57  
25,32,49,56  
23,33,41,48, 58,65  
Functionality at Pow er-Up (PLL Mode)  
100M_133M#  
DIF_IN MHz  
DIF[x]  
1
0
100.00  
133.33  
DIF_IN  
DIF_IN  
PLL Operating Mode Readback  
HIBW_BYPM_LOBW#  
Byte0, bit 7  
Byte 0, bit 6  
Low (Low BW)  
Mid (Bypass)  
0
0
1
0
1
1
High (High BW)  
PLL Operating Mode  
HIBW_BYPM_LOBW#  
Mode  
Low  
Mid  
PLL Low BW  
Bypass  
High  
PLL High BW  
Note: PLL is OFF in Bypass Mode.  
SMBus Addressing  
SMB_A1_tri  
SMB_A0_tri  
SMBus Address  
0
0
0
M
1
D8  
DA  
DE  
C2  
C4  
C6  
CA  
CC  
CE  
0
M
M
M
1
0
M
1
0
1
M
1
1
©2018 Integrated Device Technology, Inc  
14  
August 14, 2018  
9ZXL1232E / 9ZXL1252E Datasheet  
Test Loads  
Low-Power HCSL Output Test Load  
(standard PCIe source-terminated test load)  
Rs  
CL  
L
Test  
Points  
Differential Zo  
CL  
Rs  
Table 15. Parameters for Low -Power HCSL Output Test Load  
Device  
Rs (Ω)  
Zo (Ω)  
L (inches)  
C (pF)  
L
27  
33  
85  
100  
85  
10  
10  
10  
10  
2
2
2
2
9ZXL123x  
Internal  
7.5  
9ZXL125x*  
100  
* Contact factory for versions of this device with Zo = 100Ω.  
Alternate Terminations  
The LP-HCSL output can easily drive other logic families. See “AN-891 Driving LVPECL, LVDS, and CML Logic with IDT's “Universal”  
Low-Power HCSL Outputs” for termination schemes for LVPECL, LVDS, CML and SSTL.  
©2018 Integrated Device Technology, Inc  
15  
August 14, 2018  
9ZXL1232E / 9ZXL1252E Datasheet  
General SMBus Serial Interface Information  
How to Write  
How to Read  
▪ Controller (host) sends a start bit  
▪ Controller (host) will send a start bit  
▪ Controller (host) sends the write address  
▪ IDT clock will acknowledge  
▪ Controller (host) sends the write address  
▪ IDT clock will acknowledge  
▪ Controller (host) sends the beginning byte location = N  
▪ IDT clock will acknowledge  
▪ Controller (host) sends the beginning byte location = N  
▪ IDT clock will acknowledge  
▪ Controller (host) sends the byte count = X  
▪ IDT clock will acknowledge  
▪ Controller (host) will send a separate start bit  
▪ Controller (host) sends the read address  
▪ IDT clock will acknowledge  
▪ Controller (host) starts sending Byte N through Byte N+X-1  
▪ IDT clock will acknowledge each byte one at a time  
▪ Controller (host) sends a stop bit  
▪ IDT clock will send the data byte count = X  
▪ IDT clock sends Byte N+X-1  
▪ IDT clock sends Byte 0 through Byte X (if X(H) was written to  
Index Block Write Operation  
Byte 8)  
Controller (Host)  
starT bit  
Slave Address  
WR WRite  
IDT (Slave/Receiver)  
▪ Controller (host) will need to acknowledge each byte  
▪ Controller (host) will send a not acknowledge bit  
▪ Controller (host) will send a stop bit  
T
ACK  
ACK  
ACK  
ACK  
Index Block Read Operation  
Beginning Byte = N  
Data Byte Count = X  
Beginning Byte N  
Controller (Host)  
starT bit  
IDT (Slave/Receiver)  
T
Slave Address  
WRite  
WR  
ACK  
ACK  
Beginning Byte = N  
O
O
O
O
O
O
RT  
RD  
Repeat starT  
Slave Address  
ReaD  
Byte N + X - 1  
ACK  
ACK  
P
stoP bit  
Data Byte Count=X  
Beginning Byte N  
ACK  
ACK  
O
O
O
O
O
O
Byte N + X - 1  
N
P
Not acknowledge  
stoP bit  
©2018 Integrated Device Technology, Inc  
16  
August 14, 2018  
9ZXL1232E / 9ZXL1252E Datasheet  
SMBus Table: PLL Mode and Frequency Select Register  
Byte 0  
Pin #  
Name  
Control Function  
Type  
0
1
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
5
5
PLL Mode 1  
PLL Mode 0  
PLL Operating Mode Rd back 1  
PLL Operating Mode Rd back 0  
Reserved  
R
R
Latch  
See PLL Operating Mode Readback  
table  
Latch  
0
Reserved  
0
—
—
—
4
PLL_SW_EN  
PLL Mode 1  
PLL Mode 0  
100M_133M#  
Enable S/W control of PLL BW  
PLL Operating Mode 1  
PLL Operating Mode 1  
Frequency Select Readback  
RW  
RW  
RW  
R
HW Latch  
SMBus Control  
0
1
See PLL Operating Mode Readback  
Table  
1
133MHz  
100MHz  
Latch  
Note: Setting bit 3 to '1' allows the user to override the latch value from pin 5 via use of bits 2 and 1. Use the values from the PLL  
Operating Mode Readback table. Note that Bits 7 and 6 will keep the value originally latched on pin 5. If these bits are changed, a warm  
reset of the system must be completed.  
SMBus Table: Output Control Register  
Byte 1  
Pin #  
Name  
Control Function  
Type  
0
1
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
47/46  
43/42  
39/38  
35/34  
30/31  
26/27  
21/22  
17/18  
DIF_7_En  
DIF_6_En  
DIF_5_En  
DIF_4_En  
DIF_3_En  
DIF_2_En  
DIF_1_En  
DIF_0_En  
Output Enable  
Output Enable  
Output Enable  
Output Enable  
Output Enable  
Output Enable  
Output Enable  
Output Enable  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
1
1
1
1
1
1
1
1
Low/Low  
OE# Pin Control  
SMBus Table: Output Control Register  
Byte 2  
Pin #  
Name  
Control Function  
Type  
0
1
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Reserved  
0
0
0
0
1
1
1
1
Reserved  
Reserved  
Reserved  
64/63  
59/60  
54/55  
50/51  
DIF_11_En  
DIF_10_En  
DIF_9_En  
DIF_8_En  
Output Enable  
RW  
RW  
RW  
RW  
Output Enable  
Output Enable  
Output Enable  
Low/Low  
OE# Pin Control  
©2018 Integrated Device Technology, Inc  
17  
August 14, 2018  
9ZXL1232E / 9ZXL1252E Datasheet  
SMBus Table: Reserved Register  
Byte 3  
Pin #  
Name  
Control Function  
Reserved  
Type  
Type  
Type  
0
0
0
1
1
1
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
0
0
0
0
0
0
0
0
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
SMBus Table: Reserved Register  
Byte 4  
Pin #  
Name  
Control Function  
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
0
0
0
0
0
0
0
0
SMBus Table: Vendor & Revision ID Register  
Byte 5  
Pin #  
Name  
Control Function  
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
—
—
—
—
—
—
—
—
RID3  
RID2  
RID1  
RID0  
VID3  
VID2  
VID1  
VID0  
R
R
R
R
R
R
R
R
0
1
0
0
0
0
0
1
REVISION ID  
VENDOR ID  
E rev = 0100  
—
—
—
—
—
—
—
—
©2018 Integrated Device Technology, Inc  
18  
August 14, 2018  
9ZXL1232E / 9ZXL1252E Datasheet  
SMBus Table: Device ID  
Byte 6  
Pin #  
Name  
Control Function  
Device ID 7 (MSB)  
Type  
0
1
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
—
—
—
—
—
—
—
—
R
R
R
R
R
R
R
R
1
1
1
x
x
x
x
x
Device ID 6  
Device ID 5  
Device ID 4  
Device ID 3  
Device ID 2  
Device ID 1  
Device ID 0  
9ZXL1232E: E8h  
9ZXL1252E: F8h  
SMBus Table: Byte Count Register  
Byte 7  
Pin #  
Name  
Control Function  
Reserved  
Type  
0
1
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
0
0
0
0
1
0
0
0
Reserved  
Reserved  
—
—
—
—
—
BC4  
BC3  
BC2  
BC1  
BC0  
RW  
RW  
RW  
RW  
RW  
Writing to this register configures  
how many bytes will be read back.  
Default value is 8 hex, so 9 bytes (0 to  
8) will be read back by default.  
SMBus Table: Reserved Register  
Byte 8  
Pin #  
Name  
Control Function  
Type  
0
1
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
0
0
0
0
0
0
0
0
©2018 Integrated Device Technology, Inc  
19  
August 14, 2018  
9ZXL1232E / 9ZXL1252E Datasheet  
Package Outline Draw ings  
The package outline drawings are appended at the end of this document and are accessible from the link below. The package information  
is the most current data available.  
www.idt.com/document/psc/64-vfqfpn-package-outline-drawing-90-x-90-x-09-mm-body-05mm-pitch-epad-615-x-615-mm-nlg64p2  
Ordering Information  
Orderable Part Number  
Package  
Carrier Type  
Temperature  
9ZXL1232EKILF  
9ZXL1232EKILFT  
9ZXL1252EKILF  
9ZXL1252EKILFT  
9 x 9 mm, 0.5mm pitch 64-VFQFPN  
9 x 9 mm, 0.5mm pitch 64-VFQFPN  
9 x 9 mm, 0.5mm pitch 64-VFQFPN  
9 x 9 mm, 0.5mm pitch 64-VFQFPN  
Tray  
-40° to +85°C  
-40° to +85°C  
-40° to +85°C  
-40° to +85°C  
Tape and Reel, Pin 1 Orientation: EIA-481C  
Tray  
Tape and Reel, Pin 1 Orientation: EIA-481C  
“LF” designates PB-free configuration, RoHS compliant.  
“E” is the device revision designator (will not correlate with the datasheet revision).  
Table 16. Pin 1 Orientation in Tape and Reel Packaging  
Part Number Suffix  
Pin 1 Orientation  
Illustration  
T
Quadrant 1 (EIA-481-C)  
Marking Diagrams  
1. “I” denotes industrial temperature range  
2. “L” denotes RoHS compliant package.  
3. “LOT” denotes the lot number.  
ICS  
ICS  
9ZXL1232EIL  
LOT  
9ZXL1252EIL  
LOT  
4. “COO” denotes country of origin.  
COO YYWW  
COO YYWW  
5. “YYWW” denotes the last two digits of the year and week the part was  
assembled.  
©2018 Integrated Device Technology, Inc  
20  
August 14, 2018  
9ZXL1232E / 9ZXL1252E Datasheet  
Revision History  
Revision Date  
Description of Change  
august 14, 2018  
April 17, 2018  
Updated block diagram.  
Updated absolute maximum supply voltage rating and VIHSMB to 3.9V.  
Removed “5V tolerant” reference in pins 12 and 13 descriptions.  
Initial release.  
December 1, 2017  
September 29, 2017  
Corporate Headquarters  
Sales  
Tech Support  
6024 Silver Creek Valley Road  
San Jose, CA 95138 USA  
www.IDT.com  
1-800-345-7015 or 408-284-8200  
Fax: 408-284-2775  
www.IDT.com/go/sales  
www.IDT.com/go/support  
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications described herein at any time,  
without notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same  
way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability  
of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not  
convey any license under intellectual property rights of IDT or any third parties.  
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be rea-  
sonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.  
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property  
of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Integrated Device Technology, Inc All rights reserved.  
©2018 Integrated Device Technology, Inc  
21  
August 14, 2018  
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