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9ZXL1530DKILF

型号：

9ZXL1530DKILF

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

23 页

PDF大小：

292 K

下载PDF手册
15-Output DB1900Z Derivative  
for PCIe Gen1–4 and UPI  
9ZXL1530D / 9ZXL1550D  
Datasheet  
Description  
Features  
▪ LP-HCSL outputs; eliminate 30 resistors, save 51mm2 of area  
The 9ZXL1530D / 9ZXL1550D are second-generation  
enhanced-performance DB1900Z-derivative differential buffers.  
The parts are pin-compatible upgrades to the 9ZXL1530B and  
9ZXL1550B, while offering a much improved phase jitter  
performance. A fixed external feedback maintains low drift for  
critical QPI/UPI applications. In fanout mode, the devices meet the  
DB2000Q additive phase jitter specification.  
(1530D)  
▪ LP-HCSL outputs with 85Ω Zout; eliminate 60 resistors, save  
103mm2 of area (1550D)  
▪ SMBus OE bits; software control of each output  
▪ 9 selectable SMBus addresses; multiple devices can share the  
same SMBus segment  
▪ Selectable PLL BW; minimizes jitter peaking in cascaded PLL  
PCIe Clocking Architectures  
topologies  
▪ Common Clocked (CC)  
▪ Hardware/SMBus control of PLL bandwidth and bypass;  
change mode without power cycle  
▪ Independent Reference (IR) with and without spread spectrum  
▪ Spread spectrum compatible; tracks spreading input clock for  
EMI reduction  
Typical Applications  
▪ 9 × 9 mm 64-VFQFPN package; small board footprint  
▪ Servers  
▪ Storage  
▪ Networking  
▪ SSDs  
Key Specifications  
▪ Cycle-to-cycle jitter: < 50ps  
▪ Output-to-output skew: < 50ps  
▪ Input-to-output delay: fixed at 0ps  
▪ Input-to-output delay variation: < 50ps  
▪ Additive phase jitter: PCIe Gen4 < 53fs rms  
▪ Additive phase jitter: IF-UPI < 70fs rms  
▪ Additive phase jitter: DB2000Q filter < 80fs rms  
Output Features  
▪ 15 Low-Power HCSL (LP-HCSL) output pairs (1530D)  
▪ 15 Low-Power HCSL (LP-HCSL) output pairs with 85Ω Zout  
(1550D)  
Block Diagram  
VDDR  
VDDA  
VDD x3  
VDDIO x4  
FBOUT_NC#  
FBOUT_NC  
PLL  
DIF_IN#  
DIF_IN  
DIF14#  
DIF14  
^100M_133M#  
^SADR[1:0]_tri  
SMBCLK  
15  
outputs  
SMBus  
Engine  
Factory  
Configuration  
SMBDAT  
DIF0#  
DIF0  
^vHIBW_BYPM-LOBW#  
^CKPWRGD_PD#  
Control Logic  
Resistors are integrated on 9ZXL1550 devices  
and external on 9ZXL1530 devices.  
GNDA  
GND x12  
©2018 Integrated Device Technology, Inc  
1
April 12, 2018  
 
 
 
 
 
 
 
9ZXL1530D / 9ZXL1550D Datasheet  
Contents  
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
PCIe Clocking Architectures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Output Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Key Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
Clock Periods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Functionality at Power-Up (PLL Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Test Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Package Outline Drawings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
©2018 Integrated Device Technology, Inc  
2
April 12, 2018  
9ZXL1530D / 9ZXL1550D Datasheet  
Pin Assignments  
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49  
1
2
3
4
5
6
7
8
9
VDDA  
GNDA  
48 VDDIO  
47 GND  
46 DIF9#  
45 DIF9  
44 DIF8#  
43 DIF8  
42 GND  
41 VDD  
^100M_133M#  
^vHIBW_BYPM_LOBW#  
^CKPWRGD_PD#  
GND  
VDDR  
9ZXL1530D  
9ZXL1550D  
EPAD is Pin 65  
DIF_IN  
DIF_IN#  
40 DIF7#  
39 DIF7  
38 DIF6#  
37 DIF6  
36 VDDIO  
35 GND  
34 DIF5#  
33 DIF5  
^SADR0_tri 10  
SMBDAT 11  
SMBCLK 12  
^SADR1_tri 13  
FBOUT_NC# 14  
FBOUT_NC 15  
GND 16  
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32  
9 x 9 mm 64-VFQFPN  
Notes: Pins with ^ prefix have internal 120kohm pull-up  
Pins with v prefix have internal 120kohm pull-down  
Pins with ^v prefix have internal 120kohm pull-up/pull-down (biased to VDD/2)  
Pin Descriptions  
Table 1. Pin Descriptions  
Number  
Name  
Type  
Description  
1
2
VDDA  
GNDA  
Power  
GND  
Power supply for PLL core.  
Ground pin for the PLL core.  
3.3V input to select operating frequency. This pin has an internal 120kΩ pull-up resistor.  
See Functionality at Power-Up table for definition.  
3
4
^100M_133M#  
Latched In  
Tri-level input to select High BW, Bypass or Low BW mode. This pin is biased to V /2  
DD  
^vHIBW_BYPM_LOBW# Latched In (Bypass Mode) with internal pull-up/pull-down resistors. See PLL Operating Mode table  
for details.  
Input notifies device to sample latched inputs and start up on first high assertion. Low  
5
^CKPWRGD_PD#  
Input  
enters Power Down Mode, subsequent high assertions exit Power Down Mode. This  
pin has internal 120kΩ pull-up resistor.  
6
7
GND  
GND  
Ground pin.  
Power supply for differential input clock (receiver). This V should be treated as an  
analog power rail and filtered appropriately. Nominally 3.3V.  
DD  
VDDR  
Power  
8
9
DIF_IN  
Input  
Input  
HCSL true input.  
DIF_IN#  
HCSL complementary input.  
©2018 Integrated Device Technology, Inc  
3
April 12, 2018  
9ZXL1530D / 9ZXL1550D Datasheet  
Table 1. Pin Descriptions (Cont.)  
Number  
Name  
Type  
Description  
SMBus address bit. This is a tri-level input that works in conjunction with other SADR  
pins, if present, to decode SMBus Addresses. It has an internal 120kΩ pull-up resistor.  
See the SMBus Addressing table.  
10  
^SADR0_tri  
Input  
11  
12  
SMBDAT  
SMBCLK  
I/O  
Data pin of SMBUS circuitry.  
Clock pin of SMBUS circuitry.  
Input  
SMBus address bit. This is a tri-level input that works in conjunction with other SADR  
pins, if present, to decode SMBus Addresses. It has an internal 120kΩ pull-up resistor.  
See the SMBus Addressing table.  
13  
^SADR1_tri  
Input  
Complementary half of differential feedback output. This pin should NOT be connected  
to anything outside the chip. It exists to provide delay path matching to get 0  
propagation delay.  
14  
15  
FBOUT_NC#  
FBOUT_NC  
Output  
Output  
True half of differential feedback output. This pin should NOT be connected to anything  
outside the chip. It exists to provide delay path matching to get 0 propagation delay.  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
GND  
DIF0  
GND  
Output  
Output  
Power  
GND  
Ground pin.  
Differential true clock output.  
Differential complementary clock output.  
Power supply for differential outputs.  
Ground pin.  
DIF0#  
VDDIO  
GND  
DIF1  
Output  
Output  
Output  
Output  
GND  
Differential true clock output.  
Differential complementary clock output.  
Differential true clock output.  
Differential complementary clock output.  
Ground pin.  
DIF1#  
DIF2  
DIF2#  
GND  
VDD  
Power  
Output  
Output  
Output  
Output  
Power  
GND  
Power supply, nominally 3.3V.  
Differential true clock output.  
Differential complementary clock output.  
Differential true clock output.  
Differential complementary clock output.  
Power supply for differential outputs.  
Ground pin.  
DIF3  
DIF3#  
DIF4  
DIF4#  
VDDIO  
GND  
DIF5  
Output  
Output  
GND  
Differential true clock output.  
Differential complementary clock output.  
Ground pin.  
DIF5#  
GND  
VDDIO  
Power  
Power supply for differential outputs.  
37  
38  
39  
DIF6  
DIF6#  
DIF7  
Output  
Output  
Output  
Differential true clock output.  
Differential complementary clock output.  
Differential true clock output.  
©2018 Integrated Device Technology, Inc  
4
April 12, 2018  
9ZXL1530D / 9ZXL1550D Datasheet  
Table 1. Pin Descriptions (Cont.)  
Number  
Name  
Type  
Description  
Differential complementary clock output.  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
DIF7#  
VDD  
Output  
Power  
GND  
Power supply, nominally 3.3V.  
Ground pin.  
GND  
DIF8  
Output  
Output  
Output  
Output  
GND  
Differential true clock output.  
Differential complementary clock output.  
Differential true clock output.  
Differential complementary clock output.  
Ground pin.  
DIF8#  
DIF9  
DIF9#  
GND  
VDDIO  
DIF10  
DIF10#  
VDDIO  
GND  
Power  
Output  
Output  
Power  
GND  
Power supply for differential outputs.  
Differential true clock output.  
Differential complementary clock output.  
Power supply for differential outputs.  
Ground pin.  
DIF11  
DIF11#  
DIF12  
DIF12#  
GND  
Output  
Output  
Output  
Output  
GND  
Differential true clock output.  
Differential complementary clock output.  
Differential true clock output.  
Differential complementary clock output.  
Ground pin.  
VDD  
PWR  
Power supply, nominally 3.3V.  
Differential true clock output.  
Differential complementary clock output.  
Differential true clock output.  
Differential complementary clock output.  
Power supply for differential outputs.  
Ground pin.  
DIF13  
DIF13#  
DIF14  
DIF14#  
VDDIO  
GND  
Output  
Output  
Output  
Output  
Power  
GND  
EPAD  
GND  
EPAD should be connected to GND.  
©2018 Integrated Device Technology, Inc  
5
April 12, 2018  
9ZXL1530D / 9ZXL1550D Datasheet  
Absolute Maximum Ratings  
Stresses above the ratings listed below can cause permanent damage to the 9ZXL1530D / 9ZXL1550D. These ratings, which are  
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other  
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating  
conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating  
temperature range.  
Table 2. Absolute Maximum Ratings  
Parameter  
Symbol  
Conditions  
Minimum  
Typical  
Maximum Units Notes  
Supply Voltage  
Input Low Voltage  
V
3.9  
V
V
1,2  
1
DDx  
V
GND - 0.5  
IL  
Input Low Voltage  
V
Except for SMBus interface.  
SMBus clock and data pins.  
V
+ 0.5  
DD  
V
1,3  
1
IH  
Input High Voltage, SMBus  
Storage Temperature  
Junction Temperature  
Input ESD Protection  
V
3.9  
150  
125  
V
IHSMB  
Ts  
-65  
°C  
°C  
V
1
Tj  
1
ESD prot Human Body Model.  
2000  
1
1 Guaranteed by design and characterization, not 100% tested in production.  
2 Operation under these conditions is neither implied nor guaranteed.  
3 Not to exceed 3.9V.  
Electrical Characteristics  
TAMB = over the specified operating range. Supply voltages per normal operation conditions; see Test Loads for loading conditions.  
Table 3. SMBus Parameters  
Parameter  
Symbol  
Conditions  
Minimum Typical  
Maximum Units Notes  
SMBus Input Low Voltage  
SMBus Input High Voltage  
SMBus Output Low Voltage  
SMBus Sink Current  
V
0.8  
V
V
ILSMB  
V
2.1  
V
DDSMB  
IHSMB  
V
At I  
0.4  
V
OLSMB  
PULLUP  
PULLUP.  
I
At V  
4
mA  
V
OL.  
Nominal Bus Voltage  
V
2.7  
3.6  
1000  
300  
1
1
1
5
DDSMB  
SCLK/SDATA Rise Time  
SCLK/SDATA Fall Time  
SMBus Operating Frequency  
t
(Max V - 0.15V) to (Min V + 0.15V).  
ns  
ns  
kHz  
RSMB  
IL  
IH  
t
(Min V + 0.15V) to (Max V - 0.15V).  
IH IL  
FSMB  
f
Maximum SMBus operating frequency.  
400  
SMBMAX  
1 Guaranteed by design and characterization, not 100% tested in production.  
2 Control input must be monotonic from 20% to 80% of input swing.  
3 Time from deassertion until outputs are > 200mV.  
4 DIF_IN input.  
5 The differential input clock must be running for the SMBus to be active.  
©2018 Integrated Device Technology, Inc  
6
April 12, 2018  
9ZXL1530D / 9ZXL1550D Datasheet  
Table 4. DIF_IN Clock Input Parameters  
Parameter  
Symbol  
Conditions  
Cross over voltage.  
Minimum Typical Maximum Units Notes  
Input Crossover Voltage – DIF_IN  
Input Swing – DIF_IN  
V
150  
300  
0.4  
-5  
900  
mV  
mV  
V/ns  
μA  
1
1
CROSS  
V
Differential value.  
SWING  
Input Slew Rate – DIF_IN  
Input Leakage Current  
dv/dt  
Measured differentially.  
8
5
1,2  
I
V
= V  
V = GND.  
DD , IN  
IN  
IN  
Measurement from differential  
waveform.  
Input Duty Cycle  
d
45  
0
55  
%
1
1
tin  
Input Jitter – Cycle to Cycle  
J
Differential measurement.  
125  
ps  
DIFIn  
1 Guaranteed by design and characterization, not 100% tested in production.  
2 Slew rate measured through ±75mV window centered around differential zero.  
Table 5. Input/Supply/Common Parameters  
TAMB = over the specified operating range. Supply voltages per normal operation conditions; see Test Loads for loading conditions.  
Parameter  
Symbol  
Conditions  
Minimum  
Typical  
Maximum Units Notes  
Supply Voltage  
V
Supply voltage for core and analog.  
3.135  
0.95  
3.3  
3.465  
3.465  
V
V
DDx  
Output Supply Voltage  
V
Supply voltage for DIF outputs, if present.  
1.05  
DDIO  
Ambient Operating  
Temperature  
T
Industrial range (T ).  
-40  
2
85  
°C  
V
AMB  
IND  
Single-ended inputs, except SMBus,  
tri-level inputs.  
Input High Voltage  
Input Low Voltage  
V
V
V
+ 0.3  
DD  
IH  
Single-ended inputs, except SMBus,  
tri-level inputs.  
V
GND - 0.3  
0.8  
+ 0.3  
V
IL  
Input High Voltage  
Input Mid Voltage  
Input Low Voltage  
V
Tri-level inputs (pins with 'tri' suffix).  
Tri-level inputs (pins with 'tri' suffix).  
Tri-level inputs (pins with 'tri' suffix).  
2.2  
1.2  
V
V
V
IH  
DD  
V
V
V
/2  
DDx  
1.8  
IL  
IL  
GND - 0.3  
0.8  
Single-ended inputs, V = GND,  
IN  
I
-5  
5
μA  
IN  
V
= V  
IN  
DD.  
Single-ended inputs.  
= 0 V; inputs with internal pull-up  
Input Current  
V
IN  
I
resistors.  
-50  
50  
μA  
INP  
V
= V ; inputs with internal pull-down  
IN  
DD  
resistors.  
F
Bypass Mode.  
1
400  
102  
136  
7
MHz  
MHz  
MHz  
nH  
ibyp  
Input Frequency  
Pin Inductance  
F
100MHz PLL Mode.  
133.33MHz PLL Mode.  
98  
100.00  
133.33  
ipll  
ipll  
pin  
F
130  
L
1
©2018 Integrated Device Technology, Inc  
7
April 12, 2018  
9ZXL1530D / 9ZXL1550D Datasheet  
Table 5. Input/Supply/Common Parameters (Cont.)  
TAMB = over the specified operating range. Supply voltages per normal operation conditions; see Test Loads for loading conditions.  
Parameter  
Symbol  
Conditions  
Minimum  
Typical  
Maximum Units Notes  
C
Logic inputs, except DIF_IN.  
DIF_IN differential clock inputs.  
Output pin capacitance.  
1.5  
1.5  
5
2.7  
6
pF  
pF  
pF  
1
1,4  
1
IN  
C
INDIF_IN  
Capacitance  
C
OUT  
From V power-up and after input clock  
DD  
Clk Stabilization  
T
stabilization or deassertion of PD# to 1st  
clock.  
1.8  
33  
ms  
1,2  
STAB  
Input SS Modulation  
Frequency PCIe  
Allowable frequency for PCIe applications  
(Triangular modulation).  
f
30  
kHz  
MODINPCIe  
Tdrive_PD#  
Tfall  
t
DIF output enable after PD# deassertion.  
Fall time of control inputs.  
300  
5
μs  
ns  
ns  
1,3  
2
DRVPD  
t
F
Trise  
t
Rise time of control inputs.  
5
2
R
1 Guaranteed by design and characterization, not 100% tested in production.  
2 Control input must be monotonic from 20% to 80% of input swing.  
3 Time from deassertion until outputs are > 200mV.  
4 DIF_IN input.  
Table 6. Current Consumption  
Parameter  
Symbol  
Conditions  
Minimum  
Typical  
Maximum Units Notes  
V
+ V  
pins, all outputs at 100MHz,  
DDR  
DDA  
I
I
54  
65  
92  
34  
mA  
mA  
mA  
DDA+R  
C = 2pF; Zo = 85Ω.  
L
Operating Supply  
Current  
V
pins, all outputs at 100MHz,  
DDIO  
I
77  
27  
DDO  
C = 2pF; Zo = 85Ω.  
L
All other V pins, all outputs at 100MHz,  
C = 2pF; Zo = 85Ω.  
DD  
I
DDx  
L
V
V
+ V  
pins, all outputs Low/Low.  
DDR  
4
5
mA  
mA  
mA  
DDA+R  
DDA  
Power Down  
Current  
I
pins, all outputs Low/Low.  
0.04  
0.46  
0.1  
0.6  
DDO  
DDIO  
I
All other V pins, all outputs Low/Low.  
DD  
DDx  
©2018 Integrated Device Technology, Inc  
8
April 12, 2018  
9ZXL1530D / 9ZXL1550D Datasheet  
Table 7. Skew and Differential Jitter Parameters  
TAMB = over the specified operating range. Supply voltages per normal operation conditions; see Test Loads for loading conditions.  
Parameter  
Symbol  
Conditions  
Minimum Typical Maximum Units Notes  
Input-to-output skew in PLL Mode at 100MHz,  
nominal temperature and voltage.  
1,2,4,5  
,8  
CLK_IN, DIF[x:0]  
t
-100  
2.2  
22  
2.9  
0
100  
3.5  
50  
ps  
ns  
ps  
ps  
SPO_PLL  
Input-to-output skew in Bypass Mode at 100MHz,  
nominal temperature and voltage.  
1,2,3,5  
,8  
CLK_IN, DIF[x:0]  
CLK_IN, DIF[x:0]  
t
PD_BYP  
Input-to-output skew variation in PLL Mode at  
100MHz, across voltage and temperature.  
1,2,3,5  
,8  
t
-50  
DSPO_PLL  
Input-to-output skew variation in Bypass Mode at  
100MHz, across voltage and temperature.  
1,2,3,5  
,8  
-250  
250  
CLK_IN, DIF[x:0]  
t
DSPO_BYP  
Input-to-output skew variation in Bypass Mode at  
100MHz, across voltage and temperature,  
1,2,3,5  
,8  
-350  
350  
5
ps  
T
= T  
.
AMB  
IND  
ps  
Random differential tracking error between two  
9ZX devices in High BW Mode.  
1,2,3,5  
,8  
CLK_IN, DIF[x:0]  
CLK_IN, DIF[x:0]  
DIF[x:0]  
t
DTE  
(rms)  
Random differential spread spectrum tracking  
error between two 9ZX devices in High BW  
Mode.  
1,2,3,5  
,8  
t
40  
50  
ps  
ps  
DSSTE  
Output-to-output skew across all outputs,  
common to PLL and Bypass Mode, at 100MHz.  
t
36  
1,2,3,8  
SKEW_ALL  
PLL Jitter Peaking  
PLL Jitter Peaking  
PLL Bandwidth  
PLL Bandwidth  
Duty Cycle  
j
j
LOBW#_BYPASS_HIBW = 1.  
LOBW#_BYPASS_HIBW = 0.  
LOBW#_BYPASS_HIBW = 1.  
LOBW#_BYPASS_HIBW = 0.  
Measured differentially, PLL Mode.  
0
0
1
1
2.5  
2
dB  
dB  
7,8  
7,8  
8,9  
8,9  
1
peak-hibw  
peak-lobw  
pll  
2
3
4
MHz  
MHz  
%
HIBW  
pll  
0.7  
45  
1
1.4  
55  
LOBW  
t
50  
DC  
Duty Cycle  
Distortion  
t
Measured differentially, Bypass Mode at 100MHz.  
-1  
0
1
%
1,10  
DCD  
PLL Mode.  
20  
3
50  
10  
ps  
ps  
1,11  
1,11  
Jitter, Cycle to Cycle  
t
jcyc-cyc  
Additive jitter in Bypass Mode.  
1 Measured into fixed 2pF load cap. Input to output skew is measured at the first output edge following the corresponding input.  
2 Measured from differential cross-point to differential cross-point. This parameter can be tuned with external feedback path, if present.  
3 All Bypass Mode input-to-output specs refer to the timing between an input edge and the specific output edge created by it.  
4 This parameter is deterministic for a given device.  
5 Measured with scope averaging on to find mean value.  
6 “t” is the period of the input clock.  
7 Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL jitter peaking.  
8 Guaranteed by design and characterization, not 100% tested in production.  
9 Measured at 3db down or half power point.  
10 Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in Bypass Mode.  
11 Measured from differential waveform.  
©2018 Integrated Device Technology, Inc  
9
April 12, 2018  
9ZXL1530D / 9ZXL1550D Datasheet  
Table 8. HCSL/LP-HCSL Outputs  
TAMB = over the specified operating range. Supply voltages per normal operation conditions; see Test Loads for loading conditions.  
Specification  
Parameter  
Symbol  
Conditions  
Minimum Typical Maximum  
Limits  
Units Notes  
Slew Rate  
dV/dt  
ΔdV/dt  
Vmax  
Scope averaging on.  
2
2.6  
7
4
1–4  
20  
V/ns  
%
1,2,3  
1,4,7  
7
Slew Rate Matching  
Maximum Voltage  
Single-ended measurement.  
19.7  
888  
Measurement on  
660  
-117  
250  
815  
1150  
single-ended signal using  
absolute value (scope  
averaging off).  
mV  
Minimum Voltage  
Vmin  
-50  
-300  
7
Crossing Voltage (abs) Vcross_abs Scope averaging off.  
Crossing Voltage (var) Δ-Vcross Scope averaging off.  
399  
24  
550  
63  
250–550  
140  
mV  
mV  
1,5,7  
1,6,7  
1 Guaranteed by design and characterization, not 100% tested in production.  
2 Measured from differential waveform.  
3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a ±150mV window around differential 0V.  
4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a ±75mV window centered on the average  
cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use  
for the edge rate calculations.  
5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e. Clock  
rising and Clock# falling).  
6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross absolute) allowed.  
The intent is to limit Vcross induced modulation by setting Δ-Vcross to be smaller than Vcross absolute.  
7 At default SMBus settings.  
©2018 Integrated Device Technology, Inc  
10  
April 12, 2018  
9ZXL1530D / 9ZXL1550D Datasheet  
Table 9. Filtered Phase Jitter Parameters - PCIe Common Clocked (CC) Architectures  
Specification  
Limits  
Parameter  
Symbol  
Conditions  
Minimum Typical Maximum  
Units Notes  
ps  
t
t
PCIe Gen1.  
13  
34  
86  
1,2,3  
(p-p)  
jphPCIeG1-CC  
PCIe Gen2 Low Band  
10kHz < f < 1.5MHz  
ps  
1,2  
0.2  
0.63  
3
(rms)  
(PLL BW of 5–16MHz or 8–16MHz,  
CDR = 5MHz).  
jphPCIeG2-CC  
PCIe Gen2 High Band  
ps  
1,2  
Phase Jitter,  
PLL Mode  
1.5MHz < f < Nyquist (50MHz)  
1.0  
0.2  
1.47  
0.34  
3.1  
(rms)  
(PLL BW of 5–16MHz or 8–16MHz,  
CDR = 5MHz).  
PCIe Gen3  
ps  
1,2  
t
1
(PLL BW of 2–4MHz or 2–5MHz,  
CDR = 10MHz).  
jphPCIeG3-CC  
(rms)  
PCIe Gen4  
ps  
1,2  
t
t
0.2  
0.34  
0.5  
(PLL BW of 2–4MHz or 2–5MHz,  
CDR = 10MHz).  
jphPCIeG4-CC  
jphPCIeG1-CC  
(rms)  
ps  
PCIe Gen1.  
0.01  
0.052  
1,2,3,4  
(p-p)  
PCIe Gen2 Low Band  
10kHz < f < 1.5MHz  
ps  
0.01  
0.0  
0.052  
0.052  
1,2,3,4  
(rms)  
(PLL BW of 5–16MHz or 8–16MHz,  
CDR = 5MHz).  
t
jphPCIeG2-CC  
PCIe Gen2 High Band  
Additive Phase  
Jitter, Bypass  
Mode  
ps  
1.5MHz < f < Nyquist (50MHz)  
Not  
Applicable  
1,2,3,4  
(rms)  
(PLL BW of 5–16MHz or 8–16MHz,  
CDR = 5MHz).  
PCIe Gen3  
ps  
t
t
0.01  
0.01  
0.052  
0.052  
1,2,3,4  
(rms)  
(PLL BW of 2–4MHz or 2–5MHz,  
CDR = 10MHz).  
jphPCIeG3-CC  
jphPCIeG4-CC  
PCIe Gen4  
ps  
1,2,3,4  
(rms)  
(PLL BW of 2–4MHz or 2–5MHz,  
CDR = 10MHz).  
©2018 Integrated Device Technology, Inc  
11  
April 12, 2018  
9ZXL1530D / 9ZXL1550D Datasheet  
Table 10. Filtered Phase Jitter Parameters – PCIe Independent Reference (IR) Architectures  
Specification  
Limit  
Parameter  
Symbol  
Conditions  
Minimum Typical Maximum  
Units Notes  
PCIe Gen2  
ps  
t
t
t
t
0.9  
0.6  
1.05  
0.68  
2
1,2,5  
(rms)  
jphPCIeG2-SRIS  
(PLL BW of 16MHz, CDR = 5MHz).  
Phase Jitter,  
PLL Mode  
PCIe Gen3  
ps  
0.7  
1,2,5  
(rms)  
jphPCIeG3-SRIS  
jphPCIeG2-SRIS  
jphPCIeG3-SRIS  
(PLL BW of 2–4MHz, CDR = 10MHz).  
PCIe Gen2  
ps  
0.01  
0.01  
0.042  
0.042  
1,2,4,5  
(rms)  
Additive Phase  
Jitter, Bypass  
Mode  
(PLL BW of 16MHz, CDR = 5MHz).  
Not  
applicable  
PCIe Gen3  
ps  
1,2,4,5  
(rms)  
(PLL BW of 2–4MHz, CDR = 10MHz).  
Notes for PCIe Filtered Phase Jitter tables (CC) and (IR).  
1 Applies to all differential outputs, guaranteed by design and characterization.  
2 Calculated from Intel™-supplied clock jitter tool when driven by 9SQL495x or equivalent with spread on and off.  
3 Sample size of at least 100K cycles. This figure extrapolates to 108ps pk-pk at 1M cycles for a BER of 1-12  
4 For RMS values, additive jitter is calculated by solving for b [b = sqrt(c2 - a2)] where “a” is rms input jitter and “c” is rms total jitter.  
.
5 IR is the new name for Separate Reference Independent Spread (SRIS) and Separate Reference no Spread (SRNS) PCIe clock architectures.  
According to the PCIe Base Specification Rev4.0 version 0.7 draft, the jitter transfer functions and corresponding jitter limits are not defined for the  
IR clock architecture. Widely accepted industry limits using widely accepted industry filters are used to populate this table. There are no accepted  
filters or limits for IR clock architectures at PCIe Gen1 or Gen4 data rates.  
Table 11. Filtered Phase Jitter Parameters – QPI/UPI  
Specification  
Parameter  
Symbol  
Conditions  
Minimum Typical Maximum  
Limit  
Units Notes  
QPI & UPI  
0.14  
0.25  
0.5  
1,2  
(100MHz or 133MHz, 4.8Gb/s, 6.4Gb/s 12UI).  
t
t
jphQPI_UPI  
QPI & UPI (100MHz, 8.0Gb/s, 12UI).  
QPI & UPI (100MHz, > 9.6Gb/s, 12UI).  
0.07  
0.06  
0.09  
0.3  
0.2  
1,2  
1,2  
ps  
Phase Jitter,  
PLL Mode  
(rms)  
0.074  
0.14  
0.2  
0.1  
0.17  
t
IF-UPI.  
1
1,4,5  
1,2,3  
jphIF-UPI  
QPI & UPI  
0.00  
0.01  
(100MHz or 133MHz, 4.8Gb/s, 6.4Gb/s 12UI).  
Additive  
Phase Jitter,  
Bypass Mode  
ps  
jphQPI_UPI  
Not  
applicable  
QPI & UPI (100MHz, 8.0Gb/s, 12UI).  
QPI & UPI (100MHz, > 9.6Gb/s, 12UI).  
IF-UPI.  
0.00  
0.00  
0.06  
0.01  
0.01  
0.07  
1,2,3  
1,2,3  
1,4  
(rms)  
t
jphIF-UPI  
1 Applies to all differential outputs, guaranteed by design and characterization.  
2 Calculated from Intel-supplied clock jitter tool, when driven by 9SQL495x or equivalent with spread on and off.  
3 For RMS values, additive jitter is calculated by solving for b [b = sqrt(c2 - a2)] where “a” is rms input jitter and “c” is rms total jitter.  
4 Calculated from phase noise analyzer when driven by Wenzel Associates source with Intel-specified brick-wall filter applied.  
5 Top number is when the buffer is in Low BW mode; bottom number is when the buffer is in High BW mode.  
©2018 Integrated Device Technology, Inc  
12  
April 12, 2018  
9ZXL1530D / 9ZXL1550D Datasheet  
Table 12. Filtered Phase Jitter Parameters - DB2000Q Filter  
Specification  
Parameter  
Symbol  
Conditions  
Minimum  
Typical  
Maximum  
Limit  
Units  
Notes  
fs  
Additive Phase Jitter  
t
100MHz  
50  
80  
1,2  
jph12k-20Madd  
(rms)  
1 Applies to all outputs when driven by Wenzel Associates source.  
2 For RMS values, additive jitter is calculated by solving for b [b = sqrt(c2 - a2)] where “a” is rms input jitter and “c” is rms total jitter.  
Table 13. Unfiltered Phase Jitter Parameters – 12kHz to 20MHz  
Specification  
Parameter  
Symbol  
Conditions  
Minimum  
Typical  
Maximum  
Limit  
Units  
Notes  
fs  
Phase Jitter, PLL  
Mode  
PLL High BW, SSC  
Off, 100MHz  
t
194  
233  
1,2  
jph12k-20MHi  
(rms)  
fs  
Phase Jitter, PLL  
Mode  
PLL Low BW, SSC  
Off, 100MHz  
Not  
applicable  
t
212  
105  
248  
124  
1,2  
jph12k-20MLo  
(rms)  
fs  
Additive Phase  
Jitter, Bypass Mode  
Bypass Mode, SSC  
Off, 100MHz  
t
1,2,3  
jph12k-20MByp  
(rms)  
1 Applies to all outputs when driven by Wenzel Associates source.  
2 12kHz to 20MHz brick wall filter.  
3 For RMS values, additive jitter is calculated by solving for b [b = sqrt(c2 - a2)] where “a” is rms input jitter and “c” is rms total jitter.  
©2018 Integrated Device Technology, Inc  
13  
April 12, 2018  
9ZXL1530D / 9ZXL1550D Datasheet  
Clock Periods  
Table 14. Clock Periods – Differential Outputs w ith Spread Spectrum Disabled  
Measurement Window  
1 Clock  
1μs  
0.1s  
0.1s  
0.1s  
1μs  
1 Clock  
- S S C  
- p p m  
+ p p m  
Long-Term  
Average  
+ S S C  
Center  
Frequency AbsPer  
-c2cjitter  
Short-Term Long-Term  
Average  
0 ppm  
Period  
Short-Term +c2cjitter  
Average  
Average  
AbsPer  
SSC On  
MHz  
Minimum  
Minimum  
Minimum  
Nominal  
Maximum  
Maximum  
Maximum Units Notes  
100.00  
133.33  
9.94900  
7.44925  
—
—
9.99900  
7.49925  
10.00000  
7.50000  
10.00100  
7.50075  
—
—
10.05100  
7.55075  
ns  
ns  
1,2,3  
1,2,4  
DIF  
Table 15. Clock Periods – Differential Outputs w ith Spread Spectrum Enabled  
Measurement Window  
1 Clock  
1μs  
0.1s  
0.1s  
0.1s  
1μs  
1 Clock  
- S S C  
- p p m  
+ p p m  
Long-Term  
Average  
+ S S C  
Short-Term  
Average  
Center  
Frequency  
MHz  
-c2cjitter  
AbsPer  
Minimum  
Short-Term Long-Term  
Average  
Minimum  
0 ppm  
Period  
Nominal  
+c2cjitter  
AbsPer  
Maximum Units Notes  
Average  
Minimum  
SSC On  
Maximum  
Maximum  
99.75  
9.94906  
7.44930  
9.99906  
7.49930  
10.02406  
7.51805  
10.02506  
7.51880  
10.02607  
7.51955  
10.05107  
7.53830  
10.10107  
7.58830  
ns  
ns  
1,2,3  
1,2,4  
DIF  
133.00  
1 Guaranteed by design and characterization, not 100% tested in production.  
2 All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with CK420BQ accuracy requirements  
(±100ppm). The buffer itself does not contribute to ppm error.  
3 Driven by SRC output of main clock, 100MHz PLL Mode or Bypass Mode.  
4 Driven by CPU output of main clock, 133MHz PLL Mode or Bypass Mode.  
©2018 Integrated Device Technology, Inc  
14  
April 12, 2018  
9ZXL1530D / 9ZXL1550D Datasheet  
Pow er Management  
Inputs  
Control Bits  
Outputs  
CKPWRGD_PD#  
DIF_IN/DIF_IN#  
SMBus EN bit  
DIFx/DIFx#  
FBOUT_NC/FBOUT_NC#  
PLL State  
0
X
X
0
1
Low/Low  
Low/Low  
Running  
Low/Low  
Running  
Running  
Off  
On  
On  
1
Running  
Pow er Connections  
Pin Number  
V
V
GND  
Description  
DD  
DDIO  
1
7
2
6
Analog PLL  
Analog input  
DIF clocks  
26, 41, 58  
19, 31, 36, 48, 51, 63  
16, 20, 25, 32, 35, 42, 47, 52, 57, 64  
Functionality at Pow er-Up (PLL Mode)  
100M_133M#  
Input (MHz)  
Output (MHz)  
1
0
100.00  
133.33  
100.00  
133.33  
PLL Operating Mode  
HIBW_BYPM_LOBW#  
Byte 0, bit [7:6]  
Low (PLL Low BW)  
Mid (Bypass)  
00  
01  
11  
High (PLL High BW)  
©2018 Integrated Device Technology, Inc  
15  
April 12, 2018  
9ZXL1530D / 9ZXL1550D Datasheet  
SMBus Addressing  
SADR[1:0]_tri  
SMBus Address (Read/Write bit = 0)  
00  
0M  
01  
D8  
DA  
DE  
C2  
C4  
C6  
CA  
CC  
CE  
M0  
MM  
M1  
10  
1M  
11  
Test Loads  
Low-Power HCSL Output Test Load  
(standard PCIe source-terminated test load)  
Rs  
CL  
L
Test  
Points  
Differential Zo  
CL  
Rs  
Table 16. Parameters for Low -Power HCSL Output Test Load  
Device  
Rs (Ω)  
Zo (Ω)  
L (inches)  
C (pF)  
L
27  
33  
85  
100  
85  
10  
10  
10  
10  
2
2
2
2
9ZXL1530  
Internal  
7.5  
9ZXL1550*  
100  
* Contact factory for versions of this device with Zo = 100Ω.  
Alternate Terminations  
The LP-HCSL output can easily drive other logic families. See “AN-891 Driving LVPECL, LVDS, and CML Logic with IDT's “Universal”  
Low-Power HCSL Outputs” for termination schemes for LVPECL, LVDS, CML and SSTL.  
©2018 Integrated Device Technology, Inc  
16  
April 12, 2018  
9ZXL1530D / 9ZXL1550D Datasheet  
General SMBus Serial Interface Information  
How to Write  
How to Read  
▪ Controller (host) sends a start bit  
▪ Controller (host) will send a start bit  
▪ Controller (host) sends the write address  
▪ IDT clock will acknowledge  
▪ Controller (host) sends the write address  
▪ IDT clock will acknowledge  
▪ Controller (host) sends the beginning byte location = N  
▪ IDT clock will acknowledge  
▪ Controller (host) sends the beginning byte location = N  
▪ IDT clock will acknowledge  
▪ Controller (host) sends the byte count = X  
▪ IDT clock will acknowledge  
▪ Controller (host) will send a separate start bit  
▪ Controller (host) sends the read address  
▪ IDT clock will acknowledge  
▪ Controller (host) starts sending Byte N–Byte N+X-1  
▪ IDT clock will acknowledge each byte one at a time  
▪ Controller (host) sends a stop bit  
▪ IDT clock will send the data byte count = X  
▪ IDT clock sends Byte N+X-1  
▪ IDT clock sends Byte 0–Byte X (if X(H) was written to Byte 8)  
▪ Controller (host) will need to acknowledge each byte  
▪ Controller (host) will send a not acknowledge bit  
▪ Controller (host) will send a stop bit  
Index Block Write Operation  
Controller (Host)  
starT bit  
Slave Address  
WR WRite  
IDT (Slave/Receiver)  
T
Index Block Read Operation  
ACK  
ACK  
ACK  
ACK  
Controller (Host)  
starT bit  
Slave Address  
WR WRite  
IDT (Slave/Receiver)  
Beginning Byte = N  
Data Byte Count = X  
Beginning Byte N  
T
ACK  
ACK  
Beginning Byte = N  
O
O
O
RT  
Repeat starT  
O
O
O
Slave Address  
RD  
ReaD  
ACK  
Byte N + X - 1  
ACK  
Data Byte Count = X  
Beginning Byte N  
P
stoP bit  
ACK  
ACK  
O
O
O
O
O
O
Byte N + X - 1  
N
P
Not  
stoP bit  
©2018 Integrated Device Technology, Inc  
17  
April 12, 2018  
9ZXL1530D / 9ZXL1550D Datasheet  
SMBus Table: PLL Mode and Frequency Select Register  
Byte 0  
Pin #  
Name  
Control Function  
Type  
0
1
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
—
—
PLL Mode 1  
PLL Mode 0  
PLL Operating Mode Readback 1  
PLL Operating Mode Readback 0  
Reserved  
R
R
Latch  
See PLL Operating Mode table  
Latch  
0
—
—
DIF_14_En  
DIF_13_En  
Output Control  
RW  
RW  
1
Disable  
Enable  
(Low/Low)  
Output Control  
1
0
Reserved  
Reserved  
0
—
100M_133M#  
Frequency Select Readback  
R
133MHz  
100MHz  
Latch  
SMBus Table: Output Control Register  
Byte 1  
Pin #  
Name  
Control Function  
Type  
0
1
Default  
Disable  
(Low/Low)  
Bit 7  
—
DIF_5_En  
Output Enable  
RW  
Enable  
1
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Reserved  
Output Enable  
Output Enable  
Output Enable  
Output Enable  
Output Enable  
Reserved  
0
1
1
1
1
1
0
—
—
—
—
—
DIF_4_En  
DIF_3_En  
DIF_2_En  
DIF_1_En  
DIF_0_En  
RW  
RW  
RW  
RW  
RW  
Disable  
(Low/Low)  
Enable  
SMBus Table: Output Control Register  
Byte 2  
Pin #  
Name  
Control Function  
Type  
0
1
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
—
—
—
DIF_12_En  
DIF_11_En  
DIF_10_En  
Output Control  
Output Control  
Output Control  
Reserved  
RW  
RW  
RW  
1
1
1
0
1
1
1
1
Disable  
(Low/Low)  
Enable  
—
—
—
—
DIF_9_En  
DIF_8_En  
DIF_7_En  
DIF_6_En  
Output Enable  
Output Enable  
Output Enable  
Output Enable  
RW  
RW  
RW  
RW  
Disable  
(Low/Low)  
Enable  
©2018 Integrated Device Technology, Inc  
18  
April 12, 2018  
9ZXL1530D / 9ZXL1550D Datasheet  
SMBus Table: Reserved Register  
Byte 3  
Pin #  
Name  
Control Function  
Type  
0
1
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
—
—
—
amp[2]  
amp[1]  
amp[0]  
RW  
RW  
RW  
1
Global Differential Output Control  
(LP-HCSL Outputs Only)  
0.3V–1V 100mV/step Default = 0.8V  
0
1
0
Reserved  
Enable S/W Control of PLL BW  
PLL Operating Mode 1  
PLL Operating Mode 1  
Reserved  
—
—
—
PLL_SW_EN  
PLL Mode 1  
PLL Mode 0  
RW  
RW  
RW  
Hardware Latch  
SMBus Control  
0
Latch  
Latch  
0
See PLL Operating Mode table  
Note: Setting bit 3 to '1' allows the user to override the latch value from pin 4 via use of bits 2 and 1. Use the values from the PLL  
Operating Mode table. Note that Byte 0, bits 7 and 6 will keep the value originally latched on pin 4. If the user changes these bits, a warm  
reset of the system will have to be accomplished.  
SMBus Table: Reserved Register  
Byte 4  
Pin #  
Name  
Control Function  
Type  
0
1
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
0
0
0
0
0
0
0
0
SMBus Table: Vendor & Revision ID Register  
Byte 5  
Pin #  
Name  
Control Function  
Type  
0
1
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
—
—
—
—
—
—
—
—
RID3  
RID2  
RID1  
RID0  
VID3  
VID2  
VID1  
VID0  
R
R
R
R
R
R
R
R
0
0
1
1
0
0
0
1
REVISION ID  
D = 0011  
VENDOR ID  
ICS/IDT = 0001  
©2018 Integrated Device Technology, Inc  
19  
April 12, 2018  
9ZXL1530D / 9ZXL1550D Datasheet  
SMBus Table: Device ID  
Byte 6  
Pin #  
Name  
Control Function  
Device ID 7 (MSB)  
Type  
0
1
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
—
—
—
—
—
—
—
—
R
R
R
R
R
R
R
R
1
x
0
x
x
0
1
1
Device ID 6  
Device ID 5  
Device ID 4  
Device ID 3  
Device ID 2  
Device ID 1  
Device ID 0  
1530/1550 is 155 Decimal or 9B Hex  
SMBus Table: Byte Count Register  
Byte 7  
Pin #  
Name  
Control Function  
Reserved  
Type  
0
1
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
0
0
0
0
1
0
0
0
Reserved  
Reserved  
—
—
—
—
—
BC4  
BC3  
BC2  
BC1  
BC0  
RW  
RW  
RW  
RW  
RW  
Writing to this register configures  
how many bytes will be read back.  
Default value is 8 hex, so 9 bytes (0 to  
8) will be read back by default.  
Package Outline Draw ings  
The package outline drawings are appended at the end of this document and are also accessible from the link below. The package  
information is the most current data available and is subject to change without notice or revision of this document.  
www.idt.com/document/psc/nlg64-package-outline-90-x-90-mm-body-050-mm-pitch-qfn-epad-size-615-x-615-mm  
Ordering Information  
Differential Output  
Impedance (Ω)  
Orderable Part Number  
Package  
Carrier Type  
Temperature  
9ZXL1530DKILF  
9ZXL1530DKILFT  
9ZXL1550DKILF  
9ZXL1550DKILFT  
33  
33  
85  
85  
9 x 9 mm, 0.50mm pitch 64-VFQFPN  
9 x 9 mm, 0.50mm pitch 64-VFQFPN  
9 x 9 mm, 0.50mm pitch 64-VFQFPN  
9 x 9 mm, 0.50mm pitch 64-VFQFPN  
Trays  
Reel  
-40°C to +85°C  
-40°C to +85°C  
-40°C to +85°C  
-40°C to +85°C  
Trays  
Reel  
“LF” designates PB-free configuration, RoHS compliant.  
“D” is the device revision designator (will not correlate with the datasheet revision).  
©2018 Integrated Device Technology, Inc  
20  
April 12, 2018  
9ZXL1530D / 9ZXL1550D Datasheet  
Marking Diagrams  
1. “I” denotes industrial temperature range  
2. “L” denotes RoHS compliant package.  
ICS  
9ZXL1550DIL  
LOT  
ICS  
9ZXL1530DIL  
LOT  
3. “YYWW” denotes the last two digits of the year and week the part was  
assembled.  
COO YYWW  
COO YYWW  
4. “COO” denotes country of origin.  
5. “LOT” denotes the lot number.  
Revision History  
Revision Date  
Description of Change  
April 12, 2018  
Updated absolute maximum supply voltage rating and VIHSMB to 3.9V.  
February 13, 2018  
▪ Updated front page text to indicate DB2000Q compatibility.  
▪ Removed reference to 5V tolerance in description of SMBDAT and SMBCLK pins.  
▪ Added DB2000Q additive phase jitter table.  
December 1, 2017  
November 2, 2017  
Removed “5V tolerant” reference in pins 11 and 12 descriptions.  
▪ Corrected PCIe, UPI phase jitter tables per characterization data.  
▪ Corrected transposed values for HiBW and Bypass Mode unfiltered phase jitter.  
September 29, 2017  
Initial release.  
Corporate Headquarters  
6024 Silver Creek Valley Road  
San Jose, CA 95138 USA  
www.IDT.com  
Sales  
Tech Support  
1-800-345-7015 or 408-284-8200  
Fax: 408-284-2775  
www.IDT.com/go/sales  
www.IDT.com/go/support  
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications described herein at any time,  
without notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same  
way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability  
of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not  
convey any license under intellectual property rights of IDT or any third parties.  
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be rea-  
sonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.  
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property  
of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Integrated Device Technology, Inc All rights reserved.  
©2018 Integrated Device Technology, Inc  
21  
April 12, 2018  
64-VFQFPN, Package Outline Drawing  
9.0 x 9.0 x 0.9 mm Body, 0.5mm Pitch, Epad 6.15 x 6.15 mm  
NLG64P2, PSC-4147-02, Rev 01, Page 1  
‹ꢀ,QWHJUDWHGꢀ'HYLFHꢀ7HFKQRORJ\ꢁꢀ,QFꢂ  
64-VFQFPN, Package Outline Drawing  
9.0 x 9.0 x 0.9 mm Body, 0.5mm Pitch, Epad 6.15 x 6.15 mm  
NLG64P2, PSC-4147-02, Rev 01, Page 2  
Package Revision History  
Description  
Date Created Rev No.  
Feb 21, 2018  
Nov 3, 2015  
Rev 01 New Format, Change QFN to VFQFPN, Added P2  
Rev 00 Initial Release  
‹ꢀ,QWHJUDWHGꢀ'HYLFHꢀ7HFKQRORJ\ꢁꢀ,QFꢂ  
厂商 型号 描述 页数 下载

IDT

 		9ZX21201 12 ，输出差分Z缓冲的第二代PCIe / 3和QPI[ 12-OUTPUT DIFFERENTIAL Z-BUFFER FOR PCIE GEN2/3 AND QPI ] 16 页

IDT

 		9ZX21201AKLF 12 ，输出差分Z缓冲的第二代PCIe / 3和QPI[ 12-OUTPUT DIFFERENTIAL Z-BUFFER FOR PCIE GEN2/3 AND QPI ] 16 页

IDT

 		9ZX21201AKLFT 12 ，输出差分Z缓冲的第二代PCIe / 3和QPI[ 12-OUTPUT DIFFERENTIAL Z-BUFFER FOR PCIE GEN2/3 AND QPI ] 16 页

IDT

 		9ZX21201BKLF 12 ，输出差分Z缓冲的第二代PCIe / 3和QPI[ 12-OUTPUT DIFFERENTIAL Z-BUFFER FOR PCIE GEN2/3 AND QPI ] 16 页

IDT

 		9ZX21201BKLFT 12 ，输出差分Z缓冲的第二代PCIe / 3和QPI[ 12-OUTPUT DIFFERENTIAL Z-BUFFER FOR PCIE GEN2/3 AND QPI ] 16 页

IDT

 		9ZX21501B 15输出差分Zbuffer的第二代PCIe / 3和QPI[ 15-Output Differential Zbuffer for PCIe Gen2/3 and QPI ] 16 页

IDT

 		9ZX21501BKLF 15输出差分Zbuffer的第二代PCIe / 3和QPI[ 15-Output Differential Zbuffer for PCIe Gen2/3 and QPI ] 16 页

IDT

 		9ZX21501BKLFT 15输出差分Zbuffer的第二代PCIe / 3和QPI[ 15-Output Differential Zbuffer for PCIe Gen2/3 and QPI ] 16 页

IDT

 		9ZX21901B 19 ，输出差分Zbuffer的第二代PCIe / 3和QPI[ 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI ] 16 页

IDT

 		9ZX21901BKLF 19 ，输出差分Zbuffer的第二代PCIe / 3和QPI[ 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI ] 16 页

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