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9ZXL0631EKILF

型号：

9ZXL0631EKILF

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

20 页

PDF大小：

303 K

下载PDF手册
6-Output DB800ZL Derivative  
for PCIe Gen1–4 and UPI  
9ZXL0631E / 9ZXL0651E  
Datasheet  
Description  
Features  
▪ LP-HCSL outputs; eliminate 12 resistors, save 20mm2 of area  
The 9ZXL0631E / 9ZXL0651E are second-generation,  
enhanced-performance DB800ZL derivatives. The parts are  
pin-compatible upgrades to the 9ZXL0631A and 9ZXL0651A,  
while offering a much improved phase jitter performance. A fixed  
external feedback maintains low drift for critical QPI/UPI  
applications.  
(0631E)  
▪ LP-HCSL outputs with 85Ω Zout; eliminate 24 resistors, save  
48mm2 of area (0651E)  
▪ 6 OE# pins; hardware control of each output  
▪ Selectable PLL BW; minimizes jitter peaking in cascaded PLL  
topologies  
PCIe Clocking Architectures  
Supported  
▪ Hardware/SMBus control of PLL bandwidth and bypass;  
change mode without power cycle  
▪ Spread spectrum compatible; tracks spreading input clock for  
▪ Common Clocked (CC)  
EMI reduction  
▪ Independent Reference (IR) with and without spread spectrum  
▪ 100MHz PLL Mode; UPI support  
▪ 5 × 5 mm 40-QFN package; small board footprint  
Typical Applications  
▪ Servers  
▪ Storage  
▪ JBOD  
Key Specifications  
▪ Cycle-to-cycle jitter < 50ps  
▪ Output-to-output skew < 50 ps  
▪ Networking  
▪ Input-to-output delay: fixed at 0ps  
▪ Input-to-output delay variation < 50ps  
▪ Phase jitter: PCIe Gen4 < 0.5ps rms  
▪ Phase jitter: QPI/UPI > = 9.6GB/s < 0.2ps rms  
▪ Phase jitter: IF-UPI < 1.0ps rms  
Output Features  
▪ 6 Low-power HCSL (LP-HCSL) output pairs (0631E)  
▪ 6 Low-power HCSL (LP-HCSL) output pairs with 85Ω Zout  
(0651E)  
Block Diagram  
VDDR  
VDDA  
VDD x9  
FBOUT_NC#  
FBOUT_NC  
PLL  
DIFIN#  
DIFIN  
DIF5#  
DIF5  
6 outputs  
SMBus  
Factory  
SMBCLK  
SMBDAT  
Engine Configuration  
DIF0#  
DIF0  
^vHIBW_BYPM-LOBW#  
^CKPWRGD_PD#  
vOE[5:0]#  
Control Logic  
Resistors are integrated on 9ZXL065x  
devices and external on9ZXL063x devices  
GNDR  
EPAD/GND  
©2018 Integrated Device Technology, Inc.  
1
August 14, 2018  
 
 
 
 
 
 
 
9ZXL0631E / 9ZXL0651E Datasheet  
Contents  
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
PCIe Clocking Architectures Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Output Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Key Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
PLL Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
SMBus Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Power Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
PLL Operating Mode Readback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
Clock Periods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Test Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Alternate Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
General SMBus Serial Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
How to Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
How to Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Package Outline Drawings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
Marking Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
©2018 Integrated Device Technology, Inc.  
2
August 14, 2018  
9ZXL0631E / 9ZXL0651E Datasheet  
Pin Assignments  
40 39 38 37 36 35 34 33 32 31  
VDDA  
1
2
3
4
5
6
7
8
9
30 NC  
^HIBW_BYPM_LOBW#  
^CKPWRGD_PD#  
GND  
29 VDD  
28 vOE3#  
27 DIF3#  
26 DIF3  
25 VDD  
24 DIF2#  
23 DIF2  
22 vOE2#  
21 VDD  
9ZXL0631  
9ZXL0651  
pin 41 is EPAD,  
connect to GND  
VDDR  
DIF_IN  
DIF_IN#  
SMBDAT  
SMBCLK  
FBOUT_NC# 10  
11 12 13 14 15 16 17 18 19 20  
40-QFN, 5 × 5 mm, 0.4mm pitch  
^ prefix indicates internal pull-up resistor  
v prefix indicates Internal pull-dow n resistor  
Pow er Management  
CKPWRGD_PD#  
DIF_IN  
SMBus EN bit  
OE[x]#  
DIF[x]  
PLL State (if not in Bypass Mode)  
0
1
X
X
0
0
1
1
X
0
1
0
1
Low/Low  
Low/Low  
Low/Low  
Running  
Low/Low  
OFF  
ON  
ON  
ON  
ON  
Running  
PLL Operating Mode  
Pow er Connections  
HIBW_BYPM_LOBW#  
Mode  
Pin Number  
Low  
Mid  
PLL Low BW  
Bypass  
V
GND  
Description  
DD  
1
41  
4
Analog PLL  
Analog input  
DIF clocks  
High  
PLL High BW  
5
Note: PLL is OFF in Bypass Mode.  
12,16,20,21,25,29,31,35,39  
41  
SMBus Addressing  
PLL Operating Mode Readback  
Address  
+ Read/Write Bit  
HIBW_BYPM_LOBW#  
Byte 0, bit 7  
Byte 0, bit 6  
1101100  
X
Low (Low BW)  
Mid (Bypass)  
0
0
1
0
1
1
High (High BW)  
©2018 Integrated Device Technology, Inc.  
3
August 14, 2018  
9ZXL0631E / 9ZXL0651E Datasheet  
Pin Descriptions  
Table 1. Pin Descriptions  
Number  
Name  
Type  
Description  
1
2
VDDA  
Power  
Power supply for PLL core.  
Tri-level input to select High BW, Bypass or Low BW Mode. Has an internal 120kΩ  
pull-up resistor. See PLL Operating Mode table for details.  
^HIBW_BYPM_LOBW#  
^CKPWRGD_PD#  
Latched In  
Input  
3
Input notifies device to sample latched inputs and start up on first high assertion. Low  
enters Power Down Mode, subsequent high assertions exit Power Down Mode. This pin  
has internal 120kΩ pull-up resistor.  
4
5
GND  
GND  
Ground pin.  
Power supply for differential input clock (receiver). This V should be treated as an  
analog power rail and filtered appropriately. Nominally 3.3V.  
DD  
VDDR  
Power  
6
7
DIF_IN  
DIF_IN#  
SMBDAT  
SMBCLK  
Input  
Input  
I/O  
HCSL true input.  
HCSL complementary input.  
8
Data pin of SMBUS circuitry.  
9
Input  
Clock pin of SMBUS circuitry.  
10  
Complementary half of differential feedback output. This pin should NOT be connected  
to anything outside the chip. It exists to provide delay path matching to get 0  
propagation delay.  
FBOUT_NC#  
Output  
11  
True half of differential feedback output. This pin should NOT be connected to anything  
outside the chip. It exists to provide delay path matching to get 0 propagation delay.  
FBOUT_NC  
VDD  
Output  
Power  
Input  
12  
13  
Power supply, nominally 3.3V.  
Active low input for enabling output 0. This pin has an internal 120kΩ pull-down.  
vOE0#  
1 = disable outputs, 0 = enable outputs.  
14  
15  
16  
17  
18  
DIF0  
DIF0#  
VDD  
Output  
Output  
Power  
Output  
Output  
Differential true clock output.  
Differential complementary clock output.  
Power supply, nominally 3.3V.  
DIF1  
Differential true clock output.  
DIF1#  
Differential complementary clock output.  
Active low input for enabling output 1. This pin has an internal 120kΩ pull-down.  
19  
vOE1#  
Input  
1 = disable outputs, 0 = enable outputs.  
20  
21  
VDD  
VDD  
Power  
Power  
Power supply, nominally 3.3V.  
Power supply, nominally 3.3V.  
Active low input for enabling output 2. This pin has an internal 120kΩ pull-down.  
22  
vOE2#  
Input  
1 = disable outputs, 0 = enable outputs.  
23  
24  
25  
26  
27  
DIF2  
DIF2#  
VDD  
Output  
Output  
Power  
Output  
Output  
Differential true clock output.  
Differential complementary clock output.  
Power supply, nominally 3.3V.  
DIF3  
Differential true clock output.  
DIF3#  
Differential complementary clock output.  
©2018 Integrated Device Technology, Inc.  
4
August 14, 2018  
9ZXL0631E / 9ZXL0651E Datasheet  
Table 1. Pin Descriptions (Cont.)  
Number  
Name  
Type  
Description  
Active low input for enabling output 3. This pin has an internal 120kΩ pull-down.  
28  
vOE3#  
Input  
1 = disable outputs, 0 = enable outputs.  
29  
30  
31  
VDD  
NC  
Power  
—
Power supply, nominally 3.3V.  
No connection.  
VDD  
Power  
Power supply, nominally 3.3V.  
Active low input for enabling output 4. This pin has an internal 120kΩ pull-down.  
32  
vOE4#  
Input  
1 = disable outputs, 0 = enable outputs.  
33  
34  
35  
36  
37  
DIF4  
DIF4#  
VDD  
Output  
Output  
Power  
Output  
Output  
Differential true clock output.  
Differential complementary clock output.  
Power supply, nominally 3.3V.  
DIF5  
Differential true clock output.  
DIF5#  
Differential complementary clock output.  
Active low input for enabling output 5. This pin has an internal 120kΩ pull-down.  
38  
vOE5#  
Input  
1 = disable outputs, 0 = enable outputs.  
39  
40  
41  
VDD  
NC  
Power  
—
Power supply, nominally 3.3V.  
No connection.  
EPAD  
GND  
Ground pad.  
Absolute Maximum Ratings  
The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause permanent damage to the  
device. Functional operation of the 9ZXL0631E / 9ZXL0651E at absolute maximum ratings is not implied. Exposure to absolute maximum  
rating conditions may affect device reliability.  
Table 2. Absolute Maximum Ratings  
Parameter  
Symbol  
Conditions  
Minimum  
Typical  
Maximum Units Notes  
Supply Voltage  
Input Low Voltage  
Input High Voltage  
Input High Voltage  
Storage Temperature  
Junction Temperature  
Input ESD Protection  
V
x
3.9  
V
V
V
V
1,2  
1
DD  
V
GND-0.5  
IL  
V
Except for SMBus interface.  
SMBus clock and data pins.  
V
+0.5  
DD  
1,3  
1
IH  
V
3.9  
150  
125  
IHSMB  
°
Ts  
-65  
C
1
Tj  
°C  
V
1
ESD prot Human Body Model.  
2500  
1
1 Guaranteed by design and characterization, not 100% tested in production.  
2 Operation under these conditions is neither implied nor guaranteed.  
3 Not to exceed 3.9V.  
©2018 Integrated Device Technology, Inc.  
5
August 14, 2018  
9ZXL0631E / 9ZXL0651E Datasheet  
Electrical Characteristics  
TA = TAMB. Supply voltages per normal operation conditions; see Test Loads for loading conditions  
Table 3. SMBus  
Parameter  
Symbol  
Conditions  
Minimum Typical Maximum Units Notes  
SMBus Input Low Voltage  
SMBus Input High Voltage  
SMBus Output Low Voltage  
SMBus Sink Current  
V
0.8  
V
V
ILSMB  
V
2.1  
V
DDSMB  
IHSMB  
V
At I  
0.4  
V
OLSMB  
PULLUP  
PULLUP.  
I
At V  
4
mA  
V
OL.  
Nominal Bus Voltage  
V
2.7  
3.6  
1000  
300  
1
1
1
5
DDSMB  
SCLK/SDATA Rise Time  
SCLK/SDATA Fall Time  
SMBus Operating Frequency  
t
(Max V - 0.15V) to (Min V + 0.15V).  
ns  
ns  
kHz  
RSMB  
IL  
IH  
t
(Min V + 0.15V) to (Max V - 0.15V).  
IH IL  
FSMB  
f
Maximum SMBus operating frequency.  
400  
MAXSMB  
1 Guaranteed by design and characterization, not 100% tested in production.  
2 Control input must be monotonic from 20% to 80% of input swing.  
3 Time from deassertion until outputs are > 200mV.  
4 DIF_IN input.  
5 The differential input clock must be running for the SMBus to be active.  
Table 4. DIF_IN Clock Input Parameters  
Parameter  
Symbol  
Conditions  
Cross over voltage.  
Minimum Typical  
Maximum Units Notes  
Input Crossover Voltage – DIF_IN  
Input Swing – DIF_IN  
V
150  
300  
0.4  
-5  
900  
mV  
mV  
V/ns  
μA  
1
1
CROSS  
V
Differential value.  
SWING  
Input Slew Rate – DIF_IN  
Input Leakage Current  
dv/dt  
Measured differentially.  
8
5
1,2  
I
V
= V  
V = GND.  
DD , IN  
IN  
IN  
Measurement from differential  
waveform.  
Input Duty Cycle  
d
45  
0
55  
%
1
1
tin  
Input Jitter – Cycle to Cycle  
J
Differential measurement.  
125  
ps  
DIFIn  
1 Guaranteed by design and characterization, not 100% tested in production.  
2 Slew rate measured through ±75mV window centered around differential zero.  
Table 5. Input/Supply/Common Parameters  
Parameter  
Symbol  
Conditions  
Minimum  
Typical  
Maximum Units Notes  
Supply Voltage  
V
x
Supply voltage for core and analog.  
3.135  
3.3  
3.465  
85  
V
DD  
Ambient Operating  
Temperature  
Industrial range (T ).  
IND  
T
-40  
2
°C  
AMB  
Single-ended inputs, except SMBus, tri-level  
inputs.  
Input High Voltage  
Input Low Voltage  
V
V
+ 0.3  
DD  
V
V
IH  
Single-ended inputs, except SMBus, tri-level  
inputs.  
V
GND - 0.3  
0.8  
IL  
©2018 Integrated Device Technology, Inc.  
6
August 14, 2018  
9ZXL0631E / 9ZXL0651E Datasheet  
Table 5. Input/Supply/Common Parameters (Cont.)  
Parameter  
Symbol  
Conditions  
Minimum  
Typical  
Maximum Units Notes  
Input High Voltage  
Input Mid Voltage  
Input Low Voltage  
V
Tri-level Inputs.  
Tri-level Inputs.  
Tri-level Inputs.  
2.2  
1.2  
V
+ 0.3  
DD  
V
V
IH  
V
V
V
/2  
DD  
1.8  
IL  
IL  
GND - 0.3  
-5  
0.8  
5
V
I
Single-ended inputs, V = GND, V = V  
DD.  
μA  
IN  
IN  
IN  
Single-ended inputs.  
Input Current  
V
= 0 V; inputs with internal pull-up resistors.  
IN  
I
-50  
50  
μA  
INP  
V
= V ; inputs with internal pull-down  
IN  
DD  
resistors.  
F
V
V
V
= 3.3V, Bypass Mode.  
1
400  
102.5  
135  
7
MHz  
MHz  
MHz  
nH  
ibyp  
DD  
DD  
DD  
Input Frequency  
Pin Inductance  
Capacitance  
F
= 3.3V, 100MHz PLL Mode.  
= 3.3V, 133.33MHz PLL Mode.  
98.5  
132  
100.00  
133.33  
ipll  
ipll  
pin  
F
L
1
1
C
Logic inputs, except DIF_IN.  
DIF_IN differential clock inputs.  
Output pin capacitance.  
1.5  
1.5  
5
pF  
IN  
INDIF_IN  
C
2.7  
6
pF  
1,4  
1
C
pF  
OUT  
From V power-up and after input clock  
DD  
Clk Stabilization  
T
stabilization or de-assertion of PD# to 1st  
clock.  
1
1.8  
ms  
1,2  
STAB  
Input SS  
Modulation  
Frequency PCIe  
Allowable frequency for PCIe applications  
f
30  
4
33  
10  
kHz  
MODINPCIe (Triangular modulation).  
DIF start after OE# assertion.  
OE# Latency  
t
5
clocks 1,2,3  
LATOE#  
DIF stop after OE# deassertion.  
DIF output enable after PD# de-assertion.  
Fall time of control inputs.  
Tdrive_PD#  
Tfall  
t
49  
300  
5
μs  
ns  
ns  
1,3  
2
DRVPD  
t
F
Trise  
t
Rise time of control inputs.  
5
2
R
1 Guaranteed by design and characterization, not 100% tested in production.  
2 Control input must be monotonic from 20% to 80% of input swing.  
3 Time from deassertion until outputs are > 200mV.  
4 DIF_IN input.  
Table 6. Current Consumption  
Parameter  
Symbol  
Conditions  
Minimum Typical  
Maximum Units Notes  
Operating Supply Current  
Operating Supply Current  
Power Down Current  
I
V
, PLL Mode at 100MHz.  
DDA  
37  
41  
3
45  
50  
4
mA  
mA  
mA  
mA  
1
DDA  
I
All other V pins at 100MHz.  
DD  
DD  
I
V
, CKPWRGD_PD# = 0.  
DDA  
1
DDAPD  
Power Down Current  
I
All other V pins, CKPWRGD_PD# = 0.  
1
2
DDPD  
DD  
1 Includes VDDR if applicable.  
©2018 Integrated Device Technology, Inc.  
7
August 14, 2018  
9ZXL0631E / 9ZXL0651E Datasheet  
Table 7. Skew and Differential Jitter Parameters  
Parameter  
Symbol  
Conditions  
Minimum Typical Maximum Units Notes  
Input-to-output skew in PLL Mode at 100MHz,  
nominal temperature and voltage.  
1,2,4,  
5,8  
CLK_IN, DIF[x:0]  
t
-100  
2.5  
-21.3  
2.6  
0
100  
4.5  
50  
ps  
ns  
ps  
SPO_PLL  
Input-to-output skew in Bypass Mode at 100MHz,  
nominal temperature and voltage.  
1,2,3,  
5,8  
CLK_IN, DIF[x:0]  
CLK_IN, DIF[x:0]  
t
PD_BYP  
Input-to-output skew variation in PLL Mode at  
100MHz, across voltage and temperature.  
1,2,3,  
5,8  
t
-50  
DSPO_PLL  
Input-to-output skew variation in Bypass Mode at  
100MHz, across voltage and temperature,  
1,2,3,  
5,8  
-250  
-350  
250  
350  
ps  
ps  
T
= 0 to 70°C.  
AMB  
CLK_IN, DIF[x:0]  
t
DSPO_BYP  
Input-to-output skew variation in Bypass Mode at  
100MHz, across voltage and temperature,  
1,2,3,  
5,8  
T
= -40 to 85°C.  
AMB  
Random differential tracking error between two 9ZX  
devices in Hi BW Mode.  
ps  
1,2,3,  
5,8  
CLK_IN, DIF[x:0]  
CLK_IN, DIF[x:0]  
DIF[x:0]  
t
3
5
DTE  
(rms)  
Random differential spread spectrum tracking error  
between two 9ZX devices in Hi BW Mode.  
1,2,3,  
5,8  
t
23  
50  
50  
ps  
ps  
DSSTE  
Output-to-output skew across all outputs, common  
to PLL and Bypass Mode, at 100MHz.  
1,2,3,  
8
t
SKEW_ALL  
PLL Jitter Peaking  
PLL Jitter Peaking  
PLL Bandwidth  
PLL Bandwidth  
Duty Cycle  
j
j
LOBW#_BYPASS_HIBW = 1.  
0
0
1.3  
1.3  
2.5  
2
dB  
dB  
7,8  
7,8  
8,9  
8,9  
1
peak-hibw  
peak-lobw  
LOBW#_BYPASS_HIBW = 0.  
pll  
LOBW#_BYPASS_HIBW = 1.  
2
2.6  
4
MHz  
MHz  
%
HIBW  
pll  
LOBW#_BYPASS_HIBW = 0.  
0.7  
45  
1.0  
1.4  
55  
LOBW  
t
Measured differentially, PLL Mode.  
Measured differentially, Bypass Mode at 100MHz.  
50.3  
DC  
Duty Cycle  
Distortion  
t
-1  
0
1
%
1,10  
DCD  
PLL Mode.  
14  
50  
5
ps  
ps  
1,11  
1,11  
Jitter, Cycle to  
Cycle  
t
jcyc-cyc  
Additive jitter in Bypass Mode.  
0.1  
1 Measured into fixed 2pF load cap. Input-to-output skew is measured at the first output edge following the corresponding input.  
2 Measured from differential cross-point to differential cross-point. This parameter can be tuned with external feedback path, if present.  
3 All Bypass Mode input-to-output specs refer to the timing between an input edge and the specific output edge created by it.  
4 This parameter is deterministic for a given device.  
5 Measured with scope averaging on to find mean value.  
6 “t” is the period of the input clock.  
7 Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL jitter peaking.  
8 Guaranteed by design and characterization, not 100% tested in production.  
9 Measured at 3db down or half power point.  
10 Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in Bypass Mode.  
11 Measured from differential waveform.  
©2018 Integrated Device Technology, Inc.  
8
August 14, 2018  
9ZXL0631E / 9ZXL0651E Datasheet  
Table 8. HCSL/LP-HCSL Outputs  
Industry  
Limits  
Parameter  
Symbol  
Conditions  
Minimum  
Typical  
Maximum  
Units Notes  
Slew Rate  
dV/dt  
Scope averaging on.  
2
2.9  
4
1 – 4  
V/ns  
%
1,2,3  
1,4,7  
Slew Rate  
Matching  
Single-ended measurement.  
ΔdV/dt  
Vmax  
7.1  
792  
-35  
372  
15  
20  
20  
1150  
Maximum  
Voltage  
Measurement on single-ended  
signal using absolute value (scope  
averaging off).  
660  
-150  
250  
850  
150  
550  
140  
mV  
7
Minimum  
Voltage  
Vmin  
-300  
7
Crossing  
Voltage (abs)  
Scope averaging off.  
Scope averaging off.  
Vcross_abs  
Δ-Vcross  
250 – 550  
140  
mV  
mV  
1,5,7  
1,6,7  
Crossing  
Voltage (var)  
1 Guaranteed by design and characterization, not 100% tested in production.  
2 Measured from differential waveform.  
3 Slew rate is measured through the Vswing voltage range centered around differential 0 V. This results in a ±150mV window around differential 0V.  
4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a ±75mV window centered on the average  
cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use  
for the edge rate calculations.  
5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e. Clock  
rising and Clock# falling).  
6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross absolute) allowed.  
The intent is to limit Vcross induced modulation by setting Δ-Vcross to be smaller than Vcross absolute.  
7 At default SMBus settings.  
Table 9. Filtered Phase Jitter Parameters - PCIe Common Clocked (CC) Architectures  
Industry  
Limits  
Parameter  
Symbol  
Conditions  
Minimum Typical Maximum  
Units Notes  
PCIe Gen 1.  
ps  
t
t
13.4  
30  
86  
1,2,3  
(p-p)  
jphPCIeG1-CC  
PCIe Gen 2 Low Band  
10kHz < f < 1.5MHz  
(PLL BW of 5–16MHz or 8–16MHz,  
CDR = 5MHz).  
ps  
1,2  
0.2  
0.7  
3
(rms)  
jphPCIeG2-CC  
Phase Jitter,  
PLL Mode  
PCIe Gen 2 High Band  
1.5MHz < f < Nyquist (50MHz)  
(PLL BW of 5–16MHz or 8–16MHz,  
CDR = 5MHz).  
ps  
1,2  
1.0  
1.5  
3.1  
(rms)  
PCIe Gen 3 (PLL BW of 2–4MHz or  
2–5MHz, CDR = 10MHz).  
ps  
1,2  
t
t
0.2  
0.2  
0.4  
0.4  
1
jphPCIeG3-CC  
jphPCIeG4-CC  
(rms)  
PCIe Gen 4 (PLL BW of 2–4MHz or  
2–5MHz, CDR = 10MHz).  
ps  
1,2  
0.5  
(rms)  
©2018 Integrated Device Technology, Inc.  
9
August 14, 2018  
9ZXL0631E / 9ZXL0651E Datasheet  
Table 9. Filtered Phase Jitter Parameters - PCIe Common Clocked (CC) Architectures (Cont.)  
Industry  
Limits  
Parameter  
Symbol  
Conditions  
Minimum Typical Maximum  
Units Notes  
PCIe Gen 1.  
ps  
t
t
0.01  
0.06  
1,2,3,4  
(p-p)  
jphPCIeG1-CC  
PCIe Gen 2 Low Band  
10kHz < f < 1.5MHz  
(PLL BW of 5–16MHz or 8–16MHz,  
CDR = 5MHz).  
ps  
0.01  
0.06  
1,2,3,4  
(rms)  
jphPCIeG2-CC  
Additive  
PCIe Gen 2 High Band  
Not  
Phase Jitter,  
Bypass Mode  
1.5MHz < f < Nyquist (50MHz)  
(PLL BW of 5–16MHz or 8–16MHz,  
CDR = 5MHz).  
Applicable  
ps  
0.01  
0.06  
1,2,3,4  
(rms)  
PCIe Gen 3 (PLL BW of 2–4MHz or  
2–5MHz, CDR = 10MHz).  
ps  
t
t
0.01  
0.01  
0.06  
0.06  
1,2,3,4  
(rms)  
jphPCIeG3-CC  
jphPCIeG4-CC  
PCIe Gen 4 (PLL BW of 2–4MHz or  
2–5MHz, CDR = 10MHz).  
ps  
1,2,3,4  
(rms)  
Table 10. Filtered Phase Jitter Parameters - PCIe Independent Reference (IR) Architectures  
Industry  
Limits  
Parameter  
Symbol  
Conditions  
Minimum Typical Maximum  
Units Notes  
PCIe Gen 2 (PLL BW of 16MHz, CDR  
= 5MHz).  
ps  
t
t
t
t
0.9  
0.6  
1.1  
2
1,2,5  
(rms)  
jphPCIeG2-SRIS  
Phase Jitter,  
PLL Mode  
PCIe Gen 3 (PLL BW of 2–4MHz or  
2–5MHz, CDR = 10MHz).  
ps  
0.65  
0.05  
0.05  
0.7  
1,2,5  
(rms)  
jphPCIeG3-SRIS  
jphPCIeG2-SRIS  
jphPCIeG3-SRIS  
PCIe Gen 2 (PLL BW of 16MHz, CDR  
= 5MHz).  
ps  
0.01  
0.01  
1,2,4,5  
(rms)  
Additive  
Phase Jitter,  
Bypass Mode  
Not  
Applicable  
PCIe Gen 3 (PLL BW of 2–4MHz or  
2–5MHz, CDR = 10MHz).  
ps  
1,2,4,5  
(rms)  
Notes for PCIe Filtered Phase Jitter tables (CC) and (IR)  
1 Applies to all differential outputs, guaranteed by design and characterization.  
2 Calculated from Intel-supplied clock jitter tool, when driven by 9SQL495x or equivalent with spread on and off.  
3 Sample size of at least 100K cycles. This figure extrapolates to 108ps pk-pk at 1M cycles for a BER of 1-12  
.
4 For RMS values, additive jitter is calculated by solving for “b” [b = sqrt(c2 - a2)], where “a” is rms input jitter and “c” is rms total jitter.  
5 IR is the new name for Separate Reference Independent Spread (SRIS) and Separate Reference no Spread (SRNS) PCIe clock architectures.  
According to the PCIe Base Specification Rev 4.0 version 0.7 draft, the jitter transfer functions and corresponding jitter limits are not defined for  
the IR clock architecture. Widely accepted industry limits using widely accepted industry filters are used to populate this table. There are no  
accepted filters or limits for IR clock architectures at PCIe Gen1 or Gen4 data rates.  
©2018 Integrated Device Technology, Inc.  
10  
August 14, 2018  
9ZXL0631E / 9ZXL0651E Datasheet  
Table 11. Filtered Phase Jitter Parameters - QPI/UPI  
Industry  
Limits  
Parameter  
Symbol  
Conditions  
Minimum Typical Maximum  
Units Notes  
QPI & UPI (100MHz or 133MHz,  
4.8Gb/s, 6.4Gb/s 12UI).  
0.14  
0.30  
0.5  
1,2  
t
t
jphQPI_UPI  
QPI & UPI (100MHz, 8.0Gb/s, 12UI).  
QPI & UPI (100MHz, > 9.6Gb/s, 12UI).  
0.07  
0.06  
0.13  
0.1  
0.3  
0.2  
1,2  
1,2  
ps  
Phase Jitter,  
PLL Mode  
(rms)  
0.1  
0.17  
0.14  
0.2  
t
IF-UPI.  
1
1,4,5  
1,2,3  
jphIF-UPI  
QPI & UPI (100MHz or 133MHz,  
4.8Gb/s, 6.4Gb/s 12UI).  
0.0  
0.01  
Additive  
Phase Jitter,  
Bypass Mode  
ps  
jphQPI_UPI  
Not  
Applicable  
QPI & UPI (100MHz, 8.0Gb/s, 12UI).  
QPI & UPI (100MHz, > 9.6Gb/s, 12UI).  
IF-UPI.  
0.0  
0.0  
0.01  
0.01  
0.07  
1,2,3  
1,2,3  
1,4  
(rms)  
t
0.06  
jphIF-UPI  
1 Applies to all differential outputs, guaranteed by design and characterization.  
2 Calculated from Intel-supplied clock jitter tool, when driven by 9SQL495x or equivalent with spread on and off.  
3 For RMS values, additive jitter is calculated by solving for “b” [b = sqrt(c2 - a2)], where “a” is rms input jitter and “c” is rms total jitter.  
4 Calculated from phase noise analyzer when driven by Wenzel Associates source with Intel-specified brick-wall filter applied.  
5 Top number is when the buffer is in Low BW mode, bottom number is when the buffer is in High BW mode.  
Table 12. Unfiltered Phase Jitter Parameters - 12kHz to 20MHz  
Industry  
Limits  
Parameter  
Symbol  
Conditions  
Minimum Typical Maximum  
Units Notes  
fs  
Phase Jitter, PLL  
Mode  
PLL High BW, SSC OFF,  
100MHz.  
t
171  
184  
107  
225  
225  
125  
1,2  
jph12k-20MHi  
(rms)  
fs  
Phase Jitter, PLL  
Mode  
PLL Low BW, SSC OFF,  
100MHz.  
Not  
Applicable  
t
1,2  
jph12k-20MLo  
(rms)  
fs  
Additive Phase Jitter,  
Bypass Mode, SSC OFF,  
100MHz.  
t
1,2,3  
(rms)  
jph12k-20MByp  
Bypass Mode  
1 Applies to all outputs when driven by Wenzel clock source.  
2 12kHz to 20MHz brick wall filter.  
3 For RMS values, additive jitter is calculated by solving for “b” [b = sqrt(c2 - a2)], where “a” is rms input jitter and “c” is rms total jitter.  
©2018 Integrated Device Technology, Inc.  
11  
August 14, 2018  
9ZXL0631E / 9ZXL0651E Datasheet  
Clock Periods  
Table 13. Differential Outputs w ith Spread Spectrum Disabled  
Measurement Window  
1 Clock  
1μs  
0.1s  
0.1s  
0.1s  
1μs  
1 Clock  
- S S C  
- p p m  
+ p p m  
+ S S C  
Center  
SSC Frequency  
-c2cjitter  
AbsPer  
Short-Term Long-Term  
Average  
0 ppm  
Period  
Long-Term Short-Term  
Average  
+c2cjitter  
AbsPer  
Average  
Average  
OFF  
MHz  
Minimum  
Minimum  
Minimum  
Nominal  
Maximum  
Maximum  
Maximum Units  
Notes  
DIF  
100.00  
9.94900  
—
9.99900  
10.00000  
10.00100  
—
10.05100  
ns  
1,2,3,4  
Table 14. Differential Outputs w ith Spread Spectrum Enabled  
Measurement Window  
1 Clock  
1μs  
0.1s  
0.1s  
0.1s  
1μs  
1 Clock  
- S S C  
- p p m  
+ p p m  
+ S S C  
Center  
SSC Frequency  
-c2cjitter  
AbsPer  
Short-Term Long-Term  
Average  
0 ppm  
Period  
Long-Term Short-Term  
Average  
+c2cjitter  
AbsPer  
Average  
Average  
OFF  
MHz  
Minimum  
Minimum  
Minimum  
Nominal  
Maximum  
Maximum  
Maximum Units  
Notes  
DIF  
99.75  
9.94906  
9.99906  
10.02406  
10.02506  
10.02607  
10.05107  
10.10107 ns  
1,2,3,4  
1 Guaranteed by design and characterization, not 100% tested in production.  
2 All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with CK420BQ accuracy requirements  
(±100ppm). The buffer itself does not contribute to ppm error.  
3 Driven by SRC output of main clock, 100MHz PLL Mode or Bypass Mode.  
4 Driven by CPU output of main clock, 133MHz PLL Mode or Bypass Mode.  
©2018 Integrated Device Technology, Inc.  
12  
August 14, 2018  
9ZXL0631E / 9ZXL0651E Datasheet  
Test Loads  
Low-Power HCSL Output Test Load  
(standard PCIe source-terminated test load)  
Rs  
CL  
L
Test  
Points  
Differential Zo  
CL  
Rs  
Table 15. Parameters for Low -Power HCSL Output Test Load  
Device  
Rs (Ω)  
Zo (Ω)  
L (inches  
C (pF)  
L
27  
33  
85  
100  
85  
10  
10  
10  
10  
2
2
2
2
9ZXL063x  
Internal  
7.5  
9ZXL065x*  
100  
* Contact factory for versions of this device with Zo = 100Ω.  
Alternate Terminations  
The LP-HCSL output can easily drive other logic families. See “AN-891 Driving LVPECL, LVDS, and CML Logic with IDT's “Universal”  
Low-Power HCSL Outputs” for termination schemes for LVPECL, LVDS, CML and SSTL.  
©2018 Integrated Device Technology, Inc.  
13  
August 14, 2018  
9ZXL0631E / 9ZXL0651E Datasheet  
General SMBus Serial Interface Information  
How to Write  
How to Read  
▪ Controller (host) sends a start bit  
▪ Controller (host) will send a start bit  
▪ Controller (host) sends the write address  
▪ IDT clock will acknowledge  
▪ Controller (host) sends the write address  
▪ IDT clock will acknowledge  
▪ Controller (host) sends the beginning byte location = N  
▪ IDT clock will acknowledge  
▪ Controller (host) sends the beginning byte location = N  
▪ IDT clock will acknowledge  
▪ Controller (host) sends the byte count = X  
▪ IDT clock will acknowledge  
▪ Controller (host) will send a separate start bit  
▪ Controller (host) sends the read address  
▪ IDT clock will acknowledge  
▪ Controller (host) starts sending Byte N through Byte N+X-1  
▪ IDT clock will acknowledge each byte one at a time  
▪ Controller (host) sends a stop bit  
▪ IDT clock will send the data byte count = X  
▪ IDT clock sends Byte N+X-1  
▪ IDT clock sends Byte 0 through Byte X (if X(H) was written to  
Index Block Write Operation  
Byte 8)  
Controller (Host)  
IDT (Slave/Receiver)  
▪ Controller (host) will need to acknowledge each byte  
▪ Controller (host) will send a not acknowledge bit  
▪ Controller (host) will send a stop bit  
T
starT bit  
Slave Address  
WR  
WRite  
ACK  
ACK  
ACK  
ACK  
Index Block Read Operation  
Beginning Byte = N  
Data Byte Count = X  
Beginning Byte N  
Controller (Host)  
starT bit  
IDT (Slave/Receiver)  
T
Slave Address  
WRite  
WR  
ACK  
ACK  
Beginning Byte = N  
O
O
O
O
O
O
RT  
Repeat starT  
Slave Address  
ReaD  
RD  
Byte N + X - 1  
ACK  
ACK  
P
stoP bit  
Data Byte Count=X  
Beginning Byte N  
ACK  
ACK  
O
O
O
O
O
O
Byte N + X - 1  
N
P
Not acknowledge  
stoP bit  
©2018 Integrated Device Technology, Inc.  
14  
August 14, 2018  
9ZXL0631E / 9ZXL0651E Datasheet  
SMBus Table: PLL Mode and Frequency Select Register  
Byte 0  
Pin #  
Name  
Control Function  
Type  
0
1
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
2
2
PLL Mode 1  
PLL Mode 0  
PLL Operating Mode Rd back 1  
PLL Operating Mode Rd back 0  
R
R
Latch  
See PLL Operating Mode Readback Table  
Latch  
Reserved  
Reserved  
Enable S/W control of PLL BW  
0
0
0
1
1
1
—
—
—
PLL_SW_EN  
PLL Mode 1  
PLL Mode 0  
RW  
RW  
RW  
HW Latch  
SMBus Control  
PLL Operating Mode 1  
PLL Operating Mode 1  
See PLL Operating Mode Readback Table  
Reserved  
Note: Setting bit 3 to '1' allows the user to override the latch value from pin 2 via use of bits 2 and 1. Use the values from the PLL  
Operating Mode Readback table. Note that bits 7 and 6 will keep the value originally latched on pin 5. If these bits are changed, a warm  
reset of the system must be completed.  
SMBus Table: Output Disable Register  
Byte 1  
Pin #  
Name  
Control Function  
Reserved  
Type  
0
1
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
0
1
1
0
0
1
1
0
26/27  
23/24  
DIF3_En  
DIF2_En  
Output Control - '0' overrides OE# pin  
Output Control - '0' overrides OE# pin  
Reserved  
RW  
RW  
Low/Low  
OE# pin control  
Reserved  
17/18  
14/15  
DIF1_En  
DIF0_En  
Output Control - '0' overrides OE# pin  
Output Control - '0' overrides OE# pin  
Reserved  
RW  
RW  
Low/Low  
OE# pin control  
SMBus Table: Output Disable Register  
Byte 2  
Pin #  
Name  
Control Function  
Type  
0
1
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Reserved  
0
0
0
0
0
1
1
0
Reserved  
Reserved  
Reserved  
Reserved  
36/37  
33/34  
DIF5_En  
DIF4_En  
Output Control - '0' overrides OE# pin  
Output Control - '0' overrides OE# pin  
Reserved  
RW  
RW  
Low/Low  
OE# pin control  
©2018 Integrated Device Technology, Inc.  
15  
August 14, 2018  
9ZXL0631E / 9ZXL0651E Datasheet  
SMBus Table: Reserved Register  
Byte 3  
Pin #  
Name  
Control Function  
Reserved  
Type  
Type  
Type  
0
1
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
0
0
0
0
0
0
0
0
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
SMBus Table: Reserved Register  
Byte 4  
Pin #  
Name  
Control Function  
0
1
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
0
0
0
0
0
0
0
0
SMBus Table: Vendor & Revision ID Register  
Byte 5  
Pin #  
Name  
Control Function  
0
1
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
—
—
—
—
—
—
—
—
RID3  
RID2  
RID1  
RID0  
VID3  
VID2  
VID1  
VID0  
R
R
R
R
R
R
R
R
0
1
0
0
0
0
0
1
REVISION ID  
VENDOR ID  
E rev = 0100  
–
–
–
–
–
–
–
–
©2018 Integrated Device Technology, Inc.  
16  
August 14, 2018  
9ZXL0631E / 9ZXL0651E Datasheet  
SMBus Table: Device ID  
Byte 6  
Pin #  
Name  
Control Function  
Device ID 7 (MSB)  
Type  
0
1
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
—
—
—
—
—
—
—
—
R
R
R
R
R
R
R
R
1
1
1
x
x
x
x
x
Device ID 6  
Device ID 5  
Device ID 4  
Device ID 3  
Device ID 2  
Device ID 1  
Device ID 0  
0631 is E3 Hex  
0651 is F3 Hex  
SMBus Table: Byte Count Register  
Byte 7  
Pin #  
Name  
Control Function  
Reserved  
Type  
0
1
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
0
0
0
0
1
0
0
0
Reserved  
Reserved  
—
—
—
—
—
BC4  
BC3  
BC2  
BC1  
BC0  
RW  
RW  
RW  
RW  
RW  
Writing to this register configures how  
many bytes will be read back.  
Default value is 8 hex, so 9 bytes (0 to  
8) will be read back by default.  
SMBus Table: Reserved Register  
Byte 8  
Pin #  
Name  
Control Function  
Type  
0
1
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
0
0
0
0
0
0
0
0
Package Outline Draw ings  
The package outline drawings are appended at the end of this document and are accessible from the link below. The package information  
is the most current data available.  
www.idt.com/document/psc/ndndg40-package-outline-50-x-50-mm-bodyepad-350mm-sq-040-mm-pitch-qfn  
©2018 Integrated Device Technology, Inc.  
17  
August 14, 2018  
9ZXL0631E / 9ZXL0651E Datasheet  
Marking Diagrams  
1. Line 2 is the truncated part number.  
ICS  
ICS  
L0651EIL  
YYWW  
COO  
2. “YYWW” is the last digits of the year and week that the part was assembled.  
3. “COO” denotes the country of origin.  
L0631EIL  
YYWW  
COO  
4. “LOT” denotes sequential lot number.  
LOT  
LOT  
Ordering Information  
Orderable Part Number  
Package  
Carrier Type  
Temperature  
9ZXL0631EKILF  
9ZXL0631EKILFT  
9ZXL0651EKILF  
9ZXL0651EKILFT  
5 × 5 mm, 0.4mm pitch 40-QFN  
5 × 5 mm, 0.4mm pitch 40-QFN  
5 × 5 mm, 0.4mm pitch 40-QFN  
5 × 5 mm, 0.4mm pitch 40-QFN  
Tray  
Reel  
Tray  
Reel  
-40° to +85°C  
-40° to +85°C  
-40° to +85°C  
-40° to +85°C  
Revision History  
Revision Date  
Description of Change  
August 14, 2018  
April 12, 2018  
Updated block diagram.  
Updated absolute maximum supply voltage rating and VIHSMB to 3.9V.  
Fixed typos on VDD pin numbers in Power Connections table.  
Removed “5V tolerant” reference in pins 8 and 9 descriptions.  
Initial release.  
January 9, 2018  
December 1, 2017  
September 29, 2017  
Corporate Headquarters  
Sales  
Tech Support  
6024 Silver Creek Valley Road  
San Jose, CA 95138 USA  
www.IDT.com  
1-800-345-7015 or 408-284-8200  
Fax: 408-284-2775  
www.IDT.com/go/sales  
www.IDT.com/go/support  
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications described herein at any time,  
without notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same  
way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability  
of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not  
convey any license under intellectual property rights of IDT or any third parties.  
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be rea-  
sonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.  
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property  
of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Integrated Device Technology, Inc. All rights reserved.  
©2018 Integrated Device Technology, Inc.  
18  
August 14, 2018  
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