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9ZXL1231AKILFT

型号：

9ZXL1231AKILFT

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

18 页

PDF大小：

193 K

下载PDF手册
12-output DB1200ZL  
9ZXL1231  
DATASHEET  
General Description  
Features/Benefits  
The 9ZXL1231 meets the demanding requirements of the  
Intel DB1200ZL specification, including the critical low-drift  
requirements of Intel CPUs.  
• Low-power push-pull HCSL outputs; eliminate 24 resistors,  
2
save 41mm of area  
• Pin compatible to 9ZX21201; easy path to >50% power  
savings  
• Space-saving 64 VFQFPN package  
• Fixed feedback path for 0ps input-to-output delay  
• 9 Selectable SMBus Addresses; multiple devices can  
share the same SMBus Segment  
Recommended Application  
Buffer for Romley, Grantley and Purley Servers, solid state  
storage and PCIe  
• 12 OE# pins; hardware control of each output  
• PLL or bypass mode; PLL can dejitter incoming clock  
• Selectable PLL bandwidth; minimizes jitter peaking in  
downstream PLL's  
Output Features  
• 12 - Low-Power (LP) HCSL output pairs  
Key Specifications  
• Cycle-to-cycle jitter <50ps  
• Spread Spectrum Compatible; tracks spreading input clock  
for low EMI  
• Output-to-output skew <50 ps  
• Input-to-output delay variation <50ps  
• PCIe Gen3 phase jitter <1.0ps RMS  
• Phase jitter: QPI/UPI >=9.6GB/s <0.2ps rms  
Block Diagram  
OE(11:0)#  
DFB_OUT_NC  
Z-PLL  
(SS Compatible)  
DIF(11:0)  
DIF_IN  
DIF_IN#  
HIBW_BYPM_LOBW#  
100M_133M#  
CKPWRGD/PD#  
SMB_A0_tri  
Logic  
SMB_A1_tri  
SMBDAT  
SMBCLK  
9ZXL1231 REVISION J 05/25/16  
1
©2016 Integrated Device Technology, Inc.  
9ZXL1231 DATASHEET  
Pin Configuration  
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49  
VDDA  
GNDA  
GND  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
DIF_7#  
DIF_7  
vOE7#  
vOE6#  
DIF_6#  
DIF_6  
GND  
2
NC  
3
100M_133M#  
4
HIBW_BYPM_LOBW#  
CKPWRGD_PD#  
GND  
5
6
7
VDDR  
8
9ZXL1231  
connect epad to ground  
DIF_IN  
VDD  
9
DIF_IN#  
DIF_5#  
DIF_5  
vOE5#  
vOE4#  
DIF_4#  
DIF_4  
GND  
10  
11  
12  
13  
14  
15  
16  
SMB_A0_tri  
SMBDAT  
SMBCLK  
SMB_A1_tri  
DFB_OUT_NC#  
DFB_OUT_NC  
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32  
9x9mm 64-pin VFQFPN  
Note: Pins with ^ prefix have internal 120K pullup  
Pins with v prefix have internal 120K pulldowm  
Power Management Table  
PLL STATE  
IF NOT IN  
DIF_IN/  
DIF_IN#  
SMBus  
EN bit  
DIF(11:0)/  
DIF(11:0)#  
BYPASS  
MODE  
CKPWRGD_PD#  
0
X
X
0
1
Low/Low  
Low/Low  
Running  
OFF  
ON  
ON  
1
Running  
Functionality at Power-up (PLL mode)  
Power Connections  
DIF_IN  
MHz  
100.00  
133.33  
Pin Number  
100M_133M#  
DIF(11:0)  
Description  
VDD  
1
8
VDDIO  
GND  
2
7
1
0
DIF_IN  
DIF_IN  
Analog PLL  
Analog Input  
24,40,57 25,32,49,56 23,33,41,48,58  
DIF clocks  
12-OUTPUT DB1200ZL  
2
REVISION J 05/25/16  
9ZXL1231 DATASHEET  
PLL Operating Mode Readback Table  
HiBW_BypM_LoBW#  
Low (Low BW)  
Byte0, bit 7  
Byte 0, bit 6  
0
0
0
1
Mid (Bypass)  
High (High BW)  
1
1
PLL Operating Mode  
HiBW_BypM_LoBW#  
MODE  
PLL Lo BW  
Bypass  
Low  
Mid  
High  
PLL Hi BW  
NOTE: PLL is OFF in Bypass Mode  
9ZXL1231 SMBus Addressing  
Pin  
SMB_A1_tri SMB_A0_tri  
SMBus Address  
0
0
0
M
M
D8  
0
M
1
0
M
1
0
M
1
DA  
DE  
C2  
C4  
M
1
1
C6  
CA  
CC  
CE  
1
REVISION J 05/25/16  
3
12-OUTPUT DB1200ZL  
9ZXL1231 DATASHEET  
Pin Descriptions  
PIN #  
PIN NAME  
VDDA  
GNDA  
NC  
TYPE  
DESCRIPTION  
1
2
3
PWR Power for the PLL core.  
GND Ground pin for the PLL core.  
N/A No Connection.  
3.3V Input to select operating frequency.  
See Functionality Table for Definition  
Trilevel input to select High BW, Bypass or Low BW mode.  
See PLL Operating Mode Table for Details.  
3.3V Input notifies device to sample latched inputs and start up on first high assertion, or exit Power Down  
Mode on subsequent assertions. Low enters Power Down Mode.  
4
5
100M_133M#  
IN  
HIBW_BYPM_LOBW#  
IN  
IN  
6
7
8
9
CKPWRGD_PD#  
GND  
GND Ground pin.  
3.3V power for differential input clock (receiver). This VDD should be treated as an analog power rail and  
filtered appropriately.  
HCSL True input  
HCSL Complementary Input  
VDDR  
PWR  
DIF_IN  
IN  
IN  
10 DIF_IN#  
SMBus address bit. This is a tri-level input that works in conjunction with the SMB_A1 to decode 1 of 9  
SMBus Addresses.  
11 SMB_A0_tri  
IN  
12 SMBDAT  
13 SMBCLK  
I/O  
IN  
Data pin of SMBUS circuitry, 5V tolerant  
Clock pin of SMBUS circuitry, 5V tolerant  
SMBus address bit. This is a tri-level input that works in conjunction with the SMB_A0 to decode 1 of 9  
SMBus Addresses.  
14 SMB_A1_tri  
IN  
Complementary half of differential feedback output, provides feedback signal to the PLL for  
15 DFB_OUT_NC#  
OUT synchronization with input clock to eliminate phase error. This pin should NOT be connected on the circuit  
board, the feedback is internal to the package.  
True half of differential feedback output, provides feedback signal to the PLL for synchronization with the  
OUT input clock to eliminate phase error. This pin should NOT be connected on the circuit board, the feedback  
is internal to the package.  
16 DFB_OUT_NC  
17 DIF_0  
OUT HCSL true clock output  
18 DIF_0#  
OUT HCSL Complementary clock output  
Active low input for enabling DIF pair 0. This pin has an internal pull-down.  
1 =disable outputs, 0 = enable outputs  
Active low input for enabling DIF pair 1. This pin has an internal pull-down.  
1 =disable outputs, 0 = enable outputs  
19 vOE0#  
20 vOE1#  
IN  
IN  
21 DIF_1  
22 DIF_1#  
23 GND  
OUT HCSL true clock output  
OUT HCSL Complementary clock output  
GND Ground pin.  
24 VDD  
PWR Power supply, nominal 3.3V  
PWR Power supply for differential outputs  
OUT HCSL true clock output  
25 VDDIO  
26 DIF_2  
27 DIF_2#  
OUT HCSL Complementary clock output  
Active low input for enabling DIF pair 2. This pin has an internal pull-down.  
1 =disable outputs, 0 = enable outputs  
Active low input for enabling DIF pair 3. This pin has an internal pull-down.  
1 =disable outputs, 0 = enable outputs  
28 vOE2#  
29 vOE3#  
IN  
IN  
30 DIF_3  
31 DIF_3#  
32 VDDIO  
33 GND  
OUT HCSL true clock output  
OUT HCSL Complementary clock output  
PWR Power supply for differential outputs  
GND Ground pin.  
34 DIF_4  
35 DIF_4#  
OUT HCSL true clock output  
OUT HCSL Complementary clock output  
Active low input for enabling DIF pair 4. This pin has an internal pull-down.  
1 =disable outputs, 0 = enable outputs  
36 vOE4#  
IN  
Active low input for enabling DIF pair 5. This pin has an internal pull-down.  
1 =disable outputs, 0 = enable outputs  
37 vOE5#  
IN  
12-OUTPUT DB1200ZL  
4
REVISION J 05/25/16  
9ZXL1231 DATASHEET  
Pin Descriptions (cont.)  
PIN #  
PIN NAME  
TYPE  
DESCRIPTION  
38 DIF_5  
39 DIF_5#  
40 VDD  
OUT HCSL true clock output  
OUT HCSL Complementary clock output  
PWR Power supply, nominal 3.3V  
GND Ground pin.  
41 GND  
42 DIF_6  
43 DIF_6#  
OUT HCSL true clock output  
OUT HCSL Complementary clock output  
Active low input for enabling DIF pair 6. This pin has an internal pull-down.  
1 =disable outputs, 0 = enable outputs  
Active low input for enabling DIF pair 7. This pin has an internal pull-down.  
1 =disable outputs, 0 = enable outputs  
44 vOE6#  
45 vOE7#  
IN  
IN  
46 DIF_7  
47 DIF_7#  
48 GND  
OUT HCSL true clock output  
OUT HCSL Complementary clock output  
GND Ground pin.  
49 VDDIO  
50 DIF_8  
51 DIF_8#  
PWR Power supply for differential outputs  
OUT HCSL true clock output  
OUT HCSL Complementary clock output  
Active low input for enabling DIF pair 8. This pin has an internal pull-down.  
1 =disable outputs, 0 = enable outputs  
Active low input for enabling DIF pair 9. This pin has an internal pull-down.  
1 =disable outputs, 0 = enable outputs  
52 vOE8#  
53 vOE9#  
IN  
IN  
54 DIF_9  
55 DIF_9#  
56 VDDIO  
57 VDD  
OUT HCSL true clock output  
OUT HCSL Complementary clock output  
PWR Power supply for differential outputs  
PWR Power supply, nominal 3.3V  
GND Ground pin.  
58 GND  
59 DIF_10  
60 DIF_10#  
OUT HCSL true clock output  
OUT HCSL Complementary clock output  
Active low input for enabling DIF pair 10. This pin has an internal pull-down.  
1 =disable outputs, 0 = enable outputs  
Active low input for enabling DIF pair 11. This pin has an internal pull-down.  
1 =disable outputs, 0 = enable outputs  
61 vOE10#  
62 vOE11#  
IN  
IN  
63 DIF_11  
64 DIF_11#  
65 epad  
OUT HCSL true clock output  
OUT HCSL Complementary clock output  
GND Connect epad to Ground  
Absolute Maximum Ratings  
Stresses above the ratings listed below can cause permanent damage to the 9ZXL1231. These ratings, which are standard  
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other  
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum  
rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the  
recommended operating temperature range.  
PARAMETER  
SYMBOL  
CONDITIONS  
UNITS NOTES  
MIN  
TYP  
MAX  
4.6  
Supply Voltage  
Input Low Voltage  
Input High Voltage  
Input High Voltage  
VDDx  
VIL  
V
V
V
V
1,2  
1
GND-0.5  
VIH  
Except for SMBus interface  
SMBus clock and data pins  
VDD+0.5  
5.5  
1,3  
1
VIHSMB  
°C  
°C  
V
1
1
1
Storage Temperature  
Junction Temperature  
Input ESD protection  
Ts  
Tj  
ESD prot  
-65  
150  
125  
Human Body Model  
2000  
1Guaranteed by design and characterization, not 100% tested in production.  
2 Operation under these conditions is neither implied nor guaranteed.  
3 Not to exceed 4.6V.  
REVISION J 05/25/16  
5
12-OUTPUT DB1200ZL  
9ZXL1231 DATASHEET  
Electrical Characteristics–SMBus  
TAMB = TCOM or TIND, unless noted., Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS NOTES  
SMBus Input Low Voltage  
SMBus Input High Voltage  
VILSMB  
VIHSMB  
0.8  
VDDSMB  
0.4  
V
V
2.1  
SMBus Output Low Voltage VOLSMB  
@ IPULLUP  
@ VOL  
V
SMBus Sink Current  
Nominal Bus Voltage  
SCLK/SDATA Rise Time  
IPULLUP  
VDDSMB  
tRSMB  
4
mA  
2.7  
3.6  
1000  
300  
V
1
1
1
(Max VIL - 0.15) to (Min VIH + 0.15)  
(Min VIH + 0.15) to (Max VIL - 0.15)  
ns  
ns  
SCLK/SDATA Fall Time  
SMBus Operating  
Frequency  
tFSMB  
fMAXSMB  
Maximum SMBus operating frequency  
400  
kHz  
5
1Guaranteed by design and characterization, not 100% tested in production.  
2Control input must be monotonic from 20% to 80% of input swing.  
3Time from deassertion until outputs are >200 mV  
4DIF_IN input  
5The differential input clock must be running for the SMBus to be active  
Electrical Characteristics–DIF_IN Clock Input Parameters  
TA = TCOM; Supply Voltage VDD = 3.3 V +/-5%, VDD_IO = 1.05 to 3.3V +/-5%  
PARAMETER  
SYMBOL  
VIHDIF  
CONDITIONS  
MIN  
600  
TYP  
800  
0
MAX  
1150  
300  
UNITS NOTES  
Differential inputs  
(single-ended measurement)  
Differential inputs  
Input High Voltage - DIF_IN  
Input Low Voltage - DIF_IN  
mV  
mV  
mV  
mV  
1
1
1
1
VILDIF  
VSS - 300  
300  
(single-ended measurement)  
Input Common Mode  
Voltage - DIF_IN  
VCOM  
Common Mode Input Voltage  
1000  
1450  
Peak to Peak value  
(single-ended measurement)  
Measured differentially  
VIN = VDD , VIN = GND  
Input Amplitude - DIF_IN  
VSWING  
300  
Input Slew Rate - DIF_IN  
Input Leakage Current  
Input Duty Cycle  
dv/dt  
IIN  
0.4  
-5  
8
5
V/ns  
uA  
%
1,2  
1
dtin  
Measurement from differential wavefrom  
45  
0
55  
125  
1
Input Jitter - Cycle to Cycle  
JDIFIn  
Differential Measurement  
ps  
1
1 Guaranteed by design and characterization, not 100% tested in production.  
2Slew rate measured through +/-75mV window centered around differential zero  
12-OUTPUT DB1200ZL  
6
REVISION J 05/25/16  
9ZXL1231 DATASHEET  
Electrical Characteristics–Input/Supply/Common Output Parameters  
TAMB = TCOM or TIND, unless noted., Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS NOTES  
Supply Voltage  
Output Supply Voltage  
VDDx  
VDDIO  
Supply voltage, except VDDIO  
Supply voltage for DIF outputs, if present  
3.135  
0.95  
0
3.3  
1.05  
3.465  
3.465  
70  
V
V
°C  
Commmercial range (TCOM  
)
Ambient Operating  
Temperature  
TAMB  
Industrial range (TIND  
)
-40  
85  
°C  
Single-ended inputs, except SMBus, tri-level  
Input High Voltage  
Input Low Voltage  
VIH  
VIL  
2
VDD + 0.3  
V
inputs  
Single-ended inputs, except SMBus, tri-level  
inputs  
GND - 0.3  
0.8  
V
Input High Voltage  
Input Mid Voltage  
Input Low Voltage  
VIHTRI  
VIMTRI  
VILTRI  
IIN  
Tri-Level Inputs  
2.2  
1.2  
VDD + 0.3  
V
V
Tri-Level Inputs  
Tri-Level Inputs  
VDD/2  
1.8  
0.8  
5
GND - 0.3  
-5  
V
Single-ended inputs, VIN = GND, VIN = VDD  
uA  
Single-ended inputs  
VIN = 0 V; Inputs with internal pull-up resistors  
VIN = VDD; Inputs with internal pull-down resistors  
Input Current  
IINP  
-200  
200  
uA  
Fibyp  
Fipll  
VDD = 3.3 V, Bypass mode  
VDD = 3.3 V, 100MHz PLL mode  
VDD = 3.3 V, 133.33MHz PLL mode  
33  
90  
150  
110  
147  
7
MHz  
MHz  
MHz  
Input Frequency  
Pin Inductance  
Capacitance  
100.00  
133.33  
Fipll  
120  
Lpin  
nH  
pF  
pF  
1
1
CIN  
Logic Inputs, except DIF_IN  
DIF_IN differential clock inputs  
1.5  
1.5  
5
CINDIF_IN  
2.7  
1,4  
COUT  
Output pin capacitance  
6
pF  
1
From VDD Power-Up and after input clock  
stabilization or de-assertion of PD# to 1st clock  
Allowable Frequency for PCIe Applications  
(Triangular Modulation)  
Clk Stabilization  
TSTAB  
0.18  
1.8  
ms  
1,2  
Input SS Modulation  
Frequency PCIe  
fMODINPCIe  
tLATOE#  
tDRVPD  
30  
4
33  
10  
kHz  
DIF start after OE# assertion  
DIF stop after OE# deassertion  
DIF output enable after  
OE# Latency  
Tdrive_PD#  
clocks 1,2,3  
300  
us  
1,3  
PD# de-assertion  
Tfall  
tF  
Fall time of control inputs  
5
5
ns  
ns  
2
2
Trise  
tR  
Rise time of control inputs  
1Guaranteed by design and characterization, not 100% tested in production.  
2Control input must be monotonic from 20% to 80% of input swing.  
3Time from deassertion until outputs are >200 mV  
4DIF_IN input  
REVISION J 05/25/16  
7
12-OUTPUT DB1200ZL  
9ZXL1231 DATASHEET  
Electrical Characteristics–DIF Low Power HCSL Outputs  
TAMB = TCOM or TIND, unless noted., Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP MAX UNITS NOTES  
V/ns  
V/ns  
%
TAMB = TCOM, Scope averaging on  
TAMB = TIND Scope averaging on  
Slew rate matching, Scope averaging on  
1.5  
1.5  
3.3  
3.1  
7
4
1,2,3  
1,2,3  
1,2,4  
Slew rate  
dV/dt  
4.5  
20  
Slew rate matching  
Voltage High  
dV/dt  
Δ
Statistical measurement on single-ended signal  
using oscilloscope math function. (Scope  
averaging on)  
VHigh  
660  
778  
0
850  
mV  
Voltage Low  
VLow  
-150  
150  
Max Voltage  
Min Voltage  
Crossing Voltage (abs)  
Crossing Voltage (var)  
Vmax  
Vmin  
Vcross_abs  
Measurement on single ended signal using  
absolute value. (Scope averaging off)  
Scope averaging off  
868  
-64  
430  
17  
1150  
mV  
-300  
250  
550  
140  
mV  
mV  
1,5  
1,6  
-Vcross  
Scope averaging off  
Δ
1Guaranteed by design and characterization, not 100% tested in production.  
2 Measured from differential waveform  
3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around  
differential 0V.  
4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on  
the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the  
oscilloscope is to use for the edge rate calculations.  
5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising  
edge (i.e. Clock rising and Clock# falling).  
6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross  
absolute) allowed. The intent is to limit Vcross induced modulation by setting -Vcross to be smaller than Vcross absolute.  
Δ
7 At default SMBus settings.  
Electrical Characteristics–Current Consumption  
TAMB = TCOM or TIND, unless noted., Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN TYP MAX  
UNITS  
NOTES  
VDDA, PLL Mode@100MHz  
VDDA, PLL Bypass Mode@100MHz  
All other VDD pins  
18  
6
16  
20  
10  
25  
mA  
mA  
mA  
1
1
IDDA  
Operating Supply Current  
IDD  
IDDIO  
VDDIO for DIF outputs, if applicable  
VDDA, PLL Mode@100MHz  
VDDA, PLL Bypass Mode@100MHz  
All other VDD pins  
91  
3
3
110  
5
5
mA  
mA  
mA  
mA  
1
1
IDDA  
Power Down Current  
IDD  
0.01  
1
IDDIO  
VDDIO for DIF outputs, if applicable  
0.01  
0.3  
mA  
1.  
Includes VDDR if applicable  
12-OUTPUT DB1200ZL  
8
REVISION J 05/25/16  
9ZXL1231 DATASHEET  
Electrical Characteristics–Skew and Differential Jitter Parameters  
TAMB = TCOM or TIND, unless noted., Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions  
PARAMETER  
SYMBOL  
tSPO_PLL  
CONDITIONS  
MIN TYP MAX  
UNITS  
ps  
NOTES  
Input-to-Output Skew in PLL mode  
@ nominal temperature and voltage  
Input-to-Output Skew in Bypass mode  
@ nominal temperature and voltage  
Input-to-Output Skew Varation in PLL mode  
across voltage and temperature  
CLK_IN, DIF[x:0]  
-100  
2.5  
-60  
3.6  
0
100  
4.5  
50  
1,2,4,5,8  
CLK_IN, DIF[x:0]  
CLK_IN, DIF[x:0]  
tPD_BYP  
ns  
ps  
1,2,3,5,8  
1,2,3,5,8  
tDSPO_PLL  
-50  
Input-to-Output Skew Varation in Bypass mode  
TAMB = TCOM  
-250  
-350  
250  
350  
ps  
ps  
1,2,3,5,8  
1,2,3,5,8  
CLK_IN, DIF[x:0]  
tDSPO_BYP  
Input-to-Output Skew Varation in Bypass mode  
TAMB = TIND  
Output-to-Output Skew across all outputs  
@100MHz, TAMB = TCOM  
Output-to-Output Skew across all outputs @  
100MHz, TAMB = TIND  
30  
30  
50  
65  
ps  
ps  
1,2,3,8  
1,2,3,8  
DIF{x:0]  
tSKEW_ALL  
PLL Jitter Peaking  
PLL Jitter Peaking  
PLL Bandwidth  
PLL Bandwidth  
Duty Cycle  
jpeak-hibw  
jpeak-lobw  
pllHIBW  
pllLOBW  
tDC  
LOBW#_BYPASS_HIBW = 1  
LOBW#_BYPASS_HIBW = 0  
LOBW#_BYPASS_HIBW = 1  
LOBW#_BYPASS_HIBW = 0  
0
0
1.2  
0.8  
3
2.5  
2
dB  
dB  
7,8  
7,8  
8,9  
8,9  
1
2
4
MHz  
MHz  
%
0.7  
45  
1.1  
50  
1.4  
55  
Measured differentially, PLL Mode  
Measured differentially, Bypass Mode  
@100MHz  
Duty Cycle Distortion  
Jitter, Cycle to cycle  
tDCD  
-1.5  
-0.6  
0
%
1,10  
PLL mode  
Additive Jitter in Bypass Mode  
34  
1
50  
5
ps  
ps  
1,11  
1,11  
tjcyc-cyc  
Notes for preceding table:  
1
Measured into fixed 2 pF load cap. Input to output skew is measured at the first output edge following the corresponding input.  
Measured from differential cross-point to differential cross-point. This parameter can be tuned with external feedback path, if present.  
All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it.  
2
3
4 This parameter is deterministic for a given device  
5
Measured with scope averaging on to find mean value.  
6.t is the period of the input clock  
7 Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL jitter peaking.  
8.  
Guaranteed by design and characterization, not 100% tested in production.  
9
Measured at 3 db down or half power point.  
10 Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mod  
11 Measured from differential waveform  
REVISION J 05/25/16  
9
12-OUTPUT DB1200ZL  
9ZXL1231 DATASHEET  
Electrical Characteristics–Phase Jitter Parameters  
TAMB = TCOM or TIND, unless noted., Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions  
PARAMETER  
SYMBOL  
tjphPCIeG1  
CONDITIONS  
MIN TYP MAX IND.LIMIT UNITS  
Notes  
1,2,3  
1,2  
PCIe Gen 1  
PCIe Gen 2 Lo Band  
10kHz < f < 1.5MHz  
34  
45.1  
1.43  
86  
3
ps (p-p)  
ps  
(rms)  
ps  
(rms)  
ps  
(rms)  
ps  
(rms)  
ps  
(rms)  
ps  
1.2  
tjphPCIeG2  
PCIe Gen 2 High Band  
1.5MHz < f < Nyquist (50MHz)  
PCIe Gen 3  
3.1  
1
2.2  
0.5  
2.63  
0.59  
1,2  
1,2,4  
1,4  
tjphPCIeG3  
Phase Jitter, PLL Mode  
(PLL BW of 2-4MHz, CDR = 10MHz)  
QPI & SMI  
(100MHz or 133MHz, 4.8Gb/s, 6.4Gb/s 12UI)  
QPI & SMI  
0.24 0.32  
0.14 0.23  
0.12 0.18  
0.5  
0.3  
tjphQPI_SMI  
1,4  
(100MHz, 8.0Gb/s, 12UI)  
QPI & SMI  
(100MHz, 9.6Gb/s, 12UI)  
0.2  
n/a  
n/a  
1,4  
(rms)  
tjphPCIeG1  
PCIe Gen 1  
PCIe Gen 2 Lo Band  
10kHz < f < 1.5MHz  
3.7  
0.1  
5.1  
0.2  
ps (p-p)  
ps  
(rms)  
ps  
(rms)  
ps  
(rms)  
ps  
1,2,3  
1,2,5  
tjphPCIeG2  
PCIe Gen 2 High Band  
1.5MHz < f < Nyquist (50MHz)  
PCIe Gen 3  
0.4  
0.0  
0.5  
n/a  
1,2,5  
1,2,4,5  
1,4,5  
0.1  
n/a  
AdditivePhase Jitter,  
tjphPCIeG3  
(PLL BW of 2-4 or 2-5 MHz, CDR = 10MHz)  
QPI & SMI  
(100MHz or 133MHz, 4.8Gb/s, 6.4Gb/s 12UI)  
QPI & SMI  
Bypass mode  
0.14  
0.2  
n/a  
n/a  
n/a  
(rms)  
ps  
(rms)  
ps  
tjphQPI_SMI  
0.00 0.01  
0.00 0.01  
1,4,5  
(100MHz, 8.0Gb/s, 12UI)  
QPI & SMI  
(100MHz, 9.6Gb/s, 12UI)  
1,4,5  
(rms)  
1 Applies to all outputs.  
2 See http://www.pcisig.com for complete specs  
3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.  
4 Calculated from Intel-supplied Clock Jitter Tool v 1.6.3  
5 For RMS figures, additive jitter is calculated by solving the following equation: Additive jitter = SQRT[(total jittter)^2 - (input jitter)^2]  
12-OUTPUT DB1200ZL  
10  
REVISION J 05/25/16  
9ZXL1231 DATASHEET  
Clock Periods–Differential Outputs with Spread Spectrum Disabled  
Measurement Window  
1 Clock  
1us  
-SSC  
0.1s  
- ppm  
0.1s  
0.1s  
+ ppm  
Long-Term  
Average  
Max  
1us  
+SSC  
Short-Term  
Average  
Max  
1 Clock  
Center  
Freq.  
MHz  
SSC OFF  
-c2c jitter  
AbsPer  
Min  
0 ppm  
Period  
Nominal  
+c2c jitter Units  
AbsPer  
Short-Term Long-Term  
Average  
Min  
Average  
Min  
Max  
100.00  
133.33  
9.94900  
7.44925  
9.99900  
7.49925  
10.00000  
7.50000  
10.00100  
7.50075  
10.05100  
7.55075  
ns  
ns  
DIF  
Clock Periods–Differential Outputs with Spread Spectrum Enabled  
Measurement Window  
1 Clock  
1us  
-SSC  
0.1s  
- ppm  
0.1s  
0.1s  
+ ppm  
Long-Term  
Average  
Max  
1us  
+SSC  
Short-Term  
Average  
Max  
1 Clock  
Center  
Freq.  
MHz  
SSC ON  
-c2c jitter  
AbsPer  
Min  
0 ppm  
Period  
Nominal  
+c2c jitter Units Notes  
AbsPer  
Max  
Short-Term Long-Term  
Average  
Min  
Average  
Min  
99.75  
133.00  
9.94906  
7.44930  
9.99906  
7.49930  
10.02406  
7.51805  
10.02506  
7.51880  
10.02607  
7.51955  
10.05107  
7.53830  
10.10107  
7.58830  
ns  
ns  
1,2,3  
1,2,4  
DIF  
Notes:  
1Guaranteed by design and characterization, not 100% tested in production.  
2 All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with CK420BQ/CK410B+  
accuracy requirements (+/-100ppm). The 9ZXL1231 itself does not contribute to ppm error.  
3
Driven by SRC output of main clock, 100 MHz PLL Mode or Bypass mode  
4
Driven by CPU output of main clock, 133 MHz PLL Mode or Bypass mode  
Differential Output Terminations  
Ω
Ω
Rs ( )  
DIF Zo ( )  
100  
85  
33  
27  
9ZXL Differential Test Loads  
10 inches  
Rs  
Rs  
85ohm Differential Zo  
2pF  
2pF  
Low-Power  
HCSL-  
Compatible  
Output buffer  
REVISION J 05/25/16  
11  
12-OUTPUT DB1200ZL  
9ZXL1231 DATASHEET  
General SMBus Serial Interface Information for 9ZXL1231  
How to Write  
How to Read  
• Controller (host) sends a start bit  
• Controller (host) sends the write address  
• IDT clock will acknowledge  
• Controller (host) will send a start bit  
• Controller (host) sends the write address  
• IDT clock will acknowledge  
• Controller (host) sends the beginning byte location = N  
• IDT clock will acknowledge  
• Controller (host) sends the beginning byte location = N  
• IDT clock will acknowledge  
• Controller (host) sends the byte count = X  
• IDT clock will acknowledge  
• Controller (host) starts sending Byte N through Byte  
N+X-1  
• Controller (host) will send a separate start bit  
• Controller (host) sends the read address  
• IDT clock will acknowledge  
• IDT clock will send the data byte count = X  
• IDT clock sends Byte N+X-1  
• IDT clock will acknowledge each byte one at a time  
• Controller (host) sends a Stop bit  
• IDT clock sends Byte 0 through Byte X (if X was  
written to Byte 8)  
(H)  
• Controller (host) will need to acknowledge each byte  
• Controller (host) will send a not acknowledge bit  
• Controller (host) will send a stop bit  
Index Block Write Operation  
Index Block Read Operation  
Controller (Host)  
IDT (Slave/Receiver)  
Controller (Host)  
starT bit  
IDT (Slave/Receiver)  
T
starT bit  
T
Slave Address  
Slave Address  
WRite  
WR  
WRite  
WR  
ACK  
ACK  
ACK  
ACK  
ACK  
ACK  
Beginning Byte = N  
Data Byte Count = X  
Beginning Byte N  
Beginning Byte = N  
RT  
Repeat starT  
Slave Address  
ReaD  
RD  
ACK  
O
O
O
O
O
O
Data Byte Count=X  
Beginning Byte N  
ACK  
ACK  
Byte N + X - 1  
ACK  
O
O
O
P
stoP bit  
O
O
O
Byte N + X - 1  
N
P
Not acknowledge  
stoP bit  
12-OUTPUT DB1200ZL  
12  
REVISION J 05/25/16  
9ZXL1231 DATASHEET  
SMBusTable: PLL Mode, and Frequency Select Register  
Byte 0  
Bit 7  
Pin #  
5
5
Name  
PLL Mode 1  
PLL Mode 0  
Control Function  
PLL Operating Mode Rd back 1  
PLL Operating Mode Rd back 0  
Reserved  
Type  
R
R
0
1
Default  
Latch  
Latch  
0
See PLL Operating Mode  
Readback Table  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Note:  
Reserved  
0
0
1
PLL_SW_EN  
PLL Mode 1  
PLL Mode 0  
100M_133M#  
Enable S/W control of PLL BW  
PLL Operating Mode 1  
PLL Operating Mode 1  
Frequency Select Readback  
RW  
RW  
RW  
R
HW Latch  
See PLL Operating Mode  
Readback Table  
133MHz  
SMBus Control  
1
4
Latch  
100MHz  
Setting bit 3 to '1' allows the user to overide the Latch value from pin 5 via use of bits 2 and 1. Use the values from the PLL Operating Mode  
Readback Table. Note that Bits 7 and 6 will keep the value originally latched on pin 5. A warm reset of the system will have to accomplished if the  
user changes these bits.  
SMBusTable: Output Control Register  
Byte 1  
Bit 7  
Pin #  
47/46  
Name  
Control Function  
Type  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
0
1
Default  
DIF_7_En  
DIF_6_En  
DIF_5_En  
DIF_4_En  
DIF_3_En  
DIF_2_En  
DIF_1_En  
DIF_0_En  
Output Control - '0' overrides OE# pin  
Output Control - '0' overrides OE# pin  
Output Control - '0' overrides OE# pin  
Output Control - '0' overrides OE# pin  
Output Control - '0' overrides OE# pin  
Output Control - '0' overrides OE# pin  
Output Control - '0' overrides OE# pin  
Output Control - '0' overrides OE# pin  
1
1
1
1
1
1
1
1
43/42  
39/38  
35/34  
30/31  
26/27  
21/22  
17/18  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Low/Low  
Enable  
SMBusTable: Output Control Register  
Byte 2  
Pin #  
Name  
Control Function  
Reserved  
Type  
0
1
Default  
0
0
0
0
1
1
1
1
Bit 7  
Reserved  
Reserved  
Reserved  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
64/63  
DIF_11_En  
DIF_10_En  
DIF_9_En  
DIF_8_En  
Output Control - '0' overrides OE# pin  
Output Control - '0' overrides OE# pin  
Output Control - '0' overrides OE# pin  
Output Control - '0' overrides OE# pin  
RW  
RW  
RW  
RW  
59/60  
54/55  
50/51  
Low/Low  
Enable  
SMBusTable: Reserved Register  
Byte 3  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Pin #  
Name  
Control Function  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Type  
0
1
Default  
0
0
0
0
0
0
0
0
SMBusTable: Reserved Register  
Byte 4  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Pin #  
Name  
Control Function  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Type  
0
1
Default  
0
0
0
0
0
0
0
0
SMBusTable: Vendor & Revision ID Register  
Byte 5  
Pin #  
Name  
RID3  
RID2  
RID1  
RID0  
VID3  
VID2  
VID1  
VID0  
Control Function  
Type  
R
R
R
R
R
R
R
R
0
1
Default  
-
-
-
-
-
-
-
-
X
X
X
X
0
0
0
1
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
REVISION ID  
A rev = 0000  
-
-
-
-
-
-
-
-
VENDOR ID  
REVISION J 05/25/16  
13  
12-OUTPUT DB1200ZL  
9ZXL1231 DATASHEET  
SMBusTable: DEVICE ID  
Byte 6  
Bit 7  
Pin #  
Name  
Control Function  
Device ID 7 (MSB)  
Type  
R
R
R
R
R
R
R
R
0
1
Default  
-
-
-
-
-
-
-
-
1
1
1
0
0
1
1
1
Device ID 6  
Device ID 5  
Device ID 4  
Device ID 3  
Device ID 2  
Device ID 1  
Device ID 0  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
1231 is 231 Decimal  
or E7 Hex  
SMBusTable: Byte Count Register  
Byte 7  
Pin #  
Name  
Control Function  
Reserved  
Type  
0
1
Default  
0
0
0
0
1
0
0
0
Bit 7  
Reserved  
Reserved  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
-
-
-
-
-
BC4  
BC3  
BC2  
BC1  
BC0  
RW  
RW  
RW  
RW  
RW  
Default value is 8 hex, so 9  
bytes (0 to 8) will be read back  
by default.  
Writing to this register configures how  
many bytes will be read back.  
SMBusTable: Reserved Register  
Byte 8 Pin # Name  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Control Function  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Type  
0
1
Default  
0
0
0
0
0
0
0
0
12-OUTPUT DB1200ZL  
14  
REVISION J 05/25/16  
9ZXL1231 DATASHEET  
Marking Diagram  
ICS  
ICS  
9ZXL1231AKL  
LOT  
9ZXL1231AIL  
LOT  
COO YYWW  
COO YYWW  
Notes:  
1. “L” denotes RoHS compliant package.  
2. “I” denotes industrial temperature range.  
3. “LOT” denotes the lot number.  
4. “COO”: country of origin.  
5. “YYWW” is the last two digits of the year and week that the part was assembled.  
REVISION J 05/25/16  
15  
12-OUTPUT DB1200ZL  
9ZXL1231 DATASHEET  
Package Outline and Package Dimensions (64-pin VFQFPN)  
(Ref)  
ND & NE  
Even  
Seating Plane  
(ND-1)x  
(Ref)  
e
A1  
Index Area  
(Typ)  
If ND & NE  
are Even  
L
A3  
e
2
N
1
2
N
Anvil  
Singulation  
1
2
(NE-1)x  
(Ref)  
e
-- or --  
E2  
E
E2  
2
Sawn  
Singulation  
Top View  
b
A
C
(Ref)  
ND & NE  
Odd  
e
Thermal Base  
D
D2  
2
C
D2  
0.08  
Millimeters  
Symbol  
Min  
0.8  
0
Max  
1.0  
A
A1  
0.05  
A3  
0.25 Reference  
0.18 0.3  
0.50 BASIC  
9.00 x 9.00  
b
e
D x E BASIC  
D2 MIN./MAX.  
E2 MIN./MAX.  
L MIN./MAX.  
N
6.00  
6.25  
6.25  
0.50  
6.00  
0.30  
64  
16  
16  
ND  
NE  
Ordering Information  
Part / Order Number Shipping Package  
Package  
64-pin VFQFPN  
64-pin VFQFPN  
64-pin VFQFPN -40°C to +85°C  
64-pin VFQFPN -40°C to +85°C  
Temperature  
0 to +70°C  
0 to +70°C  
9ZXL1231AKLF  
9ZXL1231AKLFT  
9ZXL1231AKILF  
9ZXL1231AKILFT  
Trays  
Tape and Reel  
Trays  
Tape and Reel  
"LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.  
“A” is the device revision designator (will not correlate with the datasheet revision).  
12-OUTPUT DB1200ZL  
16  
REVISION J 05/25/16  
9ZXL1231 DATASHEET  
Revision History  
Rev. Issuer Issue Date Description  
Page #  
1. Updated QPI references to QPI/UPI  
2. Updated DIF_IN table to match PCI SIG specification, no silicon change  
G
RDW 11/20/2015  
1,6  
H
J
RDW  
RDW  
12/2/2015 Corrected typo in I-temp marking diagram.  
5/25/2016 Add I-temp to ordering information.  
15  
16  
REVISION J 05/25/16  
17  
12-OUTPUT DB1200ZL  
Corporate Headquarters  
6024 Silver Creek Valley Road  
San Jose, CA 95138 USA  
Sales  
Tech Support  
www.idt.com/go/support  
1-800-345-7015 or 408-284-8200  
Fax: 408-284-2775  
www.IDT.com  
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in  
this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined  
in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether  
express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This  
document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.  
IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably  
expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.  
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Product specification subject to change without notice. Other trademarks and service marks used herein, including protected  
names, logos and designs, are the property of IDT or their respective third party owners.  
Copyright ©2016 Integrated Device Technology, Inc.. All rights reserved.  
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