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CYM1441PZ-25C

型号:

CYM1441PZ-25C

描述:

256K ×8静态RAM模块[ 256K x 8 Static RAM Module ]

品牌:

CYPRESS[ CYPRESS ]

页数:

6 页

PDF大小:

162 K

41  
CYM1441  
256K x 8 Static RAM Module  
Functional Description  
Features  
• High-density 2-megabit SRAM module  
• High-speed CMOS SRAMs  
— Access time of 20 ns  
• Low active power  
The CYM1441 is a very high performance 2-megabit static  
RAM module organized as 256K words by 8 bits. The module  
is constructed using eight 256K x 1 static RAMs in SOJ pack-  
ages mounted onto an epoxy laminate substrate with pins. Two  
chip selects (CSL and CSU) are used to independently enable  
the upper and lower 4 bits of the data word. Writing to the  
memory module is accomplished when the chip select (CS)  
and write enable (WE) inputs are both LOW. Data on the eight  
input pins (DI0 through DI7) is written into the memory location  
specified on the address pins (A0 through A17). Reading the  
device is accomplished by taking chip select (CS) LOW while  
write enable (WE) remains inactive or HIGH. Under these con-  
ditions, the contents of the memory location specified on the  
address pins will appear on the appropriate data output pins  
(DO0 through DO7). The data output pins remain in a high-  
impedance state unless the module is selected and write en-  
able (WE) is HIGH.Two pins (PD0 and PD1) are used to identify  
module memory density in applications where alternate ver-  
sions of the JEDEC-standard modules can be interchanged.  
— 5.3W (max.)  
• SMD technology  
• Separate data I/O  
• 60-pin ZIP package  
• TTL-compatible inputs and outputs  
• Low profile  
— Max. height of 0.5 in.  
• Small PCB footprint  
— 1.14 sq. in.  
Logic Block Diagram  
Pin Configuration  
ZIP  
TopView  
A - A  
0
17  
1
GND  
2
(OPEN)PD  
0
3
5
PD (GND)  
1
4
NC  
NC  
WE  
CS  
V
CC  
6
7
DI  
4
8
DI  
DO  
A
A
A
A
GND  
DI  
DO  
0
9
DO  
4
U
10  
12  
14  
16  
18  
20  
22  
24  
26  
28  
30  
0
11  
13  
15  
17  
19  
21  
23  
25  
27  
29  
NC  
0
A
1
2
A
3
4
256K x 1  
SRAM  
256K x 1  
SRAM  
256K x 1  
SRAM  
256K x 1  
SRAM  
A
5
6
A
7
DI  
5
1
1
DO  
5
V
CC  
WE  
A
A
DO - DO  
8
4
7
DI - DI  
4
9
7
NC  
CS  
L
CS  
L
31  
33  
35  
37  
39  
41  
43  
45  
47  
49  
51  
53  
55  
57  
59  
CS  
NC  
NC  
U
32  
34  
36  
38  
40  
42  
44  
46  
48  
50  
52  
54  
56  
58  
60  
NC  
NC  
V
CC  
256K x 1  
SRAM  
256K x 1  
SRAM  
256K x 1  
SRAM  
256K x 1  
SRAM  
DI  
6
DI  
2
DO  
GND  
6
DO  
2
A
10  
A
12  
A
14  
A
16  
A
11  
A
13  
A
15  
A
17  
DO - DO  
0
3
DI - DI  
0
3
NC  
DI  
DI  
7
3
DO  
7
DO  
3
V
CC  
NC  
NC  
GND  
NC  
NC  
Cypress Semiconductor Corporation  
Document #: 38-05271 Rev. **  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Revised March 15, 2002  
CYM1441  
Selection Guide  
1441-20  
20  
1441-25  
25  
1441-35  
35  
1441-45  
45  
Maximum Access Time (ns)  
Maximum Operating Current (mA)  
960  
960  
960  
960  
Maximum Standby Current (mA)  
320  
320  
320  
320  
Shaded area contains preliminary information.  
DC Voltage Applied to Outputs  
in High Z State................................................0.5V to +7.0V  
Maximum Ratings  
(Above which the useful life may be impaired.)  
DC Input Voltage ............................................0.5V to +7.0V  
Storage Temperature .................................55°C to +125°C  
Operating Range  
Ambient Temperature with  
Power Applied...............................................10°C to +85°C  
Ambient  
Temperature  
Supply Voltage to Ground Potential............... 0.5V to +7.0V  
Range  
VCC  
Commercial  
0°C to +70°C  
5V ± 10%  
Electrical Characteristics Over the Operating Range  
Parameter  
VOH  
Description  
Output HIGH Voltage  
Output LOW Voltage  
Input HIGH Voltage  
Test Conditions  
VCC = Min., IOH = 4.0 mA  
VCC = Min., IOL = 12.0 mA  
Min.  
Max.  
Unit  
2.4  
V
V
VOL  
VIH  
VIL  
IIX  
0.4  
VCC  
0.8  
2.2  
0.5  
80  
50  
V
Input LOW Voltage[1]  
V
Input Load Current  
GND < VI < VCC  
+80  
+50  
960  
320  
µA  
µA  
mA  
mA  
IOZ  
ICC  
ISB1  
Output Leakage Current  
VCC Operating Supply Current  
GND < VO < VCC, Output Disabled  
VCC = Max., IOUT = 0 mA, CS < VIL  
Automatic CS  
Max. VCC, CS > VIH,  
Power-Down Current  
Min. Duty Cycle = 100%  
ISB2  
Automatic CS  
Power-Down Current  
Max. VCC, CS > VCC - 0.2V,  
VIN > VCC - 0.2V or VIN < 0.2V  
160  
mA  
Capacitance[2]  
Parameter  
Description  
Input Capacitance  
Test Conditions  
Max.  
Unit  
CIN  
TA = 25°C, f = 1 MHz,  
VCC = 5.0V  
60  
15  
pF  
pF  
COUT  
Output Capacitance  
AC Test Loads and Waveforms  
R1329  
R1329Ω  
ALL INPUT PULSES  
90%  
5V  
5V  
OUTPUT  
3.0V  
90%  
OUTPUT  
R2  
202Ω  
10%  
10%  
R2  
202Ω  
GND  
30 pF  
5 pF  
< 5 ns  
< 5 ns  
INCLUDING  
JIG AND  
SCOPE  
INCLUDING  
JIG AND  
SCOPE  
(a)  
(b)  
Equivalent to:  
THÉVENIN EQUIVALENT  
125Ω  
1.9V  
OUTPUT  
Notes:  
1. VIN (min.) = 3.0V for pulse widths less than 20 ns.  
2. Tested on a sample basis.  
Document #: 38-05271 Rev. **  
Page 2 of 6  
CYM1441  
Switching Characteristics Over the Operating Range[3]  
1441-20  
1441-25  
1441-35  
1441-45  
Parameter  
Description  
Min. Max. Min. Max. Min. Max. Min. Max.  
Unit  
READ CYCLE  
tRC  
Read Cycle Time  
20  
3
25  
3
35  
3
45  
3
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tAA  
Address to Data Valid  
Data Hold from Address Change  
CS LOW to Data Valid  
CS LOW to Low Z  
20  
20  
12  
20  
25  
25  
15  
25  
35  
35  
25  
35  
45  
45  
30  
45  
tOHA  
tACS  
tLZCS  
tHZCS  
tPU  
3
3
3
3
CS HIGH to High Z[4]  
CS LOW to Power-Up  
0
0
0
0
tPD  
CS HIGH to Power-Down  
WRITE CYCLE[5]  
tWC  
Write Cycle Time  
20  
15  
15  
2
25  
20  
20  
2
35  
30  
30  
2
45  
35  
35  
2
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tSCS  
tAW  
CS LOW to Write End  
Address Set-Up to Write End  
Address Hold from Write End  
Address Set-Up to Write Start  
WE Pulse Width  
tHA  
tSA  
0
0
0
2
tPWE  
tSD  
15  
13  
0
20  
15  
0
25  
20  
0
30  
20  
0
Data Set-Up to Write End  
Data Hold from Write End  
WE HIGH to Low Z  
tHD  
tLZWE  
tHZWE  
3
3
3
3
WE LOW to High Z[4]  
0
13  
0
15  
0
20  
0
25  
Shaded area contains preliminary information.  
Switching Waveforms  
[6,7]  
Read Cycle No. 1  
t
RC  
ADDRESS  
t
AA  
t
OHA  
DATAOUT  
PREVIOUS DATA VALID  
DATA VALID  
Notes:  
3. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified  
IOL/IOH and 30-pF load capacitance.  
4.  
tHZCS and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured ±500 mV from steady state voltage.  
5. The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can  
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.  
6. WE is HIGH for read cycle.  
7. Device is continuously selected, CS = VIL  
.
Document #: 38-05271 Rev. **  
Page 3 of 6  
CYM1441  
Switching Waveforms (continued)  
Read Cycle No. 2 [6,8]  
t
RC  
CS  
t
ACS  
t
HZCS  
t
LZCS  
HIGH  
IMPEDANCE  
HIGH IMPEDANCE  
DATA VALID  
DATAOUT  
t
PD  
t
PU  
ICC  
V
50%  
CC  
50%  
SUPPLY  
ISB  
CURRENT  
Write Cycle No. 1 (WE Controlled) [5]  
t
WC  
ADDRESS  
t
SCS  
CS  
t
t
HA  
AW  
t
SA  
t
PWE  
WE  
t
t
HD  
SD  
DATAIN  
DATA VALID  
t
t
LZWE  
HZWE  
HIGH IMPEDANCE  
DATAOUT  
DATA UNDEFINED  
Write Cycle No. 2 (CS Controlled) [5,9]  
t
WC  
ADDRESS  
t
SA  
t
SCS  
CS  
t
t
HA  
AW  
t
PWE  
WE  
t
t
HD  
SD  
DATAIN  
DATA VALID  
t
HZWE  
HIGH IMPEDANCE  
DATAOUT  
DATA UNDEFINED  
Notes:  
8. Address valid prior to or coincident with CS transition LOW.  
9. If CS goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.  
Document #: 38-05271 Rev. **  
Page 4 of 6  
CYM1441  
Truth Table  
CS  
H
WE  
X
Input/Output  
High Z  
Mode  
Deselect/Power-Down  
Read  
L
H
Data Out  
Data In  
L
L
Write  
Ordering Information  
Package  
Operating  
Range  
Speed  
20  
Ordering Code  
CYM1441PZ-20C  
CYM1441PZ-25C  
CYM1441PZ-35C  
CYM1441PZ-45C  
Name  
PZ04  
PZ04  
PZ04  
PZ04  
Package Type  
60-Pin ZIP Module  
60-Pin ZIP Module  
60-Pin ZIP Module  
60-Pin ZIP Module  
Commercial  
Commercial  
Commercial  
Commercial  
25  
35  
45  
Shaded area contains preliminary information.  
Package Diagrams  
60-Pin ZIP Module PZ04  
BottomView  
0.330  
MAX  
3.440  
3.460  
0.050  
0.050  
0.500  
MAX  
0.120  
0.150  
0.008  
0.014  
0.250  
TYP  
0.100  
TYP  
0.050  
TYP  
0.135  
0.165  
0.015  
0.025  
0.100  
TYP  
Pin 1  
DIMENSIONS IN INCHES  
MIN.  
MAX.  
Document #: 38-05271 Rev. **  
Page 5 of 6  
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize  
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.  
CYM1441  
Document Title: CYM1441 256K x 8 Static RAM Module  
Document Number: 38-05271  
Issue  
Date  
Orig. of  
Change  
REV.  
ECN NO.  
Description of Change  
**  
114172  
3/19/02  
DSG  
Change from Spec number: 38-M-00020 to 38-05271  
Document #: 38-05271 Rev. **  
Page 6 of 6  
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