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CYM9263-50C

型号：

CYM9263-50C

描述：

64K （ 128K ， 256K ， 512K ）× 72 SRAM模块[ 64K(128K, 256K, 512K) x 72 SRAM Module ]

品牌：

CYPRESS[ CYPRESS ]

页数：

12 页

PDF大小：

210 K

下载PDF手册
62A  
CYM9260  
CYM9261B  
CYM9262A  
CYM9263  
64K x 72 SRAM Module  
128K x 72 SRAM Module  
256K x 72 SRAM Module  
512K x 72 SRAM Module  
surface mount packages on an epoxy laminate board with  
pins. The modules are designed to be incorporated into large  
memory arrays.  
Features  
• Operates at 66 MHz  
• Uses64K x18, 128K x18, or256K x18highperformance  
synchronous SRAMs  
• 168-position Angled DIMM from Amp p/n 179508-2  
• 3.3V inputs/data outputs  
The module is configured as either one or two banks, where  
each bank has separate chip select and output enable con-  
trols. Separate clocks are provided for every pair of SRAMs’s.  
Multiple ground pins and on-board decoupling capacitors en-  
sure high performance with maximum noise immunity.  
Functional Description  
All components on the cache modules are surface mounted on  
a multi-layer epoxy laminate (FR-4) substrate. The contact  
pins are plated with 150 micro-inches of nickel covered by 30  
micro-inches of gold flash.  
The CYM9260, CYM9261, CYM9262, and the CYM9263 are  
high-performance synchronous memory modules organized  
as 64K(9260), 128K(9261), 256K(9262), or 512K(9263) by 72  
bits. These modules are constructed from either 128K x  
18(9260,9261B,9262A) or 256K x 18 (9263) SRAMs in plastic  
LogicBlockDiagram- CYM9260  
V
cc3  
V
cc3  
R2  
R4  
A[15:0]  
WE[7:0]  
ADSP  
DQ[0:15]  
DQP[0:1]  
R3  
A
15:0  
OE[0:1]  
ADSP  
OE  
OE0  
CS0  
D[0:63]  
DP[0:7]  
CS[0:1]  
CS  
WEH  
WEL  
R1  
ADSC  
CLK  
BANK 0  
CLK[0:3]  
R1, R2, R3, R4 are optional resistors  
R1, R2, R4 are mounted for access using ADSC  
R3, R2, R4 are mounted for access using ADSP  
PD  
PD  
1
0
GND NC  
BANK 0  
64Kx72  
Cypress Semiconductor Corporation  
Document #: 38-05002 Rev. **  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
Revised March 27, 2002  
CYM9260  
CYM9261B  
CYM9262A  
CYM9263  
LogicBlockDiagram- CYM9261B/CYM9262A  
V
cc3  
V
cc3  
R2  
R4  
A[17:0]  
WE[0:7]  
ADSP  
DQ[0:15]  
DQP[0:1]  
R3  
A
17:0  
OE[0:1]  
ADSP  
OE  
OE0  
CE0  
D[0:63]  
DP[0:7]  
CS[0:1]  
CS  
WEH  
WEL  
ADSC  
CLK  
R1  
BANK 0  
CLK[0:3]  
D[0:15]  
DQ[0:1]  
A
17:0  
ADSP  
OE  
OE1  
CE1  
R1, R2, R3, R4 are optional resistors  
R1, R2, R4 are mounted for access using ADSC  
R3, R2, R4 are mounted for access using ADSP  
CS  
WEH  
WEL  
PD  
PD  
1
0
ADSC  
CLK  
NC  
GND BANK 0  
128Kx72  
256KX72  
GND GND  
BANK 0 & 1  
BANK 1  
Document #: 38-05002 Rev. **  
Page 2 of 12  
CYM9260  
CYM9261B  
CYM9262A  
CYM9263  
LogicBlockDiagram- CYM9263  
V
cc3  
V
cc3  
R2  
R4  
A[17:0]  
WE[0:7]  
DQ[0:15]  
DQP[0:1]  
R3  
ADSP  
A
17:0  
OE[0:1]  
ADSP  
OE  
OE0  
CE0  
D[0:63]  
DP[0:7]  
CS[0:1]  
CS  
WEH  
WEL  
ADSC  
CLK  
R1  
BANK 0  
CLK[0:3]  
D[0:15]  
DQ[0:1]  
A
17:0  
ADSP  
OE  
R1, R2, R3, R4 are optional resistors  
R1, R2, R4 are mounted for access using ADSC  
R3, R2, R4 are mounted for access using ADSP  
OE1  
CE1  
CS  
WEH  
WEL  
ADSC  
CLK  
PD  
PD  
1
0
NC  
NC  
BANK 0 & 1  
BANK 1  
512KX72  
Selection Guide  
Synchronous Cache Module  
CYM9261B-66 CYM9262A-66  
256 K x 72  
Part Number  
Cache Size  
CYM9260-66  
CYM9263-66  
64 K x 72  
4 of 64K x 18  
66  
128 K x 72  
4 of 128K x 18  
66  
512 K x 72  
SRAMs Used  
8 of 128K x 18  
66  
8 of 256K x 18  
66  
System Clock (MHz)  
Data tCDV  
10.3 ns  
10.3 ns  
10.3 ns  
10.3 ns  
Document #: 38-05002 Rev. **  
Page 3 of 12  
CYM9260  
CYM9261B  
CYM9262A  
CYM9263  
Pin Configuration  
Dual Read-Out SIMM (DIMM)  
Top View  
GND  
1
2
3
4
5
6
7
85  
86  
GND  
D
D
DP  
63  
62  
7
61  
D
87  
88  
89  
90  
91  
92  
93  
94  
V
GND  
CC3  
D
D
D
D
60  
58  
59  
57  
GND  
GND  
D
D
56  
55  
8
DP  
6
54  
9
D
10  
GND  
V
CC3  
D
D
GND  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
95  
96  
97  
98  
99  
D
D
GND  
D
D
GND  
D
D
53  
51  
52  
50  
D
DP  
49  
5
48  
47  
V
D
D
100  
101  
102  
103  
104  
105  
106  
107  
108  
109  
110  
111  
112  
113  
114  
115  
116  
117  
118  
119  
120  
121  
122  
123  
124  
CC3  
46  
44  
45  
43  
GND  
D
GND  
D
42  
41  
D
40  
DP  
4
GND  
V
CC3  
D
39  
D
D
38  
36  
D
37  
GND  
GND  
D
D
D
35  
33  
34  
32  
D
GND  
CLK3  
GND  
CLK2  
GND  
GND  
D
DP  
31  
3
30  
D
D
29  
V
D
CC3  
GND  
D
28  
27  
25  
D
GND  
D
D
26  
GND  
37  
38  
39  
40  
DP  
D
24  
2
22  
D
23  
V
GND  
CC3  
D
21  
D
20  
D
GND  
D
19  
D
GND  
D
D
GND  
D
D
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
125  
126  
127  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
139  
140  
141  
142  
143  
144  
145  
146  
147  
148  
149  
150  
151  
152  
153  
154  
155  
156  
157  
158  
159  
18  
17  
16  
15  
DP  
1
V
CC3  
D
D
GND  
D
14  
12  
13  
11  
GND  
10  
D
9
D
8
DP  
0
GND  
V
D
D
CC3  
D
D
7
5
6
4
GND  
GND  
D
D
D
D
CC3  
3
1
2
0
V
GND  
PD  
PD  
NC  
GND  
A
A
GND  
A
A
GND  
A
0
1
A
17  
GND  
A
16  
14  
15  
A
13  
V
CC3  
A
12  
10  
11  
A
9
GND  
A
67  
7
8
6
A
5
68  
69  
70  
71  
72  
73  
74  
75  
75  
77  
78  
79  
80  
81  
82  
A
GND  
V
CC3  
A
A
3
4
2
0
A
A
1
A
ADSP  
GND  
CLK0  
GND  
CLK1  
GND  
WE7  
WE5  
GND  
GND  
WE6  
WE4  
GND  
WE2  
WE0  
160  
161  
162  
163  
164  
165  
166  
167  
168  
WE3  
WE1  
V
CC3  
GND  
OE0  
CS0  
GND  
OE1  
CS1  
GND  
83  
84  
D
CYM9260  
CYM9261B  
CYM9262A  
CYM9263  
Pin Definitions  
Signal  
Description  
VCC3  
3V Supply  
GND  
Ground  
A[17:0]  
OE[1:0]  
WE[7:0]  
CS[1:0]  
PD0–PD1  
D[63:0]  
DP[7:0]  
CLK[0:3]  
ADSP  
Addresses From Processor  
Output Enables For The Two Banks  
Byte Write Enables  
Chip Select For The Two Banks  
Presence Detect Output Pins  
Data Lines From Processor  
Data Parity Lines From Processor  
Clock Lines To The Module  
Address Strobe From The Processor  
Signal Not Connected On Module  
Reserved  
NC  
RSVD  
Presence Detect Pins  
PD1  
GND  
NC  
PD0  
NC  
CYM9260 - 64K x 72  
CYM9261 - 128K x 72  
CYM9262 - 256K x 72  
CYM9263 - 512K x 72  
GND  
GND  
NC  
GND  
NC  
Document #: 38-05002 Rev. **  
Page 5 of 12  
CYM9260  
CYM9261B  
CYM9262A  
CYM9263  
DC Input Voltage ........................................... –0.5V to +4.6V  
Maximum Ratings  
Output Current into Outputs (LOW)............................. 20 mA  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
Operating Range  
Storage Temperature................................. –55°C to +125°C  
Ambient  
Ambient Temperature  
with Power Applied ........................................ –0°C to +70°C  
Range  
Temperature  
VCC  
Commercial  
0°C to +70°C  
3.3V ± 5%  
3.3V Supply Voltage to Ground Potential ..... –0.5V to +4.5V  
DC Voltage Applied to Outputs  
in High Z State.............................................. –0.5V to +4.6V  
Electrical Characteristics Over the Operating Range  
Parameter  
VIH  
Description  
Input HIGH Voltage  
Input LOW Voltage  
Output HIGH Voltage  
Output LOW Voltage  
Test Condition  
Min.  
2.2  
Max.  
Unit  
V
VCC + 0.3  
0.8  
VIL  
–0.3  
2.4  
V
VOH  
VCC = Min., IOH = –4 mA  
VCC = Min., IOL = 8 mA  
V
VOL  
0.4  
V
ICC (9260)  
ICC (9261)  
ICC (9262)  
ICC (9263)  
VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC  
VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC  
VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC  
VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC  
1000  
1000  
1200  
2400  
mA  
mA  
mA  
mA  
Capacitance[1]  
Parameter  
Description  
Test Conditions  
Max.  
24  
14  
20  
40  
24  
16  
20  
40  
9
Unit  
pF  
pF  
pF  
pF  
pF  
pF  
pF  
pF  
pF  
pF  
pF  
pF  
pF  
pF  
pF  
pF  
CA  
Address Input Capacitance  
Control Input Capacitance  
Input/Output Capacitance  
Clock Capacitance  
TA = 25°C, f = 1 MHz,  
9260  
9261  
9262  
9263  
9260  
9261  
9262  
9263  
9260  
9261  
9262  
9263  
9260  
9261  
9262  
9262  
VCC = 5.0V  
CI  
TA = 25°C, f = 1 MHz,  
VCC = 5.0V  
CO  
TA = 25°C, f = 1 MHz,  
VCC = 5.0V  
5
8
16  
6
CCLK  
TA = 25°C, f = 1 MHz,  
VCC = 5.0V  
3
5
10  
Note:  
1. Tested initially and after any design or process changes that may affect these parameters.  
Document #: 38-05002 Rev. **  
Page 6 of 12  
CYM9260  
CYM9261B  
CYM9262A  
CYM9263  
AC Test Loads and Waveforms[3]  
R1  
V
CCQ  
OUTPUT  
ALL INPUT PULSES  
OUTPUT  
3.3V  
GND  
90%  
10%  
R = 50 Ω  
L
90%  
10%  
R2  
5 pF  
V =1.5V  
L
INCLUDING  
JIG AND  
SCOPE  
≤ 3 ns  
≤ 3 ns  
(a)  
(b)[2]  
Switching Characteristics Over the Operating Range  
CYM9260/61/62/63  
66 MHz 50 MHz  
Parameter  
tCYC  
Description  
Min.  
Max.  
Min.  
20  
8
Max.  
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Clock Cycle Time  
Clock HIGH  
15  
6
tCH  
tCL  
Clock LOW  
6
8
tAS  
Address Set-Up Before CLK Rise  
Address Hold After CLK Rise  
Data Output Valid After CLK Rise  
Data Output Hold After CLK Rise  
ADSP, ADSC Set-Up Before CLK Rise  
ADSP, ADSC Hold After CLK Rise  
WH, WL Set-Up Before CLK Rise  
WH, WL Hold After CLK Rise  
Data Input Set-Up Before CLK Rise  
Data Input Hold After CLK Rise  
Chip Select Set-Up  
3.1  
0.5  
3.1  
0.5  
tAH  
tCDV  
tDOH  
tADS  
tADSH  
tWES  
tWEH  
tDS  
10.3  
14  
3
3
3.1  
0. 5  
3.1  
0.5  
3.3  
0.5  
3.1  
0.5  
3.1  
0.5  
3.1  
0.5  
3.3  
0.5  
3.1  
0.5  
tDH  
tCSS  
tCSH  
tEOZ  
Chip Select Hold After CLK Rise  
OE HIGH to Output High Z[4]  
OE LOW to Output Valid  
7
7
tEOV  
7
7
Notes:  
2. Resistor values for VCCQ = 3.3V are R1 = 317Ω and R2 = 351 Ω.  
3. Unless otherwise noted, test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output  
loading of the specified IOL/IOH and load capacitance. Shown in (a) and (b) of AC Test Loads. All measurements are made at room temperature.  
4.  
tEOZ is specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 500 mV from steady-state voltage.  
Document #: 38-05002 Rev. **  
Page 7 of 12  
CYM9260  
CYM9261B  
CYM9262A  
CYM9263  
Switching Waveforms  
Single Read[5]  
t
t
CL  
t
CYC  
CH  
CLK  
t
t
CSH  
CSS  
CS  
t
AS  
t
AH  
ADDRESS  
t
t
ADSH  
ADS  
[6]  
ADSP  
or  
ADSC  
t
t
WEH  
WES  
[7]  
WH, WL  
t
t
DOH  
CDV  
DATA OUT  
Single Write Timing (Using ADSC)  
t
t
CL  
CH  
CLK  
CS  
t
t
CSH  
CSS  
t
AS  
t
AH  
ADDRESS  
t
t
ADSH  
ADS  
ADSC  
t
t
WEH  
WES  
WH, WL  
t
t
DH  
DS  
DATA IN  
DATA OUT  
t
EOZ  
OE  
Notes:  
5. OE is LOW throughout this operation.  
6. If ADSP is asserted while CS is HIGH, ADSP will be ignored.  
7. ADSP has no effect on ADV, WL, and WH if CS is HIGH.  
Document #: 38-05002 Rev. **  
Page 8 of 12  
CYM9260  
CYM9261B  
CYM9262A  
CYM9263  
Switching Waveforms (continued)  
Single Write Cycle Using ADSP  
t
t
CL  
CH  
CLK  
t
t
CSS  
CSH  
CS  
t
AS  
t
AH  
ADDRESS  
ADSP  
t
t
ADSH  
ADS  
t
t
WEH  
WES  
[7]  
WH, WL  
t
t
DH  
DS  
DATA IN  
DATA OUT  
t
EOZ  
OE  
Output (Controlled by OE)  
DATA OUT  
t
t
EOV  
EOZ  
OE  
Output Timing (Controlled by CS)  
CLK  
t
t
ADSH  
ADS  
t
t
ADS  
ADSH  
ADSC  
t
t
CSH  
CSS  
t
t
CSH  
CSS  
CS  
t
t
CSOZ  
CDV  
DATA OUT  
Document #: 38-05002 Rev. **  
Page 9 of 12  
CYM9260  
CYM9261B  
CYM9262A  
CYM9263  
Switching Waveforms (continued)  
Output Timing (Controlled by WH/ WL)  
CLK  
t
ADSH  
t
t
t
ADSH  
ADS  
ADS  
ADSC and  
ADSP  
t
t
WES  
WEH  
WH, WL  
t
t
WEOZ  
WEOV  
DATA OUT  
Ordering Information  
Speed  
(MHz)  
Package  
Name  
Operating  
Range  
Ordering Code  
Package Type  
Description  
50  
CYM9260-50C  
CYM9261B-50C  
CYM9262A-50C  
CYM9263-50C  
CYM9260-66C  
CYM9261B-66C  
CYM9262A-66C  
CYM9263-66C  
PM43  
PM43  
PM43  
PM44  
PM43  
PM43  
PM43  
PM44  
168-Pin Dual-Readout SIMM (DIMM) Sync 64K x 72  
168-Pin Dual-Readout SIMM (SIMM) Sync 128K x 72  
168-Pin Dual-Readout SIMM (DIMM) Sync 256K x 72  
168-Pin Dual-Readout SIMM (DIMM) Sync 512K x 72  
168-Pin Dual-Readout SIMM (DIMM) Sync 64K x 72  
168-Pin Dual-Readout SIMM (SIMM) Sync 128K x 72  
168-Pin Dual-Readout SIMM (DIMM) Sync 256K x 72  
168-Pin Dual-Readout SIMM (DIMM) Sync 512K x 72  
Commercial  
66  
Document #: 38-05002 Rev. **  
Page 10 of 12  
CYM9260  
CYM9261B  
CYM9262A  
CYM9263  
Package Diagrams  
168-Pin Single-Sided DIMM PM43  
168-Pin Dual Sided DIMM PM44  
Document #: 38-05002 Rev. **  
Page 11 of 12  
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize  
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.  
CYM9260  
CYM9261B  
CYM9262A  
CYM9263  
Document Title: CYM9260, CYM9261B, CYM9262A, CYM9263 64K/128K/256K/512K x 72 SRAM Module  
Document Number: 38-05002  
Issue  
Date  
Orig. of  
Change  
REV.  
ECN NO.  
Description of Change  
**  
114556  
04/02/02  
DSG  
Change from Spec number: 38-M-00082 to 38-05002  
Document #: 38-05002 Rev. **  
Page 12 of 12  
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SUMIDA

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ETC

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CYPRESS

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CYPRESS

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