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CYK001M16ZCCAU-70BAI

型号：

CYK001M16ZCCAU-70BAI

描述：

16兆位（ 1M ×16 ）伪静态RAM[ 16-Mbit (1M x 16) Pseudo Static RAM ]

品牌：

CYPRESS[ CYPRESS ]

页数：

11 页

PDF大小：

312 K

下载PDF手册
CYK001M16ZCCA  
MoBL3™  
16-Mbit (1M x 16) Pseudo Static RAM  
(I/O0 through I/O15) are placed in a high-impedance state  
when: deselected (CE HIGH), outputs are disabled (OE  
HIGH), both Byte High Enable and Byte Low Enable are  
disabled (BHE, BLE HIGH), or during a write operation (CE  
LOW and WE LOW).  
Writing to the device is accomplished by asserting Chip  
Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low  
Enable (BLE) is LOW, then data from I/O pins (I/O0 through  
I/O7), is written into the location specified on the address pins  
(A0 through A17). If Byte High Enable (BHE) is LOW, then data  
from I/O pins (I/O8 through I/O15) is written into the location  
specified on the address pins (A0 through A17).  
Features  
• Wide voltage range: 2.70V–3.30V  
• Access Time: 55 ns, 70 ns  
• Ultra-low active power  
— Typical active current: 3 mA @ f = 1 MHz  
— Typical active current: 13 mA @ f = fmax  
• Ultra low standby power  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
• Deep Sleep Mode  
Reading from the device is accomplished by asserting Chip  
Enable (CE)and Output Enable (OE) inputs LOW while forcing  
the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is  
LOW, then data from the memory location specified by the  
address pins will appear on I/O0 to I/O7. If Byte High Enable  
(BHE) is LOW, then data from memory will appear on I/O8 to  
• Offered in a 48-ball BGA Package  
Functional Description  
The CYK001M16ZCCAU is a high-performance CMOS  
Pseudo static RAM organized as 1M words by 16 bits that  
supports an asynchronous memory interface. This device  
features advanced circuit design to provide ultra-low active  
current. This is ideal for providing More Battery Life™ (MoBL®)  
in portable applications such as cellular telephones. The  
device can be put into standby mode when deselected (CE  
HIGH or both BHE and BLE are HIGH). The input/output pins  
I/O15. Refer to the truth table for a complete description of read  
and write modes.  
This device incorporates a Low Power mode wherein data  
integrity is not guaranteed, but Power Consumption reduces  
to less than 100 µW. This mode (Deep Sleep Mode) is enabled  
by driving ZZ LOW.See the Truth Table for a complete  
description of Read, Write, and Deep Sleep mode.  
DATA IN DRIVERS  
Logic Block Diagram  
A10  
A 9  
A 8  
A 7  
A 6  
A 5  
A 4  
A 3  
1M × 16  
RAM Array  
I/O0–I/O7  
I/O8–I/O15  
A 2  
A 1  
A 0  
COLUMN DECODER  
BHE  
WE  
CE  
OE  
BLE  
ZZ  
Power-Down  
Circuit  
BHE  
BLE  
CE  
Note:  
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Document #: 38-05454 Rev. *B  
Revised May 15, 2004  
CYK001M16ZCCA  
MoBL3™  
Pin Configuration[2, 3, 4]  
FBGA  
Top View  
1
2
4
3
5
6
A
A
A
2
ZZ  
I/O  
OE  
BLE  
0
1
A
B
I/O BHE  
A
CE  
I/O  
A
0
8
4
3
I/O  
A
A
6
I/O  
I/O  
2
C
D
E
F
5
10  
9
1
A
V
SS  
Vcc  
Vss  
I/O  
I/O  
3
A17  
7
11  
GND  
A
16  
V
CC  
I/O  
I/O  
12  
4
A
A
15  
I/O  
I/O  
5
I/O  
I/O  
14  
13  
14  
6
A
A
A
G
I/O  
WE  
I/O  
19  
13  
12  
15  
7
A
A
A
A
H
A
18  
10  
9
11  
NC  
8
Product Portfolio[5]  
Power Dissipation  
Operating ICC(mA)  
f = 1MHz f = fmax  
Speed  
(ns)  
Product  
VCC Range (V)  
Typ.[5]  
Standby ISB2(µA)  
Min.  
2.70  
Max.  
3.30  
Typ.[5]  
Max.  
5
Typ.[5]  
13  
Max.  
22  
Typ.[5]  
Max.  
CYK001M16ZCCAU  
3.0  
55  
70  
3
80  
150  
17  
Notes:  
2. DNU pins have to be left floating.  
3. Ball H6 can be used to upgrade to 32M density.  
4. NC “no connect”—not connected internally to the die.  
5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V  
CC  
, T = 25°C.  
A
CC(typ.)  
Document #: 38-05454 Rev. *B  
Page 2 of 11  
CYK001M16ZCCA  
MoBL3™  
DC Voltage Applied to Outputs  
Maximum Ratings  
in High Z State[6, 7, 8] ........................................–0.4V to 3.7V  
DC Input Voltage[6, 7, 8].....................................–0.4V to 3.7V  
Output Current into Outputs (LOW)............................. 20 mA  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
Storage Temperature ................................–65°C to + 150°C  
Static Discharge Voltage.......................................... > 2001V  
Ambient Temperature with  
(per MIL-STD-883, Method 3015)  
Power Applied............................................–55°C to + 125°C  
Latch-Up Current....................................................> 200 mA  
Supply Voltage to Ground Potential................. –0.4V to 4.6V  
Operating Range  
Device  
Range  
Ambient Temperature  
VCC  
CYK001M16ZCCA  
Industrial  
–25°C to +85°C  
2.70V to 3.30V  
DC Electrical Characteristics (Over the Operating Range)  
CYK001M16ZCCAU- CYK001M16ZCCAU-  
55  
70  
Parameter  
VCC  
VOH  
Description  
Supply Voltage  
Output HIGH  
Voltage  
Test Conditions  
IOH = –-0.1 mA  
Min. Typ.[5] Max. Min. Typ.[5] Max. Unit  
2.7  
3.0  
3.3  
2.7  
3.3  
V
V
VCC  
VCC  
–0.4  
–0.4  
VOL  
VIH  
VIL  
IIX  
Output LOW  
Voltage  
Input HIGH  
Voltage  
Input LOW  
Voltage  
Input Leakage  
Current  
IOL = 0.1mA  
0.4  
0.4  
V
V
VCC= 2.7V to 3.3V  
0.8 *  
VCC  
–0.4  
VCC  
+
0.8 *  
VCC  
+
0.4V VCC  
0.4V  
0.4  
+1  
+1  
-0.4  
–1  
0.4  
+1  
+1  
V
GND < VIN < VCC  
–1  
µA  
µA  
IOZ  
ICC  
OutputLeakage GND < VOUT < VCC, Output Disabled  
Current  
–1  
–1  
VCC Operating  
Supply  
f = fMAX = 1/tRC  
f = 1 MHz  
VCC  
=
13  
3
22  
5
13  
3
17  
5
mA  
mA  
VCCmax  
IOUT = 0 mA  
CMOS  
Current  
levels  
ISB1  
Automatic CE  
Power-Down  
Current —  
CE > VCC−0.2V  
VCC = 3.3V  
100  
525  
100  
525  
µA  
V
IN > VCC–0.2V,  
VIN < 0.2V)  
CMOS Inputs  
f = fMAX (Address and  
Data Only),  
f = 0 (OE, WE, BHE  
and BLE), VCC = 3.30V  
ISB2  
Automatic CE  
Power-Down  
Current —  
CE > VCC – 0.2V  
VCC = 3.3V  
80  
150  
50  
80  
150  
50  
µA  
µA  
V
IN > VCC –0.2VorVIN  
< 0.2V,  
CMOS Inputs  
f = 0, VCC = 3.30V  
IZZ  
Deep Sleep  
Current  
VCC = VCCMAX; ZZ =  
LOW  
Notes:  
6. V  
7. V  
= –0.5V for pulse durations less than 20 ns.  
IL(MIN)  
IH(Max)  
= Vcc + 0.5V for pulse durations less than 20 ns.  
8. Overshoot and undershoot specifications are characterized and are not 100% tested.  
Document #: 38-05454 Rev. *B  
Page 3 of 11  
CYK001M16ZCCA  
MoBL3™  
Capacitance[9]  
Parameter  
CIN  
Description  
Input Capacitance  
Output Capacitance  
Test Conditions  
TA = 25°C, f = 1 MHz,  
Max.  
Unit  
pF  
8
8
V
CC = VCC(typ)  
COUT  
pF  
Thermal Resistance[9]  
Parameter  
Description  
Test Conditions  
BGA  
Unit  
ΘJA  
Thermal Resistance  
Test conditions follow standard test methods and  
55  
°C/W  
(Junction to Ambient)  
procedures for measuring thermal impedance, per EIA  
/ JESD51.  
ΘJC  
Thermal Resistance  
(Junction to Case)  
17  
°C/W  
AC Test Loads and Waveforms  
R1  
ALL INPUT PULSES  
VCC  
OUTPUT  
VCC  
GND  
90%  
90%  
10%  
10%  
Fall Time = 1 V/ns  
R2  
30 pF  
Rise Time = 1 V/ns  
INCLUDING  
JIG AND  
SCOPE  
Equivalent to:  
THEVENIN EQUIVALENT  
RTH  
OUTPUT  
VTH  
Parameters  
3.0V VCC  
22000  
22000  
11000  
1.50  
Unit  
Ω
R1  
R2  
RTH  
VTH  
Ω
Ω
V
Note:  
9. Tested initially and after any design or process changes that may affect these parameters.  
Document #: 38-05454 Rev. *B  
Page 4 of 11  
CYK001M16ZCCA  
MoBL3™  
Switching Characteristics Over the Operating Range[10, 11, 12, 13, 14]  
55 ns[14]  
Max.  
70 ns  
Parameter  
Read Cycle  
tRC  
Description  
Min.  
55[14]  
5
Min.  
70  
5
Max.  
Unit  
Read Cycle Time  
Address to Data Valid  
Data Hold from Address Change  
CE LOW to Data Valid  
OE LOW to Data Valid  
OE LOW to LOW Z[11, 13]  
OE HIGH to High Z[11, 13]  
CE LOW to Low Z[11, 13]  
CE HIGH to High Z[11, 13]  
BLE/BHE LOW to Data Valid  
BLE/BHE LOW to Low Z[11, 13]  
BLE/BHE HIGH to HIGH Z[11, 13]  
Address Skew  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tAA  
55  
70  
tOHA  
tACE  
tDOE  
tLZOE  
tHZOE  
tLZCE  
tHZCE  
tDBE  
tLZBE  
tHZBE  
55  
25  
70  
35  
5
2
5
5
25  
25  
25  
55  
25  
70  
5
5
10  
0
25  
10  
[14]  
tSK  
Write Cycle[12]  
tWC  
tSCE  
tAW  
tHA  
Write Cycle Time  
CE LOW to Write End  
55  
45  
45  
0
70  
60  
60  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Address Set-up to Write End  
Address Hold from Write End  
Address Set-up to Write Start  
WE Pulse Width  
BLE/BHE LOW to Write End  
Data Set-up to Write End  
Data Hold from Write End  
WE LOW to High-Z[11, 13]  
WE HIGH to Low-Z[11, 13]  
tSA  
0
0
tPWE  
tBW  
tSD  
tHD  
tHZWE  
40  
50  
25  
0
45  
60  
45  
0
25  
25  
tLZWE  
5
5
Notes:  
10. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 ns/V, timing reference levels of V  
/2, input pulse levels  
CC(typ)  
of 0V to V  
, and output loading of the specified I /I as shown in the “AC Test Loads and Waveforms” section.  
OL OH  
CC(typ.)  
11. t  
, t  
, t  
, and t  
transitions are measured when the outputs enter a high impedence state.  
HZOE HZCE HZBE  
HZWE  
12. The internal Write time of the memory is defined by the overlap of WE, CE = V , BHE and/or BLE = V . All signals must be ACTIVE to initiate a write and any  
IL  
IL  
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates  
the write.  
13. High-Z and Low-Z parameters are characterized and are not 100% tested.  
14. To achieve 55-ns performance, the read access should be CE controlled. In this case t  
is the critical parameter and t is satisfied when the addresses are  
SK  
ACE  
stable prior to chip enable going active. For the 70-ns cycle, the addresses must be stable within 10 ns after the start of the read cycle  
Document #: 38-05454 Rev. *B  
Page 5 of 11  
CYK001M16ZCCA  
MoBL3™  
Switching Waveforms  
Read Cycle 1 (Address Transition Controlled)[14, 15, 16]  
tRC  
ADDRESS  
tAA  
tSK  
tOHA  
DATA OUT  
PREVIOUS DATA VALID  
DATA VALID  
Read Cycle 2 (OE Controlled)[14, 16]  
ADDRESS  
tRC  
t
SK  
CE  
tHZCE  
tACE  
BHE/BLE  
tDBE  
tHZBE  
tLZBE  
OE  
tHZOE  
tDOE  
tLZOE  
HIGH  
IMPEDANCE  
HIGH IMPEDANCE  
tLZCE  
DATA OUT  
DATA VALID  
ICC  
V
CC  
50%  
50%  
SUPPLY  
ISB  
CURRENT  
Notes:  
15. Device is continuously selected. OE, CE = V .  
IL  
16. WE is HIGH for Read Cycle.  
Document #: 38-05454 Rev. *B  
Page 6 of 11  
CYK001M16ZCCA  
MoBL3™  
Switching Waveforms (continued)  
Write Cycle 1 (WE Controlled)[12, 13, 17, 18, 19]  
tWC  
ADDRESS  
CE  
tSCE  
tAW  
tHA  
tSA  
tPWE  
WE  
tBW  
BHE/BLE  
OE  
tSD  
tHD  
VALID DATA  
DATA I/O  
DON’T CARE  
tHZOE  
Write Cycle 2 (CE Controlled)[12, 13, 17, 18, 19]  
t WC  
ADDRESS  
CE  
tSCE  
t
SA  
tHA  
tAW  
tPWE  
WE  
tBW  
BHE/BLE  
OE  
tSD  
tHZOE  
tHD  
VALID DATA  
DATA I/O  
DON’T CARE  
Notes:  
17. Data I/O is high impedance if OE > V  
.
IH  
18. If Chip Enable goes INACTIVE with WE = V , the output remains in a high-impedance state.  
IH  
19. During the DON’T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.  
Document #: 38-05454 Rev. *B  
Page 7 of 11  
CYK001M16ZCCA  
MoBL3™  
Switching Waveforms (continued)  
Write Cycle 3 (WE Controlled, OE LOW)[18, 19]  
tWC  
ADDRESS  
CE  
tSCE  
tBW  
BHE/BLE  
tAW  
tHA  
tSA  
tPWE  
WE  
tSD  
tHD  
DON’T CARE  
DATAI/O  
VALID DATA  
tLZWE  
tHZWE  
Write Cycle 4 (BHE/BLE Controlled, OE LOW)[18, 19]  
tWC  
ADDRESS  
CE  
tSCE  
tAW  
tHA  
tBW  
BHE/BLE  
tSA  
tPWE  
WE  
tSD  
tHD  
DON’T CARE  
DATA I/O  
VALID DATA  
Document #: 38-05454 Rev. *B  
Page 8 of 11  
CYK001M16ZCCA  
MoBL3™  
Deep Sleep Mode  
This mode can be used to lower the power consumption of the  
PSRAM in an application. In this mode, the data integrity of the  
PSRAM is not guaranteed. Deep Sleep Mode can be enabled  
by driving ZZ LOW. The device stays in the deep sleep mode  
until ZZ is driven HIGH.  
Deep Sleep Mode—Entry/Exit[20]  
Deep Sleep Mode  
ZZ  
t
R
t
CDR  
CE or  
BLE / BHE  
Deep Sleep Access Timings[21, 22]  
Parameter  
Description  
Chip Deselect to ZZ LOW  
Operation Recovery Time  
Min.  
0
Max.  
Unit  
ns  
µs  
tCDR  
tR  
200  
Truth Table[23]  
ZZ  
H
H
CE  
H
X
WE  
X
X
OE  
X
X
BHE BLE  
Inputs/Outputs  
High Z  
High Z  
Mode  
Deselect/Power-down  
Deselect/Power-down  
Power  
Standby (ISB  
Standby (ISB  
X
H
L
X
H
L
)
)
H
L
H
L
Data Out (I/O0–I/O15  
)
Read (Upper Byte and Lower Active (ICC)  
Byte)  
H
H
L
L
H
H
L
L
H
L
L
Data Out (I/O0–I/O7);  
I/O8–I/O15 in High Z  
Data Out (I/O8–I/O15);  
I/O0–I/O7 in High Z  
Read (Lower Byte only)  
Active (ICC  
)
H
Read (Upper Byte only)  
Active (ICC)  
H
H
H
H
L
L
L
L
H
H
H
L
H
H
H
X
L
H
L
L
L
H
L
High Z  
High Z  
High Z  
Output Disabled  
Output Disabled  
Output Disabled  
Active (ICC  
Active (ICC  
Active (ICC  
)
)
)
L
Data In (I/O0–I/O15  
)
Write (Upper Byte and Lower Active (ICC)  
Byte)  
H
H
L
L
L
L
X
X
X
X
H
L
L
H
H
Data In (I/O0–I/O7);  
I/O8–I/O15 in High Z  
Data In (I/O8–I/O15);  
I/O0 –I/O7 in High Z  
Write (Lower Byte Only)  
Active (ICC  
Active (ICC  
Deep Sleep (IZZ)  
)
Write (Upper Byte Only)  
Deep Power-down  
)
L
H
H
High Z  
Notes:  
20. OE and the data pins are in a “don’t care” state while the device is in Deep Sleep Mode.  
21. All other timing parameters are as shown in the switching characteristics section.  
22. t applies only in the Deep Sleep Mode.  
R
23. H = Logic HIGH, L = Logic LOW, X = Don’t Care.  
Document #: 38-05454 Rev. *B  
Page 9 of 11  
CYK001M16ZCCA  
MoBL3™  
Ordering Information  
Speed  
Package  
Name  
BA48K  
Operating  
Range  
Industrial  
(ns)  
55  
Ordering Code  
CYK001M16ZCCAU-55BAI  
Package Type  
48-ball Fine Pitch BGA (6 mm × 8mm × 1.2 mm)  
70  
CYK001M16ZCCAU-70BAI  
BA48K  
48-ball Fine Pitch BGA (6 mm × 8mm × 1.2 mm)  
Industrial  
Package Diagram  
48-Lead FBGA (6 x 8 x 1.2 mm) BA48K  
BOTTOM VIEW  
TOP VIEW  
A1 CORNER  
Ø0.05 M C  
Ø0.25 M C A B  
Ø0.30 0.05ꢀ(48X  
A1 CORNER  
1
2
3
5
6
6
5
3
2
1
(
(
A
B
A
B
C
C
D
D
E
F
E
F
G
H
G
H
1.475  
A
A
0.75  
3.75  
6.00 0.10  
B
6.00 0.10  
B
0.15ꢀ(8X  
REFERENCE JEDEC MO-207  
SEATING PLANE  
51-85193-*A  
C
MoBL is a registered trademark and MoBL3 and More Battery Life are trademarks of Cypress Semiconductor Corporation. All  
product and company names mentioned in this document may be the trademarks of their respective holders.  
Document #: 38-05454 Rev. *B  
Page 10 of 11  
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize  
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.  
Cypressproductsarenotwarrantednorintendedtobeusedformedical, life-support, life-saving, criticalcontrolorsafetyapplications, unlesspursuanttoanexpresswrittenagreementwithCypress.  
CYK001M16ZCCA  
MoBL3™  
Document History Page  
Document Title: CYK001M16ZCCA MoBL3™ 16-Mbit (1M x 16) Pseudo Static RAM  
Document Number: 38-05454  
Issue  
Date  
01/27/04  
Orig. of  
Change  
AWK  
REV.  
**  
*A  
ECN NO.  
132407  
220121  
Description of Change  
New Data Sheet  
Changed the datasheet from AdvanceInformation to Final  
Added 55-ns speed bin and address skew restriction for 55-ns speed bin.  
Changed Izz from 30 µA to 50 µA.  
See ECN  
REF  
*B  
230851  
See ECN  
AJU  
Changed ball A6 from NC to ZZ  
Modified ordering code in “Ordering Information” table on page 10  
Replaced package diagram  
Modified MAX limit on DC Input voltage in ‘Maximum Ratings’ section  
Document #: 38-05454 Rev. *B  
Page 11 of 11  
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