HYS64(72)V4120GU-10
4M x 64/72 SDRAM-Module
A serial presence detect storage device - E 2PROM - is assembled onto the module. Information about the module
configuration, speed, etc. is written into the E 2PROM device during module production using a serial presence
detect protocol ( I2C synchronous 2-wire bus)
PD-Table:
Byte#
Description
SPD Entry Value
Hex
x64 x72
-10 -10
0
1
2
3
4
Number of SPD bytes
128
256
80
08
04
0B
09
80
08
04
0B
09
Total bytes in Serial PD
Memory Type
SDRAM
11
Number of Row Addresses (without BS bits)
Number of Column Addresses
(for x8 SDRAM)
9
5
6
7
8
9
Number of DIMM Banks
Module Data Width
2
64 / 72
0
02
40
00
01
A0
80
00
80
02
48
00
01
A0
80
02
80
Module Data Width (contd’ )
Module Interface Levels
SDRAM Cycle Time at CL=3
LVTTL
10.0 ns
8.0 ns
none / ECC
10 SDRAM Access Time from Clock at CL=3
11 Dimm Config (Error Det/Corr.)
12 Refresh Rate/Type
Self-Refresh,
15.6µs
13 SDRAM width, Primary
x8
08
00
01
08
08
01
14 Error Checking SDRAM data width
n/a / x8
15 Minimum clock delay for back-to-back ran-
dom column address
tccd = 1 CLK
16 Burst Length supported
17 Number of SDRAM banks
18 Supported CAS Latencies
1, 2, 4, 8 & full page 8F
02
8F
02
07
2
CAS latency = 1, 2 07
& 3
19 CS Latencies
CS latency = 0
01
01
00
01
01
00
20 WE Latencies
Write latency = 0
21 SDRAM DIMM module attributes
non buffered/non
reg.
22 SDRAM Device Attributes :General
23 SDRAM Cycle Time at CL = 2
Vcc tol +/- 10%
15.0 ns
9.0 ns
06
F0
90
78
6C
1E
14
06
F0
90
78
6C
1E
14
24 SDRAM Access Time from Clock at CL = 2
25 SDRAM Cylce Time at CL = 1
30 ns
26 SDRAM Access Time from Clock at CL = 1
27 Minimum Row Precharge Time
27 ns
30 ns
28 Minimum Row Active to Row Active delay
tRRD
20 ns
Semiconductor Group
10
