HYS64(72)V2200/4220GCU-10
SDRAM-Modules
Notes:
1. The specified values are valid when addresses are changed no more than once during tck(min.)
and when No Operation commands are registered on every rising clock edge during tRC(min).
Values are shown per module bank.
2. The specified values are valid when data inputs (DQs’) are stable during tRC(min.).
3. All AC characteristics are shown for device level.
An initial pause of 100µs is required after power-up, then a Precharge All Banks command must
be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can
begin.
4. AC timing tests have V = 0.4 V and V = 2.4 V with the timing referenced to the 1.4 V crossover
il
ih
point. The transition time is measured between V and V . All AC measurements assume t =1ns
ih
il
T
with the AC output load circuit show. Specified tac and toh parameters are measured with a 50
pF only, without any resistive termination and with a input signal of 1V / ns edge rate between
0.8V and 2.0 V.
tCH
+ 1.4 V
2.4 V
CLOCK
50 Ohm
0.4 V
tCL
t
T
Z=50 Ohm
tSETUP tHOLD
I/O
50 pF
1.4V
INPUT
tAC
tAC
I/O
tLZ
tOH
50 pF
Measurement conditions for
tac and toh
1.4V
OUTPUT
tHZ
fig.1
5. If clock rising time is longer than 1ns, a time (t /2 -0.5) ns has to be added to this parameter.
T
6. Rated at 1.5 V
7. If t is longen than 1 ns, a time (t -1) ns has to be added to this parameter.
T
T
8. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh
commands must be given to “wake-up“the device.
9. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after
CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied
once the Self Refresh Exit command is registered.
10.Referenced to the time which the output achieves the open circuit condition, not to output voltage
levels.
11.t
is equivalent to t
+ t
.
DAL
DPL
RP
Semiconductor Group
10
