CYPD5225-96BZXI,PDF,CYPD5225-96BZXI PDF资料,Datasheet,下载CYPD5225-96BZXI技术资料

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PRELIMINARY

EZ-PD™ CCG5

USB Type-C Port Controller

General Description

EZ-PD™ CCG5 is a dual USB Type-C controller that complies with the latest USB Type-C and PD standards. EZ-PD CCG5 provides

a complete dual USB Type-C and USB-Power Delivery port control solution for PCs, notebook, and dock. It can also be used in dual

role and downstream facing port applications. EZ-PD CCG5 uses Cypress’s proprietary M0S8 technology with a 32-bit, 48-MHz ARM^®

Cortex^®-M0 processor with 128 KB flash and integrates two complete Type-C Transceivers including the Type-C termination resistors

R_Pand R_D. CCG5 also integrates high voltage regulator. CCG5 is available in 40-QFN (1 port) and 96-BGA (2 ports).

Integrated Digital Blocks

■ Up to two integrated timers and counters to meet response

times required by the USB-PD protocol

Applications

■ PCs, Notebook, and Dock

■ Four run-time serial communication blocks (SCBs) with 

Features

reconfigurable I²C, SPI, or UART functionality

Type-C and USB-PD Support

■ Integrated USB Power Delivery 3.0 support

Clocks and Oscillators

■ Integrated oscillator eliminating the need for external clock

■ Two integrated USB-PD Type-C ports

■ Integrated UFP^[1](R_D) and current sources for DFP^[2](R_P) on

both Type-C ports

Low-Power Operation

■ 2.7-V to 21.5-V operation

■ Independent supply voltage pin for GPIO that allows 1.71-V to

5.5-V signaling on the I/Os

■ Integrated dead battery termination for DRP (Power

Source/Sink) applications

■ Integrated VCONN FETs to power EMCA cables

■ Integrated fast role swap and extended data messaging

■ Integrated High Voltage LDO, operational up to 21.5V

■ Integrated 2x USB Analog Mux

System-Level ESD on CC, D+/-, and SBU Pins

■ ±8-kVContactDischargeand±15-kVAirGapDischargebased

on IEC61000-4-2 level 4C

Hot Swappable I/Os

■ Port 1 I²C pins and CC1, CC2 pins are hot-swappable

■ Integrated 2x SBU Analog Mux

■ Integrated 2x USB Charger detect blocks (BC v1.2, Apple

Charging)

Packages

■ 6.0 mm  6.0 mm, 0.6 mm, 40-pin QFN, 

6.0 mm  6.0 mm, 1.0 mm, 96-ball BGA

■ Integrated OVP and OCP protection on the VBUS

■ Integrated OCP protection on the VCONN

■ Integrated high voltage protection on CC and SBU pins to

protectagainstaccidentalshortstotheVBUSpinontheType-C

connector

■ Supports industrial temperature range (–40 °C to +85 °C)

■ Integrated Current sense amplifier that supports high-side

current sensing

■ Integrated gate drivers for external VBUS PFET control on

Type-C Ports

■ Supports high-voltage tolerant PFET-controlled GPIOs

32-bit MCU Subsystem

■ 48-MHz ARM Cortex-M0 CPU

■ 128-KB Flash

■ 12-KB SRAM

Notes

1. UFP refers to Power Sink.

2. DFP refers to Power Source.

Errata: For information on silicon errata, see “Errata” on page 36. Details include trigger conditions, devices affected, and proposed workaround.

Cypress Semiconductor Corporation

Document Number: 002-17682 Rev. *B

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised June 3, 2017

PRELIMINARY

EZ-PD™ CCG5

Logic Block Diagram

CCG5: Single--Chip Type- C Controller

MCU Subsystem

I/O Subsystem

CC

Integrated Digital Blocks

2x TCPWM

ARM

CORTEX -M0

48 MHz

SCB

(I²C, SPI, UART)

VCONN

SCB

28 GPIO

Pins

(I²C, SPI, UART)

Flash

(128KB)

SCB

(I²C, SPI, UART)

SCB

(I²C, SPI, UART)

SRAM

(12KB)

USB PD Subsystem x2

Baseband MAC

VBUS OVP

Protection

System

Resources

HV Protection

On CC & SBU

Baseband PHY

Under Voltage

Protection

Hi-Voltage LDO

( 21.5V)

2x SBU Analog

Mux Switch

1x8- bit SAR ADC

2x V_CONNFETs

2x Gate Drivers

2x2 USB Analog

Mux Switch

VBUS/VCONN OCP

Protection

2x USB Charge

Detect

Document Number: 002-17682 Rev. *B

Page 2 of 38

PRELIMINARY

EZ-PD™ CCG5

Contents

Functional Overview ........................................................4

USB-PD Subsystem (SS) ............................................4

CPU and Memory Subsystem .....................................6

Power System Overview ..................................................7

Peripherals ..................................................................8

GPIO ...........................................................................8

Pinouts ..............................................................................9

Application Diagrams .....................................................16

Electrical Specifications ................................................18

Absolute Maximum Ratings .......................................18

Device-Level Specifications ......................................18

Digital Peripherals .....................................................21

System Resources ....................................................22

Ordering Information ......................................................30

Ordering Code Definitions .........................................30

Package Diagrams ..........................................................31

Acronyms ........................................................................33

Document Conventions .................................................34

Units of Measure .......................................................34

References and Links To Applications Collaterals ....35

Errata ...............................................................................36

Document History Page .................................................37

Sales, Solutions, and Legal Information ......................38

Worldwide Sales and Design Support .......................38

Products ....................................................................38

PSoC® Solutions ......................................................38

Cypress Developer Community .................................38

Technical Support .....................................................38

Document Number: 002-17682 Rev. *B

Page 3 of 38

PRELIMINARY

EZ-PD™ CCG5

Functional Overview

USB-PD Subsystem (SS)

USB-PD Physical Layer

To support the latest USB-PD 3.0 specification, CCG5 has imple-

mented the Fast Role Swap (FRS) feature. The FRS feature

enables externally powered docks and hubs to rapidly switch to

bus power when their external power supply is removed. CCG5

also supports DeepSleep in notebook systems where CCG5 is

expecting FRS detection.

The CCG5 has two USB-PD subsytems consisting of the

USB-PD physical layer (PHY) block and supporting circuits. The

USB-PD PHY consists of a transmitter and receiver that commu-

nicate BMC and 4b/5b encoded data over the CC channel per

the PD 3.0 standard. All communication is half-duplex. The PHY

practices collision avoidance to minimize communication errors

on the channel.

For more details, refer to Sec 6.3.17 in the USB-PD 3.0

specification.

CCG5 is designed to be fully interoperable with revision 3.0 of

the USB Power Delivery specification as well as revision 2.0 of

the USB Power Delivery specification.

In addition, the CCG5 USB-PD block includes all termination

resistors (R_Pand R_D) and their switches as required by the USB

Type-C spec. R_Pand R_Dresistors are required to implement

connection detection, plug orientation detection, and for estab-

lishing the USB source/sink roles.

CCG5 supports Extended Messages containing data of up to 260

bytes. The Extended Messages will be larger than expected by

the USB-PD 2.0 hardware. To accommodate Revision 2.0 based

systems, a Chunking mechanism is implemented such that

Messages are limited to Revision 2.0 sizes unless it is

discovered that both systems support the longer Message

lengths.

The integrated R_Presistor enables CCG5 to be configured as a

DFP. The R_Presistor is implemented as a current source and can

be programmed to support the complete range of current

capacity on the VBUS defined in the USB Type-C Spec.

The R_Dresistor is used to identify CCG5 as a UFP in a DRP

application. The R_Dresistor on CC pins is required even when

the part is not powered for dead battery termination detection

and charging.

Figure 1. USB-PD Subsystem

Document Number: 002-17682 Rev. *B

Page 4 of 38

PRELIMINARY

EZ-PD™ CCG5

VCONN FET

internal bandgap voltage, and an internal voltage proportional to

the absolute temperature. All GPIOs on the chip has access to

the ADCs through the chip-wide analog mux bus. The CC1 and

CC2 pins of both Type-C ports are not available to connect to the

mux bus.

CCG5 has two power supply inputs, V5V_P1 and V5V_P2 pins,

for providing power to EMCA cables through integrated VCONN

FETs. There are two VCONN FETs per PD port to power either

CC1 or CC2 pins. These FETs can provide 1.5-W power over

VCONN on the CC1 and CC2 pins for the EMCA cables. CCG5

also supports integrated OCP on VCONN.

SBU Mux

CCG5 has an integrated 2x SBU Switch and a 2x High-speed

Switch. The SBU switch mux contains 2x1 MUX and a single 2x2

cross bar SBU switch per the Type-C port. The 2x1 MUX allows

to select between the Display Port or Thunderbolt alternate

mode and the single-ended 2x2 switch allows to route signals to

the appropriate SBU1/2 based on CC (Type-C plug) orientation.

ADC

The USB-PD subsystem contains one 8-bit successive approxi-

mation register (SAR) ADC for analog to digital conversions. The

ADCs include an 8-bit DAC and a comparator. The DAC output

forms the positive input of the comparator. The negative input of

the comparator is from a 4-input multiplexer. The four inputs of

the multiplexer are a pair of global analog multiplex busses, an

Figure 2. CCG5 SBU Crossbar Switch Block Diagram

USB HS Mux

The HS mux can connect DP_TOP or DP_Bottom to the UART

Tx pin. Similarly the DN_TOP or DN_Bottom can be routed to the

UART_Rx pin. The HS mux also contains charger detection/

emulation for USB BC1.2 and Apple. The charger detection

block is connected to the D+/D- from the system as shown in

Figure 3.

The maximum operating frequency of UART is 1 Mbps. The HS

mux contains a 2x2 cross bar switch to route the system D± lines

to the Type-C Top or Bottom lines as per the CC (Type-C plug)

orientation and connect the UART (Debug) pairs to unused D±

Top or Bottom.

Figure 3. CCG5 DP/DM Switch Block Diagram

Overvoltage and Undervoltage Protection on VBUS

21.5 V) to derive operating supply voltage. The VSYS always

takes priority over VBUS_P1/VBUS_P2. In the absence of

VSYS, the regulator powers CCG5 either from VBUS_P1 or

VBUS_P2.

CCG5 implements an undervoltage/overvoltage (UVOV)

detection circuit for the VBUS supply. The threshold for OV and

UV detection can be set independently. Both UV and OV detector

have programmable thresholds and is controlled by the

firmware.

PFET Gate Driver for VBUS

CCG5 supports the consumer-side and provider-side external

power FET Drivers for PFET. The VBUS_P_CTRL and

VBUS_C_CTRL gate drivers can drive only low or high-Z, thus

requiring an external pull-up. These pins are VBUS

voltage-tolerant.

Overcurrent Protection on VBUS

CCG5 integrates a high-side current sense amplifier to detect

overcurrent on the VBUS. Overcurrent protection is enabled by

sensing the current through the 10-m sense resistor using the

“CSP_Px” and “CSN_Px” pins.

Charger Detect

VBUS Discharge

CCG5 integrates battery charger emulation and detection for

USB BC.1.2, Apple charge.

CCG5 also has integrated VBUS discharge FETs and resistors

for each port. It is used to discharge VBUS to meet the USB-PD

Specification timing on a detach condition and negative voltage

transition.

IEC Compliant VBUS, CC, and SBU Lines

The chip supports IEC-compliant ESD protection on VBUS, CC,

D±, and SBU lines.

VBUS Regulator

CCG5 can operate from three power supplies – VSYS, VBUS1,

and VBUS2. CCG5 integrates the regulator (that supports up to

Document Number: 002-17682 Rev. *B

Page 5 of 38

PRELIMINARY

EZ-PD™ CCG5

High-Voltage Tolerant SBU and CC Lines

Flash

The chip supports high-voltage tolerant SBU and CC lines. In the

case of SBU/CC short to VBUS through connectors, these lines

will be protected internally.

The EZ-PD CCG5 device has a flash module with a flash accel-

erator, tightly coupled to the CPU to improve average access

times from the flash block. The flash block is designed to deliver

two wait-states (WS) access time at 48 MHz and with 0-WS

access time at 16 MHz. The flash accelerator delivers 85% of

single-cycle SRAM access performance on average. Part of the

flash module can be used to emulate EEPROM operation if

required.

CPU and Memory Subsystem

CPU

The Cortex-M0 CPU in EZ-PD CCG5 is part of the 32-bit MCU

subsystem, which is optimized for low-power operation with

extensive clock gating.

SROM

A supervisory ROM that contains boot and configuration routines

is provided.

The CPU also includes a serial wire debug (SWD) interface,

which is a 2-wire form of JTAG. The debug configuration used for

EZ-PD CCG5 has four break-point (address) comparators and

two watchpoint (data) comparators.

SRAM

CCG5 supports 12-KB SRAM.

Document Number: 002-17682 Rev. *B

Page 6 of 38

PRELIMINARY

EZ-PD™ CCG5

Power System Overview

Table 1. CCG5 Power Modes

Mode

Figure 4 provides an overview of the EZ-PD CCG5 power

system. CCG5 can operate from three possible external supply

sources: VBUS_P1/VBUS_P2 (4 - 21.5 V) or VSYS (2.7 - 5.5 V).

The VBUS_P1 and VBUS_P2 supply is regulated inside the chip

with a LDO. The switched supply, VDDD, is either used directly

inside some analog blocks or further regulated down to VCCD,

which powers majority of the core using the regulators. CCG5

has three different power modes: Active, Sleep, and Deep Sleep.

Transitions between these power modes are managed by the

power system. A separate power domain, VDDIO, is provided for

the GPIOs. The VDDD and VCCD pins, both outputs of

regulators, are brought out for connecting a 1-µF and 0.1-µF

capacitor respectively for the regulator stability only. These pins

are not supported as power supplies. In CCG5, the V_DDDcan be

shorted to the V_DDIOat system level.

Description

Power is Valid and XRES is not asserted. An

internal reset source is asserted or Sleep

Controller is sequencing the system out of reset.

RESET

ACTIVE

SLEEP

Power is Valid and CPU is executing

instructions.

Power is Valid and CPU is not executing

instructions. All logic that is not operating is clock

gated to save power.

Main regulator and most blocks are shut off.

DEEP SLEEP DeepSleep regulator powers logic, but only

low-frequency clock if available.

Figure 4. EZ-PD CCG5 Power System

LDO

VBUS_P1

VBUS_P2

V_DDD

VSYS

CC1_P2

CC2_P2

CC2_P1

V5V_P2

CC1_P1

V5V_P1

V_DDIO

Core Regulator

(SRSS-Lite)

V_CCD

2 x CC

Tx/Rx

GPIOs

Core

V_SS

Document Number: 002-17682 Rev. *B

Page 7 of 38

PRELIMINARY

EZ-PD™ CCG5

Peripherals

Serial Communication Blocks (SCB)

GPIO

EZ-PD CCG5 has 28 GPIOs that includes the I²C and SWD pins,

which can also be used as GPIOs. The I²C pins from only SCB

1 are overvoltage-tolerant. The number of available GPIOs vary

with the part numbers. The GPIO block implements the following:

EZ-PD CCG5 has four SCBs, which can be configured to

implement an I²C, SPI, or UART interface. The hardware I²C

blocks implement full multi-master and slave interfaces capable

of multimaster arbitration. In the SPI mode, the SCB blocks can

be configured to act as a master or a slave.

■ Seven drive strength modes:

❐ Input only

In the I²C mode, the SCB blocks are capable of operating at

speeds up to 1 Mbps (Fast Mode Plus) and have flexible

buffering options to reduce interrupt overhead and latency for the

CPU. These blocks also support I²C that creates a mailbox

address range in the memory of EZ-PD CCG5 and effectively

reduce I²C communication to reading from and writing to an

array in memory. In addition, the blocks support 8-deep FIFOs

for receive and transmit which, by increasing the time given for

the CPU to read data, greatly reduce the need for clock

stretching caused by the CPU not having read data on time.

The I²C peripherals are compatible with the I²C Standard-mode,

Fast-mode, and Fast-mode Plus devices as defined in the NXP

I²C-bus specification and user manual (UM10204). The I²C bus

I/Os are implemented with GPIO in open-drain modes.

❐ Weak pull-up with strong pull-down

❐ Strong pull-up with weak pull-down

❐ Open drain with strong pull-down

❐ Open drain with strong pull-up

❐ Strong pull-up with strong pull-down

❐ Weak pull-up with weak pull-down

■ Input threshold select (CMOS or LVTTL)

■ Individual control of input and output buffer enabling/disabling

in addition to the drive strength modes

■ Hold mode for latching previous state (used for retaining I/O

state in Deep Sleep mode)

■ Selectable slew rates for dV/dt related noise control to improve

EMI

The I²C port on SCB 2, SCB 3 and SCB 4 blocks of EZ-PD CCG5

are not completely compliant with the I²C spec in the following:

During power-on and reset, the I/O pins are forced to the disable

state so as not to crowbar any inputs and/or cause excess

turn-on current. A multiplexing network known as a high-speed

I/O matrix is used to multiplex between various signals that may

connect to an I/O pin.

■ The GPIO cells for SCB 2 to SCB 4 I²C port are not

overvoltage-tolerant and, therefore, cannot be hot-swapped or

powered up independently of the rest of the I²C system.

■ Fast-mode Plus has an I_OLspecification of 20 mA at a V_OLof

0.4 V. The GPIO cells can sink a maximum of 8-mA I_OLwith a

V_OLmaximum of 0.6 V.

■ Fast-mode and Fast-mode Plus specify minimum Fall times,

which are not met with the GPIO cell; Slow strong mode can

help meet this spec depending on the bus load.

Timer/Counter/PWM Block (TCPWM)

EZ-PD CCG5 has up to two TCPWM blocks. Each implements

a 16-bit timer, counter, pulse-width modulator (PWM), and

quadrature decoder functionality. The block can be used to

measure the period and pulse width of an input signal (timer),

find the number of times a particular event occurs (counter),

generate PWM signals, or decode quadrature signals.

Document Number: 002-17682 Rev. *B

Page 8 of 38

PRELIMINARY

EZ-PD™ CCG5

Pinouts

Table 2. Pinout for CYPD5125-40LQXIT

Group Name

Pin Name

CC1

Port

9

Description

Analog

P4.0

USB PD connector detect/Configuration Channel 1

USB PD connector detect/Configuration Channel 2

USB 2.0 DP from the Host System

USB 2.0 DM from the Host System

UART TX from Host System/GPIO

UART RX from Host System/GPIO

USB 2.0 DP from Bottom of Type-C Connector

USB 2.0 DM from Bottom of Type-C Connector

USB 2.0 DM from Top of Type-C Connector

USB 2.0 DP from Top of Type-C Connector

Sideband Use signal

USB Type-C

CC2

7

DPLUS_SYS

DMINUS_SYS

UART_TX/GPIO

UART_RX/GPIO

DPLUS_BOT

DMINUS_BOT

DMINUS_TOP

DPLUS_TOP

SBU2

23

24

29

30

26

25

27

28

34

35

36

37

38

39

P4.1

Analog

Mux

SBU1

Sideband Use signal

AUX_P

Auxiliary signal for DisplayPort

AUX_N

Auxiliary signal for DisplayPort

LSTX

Thunderbolt Link Management UART Rx

Thunderbolt Link Management UART Tx

LSRX

Full rail control I/O for enabling/disabling Provider load PFET of

USB Type-C port 1

0: Path ON

VBUS_P_CTRL

VBUS_C_CTRL

Analog

11

12

High Z: Path OFF

VBUS Control

VBUS OCP

Full rail control I/O for enabling/disabling Consumer load PFET of

USB Type-C port1

0: Path on

High Z: Path off

CSP

CSN

Analog

P1.6

1

40

6

Current Sense positive Input for VBUS side external Rsense

Current sense negative for other side of external Rsense

SWD I/O/GPIO

SWD_IO/AR_RST/GPIO

SWD Clock/ I²C config line.

I²C config line is used to select the I²C address of HPI interface.

The state of line decides the 7 bit I²C address for HPI.

I²C Config Line Floating: 0x08

SWD_CLK/I2C_CFG_EC/ GPIO

P1.0

2

Pulled up with 1 K: 0x42

Pulled down with 1 K: 0x40

I2C_SDA_SCB2_TBT/GPIO

I2C_SCL_SCB2_TBT/GPIO

I2C_INT_TBT/GPIO

P1.1

P1.2

P1.3

P2.4

3

4

SCB2 I²C Data/GPIO

SCB2 I²C Clock/GPIO

5

TBT interrupt for port 1/GPIO

GPIOs and Serial

Interfaces

OVP_TRIP/I2C_SDA_SCB4/GPIO

14

VBUS overvoltage output indicator for port 1/SCB4 I²C Data

VBUS undervoltage or OCP Output Indicator for Port1 / SCB4 I²C

Clock / GPIO

UV_OCP_TRIP/I2C_SDA_SCB4/GPIO

P2.3

13

I2C_SDA_SCB1_EC/GPIO

I2C_SCL_SCB1_EC/GPIO

I2C_INT_EC/GPIO

P6.0

P6.1

16

17

15

18

20

21

10

SCB1 I²C Data / GPIO

SCB1 I²C Clock / GPIO

P2.5

Embedded Controller interrupt/GPIO

Hot Plug Detect I/O for port 1/GPIO

SCB3 I²C Data or GPIO or voltage selection control for VBUS

SCB3 I²C Clock or GPIO or voltage selection control for VBUS

Reset input (Active LOW)

HPD/GPIO

P3.0

I2C_SDA_SCB3 / GPIO / VSEL_2

I2C_SDA_SCB3 / GPIO /VSEL_1

XRES

P3.6

P3.7

Reset

Analog

Document Number: 002-17682 Rev. *B

Page 9 of 38

PRELIMINARY

EZ-PD™ CCG5

Table 2. Pinout for CYPD5125-40LQXIT (continued)

Group Name

Pin Name

VBUS

Port

22

19

31

32

Description

VBUS Input for Port 1(4V to 21.5V)

Power

VSYS

2.7-V to 5.5-V supply for the system

VDDD supply output (2.7V to 5.5V)

1.71V to 5.5V supply for I/Os

VDDD

Power

VDDIO

1.8V regulator output for filter capacitor. This pin cannot drive

external load.

VCCD

Power

33

8

V5V

VSS

4.85V to 5.5V supply for VCONN FET of Type-C port 1

Ground

Ground EPAD Ground

Figure 5. 40-Pin QFN Pin Map (Top View) for CYPD5125-40LQXIT

1

2

3

CSP

SWD_CLK / I2C_CLK_CFG

I2C_SDA_SCB2_TBT

I2C_SCL_SCB2_TBT

I2C_INT_TBT

30

29

28

27

UART_RX

UART_TX

DPLUS_TOP

DMINUS_TOP

4

5

6

40-QFN

(Top View)

DPLUS_BOT

DMINUS_BOT

DMINUS_SYS

DPLUS_SYS

26

25

24

23

SWD_IO/ AR_RST

7

8

9

CC2

V5V

CC1

XRES

VBUS

22

21

10

I2C_SDA_SCB3 / VSEL_1

Document Number: 002-17682 Rev. *B

Page 10 of 38

PRELIMINARY

EZ-PD™ CCG5

Table 3. Pinout for CYPD5225-96BZXI

Group Name

Pin Name

Port

Ball Location

Description

CC1_P1

CC2_P1

Analog

P4.1

K2

H2

USB PD connector detect/Configuration Channel 1

USB PD connector detect/Configuration Channel 2

USB PD connector detect/Configuration Channel 1

USB PD connector detect/Configuration Channel 2

Auxiliary signal for DisplayPort

USB Type-C Port 1

CC1_P2

K9

USB Type-C Port 2

CC2_P2

K10

B11

C11

A11

A10

A3

AUX_P_P1

AUX_N_P1

Auxiliary signal for DisplayPort

LSRX_P1

Thunderbolt Link Management UART Rx

Thunderbolt Link Management UART Tx

Sideband Use signal

LSTX_P1

SBU1_P1

SBU2_P1

A4

Sideband Use signal

DMINUS_SYS_P1

DPLUS_SYS_P1

UART_RX_P1/GPIO

UART_TX_P1/GPIO

DMINUS_BOT_P1

DPLUS_BOT_P1

DMINUS_TOP_P1

DPLUS_TOP_P1

AUX_P_P2

A7

USB 2.0 DM from the Host System

USB 2.0 DP from the Host System

UART Rx from Host System/GPIO

UART Tx from Host system/GPIO

MUX Type-C Port 1

A6

A9

P4.0

A8

Analog

P0.2

C1

USB 2.0 DM from Bottom of Type-C Connector

USB 2.0 DP from Bottom of Type-C Connector

USB 2.0 DM from Top of Type-C Connector

USB 2.0 DP from Top of Type-C Connector

Auxiliary signal for DisplayPort

B1

A2

A1

D11

E11

L11

K11

E1

AUX_N_P2

Auxiliary signal for DisplayPort

LSRX_P2

Thunderbolt Link Management UART Rx

Thunderbolt Link Management UART Tx

Sideband Use signal

LSTX_P2

SBU1_P2

SBU2_P2

F1

Sideband Use signal

DMINUS_SYS_P2

DPLUS_SYS_P2

UART_RX_P2/GPIO

UART_TX_P2/GPIO

DMINUS_BOT_P2

DPLUS_BOT_P2

DMINUS_TOP_P2

DPLUS_TOP_P2

G11

F11

J11

H11

L1

USB 2.0 DM from the Host System

USB 2.0 DP from the Host System

UART Rx from Host System/GPIO

UART Tx from Host system/GPIO

MUX Type-C Port 2

P0.1

Analog

USB 2.0 DM from Bottom of Type-C Connector

USB 2.0 DP from Bottom of Type-C Connector

USB 2.0 DM from Top of Type-C Connector

USB 2.0 DP from Top of Type-C Connector

K1

H1

G1

Full rail control I/O for enabling/disabling Provider load PFET

of USB Type-C port 1

0: Path ON

VBUS_P_CTRL_P1

VBUS_C_CTRL_P1

Analog

K3

K4

High Z: Path OFF

VBUSControlType-C

Port1

Full rail control I/O for enabling/disabling Consumer load

PFET of USB Type-C port1

0: Path on

High Z: Path off

Document Number: 002-17682 Rev. *B

Page 11 of 38

PRELIMINARY

EZ-PD™ CCG5

Table 3. Pinout for CYPD5225-96BZXI (continued)

Group Name

Pin Name

Port

Ball Location

Description

Full rail control I/O for enabling/disabling Provider load PFET

of USB Type-C port 2.

0: Path ON

High Z: Path OFF

VBUS_P_CTRL_P2

Analog

B4

VBUSControlType-C

Port2

Full rail control I/O for enabling/disabling Consumer load

PFET of USB Type-C Port 2.

0: Path on

VBUS_C_CTRL_P2

Analog

B5

High Z: Path off

CSP_P1

CSN_P1

Analog

P3.1

J1

B3

L2

Current Sense Positive Input for P1

Current Sense Negative Input for P1

Current Sense Positive Input for P2

VBUS OCP

CSP_P2

CSN_P2

K8

L7

Current Sense Negative Input for P2

GPIO

OVP_TRIP_P1 / GPIO

OVP_TRIP_P2 / GPIO

VSEL_1_P2 / GPIO

UV_OCP_TRIP_P1/GPIO

HPD_P1/GPIO

HPD_P2/GPIO

P2.4

K5

L8

VBUS overvoltage output indicator for port 1 / GPIO

VBUS overvoltage output indicator for port 2 / GPIO

Voltage selection control for VBUS on port 2 / GPIO

VBUS undervoltage of OCP output indicator for port 1/GPIO

Hot Plug Detect I/O for port 1 /GPIO

P2.2

P0.0

L4

P1.4

B6

K7

E10

P3.0

P3.4

Hot Plug Detect I/O for port 2 /GPIO

VCONN_OCP_TRIP_P2/

GPIO

P3.3

B9

VCONN OCP output indicator for port 2 / GPIO

VCONN_OCP_TRIP_P1/GPIO

UV_OCP_TRIP_P2/GPIO

VSEL_2_P2 / GPIO

P3.5

P1.5

P2.0

B8

B7

VCONN OCP output indicator for port 1/ GPIO

VBUS undervoltage or OCP output indicator for port 2/GPIO

Voltage selection control for VBUS on port 2 / GPIO

H10

I2C_SCL_SCB1_EC/

GPIO

P6.1

P6.0

L6

SCB1 I²C Clock

SCB1 I²C Data

I2C_SDA_SCB1_EC/

GPIO

K6

GPIOs and Serial

Interfaces

I2C_INT_EC/GPIO

I2C_SCL_SCB2_TBT/GPIO

I2C_SDA_SCB2_TBT/GPIO

I2C_INT_TBT_P1/GPIO

I2C_INT_TBT_P2/GPIO

P2.5

P1.2

P1.1

P1.3

P2.1

L5

E2

D2

F2

G2

I²C interrupt line

SCB2 I²C Clock/GPIO

SCB2 I²C Data /GPIO

I²C interrupt line/GPIO

I²C interrupt line

I2C_SCL_SCB3 / VSEL_1_P1

/GPIO

SCB3 I²C Clock/ Voltage selection control for VBUS on port

1/ GPIO

SCB3 I²C Data / Voltage selection control for VBUS on port 1

/GPIO

P3.7

P3.6

L10

J10

I2C_SDA_SCB3 / VSEL_2_P1 /

GPIO

I2C_SCL_SCB4/GPIO

I2C_SDA_SCB4/GPIO

SWD_IO/AR_RST# /GPIO

P2.3

P3.2

P1.6

F10

G10

B2

SCB4 I²C Clock /GPIO

SCB4 I²C Data /GPIO

SWD I/O / AR Reset / GPIO

SWD Clock / I²C config line / GPIO.

I²C config line is used to select the I²C address of HPI

interface. The state of line decides the 7 bit I²C address for

HPI.

SWD_CLK/I2C_CFG_EC/GPIO

XRES

P1.0

C2

H6

I²C Config Line Floating: 0x08

Pulled up with 1 K: 0x42

Pulled down with 1 K: 0x40

Reset

Analog

Reset input (Active LOW)

Document Number: 002-17682 Rev. *B

Page 12 of 38

PRELIMINARY

EZ-PD™ CCG5

Table 3. Pinout for CYPD5225-96BZXI (continued)

Group Name

Pin Name

Port

Ball Location

Description

VBUS_P1

VBUS_P2

VSYS

Power

D1

L3

VBUS Input for Port 1 (4 V to 21.5 V)

VBUS Input for Port 2 (4 V to 21.5 V)

2.7 V to 5.5 V supply for the system

VDDD supply output (2.7 V to 5.5 V)

A5

VDDD

D10

Power

1.8-V regulator output for filter capacitor. This pin cannot drive

external load.

VCCD

Power

B10

VDDIO

V5V_P1

V5V_P2

GND

NC

Power

Ground

DNU

C10

J2

1.71 V to 5.5 V supply for I/Os

4.85 V to 5.5 V supply for VCONN FET of Type-C port 1

L9

4.85 V to 5.5 V supply for VCONN FET of Type-C port 2

D5

D6

D7

D8

E4

E5

E6

E7

E8

F4

F5

F6

F7

F8

G4

G5

G6

G7

H7

G8

H4

H5

H8

Ground

Not Connect

NC

DNU

No Connect

NC

DNU

NC

DNU

Document Number: 002-17682 Rev. *B

Page 13 of 38

PRELIMINARY

EZ-PD™ CCG5

Figure 6. 96-Pin BGA Pin Map for CYPD5225-96BXZ

1

2

3

4

5

6

8

9

10

11

7

DPLUS_TO DMINUS_TO

DPLUS_SY DMINUS_S UART_Tx_P UART_Rx_

A

B

SBU1_P1

SBU2_P1

VSYS

LSTx_P1

LSRx_P1

P_P1

S_P1

YS_P1

1 / P4.0

P1 / P4.1

SWD_DATA/

TBT_RST# /

P1.6

P1.4 /

P1.5 /

P3.5 /

P3.3 /

DPLUS_BO

T_P1

VBUS_P_C VBUS_C_C

TRL_P2

CSN_P1

UV_OCP_T UV_OC_TRI VCON_OCP VCON_OCP

VCCD

VDDIO

VDDD

AUX_P_P1

AUX_N_P1

TRL_P2

RIP_P1

P_P2

_TRIP_P1

_TRIP_P2

SWD_CLK /

DMINUS_B I2C_CFG_EC

C

OT_P1

/

P1.0

I2C_SDA_SC

B 2 _ T B T /

P1.1

D

E

VBUS_P1

GND

AUX_P_P2

AUX_N_P2

I2C_SCL_SC

B 2 _ T B T /

P1.2

HPD_P2 /

P3.4

SBU1_P2

SBU2_P2

GND

I2C_INT_TBT

_P1/ P1.3

DPLUS_SYS_

P2

F

G

H

GND

DNU

GND

DNU

GND

DNU

SCL_4 / P2.3

DPLUS_TO I2C_INT_TBT

SDA_4 /

P3.2

DMINUS_SYS

_P2

P_P2

_P2/ P2.1

DMINUS_T

OP_P2

VSEL_2_P2/ UART_Tx_P2/

CC2_P1

XRES

P2.0

P0.1

SDA_3/

VSEL_2_P1/

P3.6

UART_Rx_P2

/ P0.2

J

K

L

CSP_P1

V5V_P1

CC1_P1

CSP_P2

I2C_SDA_S

CB1_EC /

P6.0

DPLUS_BO

T_P2

VBUS_P_C VBUS_C_C OVP_TRIP_

HPD_P1 /

P3.0

CSN_P2

CC1_P2

V5V_P2

CC2_P2

LSTx_P2

LSRx_P2

TRL_P1

P1 /P2.4

I2C_SCL_S

CB1_EC /

P6.1

SCL_3 /

VSEL_1_P1/

P3.7

DMINUS_B

OT_P2

VSEL_1_P2 I2C_INT_E

/P0.0 C / P2.5

OVP_TRIP_

P2/P2.2

VBUS_P2

P3.1

Type-C Port

1

Type-C Port

2

Power Pins

GND

GPIOs

Document Number: 002-17682 Rev. *B

Page 14 of 38

PRELIMINARY

EZ-PD™ CCG5

Table 4 through Table 7 provide the various configuration options for the serial interfaces.

Table 4. Serial Communication Block (SCB1) Configuration

QFN Pin BGA Pin

UART

SPI

I2C

GPIO Functionality

16

17

K6

L6

–

I2C_SDA_SCB1

I2C_SCL_SCB1

GPIO

VCONN OCP output indicator for port 1/

GPIO

B8

UART_CTS_SCB1

–

20

21

J10

L10

UART_TX_SCB1

UART_RX_SCB1

SPI_SEL_SCB1

SPI_MISO_SCB1

–

I2C_SDA_SCB3/ VSEL_2_P1 /GPIO

I2C_SCL_SCB3 / VSEL_1_P1/GPIO

18

29

30

K7

A8

A9

UART_RTS_SCB1

–

HPD_P1/GPIO

–

SPI_MOSI_SCB1

SPI_CLK_SCB1

UART_TX_P1/GPIO

UART_RX_P1/GPIO

Note: UART TX and RX of the SCB1 is also the I2C SDA and SCL of the SCB3. So if the SCB 3 is in use then SCB1 cannot be used

for UART and SPI.

Table 5. Serial Communication Block (SCB2) Configuration

QFN Pin BGA Pin

UART

SPI Master

I2C Slave

GPIO Functionality

SWD_CLK/I2C_CFG_EC/GPIO

I2C_SDA_SCB2_TBT/GPIO

I2C_SCL_SCB2_TBT/GPIO

I2C_INT_TBT_P1/GPIO

2

3

4

5

C2

D2

E2

F2

UART_RX_SCB2

UART_TX_SCB2

UART_CTS_SCB2

UART_RTS_SCB2

SPI_SEL_SCB2

SPI_MOSI_SCB2

SPI_MISO_SCB2

SPI_CLK_SCB2

–

I2C_SDA_SCB2

I2C_SCL_SCB2

–

Table 6. Serial Communication Block (SCB3) Configuration

QFN Pin BGA Pin

UART

–

SPI Master

–

I2C Slave

GPIO Functionality

20

21

J10

L10

G2

H10

L4

I2C_SDA_SCB3 UART_TX_SCB1/VSEL_2_P1 /GPIO

I2C_SCL_SCB3 UART_RX_SCB1 / VSEL_1_P1/GPIO

–

UART_CTS_SCB3

UART_TX_SCB3

UART_RX_SCB3

UART_RTS_SCB3

SPI_MISO_SCB3

SPI_MOSI_SCB3

SPI_SEL_SCB3

SPI_CLK_SCB3

–

I2C_INT_TBT_P2/GPIO

VSEL_2_P2 / GPIO

VSEL_1_P2 / GPIO

OVP_TRIP_P2 / GPIO

L8

Table 7. Serial Communication Block (SCB4) Configuration

QFN Pin BGA Pin

UART

SPI Master

–

I2C Slave

GPIO Functionality

13

14

F10

G10

L7

–

I2C_SCL_SCB4 GPIO

I2C_SDA_SCB4 GPIO

UART_TX_SCB4

UART_CTS_SCB4

UART_RX_SCB4

UART_RTS_SCB4

SPI_MOSI_SCB4

SPI_MISO_SCB4

SPI_SEL_SCB4

SPI_CLK_SCB4

–

GPIO

B9

VCONN_OCP_TRIP_P2/GPIO

HPD_P2/GPIO

E10

Document Number: 002-17682 Rev. *B

Page 15 of 38

PRELIMINARY

EZ-PD™ CCG5

Application Diagrams

Figure 7 illustrates a Dual Port Thunderbolt Notebook DRP application diagram using CYPD5225-96BXZI. The Type-C port can be

used as a power provider or a power consumer. The CCG5 device communicates with the embedded controller (EC) over I2C. It also

updates the Thunderbolt Controller via I2C to route the HighSpeed signals coming from the Type C port to the USB host (during normal

mode) or the Graphics processor unit (during Display port Alternate mode) or the Thunderbolt Host (during Thunderbolt Alternate

mode) based on the alternate mode negotiation.

Figure 7. CCG5 in a Dual Port Notebook Application using CYPD5225-40LQXIT

VBUS

SUPPLY

PORT2

VCONN

SUPPLY

( 2 PORTS)

VBUS

SUPPLY

PORT1

VBUS

CC1_1, CC2_1

CC1_2, CC2_2

CCG5(96-BGA)

HS(4)/SBU(2)

6

HS(4)/SBU(2)

6

USB Type- C

Receptacle

USB Type- C

Receptacle

3

I2C

I2 C

5

+

Ctrl

EC

THUNDERBOLT/USB/

DISPLAY PORT

Datalanes

8

GND

EC- Embedded

Controller

Document Number: 002-17682 Rev. *B

Page 16 of 38

PRELIMINARY

EZ-PD™ CCG5

Figure 8 illustrates a Single Port Thunderbolt Notebook DRP application diagram using CYPD5125-40LQXIT.

Figure 8. CCG5 in a Single Port Notebook Application using CYPD5125-40LQXIT

VBUS

SUPPLY

PORT 1

VCONN

SUPPLY

VBUS

CC1_1, CC2_1

CCG5(40-QFN)

HS(4)/SBU(2)

6

USB Type- C

Receptacle

3

I2C

I2 C

+

4

Ctrl

EC- Embedded

Controller

EC

THUNDERBOLT/USB/

DISPLAY PORT

Datalanes

8

GND

Document Number: 002-17682 Rev. *B

Page 17 of 38

PRELIMINARY

EZ-PD™ CCG5

Electrical Specifications

Absolute Maximum Ratings

Table 8. Absolute Maximum Ratings^[3]

Parameter

Description

Min

–0.5

–

Typ

–

Max

Units

V

Details/Conditions

V

Digital supply relative to V

6

SYS_MAX

SS

Max supply voltage relative to V

–

V

5V_P1

SS

–

6

V

5V_P2

Max VBUS voltage relative to Vss

–

26

V

BUS_P1_MAX

BUS_P2_MAX

DDIO_MAX

GPIO_ABS

Absolute max

–

26

V

Max supply voltage relative to V

GPIO voltage

–

VDDD

V

SS

–0.5

–25

–

V

+ 0.5

V

DDIO

I

Maximum current per GPIO

–

25

mA

GPIO injection current, Max for V

>

Absolute max, current

injected per pin

IH

–0.5

–

0.5

mA

V

GPIO_INJECTION

V

, and Min for V < V

DDD

IL SS

Electrostatic discharge human body

model

ESD_HBM

2200

–

Electrostatic discharge charged

device model

ESD_CDM

LU

500

–200

8000

–

200

–

V

mA

V

–

Pin current for latch-up

Electrostatic discharge

IEC61000-4-2

Contact discharge on CC1,

CC2 pins

ESD_IEC_CON

Electrostatic discharge

IEC61000-4-2

Air discharge for pins CC1,

CC2 pins

ESD_IEC_AIR

VCC_PIN_ABS

15000

–

24

6

V

Max voltage on CC1 and CC2 pins

Absolute max

Applicable to port pins P0.0

and P0.1

VGPIO_OVT_ABS OVT GPIO voltage

–0.5

Device-Level Specifications

All specifications are valid for –40 °C  T_A 105 °C and T_J 120 °C, except where noted. Specifications are valid for 3.0 V to 5.5 V

except where noted.

Table 9. DC Specifications

Spec ID

Parameter

Description

Min Typ Max Units

Details/Conditions

SID.PWR#23

VSYS

Power supply input voltage

3

–

5.5

V

–

VBUS_P1 and VBUS_P2 valid

range

SID.PWR#22

SID.PWR#1

VBUS

V_DDD

4

–

21.5

V

–

Regulated output voltage

2.7

3.0

–

5.5

V

UFP applications

SID.PWR#1_A V_DDD

DFP/DRP applications

V_{5V_P1}and

SID.PWR#26

Power supply Input voltage

4.85

–

5.5

V

–

V_{5V_P2}

V_DDIO

V_CCD

At system-level short the V_DDIOto

V_DDD

SID.PWR#13

SID.PWR#24

GPIO power supply

1.71

–

V_DDD

–

V

Output voltage (For Core Logic)

1.8

Note

3. Usage above the absolute maximum conditions listed in Table 8 may cause permanent damage to the device. Exposure to absolute maximum conditions for extended

periods of time may affect device reliability. The maximum storage temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature

Storage Life. When used below absolute maximum conditions but above normal operating conditions, the device may not operate to specification.

Document Number: 002-17682 Rev. *B

Page 18 of 38

PRELIMINARY

EZ-PD™ CCG5

Table 9. DC Specifications (continued)

Spec ID

Parameter

Description

Min Typ Max Units

Details/Conditions

Externalregulatorvoltagebypass

on V_CCD

SID.PWR#15

C_EFC

80 100 120

nF

µF

Power supply decoupling

capacitor on V_DDD

SID.PWR#16

SID.PWR#27

C_EXC

C_EXV

0.1

–

1

–

X5R ceramic or better

Power supply decoupling

capacitor on V_{5V_P1}and V_{5V_P2}

0.1

Active Mode, VDDD = 2.7 to 5.5 V. Typical values measured at VDDD = 3.3 V.

V5V_P1 and V5V_P2 = 5 V,

T_A= 25 °C, CC I/O IN Transmit or

Receive, no I/O sourcing current,

CPU at 24 MHz, two PD ports active

SID.PWR#4

I_DD12

Supply Current

–

10

–

mA

Sleep Mode, VDDD = 2.7 to 5.5 V. Typical values measured at VDDD = 3.3 V.

VDDD = 3.3 V, T_A= 25 °C, all blocks

except CPU are ON, CC I/O ON, no

I/O sourcingcurrent. Firmware runs

at 24 MHz.

I²C, wakeup WDT on. IMO at 24

MHz.

SID25A

SID25B

I_DD20A

–

2.5

3.0

4

5

mA

VDDD = 3.3 V, T_A= 25 °C, All

I²C, wakeup WDT on. IMO at 24

MHz.

blocks except CPU are on, CC IO

on, no I/O sourcing current for two

PD ports. Firmware runs at 24 MHz.

I_DD20A

Deep Sleep Mode, VDDD = 2.7 to 3.6V (Regulator on)

SID34

I_DD29

–

150

160

–

µA

VDDD = 3.3 V, T_A= 25 °C,

VDDD = 2.7 to 3.6V, I²C, wakeup

and WDT on.

VDDD = 3.3 V, T_A= 25 °C for two

PD ports

SID34A

I_DD29A

Power source = VDDD, Type-C Not

attached, CC enabled for wakeup,

Rp and Rd connected at 70ms

intervals by CPU. Rp, Rd

connection should be enabled for

both PD ports.

VDDD = 3.3V, CC wakeup on,

Type-C not connected.

SID_DS1

SID_DS3

I_{DD_DS1}

–

100

–

µA

VDDD = 3.3V, CC wakeup on,

DP/DM, SBU ON with

ADC/CSA/UVOV On

IDD_DS1 + DP/DM, SBU, CC ON,

ADC/CSA/UVOV ON

I_{DD_DS2}

–

500

130

–

µA

XRES Current

Supply current while XRES

asserted

Power Source = VDDD = 3.3V,

Type-C Not Attached, T_A= 25 °C

SID307

I_{DD_XR}

Table 10. AC Specifications (Guaranteed by Characterization)

Spec ID

Parameter

Description

CPU input frequency

Wakeup from sleep mode

SID.PWR#21 T_DEEPSLEEPWakeup from Deep Sleep mode

Min Typ Max Units

Details/Conditions

SID.CLK#4

F_CPU

24

–

0

48 MHz 3.0V  V_DDD5.5V

SID.PWR#20 T_SLEEP

–

35

–

µs Guaranteed by characterization

24MHz IMO. Guaranteed by

characterization

–

5

–

5

µs

SYS.XRES#5 T_XRESExternal reset pulse width

SYS.FES#1 T_{_PWR_RDY}

µs

Power-up to “Ready to accept I²C/CC

command”

Guaranteed by characterization

ms

25

Document Number: 002-17682 Rev. *B

Page 19 of 38

PRELIMINARY

EZ-PD™ CCG5

Table 11. I/O DC Specifications

Spec ID Parameter

Description

Input voltage HIGH threshold 0.7 × VDDDIO

Input voltage LOW threshold

Min

Typ

Max

Units

V

Details/Conditions

SID.GIO#37 V_{IH_CMOS}

SID.GIO#38 V_{IL_CMOS}

–

CMOS input

–

0.3 × VDDDIO

V

CMOS input

SID.GIO#39 V_{IH_VDDD2.7-}LVTTL input, VDDD < 2.7 V 0.7 × VDDDIO

–

V

–

SID.GIO#40 V_{IL_VDDD2.7-}LVTTL input, VDDD < 2.7 V

SID.GIO#41 V_{IH_VDDD2.7+}LVTTL input, VDDD  2.7 V

SID.GIO#42 V_{IL_VDDD2.7+}LVTTL input, VDDD  2.7 V

–

0.3 × VDDDIO

V

–

2.0

–

V

–

0.8

–

V

–

SID.GIO#33 V_OH

SID.GIO#34 V_OH

SID.GIO#35 V_OL

SID.GIO#36 V_OL

Output voltage HIGH level

Output voltage LOW level

Pull-up resistor value

VDDDIO – 0.6

–

V

I_OH= 4 mA at 3V VDDDIO

I_OL= 1mA at 1.8V VDDDIO

I_OL= 4mA at 1.8V VDDDIO

I_OL= 8mA at 3V VDDDIO

–

VDDDIO – 0.5

–

V

–

0.6

8.5

V

–

V

SID.GIO#5

SID.GIO#6

R_PU

R_PD

3.5

5.6

k

Pull-down resistor value

–

Input leakage current

(absolute value)

+25 °C T_A, 3V VDDD

SID.GIO#16 I_IL

–

3

2

7

nA

pF

SID.GIO#17 C_PIN

Max pin capacitance

–

VDDIO > 2.7V.

SID.GIO#43 V_HYSTTL

SID.GIO#44 V_HYSCMOS

Input hysteresis, LVTTL

15

40

–

mV Guaranteed by 

characterization.

0.05 ×

VDDDIO

Input hysteresis CMOS

–

mV

Current through protection

diode to VDDD/Vss

Guaranteed by 

µA

SID69

I_DIODE

–

100

85

characterization

Maximum total sink chip

current

SID.GIO#45 I_{TOT_GPIO}

mA

Table 12. I/O AC Specifications

(Guaranteed by Characterization)

Spec ID

SID70

Parameter

T_RISEF

T_FALLF

Description

Min Typ Max Units

Details/Conditions

Rise time in Fast Strong mode

Fall time in Fast Strong mode

2

–

12

ns 3.3 V VDDD, C_load= 25 pF

SID71

XRES

Table 13. XRES DC Specifications

Spec ID Parameter

Description

Min

Typ

Max Units

Details/Conditions

0.7 x

VDDIO

SID.XRES#1 V_IH

Input voltage HIGH threshold

–

V

CMOS input

0.3 x

VDDIO

SID.XRES#2 V_IL

Input voltage LOW threshold

Input capacitance

–

V

CMOS input

–

SID.XRES#3 C_IN

7

pF

0.05 x

VDDIO

SID.XRES#4 V_HYSXRES

Input voltage hysteresis

mV Guaranteed by characterization

Document Number: 002-17682 Rev. *B

Page 20 of 38

PRELIMINARY

EZ-PD™ CCG5

Digital Peripherals

The following specifications apply to the Timer/Counter/PWM peripherals in the Timer mode.

Pulse Width Modulation (PWM) for GPIO Pins

Table 14. PWM AC Specifications (Guaranteed by Characterization)

Spec ID

Parameter

Description

Min

–

Typ

–

Max Units

Details/Conditions

Fc max = CLK_SYS.

Maximum = 48 MHz.

SID.TCPWM.3 T_CPWMFREQOperating frequency

SID.TCPWM.4 T_PWMENEXTInput trigger pulse width

Fc

–

MHz

ns

2/Fc

–

For all trigger events

Minimum possible width of

Overflow, Underflow, and CC

(Counter equals Compare

value) outputs

SID.TCPWM.5 T_PWMEXT

Output trigger pulse width

2/Fc

–

ns

Minimum time between

successive counts

SID.TCPWM.5A T_CRES

SID.TCPWM.5B PWM_RES

SID.TCPWM.5C Q_RES

Resolution of counter

PWM resolution

1/Fc

–

ns

Minimum pulse width of PWM

output

Minimum pulse width between

quadrature-phase inputs

Quadrature inputs resolution

Table 15. Fixed I²C AC Specifications

(Guaranteed by Characterization)

Spec ID

SID153

Parameter

Description

Min

Typ Max Units

Details/Conditions

F_I2C1

Bit rate

–

1

Mbps

–

Table 16. Fixed UART AC Specifications

(Guaranteed by Characterization)

Spec ID

SID162

Parameter

Min

Typ

Max Units

Mbps

Details/Conditions

Bit rate

–

1

–

F_UART

Table 17. Fixed SPI AC Specifications

(Guaranteed by Characterization)

Spec ID

SID166

Parameter

F_SPI

Min

Typ

Max Units

MHz

Details/Conditions

SPI Operating frequency (Master; 6X

oversampling)

–

8

–

Table 18. Fixed SPI Master Mode AC Specifications (Guaranteed by Characterization)

Spec ID

SID167

Parameter

Description

Min

Typ

Max Units

Details/Conditions

T_DMO

MOSI Valid after SClock driving edge

–

15

ns

–

MISO Valid before SClock capturing

edge

Full clock, late MISO

sampling

SID168

SID169

T_DSI

20

0

–

ns

Referred to slave capturing

edge

T_HMO

Previous MOSI data hold time

–

ns

Document Number: 002-17682 Rev. *B

Page 21 of 38

PRELIMINARY

EZ-PD™ CCG5

Table 19. Fixed SPI Slave Mode AC Specifications

(Guaranteed by Characterization)

Spec ID

SID170

Parameter

T_DMI

Description

Min

Typ

Max

Units Details/Conditions

MOSI Valid before Sclock capturing

edge

40

–

ns

–

T_SCB= T_CPU

1/24MHz

=

SID171

T_DSO

MISO Valid after Sclock driving edge

–

42 + 3 × T_SCBns

MISO Valid after Sclock driving edge

in Ext Clk mode

SID171A

T_{DSO_EXT}

48

ns

–

SID172

T_HSO

Previous MISO data hold time

0

–

ns

–

SID172A

T_SSELSCK

SSEL Valid to first SCK Valid edge

100

Memory

Table 20. Flash AC Specifications

Spec ID Parameter

Description

Min Typ Max Units

Details/Conditions

Row (Block) write time (erase

and program)

SID.MEM#4 T_{ROW_WRITE}

–

20

ms

–

SID.MEM#3 T_{ROW_ERASE}

SID.MEM#8 T_ROWPROGRAM

Row erase time

–

15.5

7

ms

–

Row program time after erase

Bulk erase time (128k Bytes)

Total device program time

Flash endurance

SID178

SID180

T_BULKERASE

T_DEVPROG

–

35

25

–

ms

–

s

SID.MEM#6 F_END

100k

cycles

Flash retention, T_A≤ 55 °C, 

SID182

F_RET1

F_RET2

20

10

–

years

–

100 K P/E cycles

Flash retention, T_A≤ 85 °C, 

10 K P/E cycles

SID182A

System Resources

Power-on-Reset (POR) with Brown Out

Table 21. Imprecise Power On Reset (PRES)

Spec ID

SID185

SID186

Parameter

V_RISEIPOR

V_FALLIPOR

Description

Rising trip voltage

Falling trip voltage

Min

Typ

Max Units

Details/Conditions

0.80

0.70

–

1.50

1.4

V

Guaranteed by 

characterization

Table 22. Precise Power On Reset (POR) (Guaranteed by Characterization)

Spec ID

Parameter

Description

Min

Typ

–

Max Units

Details/Conditions

Brown-out Detect (BOD) trip voltage

in active/sleep modes

SID190

SID192

V_FALLPPOR

1.48

1.62

1.5

V

Guaranteed by 

characterization

V_FALLDPSLPBOD trip voltage in Deep Sleep mode 1.1

–

Document Number: 002-17682 Rev. *B

Page 22 of 38

PRELIMINARY

EZ-PD™ CCG5

SWD Interface

Table 23. SWD Interface Specifications

Spec ID

SID.SWD#1

Parameter

Description

Min

Typ

Max Units Details/Conditions

SWDCLK 1/3 CPU

F_SWDCLK1

3.3V  VDDDIO  5.5V

2.7V  VDDDIO  3.3V

–

14

7

MHz

clock frequency

SWDCLK 1/3 CPU

SID.SWD#2

F_SWDCLK2

–

clock frequency

SID.SWD#3

SID.SWD#4

SID.SWD#5

SID.SWD#6

T_SWDI_SETUP T = 1/f SWDCLK

T_SWDI_HOLD T = 1/f SWDCLK

T_SWDO_VALID T = 1/f SWDCLK

T_SWDO_HOLD T = 1/f SWDCLK

0.25 × T

–

ns

0.25 × T

Guaranteed by 

characterization

–

1

0.50 × T ns

ns

–

Internal Main Oscillator

Table 24. IMO AC Specifications

(Guaranteed by Design)

Spec ID

Parameter

F_IMOTOL

Description

Min

Typ

Max Units Details/Conditions

Frequency variation at 24, 36, and 

48 MHz (trimmed)

SID.CLK#13

–

±2

%

–

SID226

T_STARTIMO

T_JITRMSIMO2

F_IMO

IMO start-up time

RMS jitter at 24 MHz

IMO frequency

–

145

–

7

–

µs

ps

–

SID228

SID.CLK#1

24

48

MHz

Internal Low-speed Oscillator

Table 25. ILO AC Specifications

Spec ID

SID234

Parameter

T_STARTILO1

T_ILODUTY

F_ILO

Description

I_LOstart-up time

I_LOduty cycle

Min

–

Typ

–

Max Units Details/Conditions

2

ms

%

Guaranteed by 

characterization

SID238

40

20

50

40

60

80

SID.CLK#5

I_LOfrequency

kHz

–

Table 26. PD DC Specifications

Spec ID Parameter

Description

Min

Typ

–

Max

1.2

Units Details/Conditions

SID.DC.cc_shvt.1 vSwing

SID.DC.cc_shvt.2 vSwing_low

SID.DC.cc_shvt.3 zDriver

SID.DC.cc_shvt.4 zBmcRx

Transmitter Output High Voltage

Transmitter Output Low Voltage

Transmitter output impedance

Receiver Input Impedance

1.05

V

–

0.075

75

33

10

–

Ω

–

MΩ

Source current for USB standard

SID.DC.cc_shvt.5 Idac_std

SID.DC.cc_shvt.6 Idac_1p5a

SID.DC.cc_shvt.7 Idac_3a

64

–

96

µA

–

Source current for 1.5A at 5-V

165.6

303.6

194.4

356.4

Source current for 3A at 5-V adver-

tisement

Pull down termination resistance

when acting as UFP (upstream

facing port)

SID.DC.cc_shvt.8 Rd

4.59

4.08

–

5.61

6.12

kΩ

–

Pull down termination resistance

when acting as UFP, with dead

battery (upstream facing port)

SID.DC.cc_shvt.9 Rd_db

Document Number: 002-17682 Rev. *B

Page 23 of 38

PRELIMINARY

EZ-PD™ CCG5

Table 26. PD DC Specifications (continued)

Spec ID Parameter

Description

Min

Typ

Max

Units Details/Conditions

CC impedance to ground when

disabled

SID.DC.cc_shvt.10 zOPEN

108

–

kΩ

–

CC Voltages on DFP side-Standard

USB

SID.DC.cc_shvt.11 DFP_default_0p2

0.15

–

0.25

V

SID.DC.cc_shvt.12 DFP_1.5A_0p4

SID.DC.cc_shvt.13 DFP_3A_0p8

SID.DC.cc_shvt.14 DFP_3A_2p6

CC Voltages on DFP side-1.5A

CC Voltages on DFP side-3A

0.35

0.75

2.45

–

0.45

0.85

2.75

V

–

UFP_default_0p6 CC Voltages on UFP side-Standard

SID.DC.cc_shvt.15

0.61

–

0.7

V

–

6

USB

SID.DC.cc_shvt.16 UFP_1.5A_1p23 CC Voltages on UFP side-1.5A

1.16

0.3

10

–

1.31

0.6

50

V

%

–

SID.DC.cc_shvt.17 Vattach_ds

SID.DC.cc_shvt.18 Rattach_ds

SID.DC.cc_shvt.19 VTX_step

Deep sleep attach threshold

Deep sleep pull-up resistor

TX Drive voltage step size

kΩ

mV

80

120

Voltage threshold for Fast Swap

Detect

SID.DC.cc_shvt.30 FS_0p53

0.49

–

0.58

V

–

Analog to Digital Converter

Table 27. ADC DC Specifications

Spec ID

SID.ADC.1

Parameter

Resolution

Description

ADC resolution

Min

–

Typ

8

Max

–

Units Details/Conditions

Bits

LSB

–

SID.ADC.2

SID.ADC.3

SID.ADC.4

INL

Integral non-linearity

Differential non-linearity

Gain error

–2.5

–0.6

–

2.5

0.6

DNL

–

Gain Error

–

Reference voltage

generated from

V_DDD

SID.ADC.5

SID.ADC.6

VREF_ADC1

VREF_ADC2

Reference voltage of ADC

V_DDDmin

–

V_DDMax

V

Reference voltage

generate from

bandgap

1.96

2.0

2.04

Table 28. ADC AC Specifications

Spec ID Parameter

SID.ADC.7 SLEW_Max

Description

Min Typ

Max

Units Details/Conditions

V/ms

Rate of change of sampled voltage

signal

–

3

–

Table 29. VBUS Regulator AC Specifications

Spec ID Parameter

Description

Min Typ Max Units Details/Conditions

Apply V_BUSand

measure start time

on V_DDDpin.

Total start up time for the regulator supply

outputs

SID.AC.20VREG.1 T_START

–

120

µs

Time from assertion

of an internal

disable signal to for

load current on

Regulator power down time from vreg_en

= 0 to regulator disable

SID.AC.20VREG.2 T_STOP

–

1

µs

V_DDDto decrease

from 30 mA to

10 μA.

Document Number: 002-17682 Rev. *B

Page 24 of 38

PRELIMINARY

EZ-PD™ CCG5

Table 30. VSYS Switch Specifications

Spec ID Parameter

Description

Min Typ Max Units Details/Conditions

Measuredwithaload

current of 5 mA to

Resistance from supply input to output

supply V_DDD

SID.DC.VDDDSW.1 Res_sw

–

1.5

Ω

10 mA on V_DDD

.

Table 31. CSA DC Specifications

Spec ID

DC.CSA.100

DC.CSA.101

DC.CSA.102

DC.CSA.103

DC.CSA.104

DC.CSA.105

Parameter

ACC1

Description

Min Typ Max Units Details/Conditions

CSA accuracy for 13 mV ≤ Vsense ≤ 20 mV –26

CSA accuracy for 20 mV ≤ Vsense ≤ 24 mV –17

CSA accuracy for 25 mV ≤ Vsense ≤ 35 mV –14

CSA accuracy for 36 mV ≤ Vsense ≤ 53 mV –10

–

26

17

14

10

7

%

ACC2

ACC3

ACC4

ACC5

CSA accuracy for 54 mV ≤ Vsense ≤ 75 mV

CSA accuracy for 76 mV ≤ Vsense ≤ 97 mV

–7

–5

Active Mode

ACC6

5

CSA accuracy for 98 mV ≤ Vsense ≤

132 mV

DC.CSA.106

DC.CSA.107

ACC7

ACC8

–4

–3

–

4

3

%

CSA accuracy for 133 mV ≤ Vsense ≤

193 mV

DC.CSA.108

DC.CSA.109

DC.CSA.110

DC.CSA.111

ACC9

CSA accuracy for 13 mV ≤ Vsense ≤ 23 mV –26

CSA accuracy for 24 mV ≤ Vsense ≤ 31 mV –17

CSA accuracy for 32 mV ≤ Vsense ≤ 50 mV –14

CSA accuracy for 51 mV ≤ Vsense ≤ 85 mV –10

–

26

17

14

10

%

ACC10

ACC11

ACC12

DeepSleep Mode

CSA accuracy for 86 mV ≤ Vsense ≤

139 mV

DC.CSA.112

DC.CSA.113

ACC13

ACC14

Av

–7

–

7

5

%

CSA accuracy for 140 mV ≤ Vsense ≤

193 mV

–5

Nominal Gain Values supported: 10,15,20,

30,4050,70,100

DC.CSA.114

DC.CSA.115

10

–

100

2.5

V/V

–

Av_E_Trim Gain Error after Trim

–2.5

Table 32. CSA AC Specifications

Spec ID

DC.CSA.100

DC.CSA.101

DC.CSA.102

DC.CSA.103

DC.CSA.104

DC.CSA.105

Parameter

ACC1

Description

Min Typ Max Units Details/Conditions

CSA accuracy for 13 mV ≤ Vsense ≤ 20 mV -26

CSA accuracy for 20 mV ≤ Vsense ≤ 24 mV -17

CSA accuracy for 25 mV ≤ Vsense ≤ 35 mV -14

CSA accuracy for 36 mV ≤ Vsense ≤ 53 mV -10

CSA accuracy for 54 mV ≤ Vsense ≤ 75 mV -7

CSA accuracy for 76 mV ≤ Vsense ≤ 97 mV -5

-

26

17

14

10

7

%

ACC2

ACC3

ACC4

ACC5

Active Mode

ACC6

5

CSA accuracy for 98 mV ≤ Vsense ≤

132 mV

DC.CSA.106

DC.CSA.107

ACC7

ACC8

-4

-

4

3

%

CSA accuracy for 133 mV ≤ Vsense ≤

193 mV

-3

Document Number: 002-17682 Rev. *B

Page 25 of 38

PRELIMINARY

EZ-PD™ CCG5

Table 32. CSA AC Specifications (continued)

Spec ID

DC.CSA.108

DC.CSA.109

DC.CSA.110

DC.CSA.111

Parameter

ACC9

Description

Min Typ Max Units Details/Conditions

CSA accuracy for 13 mV ≤ Vsense ≤ 23 mV -26

CSA accuracy for 24 mV ≤ Vsense ≤ 31 mV -17

CSA accuracy for 32 mV ≤ Vsense ≤ 50 mV -14

CSA accuracy for 51 mV ≤ Vsense ≤ 85 mV -10

-

26

17

14

10

%

ACC10

ACC11

ACC12

DeepSleep Mode

CSA accuracy for 86 mV ≤ Vsense ≤

139 mV

DC.CSA.112

DC.CSA.113

ACC13

ACC14

Av

-7

-

7

5

%

CSA accuracy for 140 mV ≤ Vsense ≤

193 mV

-5

Nominal Gain Values supported: 10,15,20,

30,4050,70,100

DC.CSA.114

DC.CSA.115

10

-

100

2.5

V/V

–

Av_E_Trim Gain Error after Trim

-2.5

Table 33. UV/OV Specifications

Spec ID

Parameter

Description

Min

Typ Max Units Details/Conditions

Delay from UV threshold trip to output

GPIO toggle

SID.UVOV.AC.1

T_{OV_GPIO}

–

20

50

20

µs

Delay from UV threshold trip to external

PFET power gate turn off

SID.UVOV.AC.2

SID.UVOV.AC.3

T_{OV_GATE}

T_{UV_GPIO}

–

Delay from UV threshold trip to output

GPIO toggle

Table 34. PFET Gate Driver DC Specifications

Spec ID

Parameter

Rpd

Description

Min

Typ Max Units Details/Conditions

kΩ

SID.DC.PGDO.1

Resistance when “pull_dn” enabled

–

5

–

Table 35. PFET Gate Driver AC Specifications

Spec ID

Parameter

Description

Min

Typ Max Units Details/Conditions

SID.AC.PGDO.2

T_{r_discharge}

Discharge Rate of output note

–

5

V/µs

–

Document Number: 002-17682 Rev. *B

Page 26 of 38

PRELIMINARY

EZ-PD™ CCG5

SBU

Table 36. SBU Switch DC Specifications

Spec ID

Parameter

Description

Min

Typ Max Units Details/Conditions

On resistances for Aux switch at 3.3-V

input

SID.DC.20sbu.1 Ron1

–

4

7

Ω

–

SID.DC.20sbu.2 Ron2

SID.DC.20sbu.4 Ileak1

On resistances for Aux switch at 1-V input

Pin lekage current for SBU1, SBU2

–

3

–

5

Ω

–

–10

10

µA

Pin lekage current for LSTX, LSRX,

AUX_P, AUX_N

SID.DC.20sbu.5 Ileak2

–1

–

1

µA

–

SID.DC.20sbu.6 Rpu_aux_1

SID.DC.20sbu.7 Rpu_aux_2

SID.DC.20sbu.8 Rpd_aux_1

SID.DC.20sbu.9 Rpd_aux_2

SID.DC.20sbu.10 Rpd_aux_3

SID.DC.20sbu.11 Rpd_aux_4

Pull up resistance on AUX_P/N

Pull down resistance on AUX_P/N

80

0.8

80

–

120 KΩ

1.2 MΩ

120 KΩ

1.2 MΩ

611 KΩ

6.11 MΩ

–

0.8

329

3.29

Over-voltage protection detection

threshold above vddio

SID.DC.20sbu.16 OVP_threshold

SID.DC.20sbu.17 lsx_ron_3p3

SID.DC.20sbu.18 lsx_ron_1

200

–

8.5

5.5

–

1200 mV

–

On resistancesof LSTX/LSRXto SBU1/2

switch at 3.3-V input

17

11

Ω

On resistancesof LSTX/LSRXto SBU1/2

switch at 1-V input

–

Switch On flat resistances of AUX_P/N to

SBU1/2 switch (from 0 to 3.3 V)

SID.DC.20sbu.19 aux_ron_flat_fs

SID.DC.20sbu.20 aux_ron_flat_hs

SID.DC.20sbu.21 lsx_ron_flat_fs

SID.DC.20sbu.22 lsx_ron_flat_hs

–

2.5

0.5

5

Switch On flat resistances of AUX_P/N to

SBU1/2 switch (from 0 to 1 V)

–

Switch On flat resistances of LSTX/LSRX

to SBU1/2 switch (from 0 to 3.3 V)

–

Switch On flat resistances of LSTX/LSRX

to SBU1/2 switch (from 0 to 1 V)

–

0.5

SID.AC.20sbu.1 Con

Switch On capacitance

–

250

50

pF

dB

–

SID.AC.20sbu.2 Coff

Switch Off capacitance- Connector side

Switch isolation at F=1 MHz

SID.AC.20sbu.3 Off_isolation

–50

Table 37. SBU Switch AC Specifications

Spec ID

Parameter

Description

SBU Switch turn-on time

SBU Switch turn-off time

Min

–

Typ Max Units Details/Conditions

SID.AC.20SBU.4 T_ON

–

200

400

µs

–

SID.AC.20SBU.5 T_OFF

–

Document Number: 002-17682 Rev. *B

Page 27 of 38

PRELIMINARY

EZ-PD™ CCG5

Table 38. DP/DM Switch DC Specifications

Spec ID

Parameter

RON_HS

Description

Min

Typ Max Units Details/Conditions

DPDM On resistance for SYS lines

(0 to 0.5 V) - HS mode

SID.DC.dpdm.1

–

8

10

50

10

1



–

DPDM On resistance for SYS lines

(0 to 3.3 V) - FS mode

SID.DC.dpdm.2

SID.DC.dpdm.5

SID.DC.dpdm.6

SID.DC.dpdm.9

SID.DC.dpdm.10

SID.DC.dpdm.11

SID.DC.dpdm.12

SID.DC.dpdm.13

RON_FS

–

Switch On capacitance at FS at

6 MHz

Con_FS

pF

µA



Switch on capacitance at HS at

240 MHz

Con_HS

pin leakage at DP/DM connector

side and host side

ileak_pin

DPDM On resistance for UART lines

(0 to 3.3 V)

RON_UART

RON_FLAT_HS

RON_FLAT_FS

RON_FLAT_UART

17

0.5

3

DPDM On Flat resistance in HS

mode (0 to 0.4 V)



DPDMOnflatresistanceinFSmode

(0 to 3.3 V)



DPDM UART On flat resistance (0 to

3.3 V)

3



SID.AC.dpdm.1

SID.AC.dpdm.2

SID.AC.dpdm.8

SID.AC.dpdm.9

BW_3dB_HS

BW_3dB_FS

3-db bandwidth

1000

100

–50

–20

–

Mhz

db

–

Off_isolation_HS Switchoff isolation for H/S

Off_isolation_FS

Switchoff isolation for F/S

db

Table 39. DP/DM Switch AC Specifications

Spec ID

SID.AC.DPDM.5

SID.AC.DPDM.6

Parameter

T_ON

T_OFF

Description

DP/DM Switch turn-on time

DP/DM Switch turn-off time

Min Typ Max Units Details/Conditions

–

200

0.4

µs

–

Table 40. VCONN Switch DC Specifications

Spec ID

Parameter

Description

Min

Typ Max Units Details/Conditions

Switch ON resistance at V5V = 5 V

with 215mA load current

SID.DC.20VCONN.1 Ron

–

1.4

–

2

Ω

–

Overcurrent detection range for

CC1/CC2

SID.DC.20VCONN.9 I_OCP

400

200

600

mA

Overvoltage protection detection

threshold above vddd or V5V

whichever is higher

SID.DC.20VCONN.10 OVP_threshold

–

1200 mV

–

Overvoltage protection detection

hysteresis

SID.DC.20VCONN.11 OVP_hysteresis

SID.DC.20VCONN.12 OCP_hysteresis

SID.DC.20VCONN.13 I_{OCP_100mA}

50

20

70

–

150

60

mV

mA

–

Overcurrent detection hysteresis

Overcurrent detection Sort test

range for CC1/CC2

130

Document Number: 002-17682 Rev. *B

Page 28 of 38

PRELIMINARY

EZ-PD™ CCG5

Table 41. VCONN Switch AC Specifications

Spec ID Parameter

Description

Min Typ Max Units Details/Conditions

SID.AC.20VCONN.1 T_ON

SID.AC.20VCONN.2 T_OFF

VCONN Switch turn-on time

VCONN Switch turn-off time

–

200

3

µs

–

Table 42. VBUS Discharge Specifications

Spec ID

Parameter

Ron1

Description

20-V NMOS ON resistance

Min Typ Max Units Details/Conditions

SID.VBUS.DISC.1

SID.VBUS.DISC.2

SID.VBUS.DISC.3

SID.VBUS.DISC.4

SID.VBUS.DISC.5

–

875

438

290

220

175

Ω

–

Ron2

Ron3

Ron4

Ron5

Document Number: 002-17682 Rev. *B

Page 29 of 38

PRELIMINARY

EZ-PD™ CCG5

Ordering Information

Table 43 lists the EZ-PD CCG5 part numbers and features.

Table 43. EZ-PD CCG5 Ordering Information

Dead Battery Termination

Part Number

Application

Type-C Ports

Role

Package

Termination

Resistor

RP^[4], RD^[5]

CYPD5225-96BZXI

Notebooks, Desktops

2

1

Yes

DRP

96-ball BGA

40-pin QFN

CYPD5125-40LQXIT Notebooks, Desktops

Yes

Ordering Code Definitions

5

PD

X

CY

-

XX

1/2

X

I

T

T = Tape and Reel

Temperature Grade: 

I = Industrial

Pb-free

Package Type: XX = FN, LQ, BZ

LQ = QFN; BZ = BGA

Number of pins in the package: XX = 40 or 96

Device Role: Unique combination of role and termination: 

X = 2 or 3 or 4 or 5

Number of Type-C Ports: 1 = 1 Port, 2 = 2 Ports

Product Type: 5 = Fifth-generation product family, CCG5

Marketing Code: PD = Power Delivery product family

Company ID: CY = Cypress

Notes

4. Termination resistor denoting a downstream facing port.

5. Termination resistor denoting an accessory or upstream facing port.

Document Number: 002-17682 Rev. *B

Page 30 of 38

PRELIMINARY

EZ-PD™ CCG5

Package Diagrams

Figure 9. 40-Pin QFN (6 × 6 × 0.6 mm), LR40A/LQ40A 4.6 × 4.6 E-PAD (Sawn) Package Outline, 001-80659

001-80659 *A

Document Number: 002-17682 Rev. *B

Page 31 of 38

PRELIMINARY

EZ-PD™ CCG5

Figure 10. 96-Ball BGA (6 × 6 × 1.0 mm), Package Outline, 002-10631

E1

2X

0.10 C

(datum B)

A1 CORNER

E

B

A

D

1110 9 8 7

6 5 4 3 2 1

A

7

B

C

D

E

F

G

H

J

K

L

A1 CORNER

6

SD

D1

(datum A)

eD

6

2X

0.10 C

eE

SE

TOP VIEW

BOTTOM VIEW

DETAIL A

0.10 C

A

A1

0.08 C

C

96XØb

5

SIDE VIEW

Ø0.15 M C A B

Ø0.05 M C

DETAIL A

NOTES:

1. ALL DIMENSIONS ARE IN MILLIMETERS.

DIMENSIONS

NOM.

SYMBOL

2. SOLDER BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020.

3. "e" REPRESENTS THE SOLDER BALL GRID PITCH.

MIN.

MAX.

1.00

-

A

A1

D

-

4. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.

SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.

N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX

SIZE MD X ME.

0.16

6.00 BSC

E

6.00 BSC

5.00 BSC

11

D1

E1

MD

ME

N

5.

DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A

PLANE PARALLEL TO DATUM C.

6.

"SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND

DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW

11

96

WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW

"SD" OR "SE" = 0.

0.30

b

0.25

0.35

eD

eE

SD

SE

0.50 BSC

0.00

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW

"SD" = eD/2 AND "SE" = eE/2.

A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK

METALIZED MARK, INDENTATION OR OTHER MEANS.

7.

0.00

8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED SOLDER

BALLS.

9. JEDEC SPECIFICATION NO. REF. : MO-225.

002-10631 *A

Document Number: 002-17682 Rev. *B

Page 32 of 38

PRELIMINARY

EZ-PD™ CCG5

Table 44. Acronyms Used in this Document (continued)

Acronyms

Acronym

opamp

OCP

OVP

PCB

Description

operational amplifier

Table 44. Acronyms Used in this Document

Acronym

ADC

Description

analog-to-digital converter

overcurrent protection

overvoltage protection

printed circuit board

power delivery

API

ARM^®

application programming interface

advanced RISC machine, a CPU architecture

configuration channel

PD

CC

PGA

PHY

programmable gain amplifier

physical layer

BOD

Brown out Detect

CPU

central processing unit

POR

PRES

PSoC^®

PWM

RAM

RISC

RMS

RTC

power-on reset

cyclic redundancy check, an error-checking

protocol

CRC

precise power-on reset

Programmable System-on-Chip™

pulse-width modulator

random-access memory

reduced-instruction-set computing

root-mean-square

CS

current sense

DFP

downstream facing port

digital input/output, GPIO with only digital 

capabilities, no analog. See GPIO.

DIO

DRP

dual role port

electrically erasable programmable read-only

memory

EEPROM

real-time clock

RX

receive

a USB cable that includes an IC that reports cable

characteristics (e.g., current rating) to the Type-C

ports

EMCA

SAR

successive approximation register

I²C serial clock

SCL

EMI

ESD

FPB

FS

electromagnetic interference

electrostatic discharge

flash patch and breakpoint

full-speed

SDA

I²C serial data

S/H

sample and hold

Serial Peripheral Interface, a communications

protocol

SPI

GPIO

IC

general-purpose input/output

integrated circuit

SRAM

SWD

TX

static random access memory

serial wire debug, a test protocol

transmit

IDE

integrated development environment

I²C, or IIC Inter-Integrated Circuit, a communications protocol

a new standard with a slimmer USB connector and

a reversible cable, capable of sourcing up to 100 W

of power

Type-C

ILO

internal low-speed oscillator, see also IMO

internal main oscillator, see also ILO

input/output, see also GPIO

low-voltage detect

IMO

I/O

Universal Asynchronous Transmitter Receiver, a

communications protocol

UART

USB

LVD

LVTTL

MCU

NC

Universal Serial Bus

low-voltage transistor-transistor logic

microcontroller unit

USB input/output, CCG5 pins used to connect to a

USB port

USBIO

XRES

external reset I/O pin

no connect

NMI

NVIC

nonmaskable interrupt

nested vectored interrupt controller

Document Number: 002-17682 Rev. *B

Page 33 of 38

PRELIMINARY

EZ-PD™ CCG5

Document Conventions

Table 45. Units of Measure (continued)

Symbol Unit of Measure

µW

Units of Measure

Table 45. Units of Measure

microwatt

milliampere

millisecond

millivolt

Symbol

°C

Unit of Measure

mA

ms

mV

nA

ns

degrees Celsius

hertz

Hz

KB

1024 bytes

nanoampere

nanosecond

ohm

kHz

k

kilohertz

kilo ohm



Mbps

MHz

M

Msps

µA

megabits per second

megahertz

pF

ppm

ps

picofarad

parts per million

picosecond

second

mega-ohm

megasamples per second

microampere

microfarad

s

sps

V

samples per second

volt

µF

µs

microsecond

microvolt

µV

Document Number: 002-17682 Rev. *B

Page 34 of 38

PRELIMINARY

EZ-PD™ CCG5

References and Links To Applications Collaterals

Knowledge Base Articles

■ Key Differences Among EZ-PD™ CCG1, CCG2, CCG3 and

CCG5 - KBA210740

■ AN95615 - Designing USB 3.1 Type-C Cables Using EZ-PD™

CCG2

■ Programming EZ-PD™ CCG2, EZ-PD™ CCG3 and EZ-PD™

■ AN95599 - Hardware Design Guidelines for EZ-PD™ CCG2

CCG5 Using PSoC® Programmer and MiniProg3 - KBA96477

■ AN210403 - Hardware Design Guidelines for Dual Role Port

■ CCGX Frequently Asked Questions (FAQs) - KBA97244

■ Handling Precautions for CY4501 CCG1 DVK - KBA210560

■ Cypress EZ-PD™ CCGx Hardware - KBA204102

■ Difference between USB Type-C and USB-PD - KBA204033

■ CCGx Programming Methods - KBA97271

Applications Using EZ-PD™ USB Type-C Controllers

■ AN210771 - Getting Started with EZ-PD™ CCG5

Reference Designs

■ EZ-PD™ CCG2 Electronically Marked Cable Assembly

(EMCA) Paddle Card Reference Design

■ Getting started with Cypress USB Type-C Products -

KBA04071

■ EZ-PD™ CCG2 USB Type-C to DisplayPort Cable Solution

■ CCG1 USB Type-C to DisplayPort Cable Solution

■ Type-C to DisplayPort Cable Electrical Requirements

■ CCG1 USB Type-C to HDMI/DVI/VGA Adapter Solution

■ EZ-PD™ CCG2 USB Type-C to HDMI Adapter Solution

■ Dead Battery Charging Implementation in USB Type-C

Solutions - KBA97273

■ CCG1 Electronically Marked Cable Assembly (EMCA) Paddle

Card Reference Design

■ TerminationResistorsRequiredfortheUSBType-CConnector

– KBA97180

■ VBUS Bypass Capacitor Recommendation for Type-C Cable

and Type-C to Legacy Cable/Adapter Assemblies – KBA97270

■ CCG1 USB Type-C to Legacy USB Device Cable Paddle Card

Reference Schematics

■ Need for Regulator and Auxiliary Switch in Type-C to

DisplayPort (DP) Cable Solution - KBA97274

■ EZ-USB GX3 USB Type-C to Gigabit Ethernet Dongle

■ EZ-PD™ CCG2 USB Type-C Monitor/Dock Solution

■ CCG2 20W Power Adapter Reference Design

■ CCG2 18W Power Adapter Reference Design

■ Need for a USB Billboard Device in Type-C Solutions –

KBA97146

■ CCG1DevicesinType-CtoLegacyCable/AdapterAssemblies

– KBA97145

■ EZ-USB GX3 USB Type-A to Gigabit Ethernet Reference

■ Cypress USB Type-C Controller Supported Solutions –

Design Kit

KBA97179

Kits

■ Termination Resistors for Type-C to Legacy Ports – KBA97272

■ CY4501 CCG1 Development Kit

■ CY4502 EZ-PD™ CCG2 Development Kit

■ CY4531 EZ-PD CCG3 Evaluation Kit

■ CY4541 EZ-PD™ CCG5 Evaluation Kit

■ Handling Instructions for CY4502 CCG2 Development Kit –

KBA97916

■ Thunderbolt™ Cable Application Using CCG3 Devices -

KBA210976

■ Power Adapter Application Using CCG3 Devices - KBA210975

■ Methods to Upgrade Firmware on CCG3 Devices - KBA210974

■ Device Flash Memory Size and Advantages - KBA210973

■ Applications of EZ-PD™ CCG5 - KBA210739

Application Notes

Datasheets

■ CCG1 Datasheet: USB Type-C Port Controller with Power

Delivery

■ CYPD1120 Datasheet: USB Power Delivery Alternate Mode

Controller on Type-C

■ AN96527 - Designing USB Type-C Products Using Cypress’s

CCG1 Controllers

■ CCG2: USB Type-C Port Controller Datasheet

■ CCG3: USB Type-C Controller Datasheet

Document Number: 002-17682 Rev. *B

Page 35 of 38

PRELIMINARY

EZ-PD™ CCG5

Errata

This section describes the errata for the CCG5. Contact your local Cypress Sales Representative if you have questions.

Part Numbers Affected

Part Number

CYPD5125-40LQXIT

CYPD5225-96BZXI

CCG5 Qualification Status

Product Status: Sampling

CCG5 Errata Summary

The following table defines the errata applicability to available CCG5 engineering samples.

Silicon Compliance

Items

Part Number

Fix Status

Revision

Impact

[1]. Integrated VBUS Discharge Circuit Not

Expected to Work

CYPD5125-40LQXIT

CYPD5225-96BZXI

ES

None

Fix available in Production Silicon

[2]. CC1, CC2, SBU1, SBU2 pins are 500V

HBM Compliant and not 8KV IEC Compliant CYPD5225-96BZXI

CYPD5125-40LQXIT

ES

None

[3]. Eye Diagram Failure for USB2.0 High

CYPD5125-40LQXIT

Speed Mode (HS mode) at 480 MHz on

CYPD5225-96BZXI

Fix available in Production Silicon

DP/DM mux

1. Integrated VBUS Discharge Circuit Not Expected to Work

■Problem Definition

On CCG5 Engineering Samples, the integrated VBUS Discharge circuit does not function. Usage of the internal VBUS

discharge can result in silicon getting damaged.

■Workaround

Use external VBUS Discharge circuit and control it using a CCG5 GPIO.

■Fix Status

Fix will be available in Production Silicon.

2. CC1, CC2, SBU1, SBU2 pins are 500V HBM Compliant and not 8KV IEC Compliant

■Problem Definition

On CCG5 Engineering Samples, CC1, CC2, SBU1, SBU2 pins are 500V HBM compliant and not 8KV IEC compliant.

■Workaround

Use ESD straps while handing the parts manually. Provide external IEC protection to these pins.

■Fix Status

CC1, CC2, SBU1, SBU2 will be 8KV IEC compliant in production parts.

3. Eye Diagram Failure for USB2.0 High Speed Mode (HS mode) at 480 MHz on DP/DM mux

■Problem Definition

CCG5 engineering samples has eye diagram failure for USB 2.0 High Speed Mode (HS mode) at 480 MHz on DP/DM mux.

■Workaround

Use external DP/DM HS MUX or short DP top pin to DP bottom pin and DM top pin to DM bottom pin on the type-C connector.

■Fix Status

Fix available in Production Silicon.

Document Number: 002-17682 Rev. *B

Page 36 of 38

PRELIMINARY

EZ-PD™ CCG5

Document History Page

Document Title: EZ-PD™ CCG5, USB Type-C Port Controller

Document Number: 002-17682

Orig. of

Change

Submission

Date

Revision

ECN

Description of Change

**

5528106

SOBI

12/07/2016 New datasheet

Updated General Description and Features.

Updated Logic Block Diagram.

*A

5606273

01/27/2017 Updated USB-PD Subsystem (SS) and reordered the Functional Overview section.

Updated GPIO.

Updated 40-Pin QFN Pin Map (Top View) for CYPD5125-40LQXIT.

Changed datasheet status to Preliminary.

Added Errata.

Added Table 4 through Table 7.

Added Table 9 through Table 42 in Device-Level Specifications.

Updated Logic Block Diagram, GPIO, and VBUS Discharge.

06/03/2017

*B

5694572

SOBI

Updated Table 2, Table 3, Table 8, and Table 44.

Updated Figure 5 through Figure 8.

Updated Figure 10 (spec 002-10631 Rev. ** to *A) in Package Diagrams.

Updated compliance with USB spec in Sales, Solutions, and Legal Information.

Updated template.

Document Number: 002-17682 Rev. *B

Page 37 of 38

PRELIMINARY

EZ-PD™ CCG5

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office

closest to you, visit us at Cypress Locations.

Products

PSoC^®Solutions

ARM^®Cortex^®Microcontrollers

cypress.com/arm

cypress.com/automotive

cypress.com/clocks

cypress.com/interface

cypress.com/iot

PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6

Automotive

Cypress Developer Community

Clocks & Buffers

Interface

Training | Components

Internet of Things

Memory

Technical Support

cypress.com/memory

cypress.com/mcu

cypress.com/support

Microcontrollers

PSoC

cypress.com/psoc

Power Management ICs

Touch Sensing

USB Controllers

Wireless Connectivity

cypress.com/pmic

cypress.com/touch

cypress.com/usb

cypress.com/wireless

Notice regarding compliance with Universal Serial Bus specification. Cypress offers firmware and hardware solutions that are certified to comply with the Universal Serial Bus specification, USB

Type-C™ Cable and Connector Specification, and other specifications of USB Implementers Forum, Inc (USB-IF). You may use Cypress or third party software tools, including sample code, to modify

the firmware for Cypress USB products. Modification of such firmware could cause the firmware/hardware combination to no longer comply with the relevant USB-IF specification. You are solely

responsible ensuring the compliance of any modifications you make, and you must follow the compliance requirements of USB-IF before using any USB-IF trademarks or logos in connection with any

modifications you make. In addition, if Cypress modifies firmware based on your specifications, then you are responsible for ensuring compliance with any desired standard or specifications as if you

had made the modification. CYPRESS IS NOT RESPONSIBLE IN THE EVENT THAT YOU MODIFY OR HAVE MODIFIED A CERTIFIED CYPRESS PRODUCT AND SUCH MODIFIED PRODUCT

NO LONGER COMPLIES WITH THE RELEVANT USB-IF SPECIFICATIONS.

including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries

worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other

intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress

hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to

modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users

(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as

provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation

of the Software is prohibited.

TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE

OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent

permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any

product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is

the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products

are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or

systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the

device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably

expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,

damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other

liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.

Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in

the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.

Document Number: 002-17682 Rev. *B

Revised June 3, 2017

Page 38 of 38

厂商	型号	描述	页数
NIDEC	CYP	[ PIANO SWITCHES (FULL PITCH) ]	5 页
NIDEC	CYP-0200MB	[ PIANO SWITCHES (FULL PITCH) ]	5 页
NIDEC	CYP-0200MC	[ PIANO SWITCHES (FULL PITCH) ]	5 页
NIDEC	CYP-0200TB	[ PIANO SWITCHES (FULL PITCH) ]	5 页
NIDEC	CYP-0200TC	[ PIANO SWITCHES (FULL PITCH) ]	5 页
NIDEC	CYP-0201MB	[ PIANO SWITCHES (FULL PITCH) ]	5 页
NIDEC	CYP-0201MC	[ PIANO SWITCHES (FULL PITCH) ]	5 页
NIDEC	CYP-0201TB	[ PIANO SWITCHES (FULL PITCH) ]	5 页
NIDEC	CYP-0201TC	[ PIANO SWITCHES (FULL PITCH) ]	5 页
NIDEC	CYP-0202MB	[ PIANO SWITCHES (FULL PITCH) ]	5 页