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CYS25G0101DX-BBC

型号：

CYS25G0101DX-BBC

品牌：

CYPRESS[ CYPRESS ]

页数：

15 页

PDF大小：

210 K

下载PDF手册
CYS25G0101DX  
SONET OC-48 Transceiver  
data recovery operations in a single chip, optimized for full  
SONET compliance.  
Features  
• SONET OC-48 operation  
• Bellcore and ITU jitter compliance  
• 2.488-GBaud serial signaling rate  
Transmit Path  
New data is accepted at the 16-bit parallel transmit interface  
at a rate of 155.52 MHz. This data is passed to a small  
integrated FIFO to allow flexible transfer of data between the  
SONET processor and the transmit serializer. As each 16-bit  
word is read from the transmit FIFO, it is serialized and sent  
out the high-speed differential line driver at a rate of 2.488  
Gbits/second.  
• Multiple selectable loopback/loop-through modes  
• Single 155.52-MHz reference clock  
• Transmit FIFO for flexible data interface clocking  
• 16-bit parallel-to-serial conversion in transmit path  
• Serial-to-16-bit parallel conversion in receive path  
• Synchronous parallel interface  
Receive Path  
— LVPECL-compliant  
As serial data is received at the differential line receiver, it is  
passed to a clock and data recovery (CDR) PLL, which  
extracts a precision low-jitter clock from the transitions in the  
data stream. This bit-rate clock is then used to sample the data  
stream and receive the data. Every 16-bit-times, a new word  
is presented at the receive parallel interface along with a clock.  
— HSTL-compliant  
• Internal transmit and receive phase-locked loops  
(PLLs)  
• Differential CML serial input  
— 50-mV input sensitivity  
Parallel Interface  
— 100Ω Internal termination and DC-restoration  
• Differential CML serial output  
The parallel I/O interface supports high-speed bus communi-  
cations using HSTL signaling levels to minimize both power  
consumption and board landscape. The HSTL outputs are  
capable of driving unterminated transmission lines of less than  
70 mm, and terminated 50Ω transmission lines of more than  
twice that length.  
— Source matched for 50Ω transmission lines (100Ω  
differential transmission lines)  
• Direct interface to standard fiber-optic modules  
• Less than 1.0W typical power  
The CYS25G0101DX Transceiver’s parallel HSTL I/O can  
also be configured to operate at LVPECL signaling levels. This  
can all be done externally by changing VDDQ, VREF, and  
creating a simple circuit at the termination of the transceiver’s  
parallel output interface.  
• 120-pin 14 mm × 14 mm TQFP  
• Standby power-saving mode for inactive loops  
• 0.25µ BiCMOS technology  
Functional Description  
Clocking  
The CYS25G0101DX SONET OC-48 Transceiver is a  
communications building block for high-speed SONET data  
communications. It provides complete parallel-to-serial and  
serial-to-parallel conversion, clock generation, and clock and  
The source clock for the transmit data path is selectable from  
either the recovered clock or an external BITS (Building  
Integrated Timing Source) reference clock. The low jitter of the  
CYS25G0101DX  
TXD[15:0]  
16  
SONET Data  
Processor  
TXCLKI  
Transmit Data  
Interface  
FIFO_RST  
FIFO_ERR  
TXCLKO  
155.52 MHz  
BITS Time  
Reference  
2
REFCLK±  
16  
Host Bus  
Interface  
RXD[15:0]  
RXCLK  
Receive Data  
Interface  
IN+  
IN–  
SD  
OUT–  
OUT+  
RD+  
RD–  
SD  
TD–  
TD+  
Serial Data  
Serial Data  
LOOPTIME  
DIAGLOOP  
LOOPA  
Data & Clock  
Direction  
Control  
Optical  
XCVR  
Optical  
Fiber Links  
LINELOOP  
RESET  
PWRDN  
LOCKREF  
LFI  
Status and  
System  
Control  
Figure 1. CYS25G0101DX System Connections  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
Document #: 38-02009 Rev. *J  
Revised December 30, 2002  
CYS25G0101DX  
CDR PLL allows loop-timed operation of the transmit data path  
while still meeting all Bellcore and ITU jitter requirements.  
redundant SONET rings that are maintained in standby, the  
CYS25G0101DX may also be dynamically powered down to  
conserve system power.  
Multiple loopback and loop-through modes are available for  
both diagnostic and normal operation. For systems containing  
Logic Block Diagram  
(155.52 MHz)  
(155.52 MHz)  
(155.52 MHz)  
RXCLK  
TXCLKI  
REFCLK±  
TXD[15:0]  
16  
RXD[15:0]  
16  
FIFO_ERR TXCLKO  
FIFO_RST  
Input  
Register  
Output  
Register  
TX PLL  
X16  
÷16  
Shifter  
FIFO  
÷16  
Recovered  
Bit-Clock  
TX Bit-Clock  
Shifter  
RX CDR  
PLL  
Retimed  
Data  
Lock-to-Ref  
LOOPTIME  
DIAGLOOP  
Lock-to-Data/  
Clock Control  
Logic  
LINELOOP  
LOOPA  
OUT±  
IN±  
PWRDN LOCKREF SD LFI RESET  
Document #: 38-02009 Rev. *J  
Page 2 of 15  
CYS25G0101DX  
Pin Configuration[1, 2]  
120-pin Thin Quad Flatpack Pin Configuration  
Top View  
NC  
90  
LFI  
RESET  
1
VCCQ  
2
89  
VSSQ  
88  
DIAGLOOP  
LINELOOP  
LOOPA  
3
REFCLK+  
4
87  
REFCLK–  
5
86  
NC  
VSSN  
6
85  
LOOPTIME  
84  
VCCN  
7
PWRDN  
VSSN  
8
83  
VSSN  
SD  
9
82  
81  
80  
79  
78  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
VSSN  
VCCN  
VSSN  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
LOCKREF  
RXD[0]  
RXD[1]  
RXD[2]  
RXD[3]  
VSSN  
VDDQ  
RXD[4]  
RXD[5]  
RXD[6]  
RXD[7]  
VSSN  
VDDQ  
RXCLK  
VSSN  
VDDQ  
NC  
TXCLKO  
VSSN  
CYS25G0101DX  
VDDQ  
TXD[0]  
TXD[1]  
TXD[2]  
TXD[3]  
VCCQ  
VSSQ  
VCCN  
VSSN  
23  
24  
TXD[4]  
TXD[5]  
TXD[6]  
TXD[7]  
TXD[8]  
TXD[9]  
25  
26  
27  
28  
29  
30  
NC  
NC  
TXD[10]  
TXD[11]  
NC  
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60  
Notes:  
1. No connect (NC) pins must be left unconnected or floating. Connecting any of these pins to the positive or negative power supply may cause improper operation  
or failure of the device.  
2. Pins 113 and 119 can be either no connect or VSSQ. Use VSSQ for compatibility with next generation of OC-48 SERDES devices. Pin 116 can be either no  
connect or VCCQ. Use VCCQ for compatibility with next generation of OC-48 SERDES devices.  
Document #: 38-02009 Rev. *J  
Page 3 of 15  
CYS25G0101DX  
Pin Descriptions  
CYS25G0101DX OC-48 SONET Transceiver  
Pin Name I/O Characteristics  
Transmit Path Signals  
Signal Description  
TXD[15:0]  
HSTL inputs,  
Parallel Transmit Data Inputs. A 16-bit word, sampled by TXCLKI↑. TXD[15] is the most  
sampled by TXCLKI↑ significant bit (the first bit transmitted).  
TXCLKI  
HSTL Clock input Parallel Transmit Data Input Clock. The TXCLKI is used to transfer the data into the input  
register of the serializer. The TXCLKI samples the data, TXD [15:0], on the rising edge of  
the clock cycle.  
TXCLKO  
VREF  
HSTL Clock output Transmit Clock Output. Divide by 16 of the selected transmit bit-rate clock. It can be used  
to coordinate byte-wide transfers between upstream logic and the CYS25G0101DX.  
Input Analog  
Reference  
Reference Voltage for HSTL Parallel Input Bus. VDDQ/2.[3]  
Receive Path Signals  
RXD[15:0]  
HSTL output,  
synchronous  
Parallel Receive Data Output. These outputs change following RXCLK↓. RXD[15] is the  
most significant bit of the output word, and is received first on the serial interface.  
RXCLK  
HSTL Clock output Receive Clock Output. Divide by 16 of the bit-rate clock extracted from the received serial  
stream. RXD [15:0] is clocked out on the falling edge of the RXCLK.  
CM_SER  
RXCN1  
RXCN2  
RXCP1  
RXCP2  
Analog  
Analog  
Analog  
Analog  
Analog  
Common Mode Termination. Capacitor shunt to VSS for common mode noise.  
Receive Loop Filter Capacitor (Negative)  
Receive Loop Filter Capacitor (Negative)  
Receive Loop Filter Capacitor (Positive)  
Receive Loop Filter Capacitor (Positive)  
Device Control and Status Signals  
REFCLK±  
Differential LVPECL Reference Clock. This clock input is used as the timing reference for the transmit and  
input  
receive PLLs. A derivative of this input clock may also be used to clock the transmit parallel  
interface. The reference clock is internally biased allowing for an AC-coupled clock signal.  
LFI  
LVTTL output  
Line Fault Indicator. When LOW, this signal indicates that the selected receive data  
stream has been detected as invalid by either a LOW input on SD, or by the receive VCO  
being operated outside its specified limits.  
RESET  
LVTTL input  
LVTTL input  
Reset for all logic functions except the transmit FIFO.  
LOCKREF  
Receive PLL Lock to Reference. When LOW, the receive PLL locks to REFCLK instead  
of the received serial data stream.  
SD  
LVTTL input  
Signal Detect. When LOW, the receive PLL locks to REFCLK instead of the received serial  
data stream. The SD is to be connected to an external optical module to indicate a loss of  
received optical power.  
FIFO_ERR  
LVTTL output  
Transmit FIFO Error. When HIGH the transmit FIFO has either under or overflowed. When  
this occurs, the FIFO’s internalclearing mechanism willclear the FIFO within 9clock cycles.  
In addition, FIFO_RST must be activated at device power-up to ensure that the in and out  
pointers of the FIFO are set to maximum separation.  
FIFO_RST  
PWRDN  
LVTTL input  
LVTTL input  
Transmit FIFO Reset. When LOW, the in and out pointers of the transmit FIFO are set to  
maximum separation. FIFO_RST must be activated at device power-up to ensure that the  
in and out pointers of the FIFO are set to maximum separation. When the FIFO is being  
reset, the output data is a 1010... pattern.  
Device Power Down. When LOW, the logic and drivers are all disabled and placed into a  
standby condition where only minimal power is dissipated.  
Loop Control Signals  
DIAGLOOP LVTTL input  
Diagnostic Loopback Control. When HIGH, transmit data is routed through the receive  
clock and data recovery and presented at the RXD[15:0] outputs. When LOW, received  
serial data is routed through the receive clock and data recovery and presented at the  
RXD[15:0] outputs.  
Note:  
3.  
VREF equals to (VCC – 1.33)V if interfacing to a parallel LVPECL interface.  
Document #: 38-02009 Rev. *J  
Page 4 of 15  
CYS25G0101DX  
CYS25G0101DX OC-48 SONET Transceiver (continued)  
Pin Name I/O Characteristics  
Signal Description  
LINELOOP  
LVTTL input  
Line Loopback Control. When HIGH, received serial data is looped back from receive to  
transmit after being reclocked by a recovered clock. When LINELOOP is LOW, the data  
passed to the OUT± line driver is controlled by LOOPA. When both LINELOOP and LOOPA  
are LOW, the data passed to the OUT± line driver is generated in the transmit shifter.  
LOOPA  
LVTTL input  
Analog Line Loopback. When LINELOOP is LOW and LOOPA is HIGH, received serial  
data is looped back from receive input buffer to transmit output buffer, but is not routed  
through the clock and data recovery PLL. When LOOPA is LOW, the data passed to the  
OUT± line driver is controlled by LINELOOP.  
LOOPTIME LVTTL input  
Loop Time Mode. When HIGH, the extracted receive bit-clock replaces transmit bit-clock.  
When LOW, the REFCLK input is multiplied by 16 to generate the transmit bit clock.  
Serial I/O  
OUT±  
Differential CML  
output  
DifferentialSerial DataOutput. ThisdifferentialCMLoutput(+3.3Vreferenced)iscapable  
of driving terminated 50Ω transmission lines or commercial fiber-optic transmitter modules.  
IN±  
Differential CML  
input  
Differential Serial Data Input. This differential input accept the serial data stream for  
deserialization and clock extraction.  
Power  
VCCN  
VSSN  
Power  
Ground  
Power  
Ground  
Power  
+3.3V supply (for digital and low-speed I/O functions)  
Signal and power ground (for digital and low-speed I/O functions)  
+3.3V quiet power (for analog functions)  
VCCQ  
VSSQ  
VDDQ  
Quiet ground (for analog functions)  
+1.5V supply for HSTL outputs[4]  
the transmit FIFO has either under or overflowed. The FIFO  
can be externally reset to clear the error indication or if no  
action is taken, the internal clearing mechanism will clear the  
FIFO in nine clock cycles. When the FIFO is being reset, the  
output data is 1010.  
CYS25G0101DX Operation  
The CYS25G0101DX is a highly configurable device designed  
to support reliable transfer of large quantities of data using  
high-speed serial links. It performs necessary clock and data  
recovery, clock generation, serial-to-parallel conversion, and  
parallel-to-serial conversion. CYS25G0101DX also provides  
various loopback functions.  
Transmit PLL Clock Multiplier  
The Transmit PLL Clock Multiplier accepts a 155.52-MHz  
external clock at the REFCLK input, and multiplies that clock  
by 16 to generate a bit-rate clock for use by the transmit shifter.  
The operating serial signaling rate and allowable range of  
REFCLK frequencies is listed in Table 7. The REFCLK phase  
noise limits to meet SONET compliancy are illustrated in  
Figure 5. The REFCLK± input is a standard LVPECL input.  
CYS25G0101DX Transmit Data Path  
Operating Modes  
The transmit path of the CYS25G0101DX supports 16-bit  
-wide data paths.  
Phase-Align Buffer  
Serializer  
Data from the input register is passed to a phase-align buffer  
(FIFO). This buffer is used to absorb clock phase differences  
between the transmit input clock and the internal character  
clock.  
The parallel data from the phase-align buffer is passed to the  
Serializer which converts the parallel data to serial data using  
the bit-rate clock generated by the Transmit PLL clock multi-  
plier. TXD[15] is the most significant bit of the output word, and  
is transmitted first on the serial interface.  
Initialization of the phase-align buffer takes place when the  
FIFO_RST input is asserted LOW. When FIFO_RST is  
returned HIGH, the present input clock phase relative to  
TXCLKO is set. Once set, the input clock is allowed to skew in  
time up to half a character period in either direction relative to  
REFCLK (i.e., ±180°). This time shift allows the delay path of  
the character clock (relative to REFLCK) to change due to  
operating voltage and temperature while not effecting the  
desired operation. FIFO_RST is an asynchronous input.  
Serial Output Driver  
The serial interface Output Driver makes use of high-perfor-  
mance differential Current Mode Logic (CML) to provide a  
source-matched driver for the transmission lines. This driver  
receives its data from the Transmit Shifters or the receive  
loopback data. The outputs have signal swings equivalent to  
that of standard LVPECL drivers, and are capable of driving  
AC-coupled optical modules or transmission lines.  
FIFO_ERR is the transmit FIFO Error indicator. When HIGH,  
Note:  
4.  
VDDQ equals VCC if interfacing to a parallel LVPECL interface.  
Document #: 38-02009 Rev. *J  
Page 5 of 15  
CYS25G0101DX  
clocks these bits into the Deserializer at the bit-clock rate. The  
Deserializer converts serial data into parallel data. RXD[15] is  
the most significant bit of the output word and is received first  
on the serial interface.  
CYS25G0101DX Receive Data Path  
Serial Line Receivers  
A differential line receiver, IN±, is available for accepting the  
input serial data stream. The serial line receiver inputs can  
accommodate high wire interconnect and filtering losses or  
transmission line attenuation (VSE > 25 mV, or 50 mV  
peak-to-peak differential), and can be AC-coupled to +3.3V or  
+5V powered fiber-optic interface modules. The common-  
mode tolerance of these line receivers accommodates a wide  
range of signal termination voltages.  
Loopback/Timing Modes  
CYS25G0101DX supports various loopback modes, as  
described below.  
Facility Loopback (Line Loopback with Retiming)  
When the LINELOOP signal is set HIGH, the Facility Loopback  
mode is activated and the high-speed serial receive data (IN±)  
is presented to the high-speed transmit output (OUT±) after  
retiming. In Facility Loopback mode, the high-speed receive  
data (IN±) is also converted to parallel data and presented to  
the low-speed receive data output pins (RXD[15:0]). The  
receive recovered clock is also divided down and presented to  
the low-speed clock output (RXCLK).  
Lock to Data Control  
Line Receiver routed to the clock and data recovery PLL is  
monitored for  
• status of signal detect (SD) pin  
• status of LOCKREF pin.  
This status is presented on the Line Fault Indicator (LFI)  
output, which changes asynchronously in the cases in which  
SD or LOCKREF go from HIGH to LOW. Otherwise, it changes  
synchronously to the REFCLK.  
Equipment Loopback (Diagnostic Loopback with Retiming)  
When the DIAGLOOP signal is set HIGH, transmit data is  
looped back to the RX PLL, replacing IN±. Data is looped back  
from the parallel TX inputs to the parallel RX outputs. The data  
is looped back at the internal serial interface and goes through  
transmit shifter and the receive CDR. SD is ignored in this  
mode.  
Clock/Data Recovery  
The extraction of a bit-rate clock and recovery of data bits from  
received serial stream is performed by a Clock/Data Recovery  
(CDR) block. The clock extraction function is performed by  
high-performance embedded phase-locked loop (PLL) that  
tracks the frequency of the incoming bit stream and aligns the  
phase of the internal bit-rate clock to the transitions in the  
selected serial data stream.  
CDR accepts a character-rate (bit-rate * 16) reference clock  
on the REFCLK input. This REFCLK input is used to ensure  
that the VCO (within the CDR) is operating at the correct  
frequency (rather than some harmonic of the bit-rate), to  
improve PLL acquisition time, and to limit unlocked frequency  
excursions of the CDR VCO when no data is present at the  
serial inputs.  
Regardless of the type of signal present, the CDR will attempt  
to recover a data stream from it. If the frequency of the  
recovered data stream is outside the limits set by the range  
controls, the CDR PLL will track REFCLK instead of the data  
stream. When the frequency of the selected data stream  
returns to a valid frequency, the CDR PLL is allowed to track  
the received data stream. The frequency of REFCLK is  
required to be within ±100 ppm of the frequency of the clock  
that drives the REFCLK signal of the remote transmitter to  
ensure a lock to the incoming data stream.  
Line Loopback Mode (Non-retimed Data)  
When the LOOPA signal is set HIGH, the RX serial data is  
directly buffered out to the transmit serial data. The data at the  
serial output is not retimed.  
Loop Timing Mode  
When the LOOPTIME signal is set HIGH, the TX PLL is  
bypassed and receive bit-rate clock is used for transmit side  
shifter.  
Reset Modes  
ALL logic circuits in the device can be reset using RESET and  
FIFO_RST signals. When RESET is set LOW, all logic circuits  
except FIFO are internally reset. When FIFO_RST is set LOW,  
the FIFO logic is reset.  
Power-down Mode  
CYS25G0101DX provides a global power-down signal  
PWRDN. When LOW, this signal powers down the entire  
device to a minimal power dissipation state. RESET and  
FIFO_RST signals should be asserted LOW along with  
PWRDN signal to ensure low power dissipation.  
LVPECL Compliance  
For systems using multiple or redundant connections, the LFI  
output can be used to select an alternate data stream. When  
an LFI indication is detected, external logic can toggle  
selection of the input device. When such a port switch takes  
place, it is necessary for the PLL to reacquire lock to the new  
serial stream.  
The CYS25G0101DX HSTL parallel I/O can be configured to  
LVPECL compliance with slight termination modifications. On  
the transmit side of the transceiver, the TXD[15:0] and TXCLKI  
can be made LVPECL compliant by setting VREF (reference  
voltage of a LVPECL signal) to VCC – 1.33V. To emulate an  
LVPECL signal on the receiver side, VDDQ needs to be set to  
3.3V and the transmission lines need to be terminated with the  
Thévenin equivalent of Zο at LVPECL ref. The signal is then  
attenuated using a series resistor at the driver end of the line  
to reduce the 3.3V swing level to an LVPECL swing level (see  
Figure 10). This circuit needs to be used on all 16 RXD[15:0]  
pins, TXCLKO, and RXCLK. The voltage divider has been  
calculated assuming the system is built with 50Ω transmission  
lines.  
External Filter  
The CDR circuit uses external capacitors for the PLL filter. A  
0.1-µF capacitor needs be connected between RXCN1 and  
RXCP1. Similarly a 0.1-µF capacitor needs to be connected  
between RXCN2 and RXCP2. The recommended packages  
and dielectric material for these capacitors are 0805 X7R or  
0603 X7R.  
Deserializer  
The CDR circuit extracts bits from the serial data stream and  
Document #: 38-02009 Rev. *J  
Page 6 of 15  
CYS25G0101DX  
Maximum Ratings  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
Power-up Requirements  
Power supply sequencing is not required if you are configuring  
VDDQ=3.3volts and all power supplies pins are connected to  
the same 3.3 volt power supply.  
Storage Temperature .................................–65°C to +150°C  
Ambient Temperature with  
Power Applied.............................................–55°C to +125°C  
Power supply sequencing is required if you are configuring  
VDDQ=1.5volts. Power must be applied in the following  
sequence: VCC (3.3) followed by VDDQ (1.5). Power supply  
ramping may occur simultaneously as long as the VCC/VDDQ  
relationship is maintained.  
VCC Supply Voltage to Ground Potential ....... –0.5V to +4.2V  
VDDQ Supply Voltage to Ground Potential ..... –0.5V to +4.2V  
DC Voltage Applied to HSTL Outputs  
in High-Z State .....................................–0.5V to VDDQ + 0.5V  
DC Voltage Applied to Other Outputs  
in High-Z State .......................................–0.5V to VCC + 0.5V  
Operating Range  
Output Current into LVTTL Outputs (LOW)..................30 mA  
Ambient  
Range  
Temperature  
VDDQ  
VCC  
DC Input Voltage....................................–0.5V to VCC + 0.5V  
Commercial 0°C to +70°C 1.4V to 1.6V[4] 3.3V ± 10%  
Static Discharge Voltage...........................................> 1100V  
(per MIL-STD-883, Method 3015)  
Industrial  
–40°C to +85°C 1.4V to 1.6V[4] 3.3V ± 10%  
Latch-up Current.....................................................> 200 mA  
Table 1. DC Specifications—LVTTL  
Parameter  
Description  
Test Conditions  
Min.  
2.4  
Max.  
Unit  
LVTTL Outputs  
VOHT  
Output HIGH Voltage  
Output LOW Voltage  
VCC = Min., IOH = –10.0 mA  
VCC = Min., IOL = 10.0 mA  
VOUT = 0V  
V
V
VOLT  
0.4  
IOS  
Output Short Circuit Current  
–20  
–90  
mA  
LVTTL Inputs  
VIHT  
Input HIGH Voltage  
Input LOW Voltage  
Input HIGH Current  
Input LOW Current  
Low = 2.1V, High = VCC + 0.5V  
Low = –3.0V, High = 0.8  
VCC = Max., VIN = VCC  
VCC = Max., VIN = 0V  
2.1  
VCC – 0.3  
0.8  
V
V
VILT  
–0.3  
IIHT  
50  
µA  
µA  
IILT  
–50  
Capacitance  
CIN  
Input Capacitance  
VCC = Max., @ f = 1 MHz  
5
pF  
Table 2. DC Specifications—Power  
Parameter  
Power  
ICC1  
Description  
Test Conditions  
Typ.  
Max.  
Unit  
Active Power Supply Current  
Standby Current  
300  
347  
5
mA  
mA  
ISB  
[5]  
Table 3. DC Specifications—Differential LVPECL Compatible Inputs (REFCLK)  
Parameter  
VINSGLE  
Description  
Input Single-ended Swing  
Input Differential Voltage  
Highest Input HIGH Voltage  
Lowest Input LOW Voltage  
Input HIGH Current  
Test Conditions  
Min.  
Max.  
Unit  
mV  
mV  
V
200  
400  
600  
1200  
VDIFFE  
VIEHH  
VIELL  
VCC – 1.2  
VCC – 2.0  
VCC – 0.3  
VCC – 1.45  
750  
V
IIEH  
VIN = VIEHH Max.  
VIN = VIELL Min.  
µA  
µA  
IIEL  
Input LOW Current  
–200  
Capacitance  
CINE  
Input Capacitance  
4
pF  
Note:  
5. See Figure 2 for differential waveform definition.  
Document #: 38-02009 Rev. *J  
Page 7 of 15  
CYS25G0101DX  
Table 4. DC Specifications—Differential CML[5]  
Parameter Description  
Transmitter CML-compatible Outputs  
Test Conditions  
Min.  
Max.  
Unit  
VOHC  
Output HIGH Voltage (VCC Referenced)  
100Ω differential load VCC – 0.5 VCC – 0.15  
100Ω differential load VCC – 1.2 VCC – 0.7  
V
V
VOLC  
Output LOW Voltage (VCC Referenced)  
Output Differential Swing  
VDIFFOC  
VSGLCO  
100Ω differential load  
100Ω differential load  
560  
280  
1600  
800  
mV  
mV  
Output Single-ended Voltage  
Receiver CML-compatible Inputs  
VINSGLC  
VDIFFC  
VICHH  
Input Single-ended Swing  
Input Differential Voltage  
Highest Input HIGH Voltage  
Lowest Input LOW Voltage  
25  
50  
1000  
2000  
VCC  
mV  
mV  
V
VICLL  
1.2  
V
V(+)  
VSGL  
V(-)  
VD  
VDIFF=V(+)-V(-)  
0.0V  
Figure 2. Differential Waveform Definition  
Test Conditions  
Table 5. DC Specifications—HSTL  
Parameter  
HSTL Outputs  
VOHH  
Description  
Min.  
VDDQ – 0.4  
Max.  
Unit  
Output HIGH Voltage  
Output LOW Voltage  
VCC = min., IOH= –4.0 mA  
V
V
VOLH  
VCC = min., IOL= 4.0 mA  
0.4  
IOSH  
Output Short Circuit Current  
VOUT = 0V  
100  
mA  
HSTL Inputs  
VIHH  
Input HIGH Voltage  
Input LOW Voltage  
Input HIGH Current  
Input LOW Current  
VREF + 0.13 VDDQ + 0.3  
V
V
VILH  
–0.3  
VREF – 0.1  
50  
IIHH  
VDDQ = max., VIN = VDDQ  
VDDQ = max., VIN = 0V  
µA  
µA  
IILH  
–40  
Capacitance  
CINH  
Input Capacitance  
VDDQ = max., @ f = 1 MHz  
5
pF  
Document #: 38-02009 Rev. *J  
Page 8 of 15  
CYS25G0101DX  
AC Waveforms  
V
3.0V  
ICHH  
3.0V  
2.0V  
0.8V  
2.0V  
0.8V  
80%  
80%  
20%  
V
= 1.4V  
< 1 ns  
V
= 1.4V  
th  
th  
20%  
< 150 ps  
GND  
V
ICLL  
< 150 ps  
< 1 ns  
(a) LVTTL Input Test Waveform  
(b) CML Input Test Waveform  
V
V
IHH  
IEHH  
80%  
80%  
80%  
20%  
80%  
20%  
V
= 0.75V  
< 1 ns  
V
= 0.75V  
th  
th  
20%  
< 1.0 ns  
20%  
< 1.0 ns  
V
V
IHL  
IELL  
< 1 ns  
(d) LVPECL Input Test Waveform  
(c) HSTL  
Input Test Waveform  
AC Test Loads  
1.5V  
3.3V  
R1  
R1  
R2  
OUTPUT  
OUTPUT  
R = 100Ω  
L
R1 = 100Ω  
R1 = 330Ω  
R2 = 510Ω  
L
C
R2 = 100Ω  
OUT+  
L
C
L
C ≤ 7 pF  
C ≤ 10 pF  
L
R
L
R2  
(Includes fixture and  
probe capacitance)  
OUT–  
(Includes fixture and  
probe capacitance)  
(c) HSTL  
AC Test Load  
(a) TTL AC Test Load  
(b) CML AC Test Load  
AC Specifications  
Table 6. AC Specifications—Parallel Interface  
Parameter  
Description  
Min.  
154.5  
6.38  
40  
Max.  
Unit  
tTS  
TXCLKI Frequency (must be frequency coherent to REFCLK)  
TXCLKI Period  
156.5  
6.47  
60  
MHz  
ns  
tTXCLKI  
tTXCLKID  
tTXCLKIR  
tTXCLKIF  
tTXDS  
TXCLKI Duty Cycle  
%
TXCLKi Rise Time  
0.3  
1.5  
ns  
TXCLKi Fall Time  
0.3  
1.5  
ns  
Write Data Set-up to ↑ of TXCLKI  
Write Data Hold from ↑ of TXCLKI  
TXCLKO Frequency  
1.5  
ns  
tTXDH  
0.5  
ns  
tTOS  
154.5  
6.38  
43  
156.5  
6.47  
57  
MHz  
ns  
tTXCLKO  
tTXCLKOD  
tTXCLKOR  
tTXCLKOF  
tRS  
TXCLKO Period  
TXCLKO Duty Cycle  
%
TXCLKO Rise Time  
0.3  
1.5  
ns  
TXCLKO Fall Time  
0.3  
1.5  
ns  
RXCLK Frequency  
154.5  
6.38  
43  
156.5  
6.47  
57  
MHz  
ns  
tRXCLK  
tRXCLKD  
tRXCLKR  
tRXCLKF  
tRXDS  
RXCLK Period  
RXCLK Duty Cycle  
RXCLK Rise Time[6]  
RXCLK Fall Time[6]  
%
0.3  
1.5  
ns  
0.3  
1.5  
ns  
Recovered Data Set-up with reference to ↑ of RXCLK  
Recovered Data Hold with reference to ↑ of RXCLK  
Valid Propagation Delay  
2.2  
ns  
tRXDH  
2.2  
ns  
tRXPD  
–1.0  
1.0  
ns  
Document #: 38-02009 Rev. *J  
Page 9 of 15  
CYS25G0101DX  
Table 7. AC Specifications—REFCLK[7]  
Parameter  
Description  
Min.  
154.5  
6.38  
35  
Max.  
156.5  
6.47  
65  
Unit  
MHz  
ns  
tREF  
REFCLK Input Frequency  
REFCLK Period  
tREFP  
tREFD  
tREFT  
tREFR  
tREFF  
REFCLK Duty Cycle  
%
REFCLK Frequency Tolerance — (relative to received serial data)[8]  
–100  
0.3  
+100  
1.5  
ppm  
ns  
REFCLK Rise Time  
REFCLK Fall Time  
0.3  
1.5  
ns  
Table 8. AC Specifications–CML Serial Outputs  
Parameter Description  
tRISE  
tFALL  
Min.  
60  
Typical  
Max.  
170  
Unit  
ps  
CML Output Rise Time (20–80%, 100Ω balanced load)  
CML Output Fall Time (80–20%, 100Ω balanced load)  
60  
170  
ps  
Table 9. Jitter Specifications  
Parameter  
Description  
Min. Typical[10] Max.[10]  
Unit  
UI  
tTJ-TXPLL  
tTJ-RXPLL  
Notes:  
Total Output Jitter for TX PLL (p-p)[9]  
0.03  
0.007  
0.035  
0.008  
0.04  
0.008  
0.05  
Total Output Jitter for TX PLL (rms)[9, 11]  
Total Output Jitter for RX CDR PLL (p-p)[9]  
Total Output Jitter for RX CDR PLL (rms)[9, 11]  
UI  
UI  
0.01  
UI  
6. RXCLk rise time and fall times are measured at the 20 to 80 percentile region of the rising and falling edge of the clock signal.  
7. The 155.52 MHz Reference Clock Phase Noise Limits for the CYS25G0101DX are illustrated in Figure 5.  
8. +20 ppm is required to meet the SONET output frequency specification.  
9. The RMS and P-to-P jitter values are measured using a 12-KHz to 20-MHz SONET filter.  
10. Typical values are measured at room temperature and the Max. values are measured at 0° C.  
11. This device passes the Bellcore specification from -10° C to 85° C.  
Document #: 38-02009 Rev. *J  
Page 10 of 15  
CYS25G0101DX  
Jitter Waveforms  
Figure 3. Jitter Transfer Waveform of CYS25G0101DX[12]  
Figure 4. Jitter Tolerance Waveform of CYS25G0101DX[12]  
Note:  
12. The bench jitter measurements were performed using an Agilent Omni-bert SONET jitter tester.  
Document #: 38-02009 Rev. *J  
Page 11 of 15  
CYS25G0101DX  
CYS25G0101DX Reference Clock Phase Noise Limits  
-75  
-85  
-95  
-105  
-115  
-125  
-135  
-145  
-155  
1,000  
10,000  
100,000  
1,000,000  
10,000,000  
100,000,000  
Frequency (Hz)  
Figure 5. CYS25G0101DX Reference Clock Phase Noise Limits  
Switching Waveforms  
Transmit Interface Timing  
tTXCLKI  
tTXCLKIDH  
tTXCLKIDL  
TXCLKI  
tTXDS tTXDH  
TXD[15:0]  
tTXCLKO  
tTXCLKODL  
tTXCLKODH  
TXCLKO  
Receive Interface Timing  
tRXCLK  
tRXCLKDL  
tRXCLKDH  
RXCLK  
tRXPD  
tRXDS  
tRXDH  
RXD[15:0]  
Document #: 38-02009 Rev. *J  
Page 12 of 15  
CYS25G0101DX  
Typical I/O Terminations  
CYS25G0101DX  
Limiting Amp  
µF  
0.1  
Ω
Zo=50  
IN+  
OUT+  
Ω
100  
OUT–  
IN–  
Ω
Zo=50  
0.1 µF  
Figure 6. Serial Input Termination  
Optical Module  
CYS25G0101DX  
µF  
0.1  
Ω
Zo=50  
IN+  
OUT+  
Ω
100  
OUT–  
IN–  
Ω
Zo=50  
0.1 µF  
Figure 7. Serial Output Termination[13]  
CYS25G0101DX  
FRAMER  
VDDQ=1.5V  
HSTL  
INPUT  
HSTL  
OUTPU  
T
Ω
Ω
Zo=50  
100  
Ω
100  
Figure 8. TXCLKO/ RXCLK Termination  
CYS25G0101DX  
FRAMER  
HSTL  
INPUT  
HSTL  
OUTPU  
T
Ω
Zo=50  
Figure 9. RXD[15:0] Termination  
VDDQ=3.3V  
FRAMER  
VDDQ=3.3V  
RXD[15;0],  
RXCLK,  
TXCLKO  
Ω
137  
Ω
Ω
80.6  
Zo=50  
LVPECL INPUT  
OUTPUT  
Ω
121  
CYS25G0101DX  
Clock Oscillator  
Figure 10. LVPECL-compliant Output Termination  
CYS25G0101DX  
VCC  
Ω
Zo=50  
0.1uF  
Ω
130  
VCC  
130  
LVPEC L  
OUTPUT  
Ω
82  
Ω
RefclockInter nall y  
Biased  
Ω
Ω
0.1uF  
Zo=50  
82  
Figure 11. AC-Coupled Clock Oscillator Termination  
Note:  
13. Serial output of CYS25G0101DX is source matched to 50Ω transmission lines (100Ω differential transmission lines).  
Document #: 38-02009 Rev. *J  
Page 13 of 15  
CYS25G0101DX  
Clock Oscillator  
CYS25G0101DX  
VCC  
Ω
Ω
Zo=50  
Zo=50  
Ω
130  
VCC  
LVPEC L  
OUTPUT  
Ω
82  
Ω
130  
Reference Cloc k Input  
Ω
82  
Figure 12. Clock Oscillator Termination  
Ordering Information  
Speed  
Standard  
Ordering Code  
Package Name  
AT120  
Package Type  
Operating Range  
Commercial  
Industrial  
CYS25G0101DX-ATC  
CYS25G0101DX-ATI  
120-pin TQFP  
120-pin TQFP  
Standard  
AT120  
Package Diagram  
120-pin Thin Quad Flatpack (14 × 14 × 1.4 mm) with Heat Slug AT120  
51-85116-**  
All product and company names mentioned in this document are the trademarks of their respective holders.  
Document #: 38-02009 Rev. *J  
Page 14 of 15  
© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize  
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.  
CYS25G0101DX  
Document History Page  
Document Title: CYS25G0101DX SONET OC-48 Transceiver  
Document Number: 38-02009  
Orig. of  
REV.  
**  
ECN NO. Issue Date Change  
Description of Change  
105847  
108024  
111834  
03/22/01  
06/20/01  
12/18/01  
SZV  
AMV  
CGX  
Change from Spec number: 38-00894 to 38-02009.  
Changed Marketing part number.  
*A  
*B  
Updated power specification in features and DC specs section. Changed  
pinout to be compatible with CYS25G0102DX in pin diagram and descrip-  
tions. Verbiage added or changed for clarity in pin descriptions section.  
Changed input sensitivity in Receive Data Path section, page 6. RXCLK rise  
time corrected to 0.3 nSec min. CML and LVPECL input waveforms updated  
intest loadand waveform section. Diagrams replacedforclarity Figures 1-10.  
Added two Refclock diagrams Figures 9 and 10.  
*C  
*D  
112712  
113791  
02/06/02  
04/24/02  
TME  
CGX  
Updated temperature range, static discharge voltage, and max total RMS  
jitter.  
Updated the single ended swing and differential swing voltage for Receiver  
CML compatible inputs. Created a separate table showing peak to peak and  
RMS jitter for both TX PLL and RX PLL.  
*E  
*F  
115940  
117906  
05/22/02  
09/06/02  
TME  
CGX  
Added Industrial temperature spec to pages 8, 11, and 15.  
Added differential waveform definition.  
Added BGA pinout and package information.  
Changed LVTTL VIHT min. from 2.0 to 2.1 volts.  
*G  
119267  
10/17/02  
CGX  
Added phase noise limits data.  
Removed BGA pinout and package information.  
Removed references to CYS25G0102DX.  
*H  
*I  
121019  
122319  
124438  
11/06/02  
12/30/02  
02/13/03  
CGX  
RBI  
Removed “Preliminary” from data-sheet  
Add power up requirements to Maximum Ratings information  
Revised power up requirements  
*J  
WAI  
Document #: 38-02009 Rev. *J  
Page 15 of 15  
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