找货询价

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

QQ咨询

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

技术支持

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

售后咨询

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

HYS72V128320GR-8-C2

型号:

HYS72V128320GR-8-C2

品牌:

INFINEON[ Infineon ]

页数:

19 页

PDF大小:

289 K

HYS 72Vx3xxGR-8  
PC100 Registered SDRAM-Modules  
3.3 V 168-pin Registered SDRAM Modules  
256 MB, 512 MB & 1 GB Densities  
168-pin JEDEC Standard, Registered 8 Byte  
Dual-In-Line SDRAM Modules for Server  
main memory applications using memory  
frequencies up to 100MHz  
Programmable CAS Latency, Burst Length,  
and Wrap Sequence (Sequential &  
Interleave)  
Auto Refresh (CBR) and Self Refresh  
All inputs and outputs are LVTTL compatible  
Serial Presence Detect with E2PROM  
One bank 32M × 72 and 64M × 72  
organization, two bank 128M × 72  
organization  
Optimized for ECC applications with very low  
input capacitances  
Utilizes SDRAMs in TSOPII-54 packages  
with registers and PLL.The two bank module  
uses stacked TSOP54 packages.  
Programmed Latencies:  
Card Size: 133.35 mm × 43.18 mm with  
Gold contact pads (JEDEC MO-161)  
CL tRCD  
tRP  
2
2
2
These Registered DIMM modules support  
operation in “registered” and “buffered” mode  
Single + 3.3 V (± 0.3 V) power supply  
Performance:  
-8  
registered buffered  
Unit  
Operation mode  
fCK  
tCK  
tAC  
Clock Frequency (max.)  
Clock Cycle Time (min.)  
Clock Access Time (max.)  
100  
10  
6
66  
15  
6
MHz  
ns  
ns  
The HYS 72Vx3xxGR-8 family are industry standard 168-pin 8-byte Dual in-line Memory Modules  
(DIMMs) which are organized as 32M × 72, 64M × 72 & 128M × 72 high speed memory arrays  
designed with Synchronous DRAMs (SDRAMs) for ECC applications. All control and address  
signals are registered on-DIMM and the design incorporates a PLL circuit for the Clock inputs. Use  
of an on-board register reduces capacitive loading on the input signals but are delayed by one cycle  
in arriving at the SDRAM devices. Decoupling capacitors are mounted on the PC board. The DIMMs  
use a serial presence detects scheme implemented via a serial E2PROM using the 2-pin I2C  
protocol. The first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes are  
available to the end user. All Infineon 168-pin DIMMs provide a high performance, flexible 8-byte  
interface in a 133.35 mm long footprint. The PCB layout is based on latest industry PC133/PC100  
standard gerber files. Besides standard PC100 applications, this module family is intended for  
applications where Registered DIMM modules are used in “buffered mode” at a 67 MHz memory  
bus speed.  
INFINEON Technologies  
1
9.01  
HYS 72Vx3xxGR-8  
PC100 Registered SDRAM-Modules  
Ordering Information  
Type  
Compliance  
Code  
Description  
SDRAM Components  
HYS 72V32301GR-8  
HYS 72V64300GR-8  
HYS 72V128320GR-8  
PC100-222-622R one bank 256 MB 128 MBit (x4)  
Reg. DIMM HYB39S128400CT-7.5  
with trp<= 15ns  
PC100-222-622R one bank 512 MB 256 MBit (x4)  
Reg. DIMM HYB39S256400CT-7.5  
with trp<= 15ns  
PC100-222-622R two bank 1 GByte 256 MBit (x4 stacked)  
Reg. DIMM  
HYB39S256400CT-7.5  
with trp<= 15ns  
Note: All part numbers end with a place code (not shown), designating the die revision. Consult  
factory for current revisions. Example: HYS 72V64300GR-8-C2, indicating Rev. C2 dies are  
used for SDRAM components.  
INFINEON Technologies  
2
9.01  
HYS 72Vx3xxGR-8  
PC100 Registered SDRAM-Modules  
Pin Definitions and Functions  
A0 - A11, A12 Address Inputs  
DQMB0 - DQMB7 Data Mask  
BA0, BA1  
Bank Selects  
CS0 - CS3  
REGE *)  
Chip Select  
DQ0 - DQ63 Data Input/Output  
Register Enable  
Hor N.C = registered mode  
L= buffered mode  
CB0 - CB7  
RAS  
Check Bits (x72 organization only) VDD  
Power (+ 3.3 V)  
Ground  
Row Address Strobe  
Column Address Strobe  
Read/Write Input  
VSS  
SCL  
SDA  
N.C.  
CAS  
Clock for Presence Detect  
Serial Data Out  
No Connection  
WE  
CKE0  
Clock Enable  
CLK0 - CLK3 Clock Input  
*) note : both operation modes are supported by this module family  
Address Format  
Density Organization Memory SDRAMs # of  
# of row/bank/ Refresh Period Interval  
Banks  
SDRAMs columns bits  
256 MB 32M × 72  
512 MB 64M × 72  
1
1
2
32M × 4  
64M × 4  
64M × 4  
18  
18  
36  
12/2/11  
13/2/11  
13/2/11  
4k  
8k  
8k  
64 ms 15.6 µs  
64 ms 7.8 µs  
64 ms 7.8 µs  
1 GB  
128M × 72  
Pin Configuration  
PIN# Symbol  
PIN# Symbol  
PIN# Symbol  
PIN# Symbol  
1
VSS  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
VSS  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
95  
96  
97  
VSS  
127  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
139  
VSS  
2
DQ0  
DQ1  
DQ2  
DQ3  
VDD  
DU  
DQ32  
DQ33  
DQ34  
DQ35  
VDD  
CKE0  
CS3  
3
CS2  
DQMB2  
DQMB3  
DU  
4
DQMB6  
DQMB7  
N.C.  
5
6
7
DQ4  
DQ5  
DQ6  
DQ7  
DQ8  
VSS  
VDD  
DQ36  
DQ37  
DQ38  
DQ39  
DQ40  
VSS  
VDD  
8
N.C.  
N.C.  
CB2  
CB3  
VSS  
N.C.  
9
N.C.  
10  
11  
12  
13  
CB6  
CB7  
VSS  
DQ9  
DQ16  
DQ41  
DQ48  
INFINEON Technologies  
3
9.01  
HYS 72Vx3xxGR-8  
PC100 Registered SDRAM-Modules  
Pin Configuration (contd)  
PIN# Symbol PIN# Symbol  
PIN# Symbol  
PIN# Symbol  
14  
DQ10  
DQ11  
DQ12  
DQ13  
VDD  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
DQ17  
DQ18  
DQ19  
VDD  
98  
DQ42  
DQ43  
DQ44  
DQ45  
VDD  
140  
141  
142  
143  
144  
145  
146  
147  
148  
149  
150  
151  
152  
153  
154  
155  
156  
157  
158  
159  
160  
161  
162  
163  
164  
165  
166  
167  
168  
DQ49  
DQ50  
DQ51  
VDD  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
99  
100  
101  
102  
103  
104  
105  
106  
107  
108  
109  
110  
111  
112  
113  
114  
115  
116  
117  
118  
119  
120  
121  
122  
123  
124  
125  
126  
DQ20  
N.C.  
DQ52  
N.C.  
DQ14  
DQ15  
CB0  
CB1  
VSS  
DQ46  
DQ47  
CB4  
CB5  
VSS  
DU  
DU  
N.C.  
REGE  
VSS  
VSS  
DQ21  
DQ22  
DQ23  
VSS  
DQ53  
DQ54  
DQ55  
VSS  
N.C.  
N.C.  
VDD  
N.C.  
N.C.  
VDD  
WE  
DQ24  
DQ25  
DQ26  
DQ27  
VDD  
CAS  
DQMB4  
DQMB5  
CS1  
RAS  
VSS  
DQ56  
DQ57  
DQ58  
DQ59  
VDD  
DQMB0  
DQMB1  
CS0  
DU  
VSS  
DQ28  
DQ29  
DQ30  
DQ31  
VSS  
DQ60  
DQ61  
DQ62  
DQ63  
VSS  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
CLK2  
N.C.  
A9  
CLK3  
N.C.  
A10 (AP)  
BA1  
VDD  
BA0  
A11  
WP  
SA0  
SDA  
SCL  
VDD  
SA1  
VDD  
CLK1  
A12  
SA2  
CLK0  
VDD  
VDD  
INFINEON Technologies  
4
9.01  
HYS 72Vx3xxGR-8  
PC100 Registered SDRAM-Modules  
RCS0  
RDQMB0  
RDQMB4  
DQM  
CS  
DQM  
CS  
DQ0-DQ3  
DQ4-DQ7  
DQ32-DQ35  
DQ0-DQ3  
DQ0-DQ3  
D0  
D8  
DQM  
CS  
DQM  
CS  
DQ36-DQ39  
DQ0-DQ3  
DQ0-DQ3  
D1  
D9  
RDQMB1  
RDQMB5  
DQM  
CS  
DQM  
CS  
DQ8-DQ11  
DQ40-DQ43  
DQ0-DQ3  
DQ0-DQ3  
D2  
D10  
DQM  
CS  
DQM  
CS  
DQ12-DQ15  
CB0-CB3  
DQ44-DQ47  
CB4-CB7  
DQ0-DQ3  
DQ0-DQ3  
D3  
D11  
DQM  
CS  
DQM  
CS  
DQ0-DQ3  
D17  
DQ0-DQ3  
D16  
RCS2  
RDQMB2  
RDQMB6  
DQM  
CS  
DQ0-DQ3  
DQM  
DQ0-DQ3  
D12  
CS  
DQ16-DQ19  
DQ20-DQ23  
DQ48-DQ51  
D4  
DQM  
DQ0-DQ3  
CS  
DQM  
DQ0-DQ3  
D13  
CS  
DQ52-DQ55  
D5  
RDQMB3  
RDQMB7  
DQM  
DQ0-DQ3  
CS  
DQM  
DQ0-DQ3  
D14  
CS  
DQ24-DQ27  
DQ56-DQ59  
D6  
DQM  
CS  
DQ0-DQ3  
DQM  
CS  
DQ0-DQ3  
D15  
DQ28-DQ31  
DQ60-DQ63  
D7  
E2PROM  
(256 word x 8 Bit)  
CLK0  
12 pF  
PLL  
SDRAMs D0-D17  
CLK1, CLK2, CLK3  
SA0  
SA1  
SA2  
SCL  
SA0  
SA1 SDA  
SA2  
SCL  
12 pF  
CS0/CS2  
DQMB0-7  
BA0, BA1  
A0-A11, A12* )  
RAS  
CAS  
CKE0  
WE  
RCS0/RCS2  
WP  
RDQMB0-7  
RBA0, RBA1  
RA0-RA11  
RRAS  
RCAS  
RCKE0  
SDRAMs D0-D17  
47 k  
SDRAMs D0-D17  
SDRAMs D0-D17  
SDRAMs D0-D17  
SDRAMs D0-D17  
SDRAMs D0-D17  
VCC  
VSS  
D0-D17, Reg., DLL  
D0-D17, Reg., DLL  
C
RWE  
REGE  
10 k  
1) DQ wirding may differ from that decribed  
*) A12 is only used for  
128 M x 72 organisation  
VCC  
in this drawing; however DQ/DQB relationship  
must be maintained as shown  
2) All resistors are 10  
unless otherwise noted  
SPB04131  
Block Diagram: One Bank 32M x 72 & 64M x 72 SDRAM DIMM Modules  
HYS72V32301 and HYS 72V64300GR Using x4 Organized SDRAMs  
INFINEON Technologies  
5
9.01  
HYS 72Vx3xxGR-8  
PC100 Registered SDRAM-Modules  
RCS0  
RCS1  
RDQMB0  
RDQMB4  
DQM  
CS DQM  
CS  
DQM  
CS DQM  
CS  
DQ0-DQ3  
DQ4-DQ7  
DQ32-DQ35  
DQ0-DQ3  
DQ0-DQ3  
DQ0-DQ3  
DQ0-DQ3  
D0  
CS DQM  
D0  
CS  
D8  
CS DQM  
D8  
CS  
DQM  
DQM  
DQ36-DQ39  
DQ0-DQ3 DQ0-DQ3  
DQ0-DQ3 DQ0-DQ3  
D1  
D1  
D9  
D9  
RDQMB1  
RDQMB5  
DQM  
DQ0-DQ3  
CS DQM  
DQ0-DQ3  
CS  
DQM  
DQ0-DQ3  
D10  
CS DQM  
CS  
DQ8-DQ11  
DQ40-DQ43  
DQ0-DQ3  
D2  
D2  
D10  
DQM  
DQ0-DQ3  
CS DQM  
DQ0-DQ3  
CS  
DQM  
DQ0-DQ3  
D11  
CS DQM  
CS  
DQ12-DQ15  
CB0-CB3  
DQ44-DQ47  
CB4-CB7  
DQ0-DQ3  
D3  
D3  
D11  
DQM  
CS DQM  
CS  
DQM  
CS DQM  
DQ0-DQ3  
D17  
CS  
DQ0-DQ3 DQ0-DQ3  
DQ0-DQ3  
D16  
D16  
D17  
RCS2  
RCS3  
RDQMB2  
RDQMB6  
DQM  
DQ0-DQ3  
CS DQM  
CS  
DQM  
DQ0-DQ3  
D12  
CS DQM  
CS  
DQ16-DQ19  
DQ48-DQ51  
DQ0-DQ3  
DQ0-DQ3  
D4  
D4  
D12  
DQM  
DQ0-DQ3  
CS DQM  
DQ0-DQ3  
CS  
DQM  
DQ0-DQ3  
D13  
CS DQM  
CS  
DQ20-DQ23  
DQ52-DQ55  
DQ0-DQ3  
D5  
D5  
D13  
RDQMB3  
RDQMB7  
DQM  
DQ0-DQ3  
CS DQM  
DQ0-DQ3  
CS  
DQM  
DQ0-DQ3  
D14  
CS DQM  
CS  
DQ24-DQ27  
DQ56-DQ59  
DQ0-DQ3  
D6  
D6  
D14  
DQM  
DQ0-DQ3  
CS DQM  
DQ0-DQ3  
CS  
DQM  
DQ0-DQ3  
D15  
CS DQM  
CS  
DQ28-DQ31  
DQ61-DQ63  
DQ0-DQ3  
D7  
D7  
D15  
E2PROM  
(256 word x 8 Bit)  
CLK0  
12 pF  
PLL  
Stacked SDRAMs D0-D17  
CLK1, CLK2, CLK3  
SA0  
SA1  
SA2  
SCL  
SA0  
SA1 SDA  
SA2  
SCL  
12 pF  
CS0-CS3  
DQMB0-7  
BA0, BA1  
A0-A11, A12* )  
RAS  
CAS  
CKE0  
WE  
RCS0-RCS3  
WP  
RDQMB0-7  
RBA0, RBA1  
RA0-RA11  
RRAS  
RCAS  
RCKE0  
Stacked SDRAMs D0-D17  
Stacked SDRAMs D0-D17  
Stacked SDRAMs D0-D17  
Stacked SDRAMs D0-D17  
Stacked SDRAMs D0-D17  
Stacked SDRAMs D0-D17  
47 k  
VCC  
VSS  
D0-D17, Reg. DLL  
D0-D17, Reg. DLL  
C
RWE  
REGE  
1.) DQ wirding may differ from that decribed  
*) A12 is only used for  
128 M x 72 organisation  
10 k  
in this drawing; however DQ/DQB relationship  
must be maintained as shown  
VCC  
2.) All resistors are 10  
unless otherwise noted  
SPB04132  
Block Diagram: Two Bank 128M x 72 SDRAM DIMM Modules  
HYS 72V128320GR Using Stacked x4 Organized SDRAMs  
INFINEON Technologies  
6
9.01  
HYS 72Vx3xxGR-8  
PC100 Registered SDRAM-Modules  
Absolute Maximum Ratings  
Parameter  
Symbol  
Limit Values  
max.  
Unit  
min.  
VIN, VOUT 1.0  
Input / Output voltage relative to VSS  
Power supply voltage on VDD to VSS  
Storage temperature range  
V
4.6  
VDD  
TSTG  
PD  
1.0  
4.6  
+150  
1
V
-55  
oC  
W
mA  
Power dissipation (per SDRAM component)  
Data out current (short circuit)  
IOS  
50  
Permanent device damage may occur if Absolute Maximum Ratingsare exceeded.  
Functional operation should be restricted to recommended operation conditions.  
Exposure to higher than recommended voltage for extended periods of time affect device reliability  
DC Characteristics  
TA = 0 to 70 °C 1); VSS = 0 V; VDD = 3.3 V ± 0.3 V  
Parameter  
Symbol  
Limit Values  
max.  
Unit  
min.  
2.0  
Input High Voltage  
VIH  
VIL  
V
DD + 0.3  
V
Input Low Voltage  
0.5  
2.4  
0.8  
V
Output High Voltage (IOUT = 4.0 mA)  
Output Low Voltage (IOUT = 4.0 mA)  
VOH  
VOL  
II(L)  
V
0.4  
10  
V
Input Leakage Current, any input  
10  
µA  
(0 V < VIN < 3.6 V, all other inputs = 0 V)  
Output Leakage Current  
IO(L)  
10  
10  
µA  
(DQ is disabled, 0 V < VOUT < VDD  
)
Capacitance  
TA = 0 to 70 °C 1); VDD = 3.3 V ± 0.3 V, f = 1 MHz  
Parameter  
Symbol  
Limit Values  
Unit  
One Bank Two Bank  
Modules Modules  
Input Capacitance  
CIN  
10  
20  
pF  
(all inputs except CLK and CKE)  
Input Capacitance (CLK)  
Input Capacitance (CKE)  
CCLK  
CCKE  
CIO  
30  
17  
10  
8
30  
30  
17  
8
pF  
pF  
pF  
pF  
pF  
Input/Output Capacitance (DQ0 - DQ63, CB0 - CB7)  
Input Capacitance (SCL, SA0 - 2)  
CSC  
CSD  
Input/Output Capacitance (SDA)  
8
8
INFINEON Technologies  
7
9.01  
HYS 72Vx3xxGR-8  
PC100 Registered SDRAM-Modules  
Operating Currents per SDRAM component  
TA = 0 to 70 °C 1), VDD = 3.3 V ± 0.3 V  
(Recommended Operating Conditions unless otherwise noted)  
Test  
Condition  
Symbol 128Mb  
max.  
256Mb  
max.  
210  
Unit  
Note  
Parameter  
2)  
Operating current  
ICC1  
150  
tRC = tRC(MIN.), tCK = tCK(MIN.)  
Outputs open, Burst  
mA  
Length = 4, CL = 3. All banks  
operated in random access,  
all banks operated in ping-  
pong manner to maximize  
gapless data access  
2)  
Precharge stand-by current  
in Power Down Mode  
tCK = min. ICC2P  
2
2
mA  
CS = VIH(MIN.), CKE VIL(MAX.)  
2)  
No operating current  
CKE ≥  
VIH(MIN.)  
ICC3N  
ICC3P  
ICC4  
45  
10  
90  
45  
mA  
mA  
mA  
tCK = min., CS = VIH(MIN.),  
2)  
CKE ≤  
VIL(MAX.)  
10  
active state (max. 4 banks)  
2), 3)  
Burst operating current  
120  
tCK = min.,  
Read command cycling  
2)  
2)  
Auto refresh current  
ICC5  
210  
1.5  
240  
2.5  
mA  
mA  
tCK = min.,  
Auto Refresh command cycling  
Self refresh current  
Self Refresh Mode,  
CKE = 0.2 V  
ICC6  
INFINEON Technologies  
8
9.01  
HYS 72Vx3xxGR-8  
PC100 Registered SDRAM-Modules  
4), 5)  
AC Characteristics (SDRAM Device Specification)  
TA = 0 to 70 °C 1); VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns  
Parameter  
Symbol Limit Values Unit Note  
min.  
max.  
Clock and Access Times  
8)  
Clock Cycle Time  
CAS Latency = 3  
CAS Latency = 2  
tCK  
fCK  
tAC  
10  
10  
ns  
ns  
Clock Frequency  
CAS Latency = 3  
CAS Latency = 2  
8)  
100  
100  
MHz  
MHz  
Access Time from Clock  
CAS Latency = 3  
6
6
ns  
ns  
CAS Latency = 2  
Clock High Pulse Width  
Clock Low Pulse Width  
Transition Time  
tCH  
tCL  
tT  
3
ns  
ns  
ns  
3
0.5  
10  
Setup and Hold Parameters  
Input Setup Time  
tIS  
2
ns  
Input Hold Time  
tIH  
1
ns  
Power Down Mode Entry Time  
Power Down Mode Exit Setup Time  
Mode Register Set-up Time  
Transition Time  
tSB  
tPDE  
tRSC  
tT  
1
CLK  
CLK  
CLK  
ns  
1
2
0.5  
10  
Common Parameters  
Row to Column Delay Time  
Row Precharge Time  
tRCD  
tRP  
tRAS  
tRC  
tRRD  
tCCD  
20  
15  
50  
70  
2
ns  
ns  
8)  
Row Active Time  
100k ns  
Row Cycle Time  
ns  
Activate (a) to Activate (b) Command Period  
CAS(a) to CAS(b) Command Period  
CLK  
CLK  
1
INFINEON Technologies  
9
9.01  
HYS 72Vx3xxGR-8  
PC100 Registered SDRAM-Modules  
AC Characteristics (SDRAM Device Specification) (contd) 4), 5)  
TA = 0 to 70 °C 1); VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns  
Parameter  
Symbol Limit Values Unit Note  
min.  
max.  
Refresh Cycle  
Refresh Period (128 Mb components)  
Refresh Period (256 Mb components)  
Self Refresh Exit Time  
tREF  
tREF  
tSREX  
1
15.6  
7.8  
µs  
µs  
6)  
CLK  
Read Cycle  
Data Out Hold Time  
tOH  
tLZ  
3
0
3
8
2
ns  
7)  
Data Out to Low Impedance  
Data Out to High Impedance  
DQM Data Out Disable Latency  
ns  
7)  
tHZ  
ns  
tDQZ  
CLK  
Write Cycle  
8)  
Data Input to Precharge  
(write recovery)  
tWR  
2
0
CLK  
CLK  
DQM Write Mask Latency  
tDQW  
INFINEON Technologies  
10  
9.01  
HYS 72Vx3xxGR-8  
PC100 Registered SDRAM-Modules  
Notes  
1. The registered DIMM modules are designed to operate under system operating conditions between 0-55 deg  
C ambient, 500 MB/sec sustained bandwidth and 0 LFM airflow. Operating at higher ambient temperatures  
needs sufficient air flow to limit the case temperature of the SDRAM components do not exceed 85oC.  
Maximum operation frequency of this module family is 100MHz when operating in registered modeand 67  
MHz when in buffered mode”  
2. These parameters depend on the cycle rate. All values are measured at 100MHz operation frequency. Input  
signals are changed once during tck excepts for Icc6 and for standby currents when tck = infinity.  
3. These parameters are measured with continous data stream during read access and all DQ toggling. CL=3 and  
BL=4 is assumed and the data-out current is excluded.  
4. An initial pause of 100 µs is required after power-up. Then a Precharge All Banks command must be given  
followed by eight Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin. Also the on-  
DIMM PLL must be given enough clock cycles to stabilize before any operation can be guaranteed.  
5. AC timing tests have VIL = 0.8 V and VIH = 2.0 V with the timing referenced to the 1.4 V crossover point. The  
transition time is measured between VIH and VIL. All AC measurements assume tT = 1 ns with the AC output  
load circuit shown. Specified tAC and tOH parameters are measured with a 50 pF only, without any resistive  
termination and with a input signal of 1 V/ns edge rate between 0.8 V and 2.0 V.  
6. Self Refresh Exit is a synchronous operation and begins on the second positive clock edge after CKE returns  
high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied after the Self Refresh Exit  
command is registered.  
7. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels.  
8. This module family uses SDRAM components with a write recovery time twr (sometimes also named tdpl) of  
two clocks and a trp (precharge time) of <=15 ns to achieve proper operation in buffered modeat a  
operation frequency of 67 MHz.  
tCH  
2.4 V  
0.4 V  
1.4 V  
CLOCK  
tT  
tCL  
tIH  
tIS  
INPUT  
1.4 V  
tAC  
tAC  
tLZ  
tOH  
I/O  
50 pF  
OUTPUT  
1.4 V  
Measurement conditions for  
AC and tOH  
tHZ  
t
IO.vsd  
Serial Presence Detect  
A serial presence detect storage device - E2PROM 34C02 - is assembled onto the module.  
Information about the module configuration, speed, etc. is written into the E2PROM device during  
module production using a serial presence detect protocol (I2C synchronous 2-wire bus)  
INFINEON Technologies  
11  
9.01  
HYS 72Vx3xxGR-8  
PC100 Registered SDRAM-Modules  
SPD-Table for Registered DIMM Modules  
Byte# Description  
SPD Entry Value  
Hex  
0
1
2
3
Number of SPD Bytes  
Total Bytes in Serial PD  
Memory Type  
128  
80  
08  
04  
0D  
256  
SDRAM  
12/13  
Number of Row Addresses  
(without BS bits)  
0C  
0D  
4
Number of Column Addresses  
Number of DIMM Banks  
Module Data Width  
Module Data Width (contd)  
Module Interface Levels  
Cycle Time at CL = 3  
11  
0B  
01  
0B  
01  
48  
00  
01  
A0  
60  
02  
82  
0B  
02  
5
1
6
7
72  
0
8
LVTTL  
10.0 ns  
6.0 ns  
ECC  
9
10  
11  
12  
Access Time from Clock at CL = 3  
DIMM Config (Error Det/Corr.)  
Refresh Rate/Type  
Self-Refresh,  
80  
82  
15.6 / 7.8 µs  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
SDRAM Width, Primary  
x4  
04  
04  
01  
0F  
04  
06  
01  
01  
1F  
0E  
A0  
60  
Error Checking SDRAM Data Width  
Minimum tCCD  
Burst Length Supported  
Number of SDRAM Banks  
SDRAM Supported CAS Latencies  
SDRAM CS Latencies  
x4  
1 CLK  
1, 2, 4, 8  
4
2 & 3  
0
SDRAM WE Latencies  
0
SDRAM DIMM Module Attributes  
SDRAM Device Attributes  
Min. Clock Cycle Time at CL = 2  
registered/buffered  
V
DD tol +/10%  
10 ns  
Max. Data Access Time from Clock for 6 ns  
CL = 2  
25  
26  
Min. Clock Cycle Time at CL = 1  
not supp.  
00  
00  
Max. Data Access Time from Clock at not supp.  
CL = 1  
27  
28  
29  
30  
31  
32  
33  
SDRAM Minimum tRP  
15 ns  
0F  
14  
14  
32  
80  
20  
10  
SDRAM Minimum tRRD  
SDRAM Minimum tRCD  
SDRAM Minimum tRAS  
Module Bank Density (per bank)  
SDRAM Input Setup Time  
SDRAM Input Hold Time  
20 ns  
20 ns  
50 ns  
256/ 512 MByte  
2 ns  
40  
80  
1 ns  
INFINEON Technologies  
12  
9.01  
HYS 72Vx3xxGR-8  
PC100 Registered SDRAM-Modules  
SPD-Table for Registered DIMM Modules (contd)  
Byte# Description  
SPD Entry Value  
Hex  
34  
35  
SDRAM Data Input Setup Time  
SDRAM Data Input Hold Time  
2 ns  
1 ns  
20  
10  
00  
36-61 Superset Information (may be used in  
future)  
62  
63  
SPD Revision  
Checksum for Bytes  
0 - 62  
1.2  
12  
DB  
1E  
1F  
64-125 Manufacturers Information  
XX  
64  
8F  
FF  
126  
Frequency Specification  
Details of Clocks  
100MHz  
127  
128+  
Unused Storage Locations  
INFINEON Technologies  
13  
9.01  
HYS 72Vx3xxGR-8  
PC100 Registered SDRAM-Modules  
Package Outlines  
Module Package  
JEDEC MO-161  
256 & 512 MByte Registered Module based  
on x4 organised SDRAMs  
133.35  
127.35  
4 max.  
Register  
Register  
41  
PLL  
3
1
10  
11  
6.35  
40  
84  
1.27±  
0.1  
3
6.35  
1.27  
42.18  
66.68  
2
85 94  
95  
124 125  
168  
Register  
Detail of Contacts  
1+0.5  
L-DIM-168-37  
1.27  
note: all tolerances are in accordance with the JEDEC standard  
INFINEON Technologies  
14  
9.01  
HYS 72Vx3xxGR-8  
PC100 Registered SDRAM-Modules  
Module Package  
JEDEC MO-161  
1 GByte Registered DIMM Module with Stacked x4 SDRAMs  
133.35  
127.35  
6.8 max.  
Register Register  
PLL  
1
10  
11  
6.35  
40  
41  
6.35  
84  
1.27±  
0.1  
3
1.27  
42.18  
66.68  
2
85 94  
95  
124 125  
168  
Register  
Detail of Contacts  
1+0.5  
L-DIM-168-37-S  
1.27  
note: all tolerances are in accordance with the JEDEC standard  
INFINEON Technologies  
15  
9.01  
HYS 72Vx3xxGR-8  
PC100 Registered SDRAM-Modules  
Functional Description  
These Registered DIMMs achieve high speed data transfer rate up to 100 MHz, when in registered  
modeand up to 67 MHz when in buffered mode. The registered modeis achieved when the  
REGE input signal is in highstate or the pin is not connected. Operation in buffered mode(REGE  
= low) needs careful system design to compensate all input signals for the extra delay time of the  
register components when in buffered mode. Buffered modeis limited to 67 Mhz operation.  
Registered Mode:  
All control and address signals are synchronized with the positive edge of externally supplied clocks  
and are registered on-DIMM and hence delayed by one clock cycle in arriving at the SDRAM  
devices. The use of the on-board register reduces the capacitive loading of the DIMM on input  
control and address signals. The SDRAM device data lines (DQ) are connected directly to the DIMM  
tabs through 10 Ohm series resistors. All the following timing diagrams and explanations show  
DIMM operation at the tabs, not SDRAM operation.  
The picture below depicts an overview of the effect of the Registered Mode on the data outputs  
(DQs) for a Read operation. Without the registers, the data is delayed according to the device CAS  
latency, in the case two clocks. With the register, the data is delayed according to the device CAS  
latency plus an additional clock cycle. This is known as the DIMM CAS latency, and in this example  
is four three. The data path can be thought of as a pipeline in which the register effectively lengthens  
the pipe by one clock cycle.  
Registered DIMM Burst Read Operation (BL = 4)  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
CLK  
Command  
Read A  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
Device  
CAS latency = 2  
DOUT A0 DOUT A1 DOUT A2 DOUT A3  
t
CK2, DQs  
DIMM  
CAS latency = 3  
DOUT A0 DOUT A1 DOUT A2 DOUT A3  
Added for on-DIMM pipeline register  
t
CK3, DQs  
One Clock  
Reg-DIMM Latency = 1  
SPT03968  
In case of a Burst Write Command the data-in is delayed one clock due the op-DIMM pipeline  
register also. Therefore, data for the first Burst Write cycle must be applied on the DQ pins on the  
next clock cycle after the Write command is issued. the remaining data inputs must be supplied on  
each subsequent rising clock edge until the burst length is completed. When the burst has finished,  
any additional data supplied to the DQ pins will be ignored.  
INFINEON Technologies  
16  
9.01  
HYS 72Vx3xxGR-8  
PC100 Registered SDRAM-Modules  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
CLK  
Command  
DQs  
NOP  
Write A  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
dont care  
DIN A0  
DIN A1  
DIN A2  
DIN A3  
The first data element and the Write  
are registered on the next clock edge  
Reg-DIMM Latency = 1 CLK  
Extra data is ignored after  
termination of a Burst.  
SPT03969  
Registered DIMM Burst Write Operation (BL = 4)  
Buffered Mode:  
Operating margins when Registered DIMM modules are used in buffered modeare derived from  
the post register timing only. For a complete system level timing the system designer must add/  
subtract to/from this margin other parameters such as, system to DIMM flight time, clow skew, clock  
jitter, external register clock to output delay etc.  
The table below shows an example for the post register timing for DIMM modules in buffered  
mode:  
Time [ns]  
Set-up  
TIme [ns]  
Hold  
Property  
Property  
Tpd.BUF.max  
Tflight.max  
Tsso.brd.max  
Tsu.SDRAM  
Period  
1.96  
3.43  
0.30  
2.00  
15.00  
Tpd.BUF.min  
Tflight.min  
0.91  
2.66  
0.0  
Tsso.brd.min  
TholdSDRAM  
-1.00  
tpd.BUF.max: The maximum time for the signal to exit the register with REGE in a low stgate. This  
is measured into 0 pf load.  
Tflight.max: The maximum time for the signal to propagate from the register to the SDRAM  
INFINEON Technologies  
17  
9.01  
HYS 72Vx3xxGR-8  
PC100 Registered SDRAM-Modules  
Tsso.brd.max: The time the flight tine is extended due to simultaneous switching outputs and  
crosstalk from other signals.  
Tsu.SDRAM: The set-up required for the SDRAM inputs.  
Tpd.BUF.min. : The minimum time for the signal to exit the register with REGE in a low state. This  
is measured into a 0 pf load.  
Tflight.min: The minimum time for the signal to propagate from the register to the SDRAM  
Thold.DRAM: The hold time required for the SDRAM inputs  
Period: Minimum cycle time expressing in ns allowed for operating these Registered DIMM  
modules in buffered mode”  
Module Label Example:  
IFXpartnumber  
HYS72V64300GR-8-C2  
C1W106112256  
64Mx72 SDRAM  
PC100-222-622R  
IFX coding for:  
- design step  
- PCB rev.  
Assembled in USA  
512MB, SYNC, 100MHz, CL2,ECC,REG  
- date code  
- lot code  
INFINEON Technologies  
18  
9.01  
HYS 72Vx3xxGR-8  
PC100 Registered SDRAM-Modules  
Rev. Changes  
13.2.2001  
Target Specification for operation up to 100 MHz in registered modeand  
67 Mhz when used in buffered mode”  
Special module family for applications based on INTELs 460GX chipset,  
where PC100 modules are used in buffered modeat 67 MHz maximum ope-  
ration frequency.  
Uses components with twr = tdpl = 2Clock which support trp <= 15ns to gua-  
rantee operation at 67MHz when these modules are used in buffered mode”  
21.6.2001  
29.06.01  
Outline Drawings updated and changed to L-DIM-168-37 & 37S  
Absolute maximum rating section added  
06.09.2001  
SCR: Thickness of modules with stacked components changed  
from 6.4 to 6.8 max.  
Datasheet changed from Preliminaryto Final”  
INFINEON Technologies  
19  
9.01  
厂商 型号 描述 页数 下载

INFINEON

HYS64-72V2200GU-8 3.3V 2M ×64 /72- 1位BANK SDRAM模块3.3V 4M ×64 /72- 2位BANK SDRAM模块[ 3.3V 2M x 64/72-Bit 1 BANK SDRAM Module 3.3V 4M x 64/72-Bit 2 BANK SDRAM Module ] 17 页

INFINEON

HYS64-74V8200GU 3.3 V 8M ×64 /72- 1位银行SDRAM模块3.3 V 16M ×64 /72- 2位银行SDRAM模块[ 3.3 V 8M x 64/72-Bit 1 Bank SDRAM Module 3.3 V 16M x 64/72-Bit 2 Bank SDRAM Module ] 17 页

INFINEON

HYS6472V16200GU 3.3 V 16M ×64 /72-位SDRAM模块3.3 V 32M ×64 /72-位SDRAM模块3.3 V 64M ×64 /72-位SDRAM模块[ 3.3 V 16M x 64/72-Bit SDRAM Modules 3.3 V 32M x 64/72-Bit SDRAM Modules 3.3 V 64M x 64/72-Bit SDRAM Modules ] 17 页

INFINEON

HYS6472V4200GU 3.3V 4M ×64 /72- 1位BANK SDRAM模块3.3V 8M ×64 /72- 2位BANK SDRAM模块[ 3.3V 4M x 64/72-Bit 1 BANK SDRAM Module 3.3V 8M x 64/72-Bit 2 BANK SDRAM Module ] 15 页

INFINEON

HYS64D128020GBDL-6-A [ DDR DRAM Module, 128MX64, 0.7ns, CMOS, SO-DIMM-200 ] 11 页

ETC

HYS64D128020GBDL-7-A ? 1GB ( 1024Mx64 ) PC2100 2银行?\n[ ?1GB (1024Mx64) PC2100 2-bank? ] 11 页

INFINEON

HYS64D128020GU-7-A 2.5 V 184针无缓冲DDR- SDRAM我模块[ 2.5 V 184-pin Unbuffered DDR-I SDRAM Modules ] 18 页

INFINEON

HYS64D128020GU-8-A 2.5 V 184针无缓冲DDR- SDRAM我模块[ 2.5 V 184-pin Unbuffered DDR-I SDRAM Modules ] 18 页

QIMONDA

HYS64D128020GU-8-A [ DDR DRAM Module, 128MX64, 0.8ns, CMOS, PDMA184 ] 18 页

INFINEON

HYS64D128021 200针的小型双列直插式内存模块[ 200-Pin Small Outline Dual-In-Line Memory Modules ] 23 页

PDF索引:

A

B

C

D

E

F

G

H

I

J

K

L

M

N

O

P

Q

R

S

T

U

V

W

X

Y

Z

0

1

2

3

4

5

6

7

8

9

IC型号索引:

A

B

C

D

E

F

G

H

I

J

K

L

M

N

O

P

Q

R

S

T

U

V

W

X

Y

Z

0

1

2

3

4

5

6

7

8

9

Copyright 2024 gkzhan.com Al Rights Reserved 京ICP备06008810号-21 京

0.215103s