8T49N004A-045NLGI8,PDF,8T49N004A-045NLGI8 PDF资料,Datasheet,下载8T49N004A-045NLGI8技术资料

Programmable FemtoClock^®NG LVPECL/LVDS

Clock Generator with 4-Outputs

IDT8T49N004I

DATASHEET

General Description

Features

The IDT8T49N004I is a four output Clock Generator with selectable

LVDS or LVPECL outputs. The IDT8T49N004I can generate any one

of four frequencies from a single crystal or reference clock. The four

frequencies are selected from the Frequency Selection Table (Table

3A) and are programmed via I²C interface. The four predefined

frequencies are selected in the user application by two frequency

selection pins. Note the desired programmed frequencies must be

used with the corresponding crystal or clock frequency as indicated

in Table 3A.

• Fourth Generation FemtoClock NG PLL technology

• Four selectable LVPECL or LVDS outputs via I²C

• CLK, nCLK input pair can accept the following differential input

levels: LVPECL, LVDS, HCSL

• FemtoClock NG VCO Range: 1.91GHz - 2.5GHz

• RMS phase jitter at 156.25MHz (12kHz - 20MHz):

228fs (typical)

• RMS phase jitter at 156.25MHz (10kHz - 1MHz): 175fs (typical)

• Full 2.5V or 3.3V power supply

• I²C programming interface

Excellent phase noise performance is maintained with IDT’s Fourth

Generation FemtoClock^®NG PLL technology, which delivers

sub-400fs RMS phase jitter.

• PCI Express (2.5Gb/s), Gen 2 (5Gb/s), and Gen 3 (8Gb/s)

jitter compliant

• -40°C to 85°C ambient operating temperature

• Lead-free (RoHS 6) packaging

Pin Assignment

24 23 22 21 20 19 18 17

25

16

15 V_EE

14

VCC

SCLK

SDATA 26

VEE 27

FSEL0

28

29

VCCA

LOCK

VEE

13 nCLK

12 CLK

11

10

9

VEE

30

31

32

VCC

XTAL_OUT

XTAL_IN

CLK_SEL

1

2

3

4

5

6

7

8

IDT8T49N004I

32-Lead VFQFN

5mm x 5mm x 0.925mm package body

3.15mm x 3.15mm E-Pad

NL Package

IDT8T49N004ANLGI REVISION A OCTOBER 15, 2013

1

IDT8T49N004I Data Sheet

PROGRAMMABLE FEMTOCLOCK^®NG LVPECL/LVDS CLOCK GENERATOR WITH 4-OUTPUTS

Block Diagram

IDT8T49N004ANLGI REVISION A OCTOBER 15, 2013

2

IDT8T49N004I Data Sheet

PROGRAMMABLE FEMTOCLOCK^®NG LVPECL/LVDS CLOCK GENERATOR WITH 4-OUTPUTS

Table 1. Pin Descriptions

Number

Name

Type

Description

1, 7, 11, 15,

18, 24, 27, 30

V_EE

Power

Negative supply pins.

2, 3

4, 21

5, 6

8

Q0, nQ0

V_CCO

Output

Power

Differential output pair. LVPECL or LVDS interface levels.

Output supply pins.

Q1, nQ1

nc

Output

Unused

Differential output pair. LVPECL or LVDS interface levels.

No connect.

9,

10

XTAL_IN

XTAL_OUT

Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.

Crystal frequency is selected from Table 3A.

Input

12

CLK

Pulldown

Non-inverting differential clock input.

Pullup/

Pulldown

13

nCLK

Inverting differential clock input. Internal resistor bias to V_CC/2.

Frequency and configuration. Selects between one of four factory

programmable power-up default configurations. The four configurations can

have different PLL states, output frequencies, output styles and output

states. These default configurations can be overwritten after power-up via

I²C. LVCMOS/LVTTL interface levels.

FSEL0,

FSEL1

14, 17

Input

Pulldown

00 = Configuration 0 (default)

01 = Configuration 1

10 = Configuration 2

11 = Configuration 3

16, 31

19, 20

22, 23

25

V_CC

Power

Output

Input

Core supply pins.

nQ3, Q3

nQ2, Q2

SCLK

Differential output pair. LVPECL or LVDS interface levels.

I²C Clock Input. LVCMOS/LVTTL interface levels.

I²C Data Input. Input: LVCMOS/LVTTL interface levels.

Output: Open Drain.

Pullup

26

SDATA

I/O

28

29

V_CCA

Power

Output

Analog supply pin.

LOCK

PLL Lock Indicator. LVCMOS/LVTTL interface levels.

Input source control pin. LVCMOS/LVTTL interface levels.

0 = XTAL (default)

32

CLK_SEL

Input

Pulldown

1 = CLK, nCLK

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Symbol

C_IN

Parameter

Test Conditions

Minimum

Typical

3.5

Maximum

Units

pF

Input Capacitance

Input Pulldown Resistor

Input Pullup Resistor

R_PULLDOWN

R_PULLUP

51

k

51

k

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3

IDT8T49N004I Data Sheet

PROGRAMMABLE FEMTOCLOCK^®NG LVPECL/LVDS CLOCK GENERATOR WITH 4-OUTPUTS

Frequency Configuration

Table 3A. Frequency Configuration Examples

Input Frequency or

Crystal Frequency

(MHz)

Input Clock

Divider

P

Input Clock

Prescaler

PS

Feedback

Divider

M

VCO

Frequency

(MHz)

Output Frequencies

(MHz)

Output Divider

N

30.72

61.44

62.5

30.72

25

1

2

5

1

2

1

2

5

1

x2

x1

x2

x1

x2

x1

x2

x1

x2

32

40

50

40

32

40

48

44

42

40

64

50

36

48

40

36

90

40

48

64

32

50

40

36

64

32

20

16

18

16

14

16

12

10

8

1966.08

2000

76.8

30.72

25

2457.6

2500

78.125

100

25

2000

106.25

122.8

125

26.5625

30.72

25

2125

1966.08

2000

133.33

148.5

150

25

2400

27

2376

25

2100

153.6

155.52

30.72

19.44

25

2457.6

2488.32

2500

156.25

100

2500

125

2500

159.375

160

26.5625

20

1912.5

1920

166.66

25

2000

30.72

61.44

25

2211.84

2250

184.32

187.5

200

25

2000

212.5

250

26.5625

25

2125

2000

300

25

8

2400

19.44

77.76

155.52

25

8

2488.32

2500

311.04

312.5

8

125

8

2500

156.25

26.5625

8

2500

318.75

6

1912.5

Continued on next page.

IDT8T49N004ANLGI REVISION A OCTOBER 15, 2013

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IDT8T49N004I Data Sheet

PROGRAMMABLE FEMTOCLOCK^®NG LVPECL/LVDS CLOCK GENERATOR WITH 4-OUTPUTS

Input Frequency or

Crystal Frequency

(MHz)

Input Clock

Divider

P

Input Clock

Prescaler

PS

Feedback

Divider

M

VCO

Frequency

(MHz)

Output Frequencies

(MHz)

Output Divider

N

322.265625

375

25.78125

25

2

1

2

5

1

x1

x2

x1

x2

150

90

40

32

40

64

50

40

6

5

4

2

1933.59375

2250

400

25

2000

425

26.5625

30.72

122.88

153.6

19.44

25

2125

491.52

1966.08

2457.6

2488.32

2500

614.4

622.08

625

1228.88

30.72

2457.6

NOTE: Each device supports 4 output frequencies (with related input or crystal value) as selected from this table Register Settings.

NOTE: XTAL operation: f_OUT= f_REF* PS * M / N; CLK, nCLK input operation: f_OUT= (f_REF/ P) * PS * M / N.

2

Table 3B. I C Register Map

Binary

Register

Register Bit

Register Address

D7

D6

M0[7]

D5

D4

D3

D2

D1

D0

0

1

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

10010

10011

10100

10101

10110

10111

M0[8]

M0[6]

M1[6]

M2[6]

M3[6]

N0[5]

N1[5]

N2[5]

N3[5]

PS0[1]

PS1[1]

PS2[1]

PS3[1]

M0[5]

M1[5]

M2[5]

M3[5]

N0[4]

M0[4]

M0[3]

M1[3]

M2[3]

M3[3]

N0[2]

N1[2]

N2[2]

N3[2]

P0[0]

P1[0]

P2[0]

P3[0]

M0[2]

M1[2]

M2[2]

M3[2]

N0[1]

N1[1]

N2[1]

N3[1]

CP0[1]

CP1[1]

CP2[1]

CP3[1]

M0[1]

M1[1]

M2[1]

M3[1]

N0[0]

N1[0]

N2[0]

N3[0]

CP0[0]

CP1[0]

CP2[0]

CP3[0]

M1[8]

M1[7]

M1[4]

2

M2[8]

M2[7]

M2[4]

3

M3[8]

M3[7]

M3[4]

4

unused

N0[6]

N0[3]

5

N1[6]

N1[4]

N1[3]

6

N2[6]

N2[4]

N2[3]

7

N3[6]

N3[4]

N3[3]

8

BYPASS0

BYPASS1

BYPASS2

BYPASS3

PS0[0]

PS1[0]

PS2[0]

PS3[0]

P0[1]

9

P1[1]

10

11

12

13

14

15

16

17

18

19

20

21

22

23

P2[1]

P3[1]

reserved LVDS_SEL0[Q3] LVDS_SEL0[Q2] reserved

reserved LVDS_SEL1[Q3] LVDS_SEL1[Q2] reserved

reserved LVDS_SEL2[Q3] LVDS_SEL2[Q2] reserved

reserved LVDS_SEL3[Q3] LVDS_SEL3[Q2] reserved

reserved

unused

LVDS_SEL0[Q1] LVDS_SEL0[Q0] reserved

LVDS_SEL1[Q1] LVDS_SEL1[Q0] reserved

LVDS_SEL2[Q1] LVDS_SEL2[Q0] reserved

LVDS_SEL3[Q1] LVDS_SEL3[Q0] reserved

reserved

unused

OE0[Q3]

OE1[Q3]

OE2[Q3]

OE3[Q3]

reserved

unused

OE0[Q2]

OE1[Q2]

OE2[Q2]

OE3[Q2]

reserved

unused

reserved

unused

OE0[Q1]

OE1[Q1]

OE2[Q1]

OE3[Q1]

reserved

unused

OE0[Q0]

OE1[Q0]

OE2[Q0]

OE3[Q0]

unused

reserved

unused

IDT8T49N004ANLGI REVISION A OCTOBER 15, 2013

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IDT8T49N004I Data Sheet

PROGRAMMABLE FEMTOCLOCK^®NG LVPECL/LVDS CLOCK GENERATOR WITH 4-OUTPUTS

2

Table 3C. I C Function Descriptions

Bits

Name

Function

Sets the PLL input clock divider. The divider value has the range of 1, 2, 4

and 5. See Table 3F. Pn[1:0] bits are programmed with values to support

default configuration settings for FSEL[1:0].

Input Clock Divider Register n

(n = 0...3)

Pn[1:0]

Sets the PLL input clock prescaler value. Valid prescaler values are x0.5, x1

or x2. See Table 3F. Set prescaler to x2 for optimum phase noise

performance. PSn[1:0] bits are programmed with values to support default

configuration settings for FSEL[1:0].

Input Prescaler Register n

(n = 0...3)

PSn(1:0)

Sets the integer feedback divider value. Based on the FemtoClock NG VCO

Integer Feedback Divider Register range, the applicable feedback dividers settings are 16 thru 250. Please note

Mn[8:1]

n

the register value presents bits [8:1] of Mn, the LSB of Mn is not in the

register. Mn[8:1] bits are programmed with values to support default

configuration settings for FSEL[1:0].

(n = 0...3)

Sets the output divider. The output divider value can range from 2, 3, 4, 5, 6

and 8, 10, 12 to 126 (step: 2). See Table 3G for the output divider coding.

Nn[6:0] bits are programmed with values to support default configuration

settings for FSEL[1:0].

Output Divider Register n

(n = 0...3)

Nn[6:0]

Sets the FemtoClock NG PLL bandwidth by controlling the charge pump

current. See Table 3H. CPn[1:0] bits are programmed with values to support

default configuration settings for FSEL[1:0].

PLL Bandwidth Register n

(n = 0...3)

CPn[1:0]

Bypasses PLL. Output of the prescaler is routed through the output divider

N to the output fanout buffer. Programming a 1 to this bit bypasses the PLL.

Programming a 0 to this bit routes the output of the prescaler through the

PLL. BYPASSn bits are programmed with values to support default

configuration settings for FSEL[1:0].

PLL Bypass Register n

(n = 0...3)

BYPASSn

Sets the outputs to Active or High Impedance. Programming a 0 to this bit

sets the outputs to High Impedance. Programming a 1, sets the outputs to

active status. OEn[Q0], OEn[Q1], OEn[Q2], and OEn[Q3] bits are

programmed with values to support default configuration settings for

FSEL[1:0].

OEn[Q0]

OEn[Q1]

OEn[Q2]

OEn[Q3]

Output Enable Register n

(n = 0...3)

Sets the differential output style to either LVDS or LVPECL interface levels.

Programming a 1 to this bit sets the output styles to LVDS levels.

Programming a 0 to this bit sets the output styles to LVPECL levels.

LVDS_SELn[Q0], LVDS_SELn[Q1], LVDS_SELn[Q2], and LVDS_SELn[Q3]

bits are programmed with values to support default configuration settings for

FSEL[1:0].

LVDS_SELn[Q0]

LVDS_SELn[Q1]

LVDS_SELn[Q2]

LVDS_SELn[Q3]

Output Style Register n

(n = 0...3)

IDT8T49N004ANLGI REVISION A OCTOBER 15, 2013

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IDT8T49N004I Data Sheet

PROGRAMMABLE FEMTOCLOCK^®NG LVPECL/LVDS CLOCK GENERATOR WITH 4-OUTPUTS

Table 3D. Feedback Divider Mn Coding

Register Bit

Mn[8:1]

Do Not Use

00001000

00001001

00001010

00001011

00001100 thru 00011111

00100000

00100001

00100010

00100011

00100100

...

Feedback Divider Mn

1 thru 15

16

18

20

22

24 thru 62

64

66

68

70

72

Mn

00110010

00110011

00110100

00110101

...

100

102

104

106

Mn

01111010

01111011

01111100

01111101

244

246

248

250

Note: Mn is always an even value. The Mn[0] bits are not implemented.

Table 3E. Input Clock Divider Pn and Prescaler PSn Coding

Input Clock

Divider

P

Input Clock

Prescaler

PS

Input Frequency (MHz)

CLK_SEL

Input

P[1:0]

PS[1:0]

00

Minimum

10

Maximum

40

1

2

4

5

x1

x0.5

x2

0

XTAL

xx

01

20

5

40

1x

40

00

x1

10

20

5

120

240

60

00

01

10

11

01

x0.5

x2

1x

00

x1

20

40

10

40

80

20

50

100

25

240

480

120

480

800

240

600

800

300

01

x0.5

x2

1x

1

CLK

00

x1

01

x0.5

x2

1x

00

x1

01

x0.5

x2

1x

IDT8T49N004ANLGI REVISION A OCTOBER 15, 2013

7

IDT8T49N004I Data Sheet

PROGRAMMABLE FEMTOCLOCK^®NG LVPECL/LVDS CLOCK GENERATOR WITH 4-OUTPUTS

Table 3F. Output Divider Nn Coding

Register Bit

N_n[6:0]

Output Frequency Range

Output Divider

N

f_{OUT_MIN}(MHz)

f_{OUT_MAX}(MHz)

000000X

0000010

0000011

0000100

0000101

000011X

000100X

000101X

000110X

000111X

001000X

...

2

Do Not Use

2

955

636.67

477.5

1250

833.33

625

3

4

5

382

500

6

318.33

238.75

191

416.67

312.5

8

10

250

12

159.1667

136.4286

119.375

(1910 ÷ N)

15.40

208.33

178.57

156.25

(2500 ÷ N)

20.16

14

16

N (even integer)

124

111101X

111111X

126

15.16

19.84

NOTE: X denotes “don’t care”.

Table 3G. Charge Pump CP Settings

Register Bit

Feedback Divider (M) Value Range

CPn1

CPn0

Minimum

16

Maximum

48

0

1

0

1

0

1

48

100

250

192

250

NOTE: FemtoClock NG PLL stability is only guaranteed over the feedback divider ranges listed is Table 3G.

IDT8T49N004ANLGI REVISION A OCTOBER 15, 2013

8

IDT8T49N004I Data Sheet

PROGRAMMABLE FEMTOCLOCK^®NG LVPECL/LVDS CLOCK GENERATOR WITH 4-OUTPUTS

Power-up Default Configuration Description

The IDT8T49N004I supports a variety of options such as different

output styles, number of programmed default frequencies, output en-

able and operating temperature range. The device options and de-

fault frequencies must be specified at the time of order and are

programmed by IDT prior to shipment. The document, Programma-

ble FemtoClock^®NG Product Ordering Guide specifies the available

order codes, including the device options and default frequency con-

figurations. Example part number: 8T49N004A-007NLGI, specifies a

quad frequency clock generator with default frequencies of

outputs that are enabled after power-up, specified over the industrial

temperature range and housed in a lead-free (6/6 RoHS) VFQFN

package.

Other order codes with respective programmed frequencies are

available from IDT upon request. After power-up changes to the out-

put frequencies are controlled by FSEL[1:0] or the I²C interface.

Changes to the style (LVDS or LVPECL) and state (active or high im-

pedance) of each individual output can also be controlled with the I²C

interface after power up.

106.25MHz, 133.333MHz, 156.25MHz and 156.25MHz, with 4 LVDS

Table 3H. Power-up Default Settings

PLL State

Output State

Output Style

FSEL1

FSEL0

Frequency

Frequency 0

Frequency 1

Frequency 2

Frequency 3

(On or Bypass)

PLL State 0

PLL State 1

PLL State 2

PLL State 3

(Active or High Impedance)

(LVDS or LVPECL)

0 (default)

Output State 0

Output State 1

Output State 2

Output State 3

Output Style 0

Output Style 1

Output Style 2

Output Style 3

0

1

0

1

Serial Interface Configuration Description

The IDT8T49N004I has an I²C-compatible configuration interface to

access any of the internal registers (Table 3B) for frequency and PLL

parameter programming. The IDT8T49N004I acts as a slave device

on the I²C bus and has the address 0b1101110. The interface

accepts byte-oriented block write and block read operations. An

address byte (P) specifies the register address (Table 3B) as the byte

position of the first register to write or read. Data bytes (registers) are

accessed in sequential order from the lowest to the highest byte

(most significant bit first, see Table 3I, 3J).

Read and write block transfers can be stopped after any complete

byte transfer. It is recommended to terminate the I²C read or write

transfer after accessing byte #23 by sending a stop command.

For full electrical I²C compliance, it is recommended to use external

pull-up resistors for SDATA and SCLK. The internal pull-up resistors

have a size of 50k typical.

Table 3I. Block Write Operation

Bit

1

START

1

2:8

9

W (0)

1

10

ACK

1

11:18

Address Byte P

8

19

ACK

1

20:27

28

ACK

1

29-36

37

ACK

1

...

ACK

1

...

STOP

1

Description

Data Byte

(P)

DataByte

(P+1)

Data Byte

...

Slave Address

7

Length (bits)

8

Table 3J. Block Read Operation

Bit

1

START

1

2:8

9

10

11:18

19

20

21:27

28

29

30:37

38

39-46

47

...

STOP

1

Description

A

C

K

A

C

K

A

C

K

A

C

K

A

C

K

A

C

K

Slave

Address

W

(0)

Address

byte P

Repeated

START

Slave

Address

R

(1)

Data Byte

(P)

DataByte

(P+1)

Data Byte

...

Length (bits)

7

1

8

1

7

1

8

1

8

1

8

1

IDT8T49N004ANLGI REVISION A OCTOBER 15, 2013

9

IDT8T49N004I Data Sheet

PROGRAMMABLE FEMTOCLOCK^®NG LVPECL/LVDS CLOCK GENERATOR WITH 4-OUTPUTS

Absolute Maximum Ratings

NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress

specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC

Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.

Item

Rating

Supply Voltage, V_CC

3.63V

Inputs, V_I

XTAL_IN

Other Input

0V to 2V

-0.5V to V_CC+ 0.5V

Outputs, I_O(LVPECL)

Continuous Current

Surge Current

50mA

100mA

Outputs, I_O(SDATA)

10mA

Outputs, I_O(LVDS)

Continuous Current

Surge Current

10mA

15mA

Package Thermal Impedance, _JA

33.1C/W (0 mps)

-65C to 150C

Storage Temperature, T_STG

DC Electrical Characteristics

Table 4A. Power Supply DC Characteristics, V = V

= 3.3V 5%, V = 0V, T = -40°C to 85°C

EE A

CC

CCO

Symbol

V_CC

Parameter

Test Conditions

Minimum

Typical

3.3

Maximum

3.465

V_CC

Units

V

Core Supply Voltage

Analog Supply Voltage

Output Supply Voltage

Analog Supply Current

Power Supply Current

Output Supply Current

3.135

V_CC– 0.32

3.135

V_CCA

V_CCO

I_CCA

I_EE

3.3

V

3.3

3.465

32

V

mA

LVPECL

LVDS

192

I_CC

125

I_CCO

LVDS

85

Table 4B. Power Supply DC Characteristics, V = V

= 2.5V 5%, V = 0V, T = -40°C to 85°C

EE A

CC

CCO

Symbol

V_CC

Parameter

Test Conditions

Minimum

Typical

2.5

Maximum

2.625

V_CC

Units

V

Core Supply Voltage

Analog Supply Voltage

Output Supply Voltage

Analog Supply Current

Power Supply Current

Output Supply Current

2.375

V_CC– 0.28

2.375

V_CCA

V_CCO

I_CCA

I_EE

2.5

V

2.5

2.625

28

V

mA

LVPECL

LVDS

184

I_CC

122

I_CCO

LVDS

82

IDT8T49N004ANLGI REVISION A OCTOBER 15, 2013

10

IDT8T49N004I Data Sheet

PROGRAMMABLE FEMTOCLOCK^®NG LVPECL/LVDS CLOCK GENERATOR WITH 4-OUTPUTS

Table 4C. LVCMOS/LVTTL DC Characteristics, V = V

= 3.3V 5% or 2.5V 5%, V = 0V, T = -40°C to 85°C

CC

CCO

EE

A

Symbol Parameter

Test Conditions

Minimum

Typical

Maximum Units

V

_CC= 3.3V

V_CC= 2.5V

_CC= 3.3V

2

V_CC+ 0.3

V

Input High

Voltage

SCLK, SDATA,

CLK_SEL, FSEL[1:0]

V_IH

1.7

-0.3

V_CC+ 0.3

SCLK, SDATA, CLK_SEL

FSEL[1:0]

V

0.8

0.7

0.5

5

V

Input Low

Voltage

V_IL

V_CC= 2.5V

V

V_CC= 3.3V or 2.5V

V

SCLK, SDATA

V

_CC= V_IN= 3.465V or 2.625V

µA

V

Input

High Current

I_IH

CLK_SEL, FSEL[1:0]

SCLK, SDATA

V_CC= V_IN= 3.465V or 2.625V

_CC= 3.465V or 2.625V, V_IN= 0V

150

V

-150

-5

Input

Low Current

I_IL

CLK_SEL, FSEL[1:0]

LOCK

V_CC= 3.465V or 2.625V, V_IN= 0V

_CCO= 3.465V

Output

V

2.6

V_OH

High Voltage;

NOTE 1

LOCK

V_CCO= 2.625V

1.8

V

Output

V_OL

Low Voltage; LOCK

NOTE 1

V_CCO= 3.465V or 2.625V

0.5

V

NOTE 1: Outputs terminated with 50 to V_CCO/2. In the Parameter Measurement Information Section, see Output Load Test Circuit Diagrams.

Table 4D. Differential DC Characteristics, V = V

= 3.3V 5% or 2.5V 5%, V = 0V, T = -40°C to 85°C

CC

CCO

EE

A

Symbol Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Input

High Current

I_IH

CLK, nCLK

V

_CC= V_IN= 3.465V or 2.625V

150

µA

nCLK

CLK

V

_CC= 3.465V or 2.625V, V_IN= 0V

-150

-5

µA

V

Input

Low Current

I_IL

V_CC= 3.465V or 2.625V, V_IN= 0V

V_PP

Peak-to-Peak Voltage

0.15

1.3

Common Mode Input Voltage;

NOTE 1

V_CMR

V_EE

V_CC– 0.85

V

NOTE 1: Common mode input voltage is at the cross point.

Table 4E. LVPECL DC Characteristics, V = V

= 3.3V 5%, V = 0V, T = -40°C to 85°C

EE A

CC

CCO

Symbol Parameter

Test Conditions

Minimum

Typical

Maximum

V_CCO– 0.75

V_CCO– 1.6

1.0

Units

V_OH

Output High Voltage; NOTE 1

Output Low Voltage; NOTE 1

Peak-to-Peak Output Voltage Swing

V_CCO– 1.1

V_CCO– 2.0

0.6

V

V_OL

V_SWING

NOTE 1: Outputs termination with 50 to V_CCO– 2V.

IDT8T49N004ANLGI REVISION A OCTOBER 15, 2013

11

IDT8T49N004I Data Sheet

PROGRAMMABLE FEMTOCLOCK^®NG LVPECL/LVDS CLOCK GENERATOR WITH 4-OUTPUTS

Table 4F. LVPECL DC Characteristics, V = V

= 2.5V 5%, V = 0V, T = -40°C to 85°C

EE A

CC

CCO

Symbol Parameter

Test Conditions

Minimum

Typical

Maximum

V_CCO– 0.75

V_CCO– 1.5

1.0

Units

V_OH

Output High Voltage; NOTE 1

Output Low Voltage; NOTE 1

Peak-to-Peak Output Voltage Swing

V_CCO– 1.2

V_CCO– 2.0

0.5

V

V_OL

V_SWING

NOTE 1: Outputs termination with 50 to V_CCO– 2V.

Table 4G. LVDS DC Characteristics, V = V

= 3.3V 5%, V = 0V, T = -40°C to 85°C

EE A

CC

CCO

Symbol

V_OD

Parameter

Test Conditions

Minimum

Typical

Maximum

454

Units

mV

V

Differential Output Voltage

V_ODMagnitude Change

Offset Voltage

247

345

V_OD

V_OS

50

1.15

1.25

1.375

50

V_OS

V_OSMagnitude Change

mV

Table 4H. LVDS DC Characteristics, V = V

= 2.5V 5%, V = 0V, T = -40°C to 85°C

EE A

CC

CCO

Symbol

V_OD

Parameter

Test Conditions

Minimum

Typical

Maximum

454

Units

mV

V

Differential Output Voltage

V_ODMagnitude Change

Offset Voltage

230

340

V_OD

V_OS

50

1.15

1.25

1.375

50

V_OS

V_OSMagnitude Change

mV

Table 5. Crystal Characteristics

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Mode of Oscillation

Fundamental

Frequency

10

40

18

50

MHz

pF

Load Capacitance (C_L)

Equivalent Series Resistance (ESR)



IDT8T49N004ANLGI REVISION A OCTOBER 15, 2013

12

IDT8T49N004I Data Sheet

PROGRAMMABLE FEMTOCLOCK^®NG LVPECL/LVDS CLOCK GENERATOR WITH 4-OUTPUTS

AC Electrical Characteristics

Table 6A. PCI Express Jitter Specifications, V = V

= 3.3V 5% or 2.5V 5%, V = 0V, T = -40°C to 85°C

CC

CCO

EE

A

Maximum

13.2

PCIe Industry

Symbol

Parameter

Test Conditions

Minimum

Typical

Specification Units

Phase Jitter

Peak-to-Peak;

NOTE 1, 4

ƒ = 100MHz, 25MHz Crystal Input

Evaluation Band: 0Hz - Nyquist

(clock frequency/2)

t_j

8.3

86

ps

(PCIe Gen 1)

ƒ = 100MHz, 25MHz Crystal Input

High Band: 1.5MHz - Nyquist

(clock frequency/2)

t_{REFCLK_HF_RMS}

(PCIe Gen 2)

Phase Jitter RMS;

NOTE 2, 4

0.78

0.05

1.35

0.10

0.34

3.1

3.0

0.8

ps

t_{REFCLK_LF_RMS}

(PCIe Gen 2)

Phase Jitter RMS; ƒ = 100MHz, 25MHz Crystal Input

NOTE 2, 4

Low Band: 10kHz - 1.5MHz

ƒ = 100MHz, 25MHz Crystal Input

Evaluation Band: 0Hz - Nyquist

(clock frequency/2)

t_{REFCLK_RMS}

(PCIe Gen 3)

Phase Jitter RMS;

NOTE 3, 4

0.175

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium

has been reached under these conditions. For additional information, refer to the PCI Express Application Note section in the datasheet.

NOTE 1: Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1

is 86ps peak-to-peak for a sample size of 10⁶clock periods.

NOTE 2: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and

reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for t_{REFCLK_HF_RMS}

(High Band) and 3.0ps RMS for t_{REFCLK_LF_RMS}(Low Band).

NOTE 3: RMS jitter after applying system transfer function for the common clock architecture. This specification is based on the PCI Express

Base Specification Revision 0.7, October 2009 and is subject to change pending the final release version of the specification.

NOTE 4: This parameter is guaranteed by characterization. Not tested in production.

IDT8T49N004ANLGI REVISION A OCTOBER 15, 2013

13

IDT8T49N004I Data Sheet

PROGRAMMABLE FEMTOCLOCK^®NG LVPECL/LVDS CLOCK GENERATOR WITH 4-OUTPUTS

Table 6B. AC Characteristics, V = V

= 3.3V 5% or 2.5V 5% V = 0V, T = -40°C to 85°

CC

CCO

EE

A

Symbol

f_{DIFF_IN}

f_VCO

Parameter

Test Conditions

Minimum

Typical

Maximum

312.5

Units

MHz

Differential Input Frequency

VCO Frequency

10

1910

2500

25MHz Crystal, f_OUT= 100MHz,

Integration Range:

258

220

164

228

175

212

213

280

332

291

232

306

234

292

299

386

fs

12kHz – 20MHz

25MHz Crystal, f_OUT= 125MHz,

Integration Range: 12kHz –

20MHz

25MHz Crystal, f_OUT= 125MHz,

Integration Range: 10kHz –

1MHz

25MHz Crystal, f_OUT

=

156.25MHz, Integration Range:

12kHz – 20MHz

RMS Phase Jitter, Random;

NOTE 1

tjit(Ø)

25MHz Crystal, f_OUT

=

156.25MHz, Integration Range:

10kHz – 1MHz

25MHz Crystal, f_OUT= 250MHz,

Integration Range: 12kHz –

20MHz

30.72MHz Crystal, f_OUT

=

491.52MHz, Integration Range:

12kHz – 20MHz

19.44MHz Crystal, f_OUT

=

622.08MHz, Integration Range:

12kHz – 20MHz

LVPECL Outputs

LVDS Outputs

LVPECL Outputs

LVDS Outputs

LVDS_SEL = 0

LVDS_SEL = 1

45

ps

Output Skew;

NOTE 2, 3

tsk(o)

t_R/ t_F

20% - 80%, LVDS_SEL = 0

20% - 80%, LVDS_SEL = 1

100

400

Output

Rise/Fall Time

N > 3 Output Divider;

LVDS_SEL = 0 or 1

47

42

53

58

20

%

odc

Output Duty Cycle

N  3 Output Divider;

LVDS_SEL = 0 or 1

PLL Lock Time;

NOTE 3, 4

t_LOCK

LOCK Output

ms

Transition

t_TRANSITIONTime;

NOTE 3, 4

20

ms

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium

has been reached under these conditions.

NOTE 1: Refer to Phase Noise Plots.

NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential

crosspoints.

NOTE 3: These parameters are guaranteed by characterization. Not tested in production.

NOTE 4: Refer to t_LOCKand t_TRANSITIONin Parameter Measurement Information.

IDT8T49N004ANLGI REVISION A OCTOBER 15, 2013

14

IDT8T49N004I Data Sheet

PROGRAMMABLE FEMTOCLOCK^®NG LVPECL/LVDS CLOCK GENERATOR WITH 4-OUTPUTS

Typical Phase Noise at 100MHz (3.3V)

Offset Frequency (Hz)

Typical Phase Noise at 125MHz (3.3V)

Offset Frequency (Hz)

15

IDT8T49N004ANLGI REVISION A OCTOBER 15, 2013

IDT8T49N004I Data Sheet

PROGRAMMABLE FEMTOCLOCK^®NG LVPECL/LVDS CLOCK GENERATOR WITH 4-OUTPUTS

Typical Phase Noise at 156.25MHz (3.3V)

Offset Frequency (Hz)

IDT8T49N004ANLGI REVISION A OCTOBER 15, 2013

16

IDT8T49N004I Data Sheet

PROGRAMMABLE FEMTOCLOCK^®NG LVPECL/LVDS CLOCK GENERATOR WITH 4-OUTPUTS

Parameter Measurement Information

2V

V_CC,

V_CCO

V_CCA

-1.3V 0.165V

-0.5V 0.125V

3.3V LVPECL Output Load AC Test Circuit

2.5V LVPECL Output Load AC Test Circuit

SCOPE

Qx

V_CC,

3.3V 5%

V_CCO

2.5V 5%

V_CCO

POWER SUPPLY

V_CCA

+

Float GND –

nQx

3.3V LVDS Output Load AC Test Circuit

2.5V LVDS Output Load AC Test Circuit

V_CC

nCLK

CLK

V_EE

Differential Input Levels

RMS Phase Jitter

IDT8T49N004ANLGI REVISION A OCTOBER 15, 2013

17

IDT8T49N004I Data Sheet

PROGRAMMABLE FEMTOCLOCK^®NG LVPECL/LVDS CLOCK GENERATOR WITH 4-OUTPUTS

Parameter Measurement Information, continued

nQ[0:3]

Q[0:3]

nQx

Qx

nQy

Qy

Output Skew

Output Duty Cycle/Pulse Width/Period

nQ[0:3]

Q[0:3]

nQ[0:3]

80%

t_F

80%

V_OD

20%

Q[0:3]

t_R

LVPECL Output Rise/Fall Time

LVDS Output Rise/Fall Time

Offset Voltage Setup

Differential Output Voltage Setup

IDT8T49N004ANLGI REVISION A OCTOBER 15, 2013

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IDT8T49N004I Data Sheet

PROGRAMMABLE FEMTOCLOCK^®NG LVPECL/LVDS CLOCK GENERATOR WITH 4-OUTPUTS

Parameter Measurement Information, continued

LockTime & Transition Time

Applications Information

Recommendations for Unused Input and Output Pins

Inputs:

Outputs:

LVCMOS Control Pins

LVPECL Outputs

All control pins have internal pullups or pulldowns; additional

resistance is not required but can be added for additional protection.

A 1k resistor can be used.

All unused LVPECL outputs can be left floating. We recommend that

there is no trace attached. Both sides of the differential output pair

should either be left floating or terminated.

CLK/nCLK Inputs

LVDS Outputs

For applications not requiring the use of the differential input, both

CLK and nCLK can be left floating. Though not required, but for

additional protection, a 1k resistor can be tied from CLK to ground.

All unused LVDS output pairs can be either left floating or terminated

with 100 across. If they are left floating, there should be no trace

attached.

Crystal Inputs

For applications not requiring the use of the crystal oscillator input,

both XTAL_IN and XTAL_OUT can be left floating. Though not

required, but for additional protection, a 1k resistor can be tied from

XTAL_IN to ground.

IDT8T49N004ANLGI REVISION A OCTOBER 15, 2013

19

IDT8T49N004I Data Sheet

PROGRAMMABLE FEMTOCLOCK^®NG LVPECL/LVDS CLOCK GENERATOR WITH 4-OUTPUTS

Wiring the Differential Input to Accept Single-Ended Levels

Figure 1 shows how a differential input can be wired to accept single

ended levels. The reference voltage V₁= V_CC/2 is generated by the

bias resistors R1 and R2. The bypass capacitor (C1) is used to help

filter noise on the DC bias. This bias circuit should be located as close

to the input pin as possible. The ratio of R1 and R2 might need to be

adjusted to position the V₁in the center of the input voltage swing.

For example, if the input clock swing is 2.5V and V_CC= 3.3V, R1 and

R2 value should be adjusted to set V₁at 1.25V. The values below are

for when both the single ended swing and V_CCare at the same

voltage. This configuration requires that the sum of the output

impedance of the driver (Ro) and the series resistance (Rs) equals

the transmission line impedance. In addition, matched termination at

the input will attenuate the signal in half. This can be done in one of

two ways. First, R3 and R4 in parallel should equal the transmission

line impedance. For most 50 applications, R3 and R4 can be 100.

The values of the resistors can be increased to reduce the loading for

slower and weaker LVCMOS driver. When using single-ended

signaling, the noise rejection benefits of differential signaling are

reduced. Even though the differential input can handle full rail

LVCMOS signaling, it is recommended that the amplitude be

reduced. The datasheet specifies a lower differential amplitude,

however this only applies to differential signals. For single-ended

applications, the swing can be larger, however V_ILcannot be less

than -0.3V and V_IHcannot be more than V_CC+ 0.3V. Though some

of the recommended components might not be used, the pads

should be placed in the layout. They can be utilized for debugging

purposes. The datasheet specifications are characterized and

guaranteed by using a differential signal.

Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels

IDT8T49N004ANLGI REVISION A OCTOBER 15, 2013

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IDT8T49N004I Data Sheet

PROGRAMMABLE FEMTOCLOCK^®NG LVPECL/LVDS CLOCK GENERATOR WITH 4-OUTPUTS

Overdriving the XTAL Interface

The XTAL_IN input can be overdriven by an LVCMOS driver or by one

side of a differential driver through an AC coupling capacitor. The

XTAL_OUT pin can be left floating. The amplitude of the input signal

should be between 500mV and 1.8V and the slew rate should not be

less than 0.2V/nS. For 3.3V LVCMOS inputs, the amplitude must be

reduced from full swing to at least half the swing in order to prevent

signal interference with the power rail and to reduce internal noise.

Figure 2A shows an example of the interface diagram for a high

speed 3.3V LVCMOS driver. This configuration requires that the sum

of the output impedance of the driver (Ro) and the series resistance

(Rs) equals the transmission line impedance. In addition, matched

termination at the crystal input will attenuate the signal in half. This

can be done in one of two ways. First, R1 and R2 in parallel should

equal the transmission line impedance. For most 50 applications,

R1 and R2 can be 100. This can also be accomplished by removing

R1 and changing R2 to 50. The values of the resistors can be

increased to reduce the loading for a slower and weaker LVCMOS

driver. Figure 2B shows an example of the interface diagram for an

LVPECL driver. This is a standard LVPECL termination with one side

of the driver feeding the XTAL_IN input. It is recommended that all

components in the schematics be placed in the layout. Though some

components might not be used, they can be utilized for debugging

purposes. The datasheet specifications are characterized and

guaranteed by using a quartz crystal as the input.

Figure 2A. General Diagram for LVCMOS Driver to XTAL Input Interface

Figure 2B. General Diagram for LVPECL Driver to XTAL Input Interface

IDT8T49N004ANLGI REVISION A OCTOBER 15, 2013

21

IDT8T49N004I Data Sheet

PROGRAMMABLE FEMTOCLOCK^®NG LVPECL/LVDS CLOCK GENERATOR WITH 4-OUTPUTS

3.3V Differential Clock Input Interface

The CLK /nCLK accepts LVDS, LVPECL, HCSL and other differential

signals. Both V_SWINGand V_OHmust meet the V_PPand V_CMRinput

requirements. Figures 3A to 3D show interface examples for the

CLK/nCLK input driven by the most common driver types. The input

interfaces suggested here are examples only. If the driver is from

another vendor, use their termination recommendation. Please

consult with the vendor of the driver component to confirm the driver

termination requirements.

3.3V

Zo = 50Ω

CLK

Zo = 50Ω

nCLK

Differential

Input

LVPECL

nCLK

R1

50Ω

R2

50Ω

Differential

Input

LVPECL

R2

50Ω

Figure 3A. CLK/nCLK Input Driven by a

3.3V LVPECL Driver

Figure 3B. CLK/nCLK Input Driven by a

3.3V LVPECL Driver

3.3V

Zo = 50Ω

*R3

*R4

CLK

R1

100Ω

nCLK

Zo = 50Ω

Differential

Input

Receiver

HCSL

LVDS

Figure 3C. CLK/nCLK Input Driven by a

3.3V HCSL Driver

Figure 3D. CLK/nCLK Input Driven by a 3.3V LVDS Driver

IDT8T49N004ANLGI REVISION A OCTOBER 15, 2013

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IDT8T49N004I Data Sheet

PROGRAMMABLE FEMTOCLOCK^®NG LVPECL/LVDS CLOCK GENERATOR WITH 4-OUTPUTS

2.5V Differential Clock Input Interface

The CLK /nCLK accepts LVDS, LVPECL, HCSL and other differential

signals. Both V_SWINGand V_OHmust meet the V_PPand V_CMRinput

requirements. Figures 4A to 4D show interface examples for the

CLK/nCLK input driven by the most common driver types. The input

interfaces suggested here are examples only. If the driver is from

another vendor, use their termination recommendation. Please

consult with the vendor of the driver component to confirm the driver

termination requirements.

2.5V

R3

R4

Zo = 50

250

CLK

Zo = 50

CLK

Zo = 50

nCLK

Differential

Input

LVPECL

nCLK

R1

50

R2

50

Differential

Input

LVPECL

R1

R2

62.5

R3

18

Figure 4A. CLK/nCLK Input Driven by a

2.5V LVPECL Driver

Figure 4B. CLK/nCLK Input Driven by a

2.5V LVPECL Driver

2.5V

Zo = 50

*R3

*R4

33

CLK

R1

100

Zo = 50

nCLK

Zo = 50

Differential

Input

Differential

Input

HCSL

R1

50

R2

50

LVDS

*Optional R3 and R4 can be 0

Figure 4C. CLK/nCLK Input Driven by a

2.5V HCSL Driver

Figure 4D. CLK/nCLK Input Driven by a 2.5V LVDS Driver

IDT8T49N004ANLGI REVISION A OCTOBER 15, 2013

23

IDT8T49N004I Data Sheet

PROGRAMMABLE FEMTOCLOCK^®NG LVPECL/LVDS CLOCK GENERATOR WITH 4-OUTPUTS

LVDS Driver Termination

For a general LVDS interface, the recommended value for the

termination impedance (Z_T) is between 90 and 132. The actual

value should be selected to match the differential impedance (Z₀) of

your transmission line. A typical point-to-point LVDS design uses a

100 parallel resistor at the receiver and a 100 differential

transmission-line environment. In order to avoid any

standard termination schematic as shown in Figure 5A can be used

with either type of output structure. Figure 5B, which can also be

used with both output types, is an optional termination with center tap

capacitance to help filter common mode noise. The capacitor value

should be approximately 50pF. If using a non-standard termination, it

is recommended to contact IDT and confirm if the output structure is

current source or voltage source type. In addition, since these

outputs are LVDS compatible, the input receiver’s amplitude and

common-mode input range should be verified for compatibility with

the output.

transmission-line reflection issues, the components should be

surface mounted and must be placed as close to the receiver as

possible. IDT offers a full line of LVDS compliant devices with two

types of output structures: current source and voltage source. The

Termination for 3.3V LVPECL Outputs

The clock layout topology shown below is a typical termination for

LVPECL outputs. The two different layouts mentioned are

recommended only as guidelines.

transmission lines. Matched impedance techniques should be used

to maximize operating frequency and minimize signal distortion.

Figures 6A and 6B show two different layouts which are

recommended only as guidelines. Other suitable clock layouts may

exist and it would be recommended that the board designers

simulate to guarantee compatibility across all printed circuit and clock

component process variations.

The differential outputs are low impedance follower outputs that

generate ECL/LVPECL compatible outputs. Therefore, terminating

resistors (DC current path to ground) or current sources must be

used for functionality. These outputs are designed to drive 50

Figure 6A. 3.3V LVPECL Output Termination

3.3V

R3

R4

125

3.3V

Z

_o= 50

+

_

LVPECL

Input

R1

84

R2

84

Figure 6B. 3.3V LVPECL Output Termination

IDT8T49N004ANLGI REVISION A OCTOBER 15, 2013

24

IDT8T49N004I Data Sheet

PROGRAMMABLE FEMTOCLOCK^®NG LVPECL/LVDS CLOCK GENERATOR WITH 4-OUTPUTS

Termination for 2.5V LVPECL Outputs

Figure 7A and Figure 9B show examples of termination for 2.5V

LVPECL driver.These terminations are equivalent to terminating 50

to V_CCO– 2V. For V_CCO= 2.5V, the V_CCO– 2V is very close to ground

level. The R3 in Figure 7B can be eliminated and the termination is

shown in Figure 7C.

2.5V

V_CCO= 2.5V

2.5V

V_CCO= 2.5V

R1

R3

50

250

+

50

+

–

50

–

2.5V LVPECL Driver

R1

50

R2

50

2.5V LVPECL Driver

R2

62.5

R4

62.5

R3

18

Figure 7A. 2.5V LVPECL Driver Termination Example

Figure 7B. 2.5V LVPECL Driver Termination Example

2.5V

V_CCO= 2.5V

50

+

50

–

2.5V LVPECL Driver

R1

50

R2

50

Figure 7C. 2.5V LVPECL Driver Termination Example

IDT8T49N004ANLGI REVISION A OCTOBER 15, 2013

25

IDT8T49N004I Data Sheet

PROGRAMMABLE FEMTOCLOCK^®NG LVPECL/LVDS CLOCK GENERATOR WITH 4-OUTPUTS

VFQFN EPAD Thermal Release Path

In order to maximize both the removal of heat from the package and

the electrical performance, a land pattern must be incorporated on

the Printed Circuit Board (PCB) within the footprint of the package

corresponding to the exposed metal pad or exposed heat slug on the

package, as shown in Figure 6. The solderable area on the PCB, as

defined by the solder mask, should be at least the same size/shape

as the exposed pad/slug area on the package to maximize the

thermal/electrical performance. Sufficient clearance should be

designed on the PCB between the outer edges of the land pattern

and the inner edges of pad pattern for the leads to avoid any shorts.

and dependent upon the package power dissipation as well as

electrical conductivity requirements. Thus, thermal and electrical

analysis and/or testing are recommended to determine the minimum

number needed. Maximum thermal and electrical performance is

achieved when an array of vias is incorporated in the land pattern. It

is recommended to use as many vias connected to ground as

possible. It is also recommended that the via diameter should be 12

to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is

desirable to avoid any solder wicking inside the via during the

soldering process which may result in voids in solder between the

exposed pad/slug and the thermal land. Precautions should be taken

to eliminate any solder voids between the exposed heat slug and the

land pattern. Note: These recommendations are to be used as a

guideline only. For further information, please refer to the Application

Note on the Surface Mount Assembly of Amkor’s Thermally/

Electrically Enhance Leadframe Base Package, Amkor Technology.

While the land pattern on the PCB provides a means of heat transfer

and electrical grounding from the package to the board through a

solder joint, thermal vias are necessary to effectively conduct from

the surface of the PCB to the ground plane(s). The land pattern must

be connected to ground through these vias. The vias act as “heat

pipes”. The number of vias (i.e. “heat pipes”) are application specific

SOLDER

EXPOSED HEAT SLUG

PIN PAD

GROUND PLANE

LAND PATTERN

(GROUND PAD)

PIN PAD

THERMAL VIA

Figure 6. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)

IDT8T49N004ANLGI REVISION A OCTOBER 15, 2013

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IDT8T49N004I Data Sheet

PROGRAMMABLE FEMTOCLOCK^®NG LVPECL/LVDS CLOCK GENERATOR WITH 4-OUTPUTS

PCI Express Application Note

PCI Express jitter analysis methodology models the system

response to reference clock jitter. The block diagram below shows the

most frequently used Common Clock Architecture in which a copy of

the reference clock is provided to both ends of the PCI Express Link.

In the jitter analysis, the transmit (Tx) and receive (Rx) serdes PLLs

are modeled as well as the phase interpolator in the receiver. These

transfer functions are called H1, H2, and H3 respectively. The overall

system transfer function at the receiver is:

Hts = H3s  H1s – H2s

The jitter spectrum seen by the receiver is the result of applying this

system transfer function to the clock spectrum X(s) and is:

Ys = Xs  H3s  H1s – H2s

In order to generate time domain jitter numbers, an inverse Fourier

Transform is performed on X(s)*H3(s) * [H1(s) - H2(s)].

PCIe Gen 2A Magnitude of Transfer Function

PCI Express Common Clock Architecture

For PCI Express Gen 1, one transfer function is defined and the

evaluation is performed over the entire spectrum: DC to Nyquist (e.g

for a 100MHz reference clock: 0Hz – 50MHz) and the jitter result is

reported in peak-peak.

PCIe Gen 2B Magnitude of Transfer Function

For PCI Express Gen 3, one transfer function is defined and the

evaluation is performed over the entire spectrum. The transfer

function parameters are different from Gen 1 and the jitter result is

reported in RMS.

PCIe Gen 1 Magnitude of Transfer Function

For PCI Express Gen 2, two transfer functions are defined with 2

evaluation ranges and the final jitter number is reported in RMS. The

two evaluation ranges for PCI Express Gen 2 are 10kHz – 1.5MHz

(Low Band) and 1.5MHz – Nyquist (High Band). The plots show the

individual transfer functions as well as the overall transfer function Ht.

PCIe Gen 3 Magnitude of Transfer Function

For a more thorough overview of PCI Express jitter analysis

methodology, please refer to IDT Application Note PCI Express

Reference Clock Requirements.

IDT8T49N004ANLGI REVISION A OCTOBER 15, 2013

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IDT8T49N004I Data Sheet

PROGRAMMABLE FEMTOCLOCK^®NG LVPECL/LVDS CLOCK GENERATOR WITH 4-OUTPUTS

Schematic Layout

Figure 9 shows an example of IDT8T49N004I application schematic.

The schematic focuses on functional connections and is not

configuration specific. Refer to the pin description and functional

tables in the datasheet to ensure that the logic control inputs are

properly set.

In order to achieve the best possible filtering, it is recommended that

the placement of the filter components be on the device side of the

PCB as close to the power pins as possible. If space is limited, the

0.1uF capacitor in each power pin filter should be placed on the

device side of the PCB and the other components can be placed on

the opposite side.

In this example, the device is operated at V_CC= V_CCO= V_CCA= 3.3V

rather than 2.5V. The CLK, nCLK inputs are provided by a 3.3V

LVPECL driver and depicted with a Y-termination rather than the

standard four resistor VCC-2V Thevinin termination for reasons of

minimum termination power and layout simplicity. Three examples of

PECL terminations are shown for the outputs to demonstrate some

of the design options available with LVPECL.

Power supply filter recommendations are a general guideline to be

used for reducing external noise from coupling into the devices. The

V_CCand V_CCOfilters start to attenuate noise at approximately 10kHz.

If a specific frequency noise component is known, such as switching

power supply frequencies, it is recommended that component values

be adjusted and if required, additional filtering be added. Additionally,

good general design practices for power plane voltage stability

suggests adding bulk capacitances in the local area of all devices.

As with any high speed analog circuitry, the power supply pins are

vulnerable to noise. To achieve optimum jitter performance, power

supply isolation is required. The IDT8T49N004I provides separate

power supplies to isolate from coupling into the internal PLL.

The schematic example focuses on functional connections and is not

configuration specific. Refer to the pin description and functional

tables in the datasheet to ensure the logic control inputs are properly

set.

IDT8T49N004ANLGI REVISION A OCTOBER 15, 2013

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IDT8T49N004I Data Sheet

PROGRAMMABLE FEMTOCLOCK^®NG LVPECL/LVDS CLOCK GENERATOR WITH 4-OUTPUTS

Figure 9. IDT8T49N004I Application Schematic

IDT8T49N004ANLGI REVISION A OCTOBER 15, 2013

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IDT8T49N004I Data Sheet

PROGRAMMABLE FEMTOCLOCK^®NG LVPECL/LVDS CLOCK GENERATOR WITH 4-OUTPUTS

LVPECL Power Considerations

This section provides information on power dissipation and junction temperature for the IDT8T49N004I.

Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the IDT8T49N004I is the sum of the core power plus the power dissipated in the load(s).

The following is the power dissipation for V_CC= 3.465V, which gives worst case results.

NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

•

Power (core)_MAX= V_{CC_MAX}* I_{EE_MAX}= 3.465V * 192mA = 665.28mW

Power (outputs)_MAX= 31.55mW/Loaded Output pair

If all outputs are loaded, the total power is 4 * 31.55mW = 126.2mW

Total Power__MAX(3.465V, with all outputs switching) = 665.28W + 126.2mW = 791.48W

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The

maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond

wire and bond pad temperature remains below 125°C.

The equation for Tj is as follows: Tj = _JA* Pd_total + T_A

Tj = Junction Temperature



_JA= Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

T_A= Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance _JAmust be used. Assuming no air flow and

a multi-layer board, the appropriate value is 33.1°C/W per Table 7 below.

Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:

85°C + 0.791W * 33.1°C/W = 111.2°C. This is below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of

board (multi-layer).

Table 7. Thermal Resistance  for 32-Lead VFQFN, Forced Convection

JA



_JAby Velocity

0

Meters per Second

1

3

Multi-Layer PCB, JEDEC Standard Test Boards

33.1°C/W

28.1°C/W

25.4°C/W

IDT8T49N004ANLGI REVISION A OCTOBER 15, 2013

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IDT8T49N004I Data Sheet

PROGRAMMABLE FEMTOCLOCK^®NG LVPECL/LVDS CLOCK GENERATOR WITH 4-OUTPUTS

3. Calculations and Equations.

The purpose of this section is to calculate the power dissipation for the LVPECL output pair.

LVPECL output driver circuit and termination are shown in Figure 12.

V_CCO

Q1

V_OUT

RL

50Ω

V_CCO- 2V

Figure 10. LVPECL Driver Circuit and Termination

To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of

V_CCO– 2V.

•

For logic high, V_OUT= V_{OH_MAX}= V_{CCO_MAX}– 0.75V

(V_{CCO_MAX}– V_{OH_MAX}) = 0.75V

For logic low, V_OUT= V_{OL_MAX}= V_{CCO_MAX}– 1.6V

(V_{CCO_MAX}– V_{OL_MAX}) = 1.6V

Pd_H is power dissipation when the output drives high.

Pd_L is the power dissipation when the output drives low.

Pd_H = [(V_{OH_MAX}– (V_{CCO_MAX}– 2V))/R_L] * (V_{CCO_MAX}– V_{OH_MAX}) = [(2V – (V_{CCO_MAX}– V_{OH_MAX}))/R_L] * (V_{CCO_MAX}– V_{OH_MAX}) =

[(2V – 0.75V)/50] * 0.75V = 18.75mW

Pd_L = [(V_{OL_MAX}– (V_{CCO_MAX}– 2V))/R_L] * (V_{CCO_MAX}– V_{OL_MAX}) = [(2V – (V_{CCO_MAX}– V_{OL_MAX}))/R_L]* (V_{CCO_MAX}– V_{OL_MAX}) =

[(2V – 1.6V)/50] * 1.6V = 12.80mW

Total Power Dissipation per output pair = Pd_H + Pd_L = 31.55mW

IDT8T49N004ANLGI REVISION A OCTOBER 15, 2013

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IDT8T49N004I Data Sheet

PROGRAMMABLE FEMTOCLOCK^®NG LVPECL/LVDS CLOCK GENERATOR WITH 4-OUTPUTS

LVDS Power Considerations

This section provides information on power dissipation and junction temperature for the IDT8T49N004I.

Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the IDT8T49N004I is the sum of the core power plus the analog power plus the power dissipated in the load(s).

The following is the power dissipation for V_CC= 3.3V +5% = 3.465V, which gives worst case results.

•

Power (core)_MAX= V_{DD_MAX}* (I_{DD_MAX}+ I_{DDA_MAX}) = 3.465V * (125mA + 32mA) = 544mW

Power (outputs)_MAX= V_{DDO_MAX}* I_{DDO_MAX}= 3.465V * 85mA = 294.525mW

Total Power__MAX= 544mW + 294.525mW = 876.645mW

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The

maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond

wire and bond pad temperature remains below 125°C.

The equation for Tj is as follows: Tj = _JA* Pd_total + T_A

Tj = Junction Temperature



_JA= Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

T_A= Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance _JAmust be used. Assuming no air flow and

a multi-layer board, the appropriate value is 33.1°C/W per Table 8 below.

Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:

85°C + 0.877W * 33.1°C/W = 112.8°C. This is below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of

board (multi-layer).

Table 8. Thermal Resistance  for 32-Lead VFQFN, Forced Convection

JA



_JAby Velocity

0

Meters per Second

1

3

Multi-Layer PCB, JEDEC Standard Test Boards

33.1°C/W

28.1°C/W

25.4°C/W

IDT8T49N004ANLGI REVISION A OCTOBER 15, 2013

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IDT8T49N004I Data Sheet

PROGRAMMABLE FEMTOCLOCK^®NG LVPECL/LVDS CLOCK GENERATOR WITH 4-OUTPUTS

Reliability Information

Table 9.  vs. Air Flow Table for a 32-Lead VFQFN

JA



_JAvs. Air Flow

Meters per Second

0

1

3

Multi-Layer PCB, JEDEC Standard Test Boards

33.1°C/W

28.1°C/W

25.4°C/W

Transistor Count

The transistor count for IDT8T49N004I is: 26,856

IDT8T49N004ANLGI REVISION A OCTOBER 15, 2013

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IDT8T49N004I Data Sheet

PROGRAMMABLE FEMTOCLOCK^®NG LVPECL/LVDS CLOCK GENERATOR WITH 4-OUTPUTS

32-Lead VFQFN Package Outline and Dimensions

IDT8T49N004ANLGI REVISION A OCTOBER 15, 2013

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IDT8T49N004I Data Sheet

PROGRAMMABLE FEMTOCLOCK^®NG LVPECL/LVDS CLOCK GENERATOR WITH 4-OUTPUTS

Ordering Information

Table 10. Ordering Information

Part/Order Number

8T49N004A-dddNLGI

8T49N004A-dddNLGI8

Marking

Package

Shipping Packaging

Tray

Temperature

-40C to 85C

IDT8T49N004A-dddNLGI “Lead-Free” 32-Lead VFQFN

Tape & Reel

NOTE: For the specific -ddd order codes, refer to the document Programmable FemtoClock^®NG Product Ordering Guide.

IDT8T49N004ANLGI REVISION A OCTOBER 15, 2013

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IDT8T49N004I Data Sheet

PROGRAMMABLE FEMTOCLOCK^®NG LVPECL/LVDS CLOCK GENERATOR WITH 4-OUTPUTS

Revision History Sheet

Rev

Table

Page

Description of Change

Date

Changed name of the IDT8T49N00xI Programmable FemtoClock^®NG Product Ordering

Information document to Programmable FemtoClock^®Ordering Product Information

Deleted quantity from Tape & Reel, Deleted Lead Free note.

9, 35

A

8/20/2013

T10

35

1

Changed title to Programmable FemtoClock^®NG LVPECL/LVDS Clock Generator with

4-Outputs.

Changed text from ‘Programmable FemtoClock^®Ordering Product Information’ to

‘Programmable FemtoClock^®NG Product Ordering Guide’.

Changed Note from ‘Programmable FemtoClock^®Ordering Product Information’ to

‘Programmable FemtoClock^®NG Product Ordering Guide’.

9

A

9/26/13

T10

T5

35

12

changed the min load capacitance from 12pF to 10pF

10/22/13

IDT8T49N004ANLGI REVISION A OCTOBER 15, 2013

36

IDT8T49N004I Data Sheet

PROGRAMMABLE FEMTOCLOCK^®NG LVPECL/LVDS CLOCK GENERATOR WITH 4-OUTPUTS

We’ve Got Your Timing Solution

6024 Silver Creek Valley Road Sales

Technical Support Sales

800-345-7015 (inside USA)

netcom@idt.com

San Jose, California 95138

+408-284-8200 (outside USA) +480-763-2056

Fax: 408-284-2775

www.IDT.com/go/contactIDT

DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,

including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not

guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the

suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any

license under intellectual property rights of IDT or any third parties.

IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to signifi-

cantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.

Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third

party owners.

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HUTSON	8T44A	[ TRIAC, 400V V(DRM), 4A I(T)RMS, TO-202, ]	2 页
TECCOR	8T44HA	晶闸管产品目录[ Thyristor Product Catalog ]	223 页
HUTSON	8T44HA	[ TRIAC, 400V V(DRM), 4A I(T)RMS, TO-202, ]	2 页
TECCOR	8T44SH	晶闸管产品目录[ Thyristor Product Catalog ]	223 页
HUTSON	8T44SH	[ 4 Quadrant Logic Level TRIAC, 400V V(DRM), 4A I(T)RMS, TO-202, ]	2 页
HUTSON	8T44TH	[ TRIAC, 400V V(DRM), 4A I(T)RMS, TO-202, ]	2 页
HUTSON	8T46HA	[ TRIAC, 400V V(DRM), 6A I(T)RMS, TO-202, ]	2 页
HUTSON	8T46SH	[ 4 Quadrant Logic Level TRIAC, 400V V(DRM), 6A I(T)RMS, TO-202 ]	2 页
HUTSON	8T46TH	[ TRIAC, 400V V(DRM), 6A I(T)RMS, TO-202, ]	2 页
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