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CYP15G0403DX-BGC

型号:

CYP15G0403DX-BGC

品牌:

CYPRESS[ CYPRESS ]

页数:

39 页

PDF大小:

767 K

PRELIMINARY  
CYP15G0403DX  
Independent Clocking Quad HOTLink II™ Transceiver  
copper cables  
Features  
circuit board traces  
• Second-generation HOTLink technology  
• Fibre-Channel- and Gigabit-Ethernet-compliant  
8B/10B-coded or 10-bit unencoded  
JTAG boundary scan  
Built-in Self-test (BIST) for at-speed channel testing  
Per-channel Link Quality Indicator  
Analog signal detect  
• Four independent channels  
— Each channel can operate at a different signaling  
rate  
Digital signal detect  
• 8-bit encoded data transport  
Frequency range detect  
— Equal to a throughput of 9.6 GBits/second  
• 10-bit unencoded data transport  
Low-power 3W typical at +3.3 VCC  
256-ball thermally enhanced BGA package  
0.25µ BiCMOS technology  
— Equal to a throughput of 12 GBits/second  
• Selectable input clocking options  
• Selectable output clocking options  
Functional Description  
• Receive framer provides alignment to COMMA or Full  
K28.5 detect  
The CYP15G0403DX Quad HOTLink IIis a point-to-point  
building block allowing the transfer of data over independent  
high-speed serial links at signaling speeds ranging from  
200-to-1500 MBaud per link. Each channel operates indepen-  
dently with its own reference clock allowing different rates on  
each channel.  
— Single or Multibyte framer for character alignment  
— Low-latency option  
• Synchronous LVTTL parallel input interface  
• Synchronous LVTTL parallel output interface  
• 200- to1500-MBaud serial signaling rate  
• Internal phase-locked loops (PLLs) with no external  
PLL components  
Each transmit channel accepts parallel characters in an Input  
Register, encodes each character for transport, and then  
converts it to serial data. Each receive channel accepts serial  
data and converts it to parallel data, decodes the data into  
characters, and presents these characters to an output  
register. Figure 1 illustrates typical connections between  
• Dual differential PECL-compatible serial inputs per  
channel  
independent  
host  
systems  
and  
corresponding  
• Dual differential PECL-compatible serial outputs per  
channel  
CYP15G0403DX chips. As a second-generation HOTLink  
device, the CYP15G0403DX extends the HOTLink family to  
faster data rates, while maintaining serial-link compatibility  
with other HOTLink devices.  
Outputs are source-matched for 50Ω  
No external bias resistors required  
Controlled edge-rates  
The transmit section of the CYP15G0403DX Quad HOTLink II  
consists of four independent byte-wide channels. Each  
channel can accept either 8-bit data characters or preencoded  
Compatible with  
Fiber-optic modules  
10  
10  
Serial Links  
10  
10  
10  
10  
10  
10  
10  
10  
10  
Serial Links  
10  
10  
10  
Independent  
CYP15G0403DX  
Independent  
CYP15G0403DX  
10  
10  
Serial Links  
Serial Links  
Backplane or  
Cabled  
Connections  
Figure 1. HOTLink II System Connections  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Document #: 38-02033 Rev. *A  
Revised February 21, 2002  
CYP15G0403DX  
PRELIMINARY  
10-bit characters. Data characters are passed from the  
Transmit Input Register to an embedded 8B/10B Encoder.  
These encoded characters are then serialized and output from  
dual Positive ECL compatible differential transmission-line  
drivers at a bit-rate of either 10- or 20-times the input reference  
clock for that channel.  
bypassed. The clocking of the parallel I/O interface may be  
changed to match different system architectures. In additional  
to clocking the transmit path interfaces, the receive interface  
may be configured to present data relative to a recovered  
clock or to a local reference clock.  
Each transmit and receive channel contains independent BIST  
pattern generator and pattern checkers. This BIST hardware  
allows full speed testing of the high-speed serial data paths in  
each transmit and receive section, and across the intercon-  
necting links.  
The receive section of the CYP15G0403DX Quad HOTLink II  
consists of four independent byte-wide channels. Each  
channel accepts a serial bit-stream from one of two  
PECL-compatible differential line receivers and, using a  
completely integrated PLL Clock Synchronizer, recovers the  
timing information necessary for data reconstruction. Each  
recovered bit-stream is deserialized and framed into  
characters, 8B/10B decoded, and checked for transmission  
errors. Recovered decoded characters are then written to an  
internal Elasticity Buffer, and presented to the destination host  
system. The integrated 8B/10B encoder/decoder may be  
HOTLink II devices are ideal for a variety of applications where  
parallel interfaces can be replaced with high-speed,  
point-to-point serial links.Some applications include intercon-  
necting backplanes on switches, routers, servers and video  
transmission systems  
Transceiver Logic Block Diagram  
×10  
×10  
×10  
×10  
×11  
×11  
×11  
×11  
Phase  
Align  
Buffer  
Phase  
Align  
Buffer  
Phase  
Align  
Buffer  
Phase  
Align  
Buffer  
Elasticity  
Buffer  
Elasticity  
Buffer  
Elasticity  
Buffer  
Elasticity  
Buffer  
Decoder  
8B/10B  
Decoder  
8B/10B  
Decoder  
8B/10B  
Encoder  
8B/10B  
Decoder  
8B/10B  
Encoder  
8B/10B  
Encoder  
8B/10B  
Encoder  
8B/10B  
Framer  
Framer  
Framer  
Framer  
Serializer  
Serializer  
Deserializer  
Deserializer  
Serializer  
Deserializer  
Serializer  
Deserializer  
RX  
RX  
RX  
RX  
TX  
TX  
TX  
TX  
Document #: 38-02033 Rev. *A  
Page 2 of 39  
CYP15G0403DX  
PRELIMINARY  
Transmit Path Block Diagram  
= Internal Signal  
REFCLKA+  
REFCLKA–  
Bit-Rate Clock  
TransmitPLL
ClockMultiplier
TXRATE  
SPDSELA  
TXCLKOA  
TX BYPASS [A..D]  
Character-Rate Clock  
OUTPUT  
TXERRA  
TXCLKA  
ENABLE[A1..D2]  
TX BIST  
ENABLE[A..D]  
8
H__ L  
TXCLKSEL[A]  
8
OUTA1+  
OUTA1–  
TXDA  
TXCTA  
10  
10  
10  
10  
2
OUTA2+  
OUTA2–  
REFCLKB+  
REFCLKB  
Bit-Rate Clock  
–  
Transmit PLL  
Clock Multiplier  
TXRATE  
SPDSELB  
TXCLKOB  
Character-Rate Clock  
TXERRB  
TXCLKB  
H L  
TXCLKSEL[B]  
OUTB1+  
OUTB1–  
8
10  
10  
10  
10  
TXDB  
OUTB2+  
OUTB2–  
2
TXCTB  
REFCLKC+  
REFCLKC–  
Bit-Rate Clock  
Transmit PLL  
Clock Multiplier  
TXRATE  
SPDSELC  
TXCLKOC  
Character-Rate Clock  
TXERRC  
TXCLKC  
H L  
TXCLKSEL[C]  
8
OUTC1+  
OUTC1–  
TXDC  
10  
10  
10  
10  
2
OUTC2+  
OUTC2–  
TXCTC  
REFCLKD+  
REFCLKD–  
Bit-Rate Clock  
Transmit PLL  
Clock Multiplier  
TXRATE  
SPDSELD  
TXCLKOD  
TXERRD  
Character-Rate Clock  
TXCLKD  
H L  
TXCLKSEL[D]  
OUTD1+  
OUTD1–  
10  
8
10  
10  
10  
TXDD  
OUTD2+  
OUTD2–  
2
TXCTD  
Document #: 38-02033 Rev. *A  
Page 3 of 39  
CYP15G0403DX  
PRELIMINARY  
Receive Path Block Diagram  
=
Internal Signal  
TRSTZ  
RLE  
RX PLL Enable  
Latch  
BOE[3:0]  
TMS  
TCLK  
TDI  
JTAG  
Boundary  
Scan  
BYTE CLOCK[A..D]  
SDASEL  
Controller  
TDO  
LFIA  
LPEN[A..D]  
Receive  
Signal  
INSELA  
Monitor  
INA1+  
INA1–  
8
RXDA[7:0]  
INA2+  
INA2–  
Clock &  
Data  
3
Recovery  
PLL  
RXSTA[2:0]  
TXLBA  
Clock  
Select  
RXCLKA+  
RXCLKA–  
÷
2
Receive  
Signal  
INSELB  
LFIB  
Monitor  
INB1+  
INB1–  
8
RXDB[7:0]  
INB2+  
INB2–  
Clock &  
Data  
Recovery  
PLL  
3
TXLBB  
RXSTB[2:0]  
Clock  
Select  
RXCLKB+  
RXCLKB–  
÷
2
Receive  
Signal  
INSELC  
LFIC  
Monitor  
INC1+  
INC1–  
8
RXDC[7:0]  
INC2+  
INC2–  
Clock &  
Data  
3
Recovery  
PLL  
RXSTC[2:0]  
TXLBC  
Clock  
Select  
RXCLKC+  
RXCLKC–  
÷
2
Receive  
Signal  
Monitor  
LFID  
INSELD  
IND1+  
8
RXDD[7:0]  
IND1–  
IND2+  
IND2–  
Clock &  
Data  
3
Recovery  
PLL  
RXSTD[2:0]  
TXLBD  
Clock  
Select  
RXCLKD+  
RXCLKD–  
RBIST[D:A]  
FRAMCHAR[A..D]  
RXRATE  
÷
2
RFEN[A..D]  
RFMODE[A..D]  
RX CLK SEL  
BYPASS  
Document #: 38-02033 Rev. *A  
Page 4 of 39  
CYP15G0403DX  
PRELIMINARY  
Pin Configuration (Top View)  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
INC1-  
OUT  
C1-  
INC2-  
OUT  
C2-  
IND1-  
OUT  
D1-  
IND2-  
OUT  
D2-  
INA1-  
OUT  
A1-  
INA2-  
OUT  
A2-  
INB1-  
OUT  
B1-  
INB2-  
OUT  
B2-  
A
B
C
D
VCC  
VCC  
VCC  
VCC  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
VCC  
VCC  
VCC  
VCC  
INC1+  
TDI  
OUT  
C1+  
INC2+  
OUT  
C2+  
IND1+  
OUT  
D1+  
IND2+  
BOE[7]  
BOE[6]  
OUT  
D2+  
INA1+  
BOE[3]  
BOE[2]  
OUT  
A1+  
INA2+  
OUT  
A2+  
INB1+  
OUT  
B1+  
INB2+  
OUT  
B2+  
TMS  
IN  
SELC  
IN  
SELB  
FRAM  
CHAR  
B
FRAM  
CHAR  
C
BOE[5]  
BOE[4]  
BOE[1]  
BOE[0]  
SDA  
SEL  
SPD  
SELD  
TX  
RATE  
RX  
RATE  
LP  
END  
TDO  
RFMO  
DELE  
TCLK  
TRSTZ  
IN  
SELD  
IN  
SELA  
FRAM  
CHAR  
A
SPD  
SELC  
LP  
ENB  
FRAM  
CHAR  
D
LP  
ENA  
RF  
ENA  
RF  
ENB  
E
F
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
TX  
ERRC  
RF  
END  
TX  
DC[0]  
RF  
ENC  
BIST  
LE  
RX  
STB[1]  
TX  
CLKO  
B
RX  
STB[0]  
TX  
DC[7]  
CLKS  
EL  
LE  
TX  
DC[4]  
TX  
DC[1]  
SPD  
SELB  
LP  
ENC  
SPD  
SELA  
RX  
DB[1]  
G
H
J
GND GND GND GND  
GND GND GND GND  
TX  
TX  
DC[5]  
TX  
DC[2]  
TX  
DC[3]  
RX  
RX  
DB[0]  
RX  
DB[5]  
RX  
DB[2]  
CTC[1]  
STB[2]  
]
RX  
DC[2]  
REFC  
LKC-  
TXCT  
C[0]  
LFIC  
RX  
DB[3]  
RX  
DB[4]  
RX  
DB[7]  
RXCL  
KB+  
K
L
RX  
DC[3]  
REFC  
LK  
C+  
TX  
CLKC  
TX  
DC[6]  
RX  
DB[6]  
LFIB  
RX  
CLKB-  
TX  
DB[6]  
RX  
RX  
RX  
RX  
REFC  
LKB+  
REFC  
LKB-  
TX  
TX  
M
N
P
R
T
DC[4]  
DC[5]  
DC[7]  
DC[6]  
DB[7]  
CLKB  
GND GND GND GND  
GND GND GND GND  
RX  
DC[1]  
RX  
DC[0]  
RX  
STC[0]  
RX  
STC[1]  
TX  
DB[5]  
TX  
DB[4]  
TX  
DB[3]  
TX  
DB[2]  
RXST  
C[2]  
TXCLK  
OC  
RXCL  
K
C+  
RX  
CLK  
C-  
TX  
DB[1]  
TX  
DB[0]  
TX  
CTB[1]  
TX  
ERRB  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
TX  
TX  
TX  
TX  
RX  
RX  
TX  
RLE  
REFC  
LK  
TX  
TX  
TX  
RX  
TX  
RX  
RX  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
U
V
W
Y
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
DD[0]  
DD[1]  
DD[2]  
CTD[1]  
DD[2]  
DD[1]  
ERRD  
DA[1]  
DA[4]  
CTA[0]  
DA[2]  
CTB[0]  
STA[2]  
STA[1]  
D-  
TX  
DD[3]  
TX  
DD[4]  
TX  
CTD[0]  
RX  
DD[6]  
RX  
DD[3]  
RX  
STD[0]  
RX  
STD[2]  
BYPA  
SS  
LE  
REFC  
LK  
D+  
TX  
CLKO  
A
TX  
DA[3]  
TX  
DA[7]  
RX  
DA[7]  
RX  
DA[3]  
RX  
DA[0]  
RX  
STA[0]  
TX  
DD[5]  
TX  
DD[7]  
LFID  
RXCL  
K
D-  
RX  
DD[4]  
RX  
STD[1]  
OELE  
TX  
RST  
RX  
CLKA+  
TX  
ERRA  
TX  
DA[2]  
TX  
DA[6]  
LFIA  
REF  
CLK  
A+  
RX  
DA[4]  
RX  
DA[1]  
TXCLK  
OD  
TX  
DD[6]  
TXCLK  
D
RX  
DD[7]  
RXCL  
K
D+  
RX  
DD[5]  
RX  
DD[0]  
N/C  
TX  
CLKA  
RX  
CLKA-  
TX  
DA[0]  
TX  
DA[5]  
TX  
CTA[1]  
REF  
CLK  
A-  
RX  
DA[6]  
RX  
DA[5]  
Document #: 38-02033 Rev. *A  
Page 5 of 39  
CYP15G0403DX  
PRELIMINARY  
Pin Configuration (Bottom View)  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
OUT  
B2-  
INB2-  
OUT  
B1-  
INB1-  
OUT  
A2-  
INA2-  
OUT  
A1-  
INA1-  
OUT  
D2-  
IND2-  
OUT  
D1-  
IND1-  
OUT  
C2-  
INC2-  
OUT  
C1-  
INC1-  
A
B
C
VCC  
VCC  
VCC  
GND  
GND  
GND  
GND  
GND  
GND  
VCC  
VCC  
VCC  
OUT  
B2+  
INB2+  
OUT  
B1+  
INB1+  
OUT  
A2+  
INA2+  
OUT  
A1+  
INA1+  
OUT  
D2+  
IND2+  
OUT  
D1+  
IND1+  
OUT  
C2+  
INC2+  
OUT  
C1+  
INC1+  
TDI  
TDO  
LP  
END  
RX  
RATE  
TX  
RATE  
SPD  
SELD  
SDA  
SEL  
BOE[1]  
BOE[0]  
BOE[3]  
BOE[5]  
BOE[4]  
BOE[7]  
FRAM  
CHAR  
C
FRAM  
CHAR  
B
IN  
SELB  
IN  
SELC  
TMS  
TRSTZ  
VCC  
RFMO  
DELE  
RF  
ENB  
RF  
ENA  
LP  
ENA  
FRAM  
CHAR  
D
LP  
ENB  
BOE[2]  
BOE[6]  
SPD  
SELC  
FRAM  
CHAR  
A
IN  
SELA  
IN  
SELD  
TCLK  
D
VCC  
GND  
GND  
VCC  
E
F
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
RX  
STB[0]  
TX  
CLKO  
B
RX  
STB[1]  
BIST  
LE  
RF  
ENC  
TX  
DC[0]  
RF  
END  
TX  
ERRC  
RX  
SPD  
LP  
SPD  
TX  
TX  
CLKS  
EL  
TX  
G
H
J
DB[1]  
SELA  
ENC  
SELB  
DC[1]  
DC[4]  
DC[7]  
LE  
GND GND GND GND  
GND GND GND GND  
RX  
DB[2]  
RX  
DB[5]  
RX  
DB[0]  
RX  
STB[2]  
TX  
DC[3]  
TX  
DC[2]  
TX  
DC[5]  
TX  
CTC[1]  
RXCL  
KB+  
RX  
RX  
RX  
LFIC  
TXCT  
C[0]  
REFC  
LKC-  
RX  
K
L
DB[7]  
DB[4]  
DB[3]  
DC[2]  
TX  
DB[6]  
RX  
CLKB-  
LFIB  
RX  
DB[6]  
TX  
DC[6]  
TX  
CLKC  
REFC  
LK  
C+  
RX  
DC[3]  
TX  
TX  
REFC  
LKB-  
REFC  
LK+  
RX  
RX  
RX  
RX  
M
N
P
R
T
CLKB  
DB[7]  
DC[6]  
DC[7]  
DC[5]  
DC[4]  
GND GND GND GND  
GND GND GND GND  
TX  
DB[2]  
TX  
DB[3]  
TX  
DB[4]  
TX  
DB[5]  
RX  
STC[1]  
RX  
STC[0]  
RX  
DC[0]  
RX  
DC[1]  
TX  
ERRB  
TX  
CTB[1]  
TX  
DB[0]  
TX  
DB[1]  
RX  
CLK  
C-  
RXCL  
K
C+  
TXCLK  
OC  
RXST  
C[2]  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
RX  
RX  
TX  
RX  
TX  
TX  
TX  
REFC  
LK  
RLE  
TX  
RX  
RX  
TX  
TX  
TX  
TX  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
U
V
W
Y
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
STA[1]  
STA[2]  
CTB[0]  
DA[2]  
CTA[0]  
DA[4]  
DA[1]  
ERRD  
DD[1]  
DD[2]  
CTD[1]  
DD[2]  
DD[1]  
DD[0]  
D-  
RX  
STA[0]  
RX  
DA[0]  
RX  
DA[3]  
RX  
DA[7]  
TX  
DA[7]  
TX  
DA[3]  
TX  
CLKO  
A
REFC  
LK  
D+  
BYPA  
SS  
LE  
RX  
STD[2]  
RX  
STD[0]  
RX  
DD[3]  
RX  
DD[6]  
TX  
CTD[0]  
TX  
DD[4]  
TX  
DD[3]  
RX  
DA[1]  
RX  
DA[4]  
REF  
CLK  
A-  
LFIA  
TX  
DA[6]  
TX  
DA[2]  
TX  
ERRA  
RX  
CLKA+  
TX  
RST  
OELE  
RX  
STD[1]  
RX  
DD[4]  
RXCL  
K
D-  
LFID  
TX  
DD[7]  
TX  
DD[5]  
TXCLK  
OD  
RX  
DA[5]  
RX  
DA[6]  
REF  
CLK  
A+  
TX  
CTA[1]  
TX  
DA[5]  
TX  
DA[0]  
RX  
CLKA-  
TX  
CLKA  
N/C  
RX  
DD[0]  
RX  
DD[5]  
RXCL  
K
D+  
RX  
DD[7]  
TXCLK  
D
TX  
DD[6]  
Document #: 38-02033 Rev. *A  
Page 6 of 39  
CYP15G0403DX  
PRELIMINARY  
Pin Descriptions  
Name  
I/O Characteristics  
Signal Description  
Transmit Path Data and Status Signals  
TXERRA  
TXERRB  
TXERRC  
TXERRD  
LVTTL Output,  
Transmit Path Error. When signal is HIGH, indicates detection of transmit Phase-Align  
changes relative to Buffer underflow or overflow. If an underflow or overflow condition is detected, TXERRx  
REFCLKx[1]  
is high until either a Word Sync Sequence is transmitted on that channel, or TXRST is  
reset LOW to recenter the transmit Phase-Align Buffers. When BIST is enabled for a  
transmit channel, BIST progress is presented on the associated TXERRx output. Once  
every 511 character times, the associated TXERRx signal pulses HIGH for one  
transmit-character clock period to indicate a pass through the BIST bit sequence.  
TXCTA[1:0]  
TXCTB[1:0]  
TXCTC[1:0]  
TXCTD[1:0]  
LVTTL Input,  
synchronous,  
sampled by the  
associated  
Transmit Control. These inputs are captured on the rising edge of the transmit interface  
clock and are passed to the data encoder. They identify the type of character captured  
on the associated TXDx[7:0] inputs. If the encoder is bypassed, these inputs are input  
data bits. When the encoder is enabled, these inputs determine if the TXDx[7:0] character  
is encoded as Data, a Special Character code, or replaced with an Special Character  
codes (see Table 3 for details).  
TXCLKx]or  
REFCLKx[1]  
TXDA[7:0]  
TXDB[7:0]  
TXDC[7:0]  
TXDD[7:0]  
LVTTL Input,  
synchronous,  
sampled by the  
associated  
Transmit Data Inputs. These data inputs are captured on the rising edge of the transmit  
interface clock and passed to the encoder. When the encoder is enabled, TXDx[7:0] is  
the data to be encoded for transport over the serial link.  
TXCLKxor  
REFCLKx[1]  
Transmit Path Control and Clock Signals  
TXRST  
LVTTL Input,  
asynchronous,  
internal pull-up,  
sampled by  
TransmitClock PhaseResetWhen LOW. ThetransmitPhase-Align Buffersareallowed  
to adjusttheir data-transfer timingtoallow error freetransfer ofdatafrom the input register  
to the encoder. When TXRST is HIGH, the internal phase relationship between the  
associated input clock and the internal character-rate clock is fixed. During Phase Reset  
alignment period, one or more characters may be added to or lost from the associated  
transmit paths This process may continue until phase of recovered clock and the  
reference clock are matched. TXRST must be LOW for a minimum of two consecutive  
rising edges of TXCLKx or REFCLKxto ensuring a correct reset.  
TXCLKxor  
REFCLKx[1]  
TXCLKOA  
TXCLKOB  
TXCLKOC  
TXCLKOD  
LVTTL Output  
TransmitClock Output. Theseoutputclocks aresynthesizedby eachchannelstransmit  
PLL and operate synchronous to the internal transmit character clock. Each clock  
operates at either the same frequency as the associated REFCLKx, or at twice the  
frequency of the associated REFCLKx as selected by TXRATE. TXCLKOx is always  
equal to the transmit VCO bit-clock frequency ÷10. These output clocks have no fixed  
phase relationship to REFCLKx.  
TXRATE  
LVTTL Input,  
Transmit PLL Clock Rate Select. When TXRATE = HIGH, the Transmit PLL multiplies  
Static Control input, all REFCLKx inputs by 20 to generate the serial bit-rate clock. When TXRATE = LOW,  
internal pull-down each transmit PLL multiples the associated REFCLKx by 10 to generate the serial bit-rate  
clock. See Table 5 for a list of operating serial rates. When REFCLKx is selected for  
clocking of the receive parallel interface, the TXRATE input also determines if the clock  
on the RXCLKx± outputs are a full or half-rate clock. When TXRATE = HIGH, these output  
clocks are half-rate clocks and follow the frequency and duty cycle of the REFCLKx input.  
When TXRATE = LOW, these output clocks are full-rate clocks and follow the frequency  
and duty cycle of the REFCLKx input.  
TXCLKA  
TXCLKB  
TXCLKC  
TXCLKD  
LVTTL Clock Input, Transmit Path Input Clocks. When selected as an input sample clock, each transmit  
internal pull-down clock will be frequency-coherent to its TXCLKOx clock, but not have a fixed phase reala-  
tionship. The internal operating phase of each input clock relative to its associated  
REFCLKx is adjusted when TXRST = LOW and locked when TXRST = HIGH.  
Receive Path Data Signals  
RXDA[7:0]  
RXDB[7:0]  
RXDC[7:0]  
RXDD[7:0]  
LVTTL Output,  
synchronous to the interface clock.  
Parallel Data Output. These outputs change following the falling edge of the receive  
selected RXCLKx↑  
output or  
REFCLKx[1] input  
Note:  
1. When REFCLKx is configured for half-rate operation (TXRATE = HIGH), these inputs are sampled relative to both the rising and falling edges of the associated  
REFCLKx.  
Document #: 38-02033 Rev. *A  
Page 7 of 39  
CYP15G0403DX  
PRELIMINARY  
Pin Descriptions (continued)  
Name  
I/O Characteristics  
Signal Description  
Parallel Status Output. These outputs change following the falling edge of the receive  
RXSTA[2:0]  
RXSTB[2:0]  
RXSTC[2:0]  
RXSTD[2:0]  
LVTTL Output,  
synchronous to the interface clock. When the decoder is bypassed, RXSTx[1:0] become the two low-order  
selected RXCLKxbits of the 10-bit received character, while RXSTx[2] = HIGH indicates the presence of  
output or  
the selected framing character in the output register.  
REFCLKx[1] input  
Receive Control and Clock Signals  
RXCLKA±  
RXCLKB±  
RXCLKC±  
RXCLKD±  
Three-state, LVTTL Receive Character Clock Output. These true and complement clocks are the Receive  
Output clock  
interface clocks which are used to control timing of data output transfers. These clocks  
are output continuously at either at half character rate or at the character rate of the data  
being received, as selected by RXRATE. When configured such that all output data paths  
are clocked by the REFCLKx instead of a recovered clock, the RXCLKx± output drivers  
present a buffered form of the associated REFCLKx. RXCLKx± are buffered forms of  
REFCLKx that are delayed in phase to align with the data. This phase difference allows  
the user to select the optimal clock (REFCLKx or RXCLKx) for setup/hold timing for their  
specific interface.  
RXRATE  
LVTTL Input  
Receive Clock Rate Select. When LOW, the RXCLKx± recovered clock outputs are  
Static Control Input, complementary clocks operating at the recovered character rate. Data for the associated  
internal pull-down receive channels should be latched on the rising edge of RXCLKx+ or falling edge of  
RXCLKx. When HIGH, the RXCLKx± recovered clock outputs are complementary  
clocks operating at half the character rate. Data for the associated receive channels  
should be latched alternately on the rising edge of RXCLKx+ and RXCLKx. When  
operated with REFCLKx clocking of the received parallel data outputs, the RXRATE input  
is not used.  
RFENA  
RFENB  
RFENC  
RFEND  
LVTTL input,  
asynchronous,  
internal pull-down  
Reframe Enable. When RFENx is HIGH, the associated channels framer is enabled to  
frame per the presently enabled framing mode.  
FRAMCHARA  
FRAMCHARB  
FRAMCHARC  
FRAMCHARD  
3-Level Select [2]  
Framing Character Select. Used to control the character or portion of a character used  
Static Control Input for character framing of each channels received data streams. When LOW, the framer  
looks for an 8-bit positive COMMA character in the data stream. When MID, the framer  
looks for both positive and negative disparity versions of the 8-bit COMMA character.  
When HIGH, the framer looks for both positive and negative disparity versions of the  
K28.5 character.  
Device Control Signals  
SPDSELA  
SPDSELB  
SPDSELC  
SPDSELD  
3-Level Select [2]  
static configuration channels transmit and receive PLLs.  
,
Serial Rate Select. These inputs specify the operating signaling-rate range of each  
input  
LOW = 200400 MBaud  
MID = 400800 MBaud  
HIGH = 8001500 MBaud  
REFCLKA±  
REFCLKB±  
REFCLKC±  
REFCLKD±  
DifferentialLVPECL Reference Clock. This clock input is used as the timing reference for the transmit and  
or single-ended receive PLLs. This input clock may also be selected to clock the transmit and receive  
LVTTL input clock parallel interfaces. For LVTTL input clock, connect clock source to a REFCLK input and  
float the other REFCLK input. For an LVPECL input level input clock has to be a differ-  
ential clock, using both inputs.  
Note:  
2. 3-Level select inputs are used for static configuration. They are ternary inputs that make use of logic levels of LOW, MID, and HIGH. The LOW level is usually  
implemented by direct connection to VSS (ground). The HIGH level is usually implemented by direct connection to VCC (power). When not connected or allowed  
to float, a 3-Level select input will self-bias to the MID level.  
Document #: 38-02033 Rev. *A  
Page 8 of 39  
CYP15G0403DX  
PRELIMINARY  
Pin Descriptions (continued)  
Name  
I/O Characteristics  
Signal Description  
Latch Control Signals and Bus  
BOE[7:0]  
LVTTL Input,  
asynchronous,  
internal pull-up  
Latch Control Data Bus. These inputs are passed to the output enablelatch when OELE  
is HIGH, and captured in this latch when OELE returns LOW. These inputs are passed  
to the BIST enable latch when BISTLE is HIGH, and captured in this latch when BISTLE  
returns LOW. These inputs are passed to the Receive channel enable/decoder mode  
latch when RLE is HIGH, and captured in this latch when RLE returns LOW. These inputs  
are passed to the transmit and receive clock select latch when CLKSELLE is HIGH, and  
captured in this latch when CLKSELLE returns LOW. These inputs are passed to the  
encoder/decoder bypass latchwhen BYPASSLE is HIGH, and captured in this latch when  
BYPASSLE returns LOW. These inputs are passed to the reframe mode enable latch  
when RFMODELE is HIGH, and captured in this latch when RFMODELE returns LOW.  
CLKSELLE  
LVTTL input,  
asynchronous,  
internal pull-up  
Clock Select Latch Enable. Selects the clock source, that is used to write data into the  
channels transmit input register and the receive clock-source is used to transfer data to  
the output registers. When CKSELLE is HIGH, the signals on the BOE[7:0] inputs directly  
control the channel input and output register clock. When BOE[x] is HIGH the input or  
output register is clocked by the associated REFCLKx. When BOE[x] is LOW, the input  
register clock is TXCLKx, and the output registers are clocked by the channels recovered  
clock (see Table 4 for details).  
BYPASSLE  
OELE  
LVTTL input,  
asynchronous,  
internal pull-up  
Encoder/Decoder Latch Enable. When BYPASSLE = HIGH, signals on the BOE[7:0]  
inputs directly control the encoder and decoder enables for each channel. When BOE[x]  
is LOW, the encoder or decoder is bypassed and raw 10-bit characters are transmitted  
or received (see Table 4 for details).  
LVTTL Input,  
asynchronous,  
internal pull-up  
Serial Driver Output Enable Latch Enable. When OELE = HIGH, the signals on the  
BOE[7:0] inputs directly control the OUTxy± differential drivers. When the BOE[x] input  
is HIGH, the associated OUTxy± differential driver is enabled. When the BOE[x] input is  
LOW, the associated OUTxy± differential driver is powered down. When OELE returns  
LOW, the last values present on BOE[7:0] are captured in the internal Output Enable  
latch. The specific mapping of BOE[7:0] signals to transmit output enables is listed in  
Table 4. When the latch is reset by TRSTZ, all outputs are reset to disable all outputs.  
RFMODELE  
LVTTL Input,  
asynchronous,  
internal pull-up  
Reframe Mode Latch Enable. When RFMODELE = HIGH, the signals on the BOE[7:0]  
inputs directly control the type of character framing used to adjust the character bound-  
aries. This signal operates in conjunction with the type of framing character selected.  
When BOE[x,x-1] = 00, the low-latency framer is selected. This will frame on each occur-  
rence of the selected framing character in the received data stream. This mode of framing  
stretches the recovered clock for one or multiple cycles to align that clock with the  
recovered data. When BOE[x,x-1] = 01, the alternate mode multi-byte parallel framer is  
selected. This requires detection of the selected framing character of the allowed dispar-  
ities in the received data stream, on identical 10-bit boundaries, on four directly adjacent  
characters. The recovered character clock remains in the same phasing regardless of  
character offset. When BOE[x,x-1]=10, the Cypress-mode multi-byte parallel framer is  
selected. This requires a pair of the selected framing character, on identical 10-bit bound-  
aries, within a span of 50 bits, before the character boundaries are adjusted. The  
recovered character clock remains in the same phasing regardless of character offset.  
See Table 4. BOE[x,x-1] = 11 is reserved for test. When RFMODELE returns low the last  
value present on BOE[7:0] are captures in the internal reframe mode latch. If the device  
is reset by TRSTZ, the latch defaults to the 01 mode to activate the alternate mode  
multi-byte framer.  
BISTLE  
LVTTL Input,  
asynchronous,  
internal pull-up  
Transmit and Receive BIST Latch Enable. When BISTLE = HIGH, the signals on the  
BOE[7:0] inputs directly control the transmit and receive BIST enables. When BOE[x]  
input is LOW, the associated transmit or receive channel is configured to generate or  
compare the BIST sequence. When the BOE[x] input is HIGH, the associated transmit  
or receive channel is configured for normal data transmission or reception. When BISTLE  
returns LOW, the last values present on BOE[7:0] are captured in the internal BIST  
Enable latch. The specific mapping of BOE[7:0] signals to transmit and receive BIST  
enables is listed in Table 4. If the device is reset by TRSTZ, the latch is set to an all HIGH  
state to disable BIST on all transmit and receive channels.  
Document #: 38-02033 Rev. *A  
Page 9 of 39  
CYP15G0403DX  
PRELIMINARY  
Pin Descriptions (continued)  
Name  
I/O Characteristics  
Signal Description  
RLE  
LVTTL Input,  
asynchronous,  
internal pull-up  
Receive Channel Power-Control/Decoder Special Character Table. When  
RLE is HIGH, the signals on the BOE[7:0] inputs directly control the power enables for  
the receive PLLs, analog logic and the decoder special character table. When a  
BOE[6,4,2,0] input is HIGH, the PLL and analog logic associated with matching receive  
channel A through D are active. When a BOE[6,4,2,0] input is LOW, the PLL and analog  
logic associated with matching receive channel A through D are placed in a power down  
mode. When RLE is HIGH, the signals on the BOE[7,5,3,1] directly control which special  
character table the decoder will use. When BOE[x] = LOW, the alternate table is used.  
When BOE[x] = HIGH, the Cypress table is used. The specific mapping of BOE[7:0]  
signals to the associated channel is listed in Table 4. When RLE returns LOW, the last  
values present on BOE[7:0] are captured in the internal RX PLL Enable and decoder  
special character table latches. If the device is reset by TRSTZ, the latch is reset to  
disable all receive channels and disable the use of the alternate special character table.  
Analog I/O and Control  
OUTA1±  
OUTB1±  
OUTC1±  
OUTD1±  
CML Differential  
Output  
Primary Differential Serial Data Outputs. These PECL-compatible CML outputs are  
capable of driving terminated transmission lines or standard fiber-optic transmitter  
modules. These outputs must be AC-coupled for PECL-compatible connections.  
OUTA2±  
OUTB2±  
OUTC2±  
OUTD2±  
CML Differential  
Output  
Secondary Differential Serial Data Outputs. These PECL-compatible CML outputs are  
capable of driving terminated transmission lines or standard fiber-optic transmitter  
modules. These outputs must be AC-coupled for PECL-compatible connections.  
INA1±  
INB1±  
INC1±  
IND1±  
LVPECLDifferential Primary Differential Serial Data Inputs. These inputs accept the serial data stream for  
Input  
deserialization and decoding. The INx1± serial streams are passed to the receiver Clock  
and Data Recovery (CDR) circuits to extract the data content when INSELx = HIGH.  
INA2±  
INB2±  
INC2±  
IND2±  
LVPECLDifferential Secondary Differential Serial Data Inputs. These inputs accept the serial data stream  
Input  
for deserialization and decoding. The INx2± serial streams are passed to the receiver  
CDR circuits to extract the data content when INSELx = LOW.  
INSELA  
INSELB  
INSELC  
INSELD  
LVTTL Input,  
asynchronous  
Receive Input Selector. Determines which external serial bit stream is passed to the  
receiver CDR circuit. When HIGH, the INx1± input is selected. When LOW, the INx2±  
input is selected.  
SDASEL  
3-Level Select [2]  
,
Signal Detect Amplitude Level Select. Allows selection of one of three predefined  
static configuration amplitude trip points for a valid signal indication, as listed in Table 6.  
input  
LPENA  
LPENB  
LPENC  
LPEND  
LVTTL Input,  
asynchronous,  
internal pull-up  
Loop-Back-Enable.  
When HIGH, the transmit serial data from the associated channel is internally routed to  
the associated receiver CDR circuit. All enabled serial drivers on the selected channel  
are forced to differential logic-1, and the serial data inputs are ignored.  
LFIA  
LFIB  
LFIC  
LFID  
LVTTL Output,  
Link Fault Indication Output. Active LOW. LFI is the logical OR of four internal condi-  
synchronous to the tions: 1. received serial data frequency outside expected range; 2. analog amplitude  
selected RXCLKxbelow expected levels; 3. transition density lower than expected; and 4. receive channel  
output or  
disabled.  
REFCLKx[1] input,  
asynchronous to  
receive channel  
enable/disable  
JTAG Interface  
TMS  
LVTTL Input,  
internal pull-up  
Test Mode Select. Used to control access to the JTAG Test Modes. If maintained HIGH  
for 5 TCLK cycles, the JTAG test controller is reset.  
TCLK  
TDO  
LVTTL Input,  
internal pull-down  
JTAG Test Clock  
Three-State  
LVTTL Output  
Test Data Out. JTAG data output buffer which is High-Z while JTAG test mode is not  
selected.  
Document #: 38-02033 Rev. *A  
Page 10 of 39  
CYP15G0403DX  
PRELIMINARY  
Pin Descriptions (continued)  
Name  
I/O Characteristics  
Signal Description  
Test Data In. JTAG data input port.  
TDI  
LVTTL Input,  
internal pull-up  
TRSTZ  
LVTTL Input,  
internal pull-up  
Test Port and Device Reset. Active LOW. Initializes the JTAG controller and all state  
machines and counters in the device. When asserted (LOW), this input asynchronously  
resets the JTAG test access port controller. When sampled LOW by the rising edge of  
REFCLKx, this input resets the internal state machines and sets the Elasticity Buffer  
pointers to a nominal offset. When the reset is removed (TRSTZ sampled HIGH by  
REFCLKx), the status and data outputs will become deterministic in less than 16  
REFCLKx cycles. The BISTLE, OELE, CLKSELLE, BYPASSLE and RLE latches are  
reset by TRSTZ.  
Power  
VCC  
+3.3V power  
GND  
Signal and power ground for all internal circuits  
Document #: 38-02033 Rev. *A  
Page 11 of 39  
CYP15G0403DX  
PRELIMINARY  
PIN  
A01  
A02  
A03  
A04  
A05  
A06  
A07  
A08  
A09  
A10  
A11  
A12  
A13  
A14  
A15  
A16  
A17  
A18  
A19  
A20  
B01  
B02  
B03  
B04  
B05  
B06  
B07  
B08  
B09  
B10  
B11  
B12  
B13  
B14  
B15  
B16  
B17  
B18  
B19  
B20  
C01  
C02  
C03  
C04  
C05  
PIN NAME  
INC1-  
PIN TYPE  
PIN  
PIN NAME  
PIN TYPE  
Serial Differential Receiver (-)  
CML Differential Output (-)  
Serial Differential Receiver (-)  
CML Differential Output (-)  
C06 FRAMCHARB 3-level select  
C07 FRAMCHARC 3-level select  
C08 GND  
OUTC1-  
INC2-  
OUTC2-  
VCC  
C09 BOE<7>  
C10 BOE<5>  
C11 BOE<3>  
C12 BOE<1>  
C13 GND  
LVTTL input w/ pull-up  
LVTTL input w/ pull-up  
LVTTL input w/ pull-up  
LVTTL input w/ pull-up  
IND1-  
Serial Differential Receiver (-)  
CML Differential Output (-)  
OUTD1-  
GND  
IND2-  
Serial Differential Receiver (-)  
CML Differential Output (-)  
Serial Differential Receiver (-)  
CML Differential Output (-)  
C14 SDASEL  
3-level select  
OUTD2-  
INA1-  
C15 SPDSELD 3-level select  
C16 VCC  
OUTA1-  
GND  
C17 TXRATE  
C18 RXRATE  
C19 LPEND  
C20 TDO  
LVTTL input w/ pull-down  
LVTTL input w/ pull-down  
LVTTL input w/ pull-down  
three-state LVTTL Output  
LVTTL input w/ pull-down  
LVTTL input w/ pull-up  
LVTTL input  
INA2-  
Serial Differential Receiver (-)  
CML Differential Output (-)  
OUTA2-  
VCC  
D01 TCLK  
INB1-  
Serial Differential Receiver (-)  
CML Differential Output (-)  
Serial Differential Receiver (-)  
CML Differential Output (-)  
Serial Differential Receiver (+)  
CML Differential Output (+)  
Serial Differential Receiver (+)  
CML Differential Output (+)  
D02 /TRSTZ  
D03 INSELD  
D04 INSELA  
D05 VCC  
OUTB1-  
INB2-  
LVTTL input  
OUTB2-  
INC1+  
OUTC1+  
INC2+  
OUTC2+  
VCC  
D06 FRAMCHARA3-level select  
D07 SPDSELC3-level select  
D08 GND  
D09 BOE<6>LVTTL input w/ pull-up  
D10 BOE<4>LVTTL input w/ pull-up  
D11 BOE<2>LVTTL input w/ pull-up  
D12 BOE<0>LVTTL input w/ pull-up  
D13 GND  
IND1+  
OUTD1+  
GND  
Serial Differential Receiver (+)  
CML Differential Output (+)  
IND2+  
OUTD2+  
INA1+  
OUTA1+  
GND  
Serial Differential Receiver (+)  
CML Differential Output (+)  
Serial Differential Receiver (+)  
CML Differential Output (+)  
D14 LPENBLVTTL input w/ pull-down  
D15 FRAMCHARD3-level select  
D16 VCC  
D17 LPENALVTTL input w/ pull-down  
D18 RFENALVTTL input w/ pull-down  
D19 RFENBLVTTL input w/ pull-down  
D20 RFMODELELVTTL input w/pull up  
E01 VCC  
INA2+  
OUTA2+  
VCC  
Serial Differential Receiver (+)  
CML Differential Output (+)  
INB1+  
OUTB1+  
INB2+  
OUTB2+  
TDI  
Serial Differential Receiver (+)  
CML Differential Output (+)  
Serial Differential Receiver (+)  
CML Differential Output (+)  
LVTTL input with pull-up  
LVTTL input w/ pull-up  
LVTTL input  
E02 VCC  
E03 VCC  
E04 VCC  
E17 VCC  
E18 VCC  
TMS  
E19 VCC  
INSELC  
INSELB  
VCC  
E20 VCC  
LVTTL input  
F01 TXERRC  
F02 RFEND  
LVTTL output  
LVTTL input w/ pull-down  
Document #: 38-02033 Rev. *A  
Page 12 of 39  
CYP15G0403DX  
PRELIMINARY  
PIN  
F03  
F04  
F17  
F18  
F19  
F20  
G01  
G02  
G03  
G04  
G17  
G18  
G19  
G20  
H01  
H02  
H03  
H04  
H17  
H18  
H19  
H20  
J01  
J02  
J03  
J04  
J17  
J18  
J19  
J20  
K01  
K02  
K03  
K04  
K17  
K18  
K19  
K20  
L01  
L02  
L03  
L04  
L17  
L18  
L19  
PIN NAME  
TXDC[0]  
RFENC  
BISTLE  
RXSTB[1]  
TXCLKOB  
RXSTB[0]  
TXDC[7]  
CLKSELLE  
TXDC[4]  
TXDC[1]  
SPDSELB  
LPENC  
PIN TYPE  
PIN  
L20  
M01  
M02  
M03  
M04  
M17  
M18  
M19  
M20  
N01  
N02  
N03  
N04  
N17  
N18  
N19  
N20  
P01  
P02  
P03  
P04  
P17  
P18  
P19  
P20  
R01  
R02  
R03  
R04  
R17  
R18  
R19  
R20  
T01  
T02  
T03  
T04  
T17  
T18  
T19  
T20  
U01  
U02  
U03  
U04  
PIN NAME  
TXDB[6]  
RXDC[4]  
RXDC[5]  
RXDC[7]  
RXDC[6]  
REFCLKB+  
REFCLKB-  
TXDB[7]  
TXCLKB  
GND  
PIN TYPE  
LVTTL input  
LVTTL input  
LVTTL input w/ pull-down  
LVTTL input w/ pull-up  
LVTTL output  
LVTTL output  
LVTTL output  
LVTTL output  
LVTTLOUT_FAST  
LVTTL output  
LVTTL output  
Differential reference clock input (+)  
Differential reference clock input (-)  
LVTTL input  
LVTTL input  
LVTTL input w/ pull-up  
LVTTL input  
LVTTL input w/ pull-down  
LVTTL input  
3-level select.  
GND  
LVTTL input w/ pull-down  
3-level select.  
GND  
SPDSELA  
RXDB[1]  
GND  
GND  
LVTTL output  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
RXDC[1]  
RXDC[0]  
RXSTC[0]  
RXSTC[1]  
TXDB[5]  
TXDB[4]  
TXDB[3]  
TXDB[2]  
RXSTC[2]  
TXCLKOC  
RXCLKC+  
RXCLKC-  
TXDB[1]  
TXDB[0]  
TXCTB[1]  
TXERRB  
VCC  
LVTTL output  
LVTTL output  
LVTTL output  
LVTTL output  
LVTTL input  
GND  
GND  
GND  
GND  
TXCTC[1]  
TXDC[5]  
TXDC[2]  
TXDC[3]  
RXSTB[2]  
RXDB[0]  
RXDB[5]  
RXDB[2]  
RXDC[2]  
REFCLKC-  
TXCTC[0]  
/LFIC  
LVTTL input  
LVTTL input  
LVTTL input  
LVTTL input  
LVTTL input  
LVTTL input  
LVTTL input  
LVTTL output  
LVTTLOUT_FAST  
LVTTLOUT_FAST  
LVTTLOUT_FAST  
LVTTL input  
LVTTL output  
LVTTL output  
LVTTL output  
LVTTL output  
LVTTL output  
LVTTL input  
Differential reference clock input (-)  
LVTTL input  
LVTTL input  
LVTTL output  
LVTTL output  
RXDB[3]  
RXDB[4]  
RXDB[7]  
RXCLKB+  
RXDC[3]  
REFCLKC+  
TXCLKC  
TXDC[6]  
RXDB[6]  
/LFIB  
LVTTL output  
VCC  
LVTTL output  
VCC  
LVTTL output  
VCC  
LVTTLOUT_FAST_ind  
LVTTL output  
VCC  
VCC  
Differential reference clock input (+)  
LVTTL input w/ pull-down  
LVTTL input  
VCC  
VCC  
TXDD[0]  
TXDD[1]  
TXDD[2]  
TXCTD[1]  
LVTTL input  
LVTTL input  
LVTTL input  
LVTTL input  
LVTTL output  
LVTTL output  
RXCLKB-  
LVTTLOUT_FAST  
Document #: 38-02033 Rev. *A  
Page 13 of 39  
CYP15G0403DX  
PRELIMINARY  
PIN  
U05  
U06  
U07  
U08  
U09  
U10  
U11  
U12  
U13  
U14  
U15  
U16  
U17  
U18  
U19  
U20  
V01  
V02  
V03  
V04  
V05  
V06  
V07  
V08  
V09  
V10  
V11  
V12  
V13  
V14  
V15  
V16  
V17  
V18  
V19  
V20  
W01  
PIN NAME  
VCC  
PIN TYPE  
PIN  
PIN NAME  
TXDD[7]  
/LFID  
PIN TYPE  
W02  
W03  
W04  
W05  
W06  
W07  
W08  
W09  
W10  
W11  
W12  
U13  
W14  
W15  
W16  
W17  
W18  
W19  
W20  
Y01  
Y02  
Y03  
Y04  
Y05  
Y06  
Y07  
Y08  
Y09  
Y10  
Y11  
LVTTL input  
RXDD[2]  
RXDD[1]  
GND  
LVTTL output  
LVTTL output  
LVTTL output  
LVTTLOUT_FAST  
RXCLKD-  
VCC  
TXERRD  
RLE  
LVTTL output  
RXDD[4]  
RXSTD[1]  
GND  
LVTTL output  
LVTTL output  
LVTTL input w/ pull up  
Differential reference clock input (-)  
LVTTL input  
REFCLKD-  
TXDA[1]  
GND  
OELE  
LVTTL input w/ pull up  
LVTTL input w/ pull-up  
LVTTLOUT_FAST  
LVTTL output  
/TXRST  
RXCLKA+  
TXERRA  
GND  
TXDA[4]  
TXCTA[0]  
VCC  
LVTTL input  
LVTTL input  
TXDA[2]  
TXDA[6]  
VCC  
LVTTL input  
LVTTL input  
RXDA[2]  
TXCTB[0]  
RXSTA[2]  
RXSTA[1]  
TXDD[3]  
TXDD[4]  
TXCTD[0]  
RXDD[6]  
VCC  
LVTTL output  
LVTTL input  
LVTTL output  
LVTTL output  
LVTTL input  
LVTTL input  
LVTTL input  
LVTTL output  
/LFIA  
LVTTL output  
REFCLKA+  
RXDA[4]  
RXDA[1]  
TXDD[6]  
TXCLKD  
RXDD[7]  
RXCLKD+  
VCC  
Differential reference clock input (+)  
LVTTL output  
LVTTL output  
LVTTL input  
LVTTL input w/ pull-down  
LVTTL output  
RXDD[3]  
RXSTD[0]  
GND  
LVTTL output  
LVTTL output  
LVTTLOUT_FAST_ind  
RXDD[5]  
RXDD[0]  
GND  
LVTTL output  
LVTTL output  
RXSTD[2]  
BYPASSLE  
REFCLKD+  
TXCLKOA  
GND  
LVTTL output  
LVTTL input w/ pull up  
Differential reference clock input (+)  
LVTTLOUT_FAST_ind  
TXCLKOD  
NC  
LVTTLOUT_FAST  
N/C, VGND pad place holder  
LVTTL input w/pull down  
LVTTLOUT_FAST  
TXCLKA  
RXCLKA-  
GND  
TXDA[3]  
TXDA[7]  
VCC  
LVTTL input  
LVTTL input  
Y12  
Y13  
Y14  
Y15  
Y16  
Y17  
Y18  
Y19  
Y20  
TXDA[0]  
TXDA[5]  
VCC  
LVTTL input  
LVTTL input  
RXDA[7]  
RXDA[3]  
RXDA[0]  
RXSTA[0]  
TXDD[5]  
LVTTL output  
LVTTL output  
LVTTL output  
LVTTL output  
LVTTL input  
TXCTA[1]  
REFCLKA-  
RXDA[6]  
RXDA[5]  
LVTTL input  
Differential reference clock input (-)  
LVTTL output  
LVTTL output  
Document #: 38-02033 Rev. *A  
Page 14 of 39  
CYP15G0403DX  
PRELIMINARY  
TXERRx output. This output indicates a continuous error until  
the Phase-Align Buffer is reset. Until the buffer fault is cleared,  
the transmitter for the associated channel outputs a  
continuous C0.7 character to indicate to the remote receiver  
that an error condition is present in the link.  
CYP15G0403DX HOTLink II Operation  
The CYP15G0403DX is a configurable device designed to  
transfer of large quantities of data, using high-speed serial  
links. This device supports four single-byte channels.  
It is possible to reset each Phase-Align Buffer individually and  
with minimal disruption of the serial data stream. When a  
Phase-Align Buffer error is present, the transmission of a Word  
Sync Sequence will re-center the buffer and will clear the error  
flag condition. Note. K28.5 characters may be added or lost  
from the data stream during reset operation. When used with  
non-Cypress devices that require a complete 16-character  
Word Sync Sequence for proper receive Elasticity Buffer  
operation, it is recommend that the reset sequence be  
followed by a Word Sync Sequence to ensure proper  
operation.  
CYP15G0403DX Transmit Data Path  
Input Register  
The bits in the Input Register for each channel support  
different bit assignments, based on if the input data is encoded  
or unencoded. These assignments are shown in Table 1.  
Table 1. Input Register Bit Assignments [3]  
Signal Name  
TXDx[0] (LSB)  
TXDx[1]  
Unencoded  
DINx[0]  
DINx[1]  
DINx[2]  
DINx[3]  
DINx[4]  
DINx[5]  
DINx[6]  
DINx[7]  
DINx[8]  
DINx[9]  
Encoded  
TXDx[0]  
TXDx[1]  
TXDx[2]  
TXDx[3]  
TXDx[4]  
TXDx[5]  
TXDx[6]  
TXDx[7]  
TXCTx[0]  
TXCTx[1]  
Encoder  
Each character, received from the input register or phase-align  
buffer, is then passed to the Encoder logic. This block inter-  
prets each character and any associated control bits, and  
outputs a 10-bit transmission character.  
TXDx[2]  
TXDx[3]  
TXDx[4]  
The operational mode controls the generated transmission  
character  
TXDx[5]  
the 10-bit preencoded character accepted in the input  
register  
the 10-bit equivalent of the 8-bit Data character accepted  
in the input register  
the 10-bit equivalent of the 8-bit Special Character code  
accepted in the input register  
the 10-bit equivalent of the C0.7 violation character if a  
Phase-Align Buffer overflow or underflow error is present  
TXDx[6]  
TXDx[7]  
TXCTx[0]  
TXCTx[1] (MSB)  
Note:  
3. LSB shifted out first.  
a character that is part of the 511-character BIST sequence  
a K28.5 character generated as an individual character or  
as part of the 16-character Word Sync sequence.  
Each input register captures eight data bits and two control bits  
on each input clock cycle. When the encoder is bypassed, the  
control bits are part of the pre-encoded 10-bit character.  
Data Encoding  
Raw data, as received from the Transmit Input Register must  
be processed to guarantee  
When the Encoder is enabled, the TXCTx[1:0] bits are inter-  
preted along with the associated TXDx[7:0] character to  
generate a specific 10-bit transmission character.  
a minimum transition density to ensure low noise clock  
extraction from the data stream.  
to reduce DC term in the original data stream.  
run-length limits to reduce the low frequency bandwidth  
requirements of the serial stream.  
to provide a means to framing the remote receiver.  
Data from each input register is passed to the associated  
Phase-Align buffer. These buffers are used to absorb clock  
phase differences between the selected input clock and the  
internal character clock.  
Initialization of these phase-align buffers takes place when the  
TXRST input is sampled LOW by TXCLKx. When TXRST is  
returned HIGH, the present input clock phase relative to  
REFCLKxis set. TXRST is an asynchronous input, but is  
sampled by each TXCLKxto synchronize it to the internal  
transmit path state machines. TXRST must be sampled LOW  
by a min.-mum of two consecutive TXCLKxclocks to ensure  
the reset operation is initiated correctly on the associated  
channels.  
When the Encoder is enabled, the characters to be transmitted  
are converted from Data or Special Character to 10-bit trans-  
mission characters, using an integrated 8B/10B encoder.  
When directed to encode the character as a Special Character  
code, the encoder will use the Special Character encoding  
rules listed in Table 15. When directed to encode the character  
as a Data character, it is encoded using the Data Character  
encoding rules in Table 14.  
The 8B/10B encoder is standards-compliant with ANSI/NCITS  
ASC X3.230-1994 (Fibre Channel), IEEE 802.3z Gigabit  
Ethernet, the IBM ESCON and FICON channels, and  
ATM Forum standards for data transport.  
Once the phase relationship if TXCLKx is set, these clocks are  
allowed to skew in phase up to half a character period in either  
direction relative to REFCLKx; i.e., ±180°. This phase shift  
allows the delay paths of the character clocks to change due  
to operating voltage and temperature.  
The Special Character codes that may be generated are listed  
If the phase offset, between the initialized location of the input  
clock and REFCLKx, exceeds the skew handling capabilities  
of the Phase-Align Buffer, an error is reported on that channel  
in Table 15.  
Document #: 38-02033 Rev. *A  
Page 15 of 39  
CYP15G0403DX  
PRELIMINARY  
The CYP15G0403DX is designed to support two independent  
Special Character code tables. This allows the  
CYP15G0403DX to operate in mixed environments with other  
CYP15G0403DXs using the enhanced Cypress command  
code set, or the command sets of other devices. Even when  
used in an environment that uses non-Cypress Special  
Character codes, the selective use of Cypress command  
codes can permit operation where running disparity and error  
handling must be managed.  
would generate. The remaining K28.5 characters in the  
sequence follow all 8B/10B coding rules. The disparity of the  
generated K28.5 characters in this sequence follow a pattern  
of either ++––++++++or ––++++++++.  
The generation of this character, once it has been started, it  
cannot be stopped until all 16 characters have been sent. The  
content of the associated input registers are ignored for the  
duration of this 16-character sequence. At the end of this  
sequence, if the TXCTx[1:0] = 11 the K28.5 character  
sequence generation is started again.  
Following conversion of each input character from 8 bits to a  
10-bit transmission character, it is passed to the Transmit  
Shifter and is shifted out LSB first, as required by ANSI and  
IEEE standards for 8B/10B coded serial data streams.  
Transmit BIST  
The transmitter interfaces contain internal pattern generators  
that can be used to validate link operation. These generators  
are enabled by the associated BOE[x] signals as listed in Table  
4 when the BISTLE latch enable input is HIGH. When enabled,  
a register in the associated transmit channel becomes a  
pattern generator by converting to a Linear Feedback Shift  
Register (LFSR). This LFSR generates a 511-character  
sequence that includes all Data and Special Character codes,  
including the explicit violation symbols. This provides a  
predictable yet pseudo-random sequence that can be  
matched to an identical LFSR in the attached Receiver.  
Transmit Modes  
Encoder Bypass  
When the Encoder is bypassed, the character captured in the  
TXDx[7:0] and TXCTx[1:0] inputs is passed directly to the  
transmit shifter without modification. With the encoder  
bypassed, the TXCTx[1:0] inputs are considered part of the  
data character and do not perform a control function on the  
TXDx[7:0] bits. The bit usage and mapping of these control  
bits when the Encoder is bypassed is shown in Table 2.  
When the BISTLE signal is HIGH, any BOE[x] input that is  
LOW enables the BIST generator in that transmit channel or  
the BIST checker in the receive channel. When BISTLE  
returns LOW, the values of all BOE[x] signals are captured in  
the BIST Enable Latch. These values remain in the BIST  
Enable Latch until BISTLE is returned high. When the system  
is reset by TRSTZ, the default is to disable BIST.  
Table 2. Encoder Bypass Mode  
Signal Name  
TXDx[0] (LSB)  
TXDx[1]  
Bus Weight  
10B Name  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
a[3]  
b
c
d
e
i
TXDx[2]  
All data and data-control information present at the associated  
TXDx[7:0] and TXCTx[1:0] inputs are ignored when BIST is  
active. If the receive channels are configured for reference  
clock operation, each pass is preceded by a 16-character  
Word Sync Sequence that provides time for Elasticity Buffer  
centering and clock frequency adjustments.  
TXDx[3]  
TXDx[4]  
TXDx[5]  
TXDx[6]  
f
Serial Output Drivers  
TXDx[7]  
g
h
j
The serial outputs use differential CML drivers to provide a  
source-matched driver for transmission lines. These drivers  
accept data from the Transmit Shifters. These outputs have  
signal swings equivalent to that of standard PECL drivers, and  
are capable of driving AC-coupled optical modules or  
AC-coupled transmission lines.  
TXCTx[0]  
TXCTx[1] (MSB)  
When the encoder is enabled, the TXCTx[1:0] data control bits  
control the interpretation of the TXDx[7:0] bits and the  
characters generated by them. These bits are interpreted as  
listed in Table 3.  
Each output can be enabled or disabled separately through  
the BOE[7:0] input, as controlled by the OELE latch-enable  
signal. When OELE is HIGH, the signals present on the  
BOE[7:0] inputs are passed through the Serial Output Enable  
latch to control the serial output drivers. The BOE[7:0] input  
associated with a specific OUTxy± driver is listed in Table 4.  
Table 3. Transmit modes  
TXCTx[1] TXCTx[0]  
Characters Generated  
Encoded data character  
K28.5 fill character  
0
0
1
1
0
1
0
1
When OELE is HIGH and BOE[x] is HIGH, the associated  
serial driver is enabled.  
Special character code  
When OELE is HIGH and BOE[x] is LOW, the associated  
driver is powered down. If both outputs for a channel are  
disabled, the internal logic for that channel is also powered  
down.  
16-character Word Sync  
sequence  
Word Sync Sequence  
When OELE returns LOW, the values present on the BOE[7:0]  
inputs are latched in the Output Enable Latch, and remain  
there until OELE returns HIGH. When a disabled transmit  
channel is re-enabled, the data on the serial outputs may not  
meet all timing specifications for up to 10ms.  
When TXCTx[1:0] = 11, a 16-character sequence of K28.5  
characters, known as a Word Sync Sequence, is generated on  
the associated channel. This sequence of K28.5 characters  
may start with either a positive or negative disparity K28.5. The  
disparity of the second and third K28.5 characters in this  
sequence are reversed from what normal 8B/10B coding rules  
Document #: 38-02033 Rev. *A  
Page 16 of 39  
CYP15G0403DX  
PRELIMINARY  
Table 4. Control Latches Signal Map  
Receive PLL  
Output  
Controlled  
(OELE)  
BIST Channel  
Enable  
Enable  
Decoder Code  
(RLE)  
Encoder/  
Decoder  
(BYPASSLE)  
Clock Select  
Reframe  
Mode  
(RFMODELE)  
Enable  
BOE Input  
BOE[7]  
BOE[6]  
BOE[5]  
BOE[4]  
BOE[3]  
BOE[2]  
BOE[1]  
BOE[0]  
(BISTLE)  
(CLKSELLE)  
OUTD2±  
OUTD1±  
OUTC2±  
OUTC1±  
OUTB2±  
OUTB1±  
OUTA2±  
OUTA1±  
Transmit D  
Receive D  
Transmit C  
Receive C  
Transmit B  
Receive B  
Transmit A  
Receive A  
Decoder D  
RXPLL D  
Decoder C  
RXPLL C  
Decoder B  
RXPLL B  
Decoder A  
RXPLL A  
Transmit D  
Receive D  
Transmit C  
Receive C  
Transmit B  
Receive B  
Transmit A  
Receive A  
Transmit D  
Receive D  
Transmit C  
Receive C  
Transmit B  
Receive B  
Transmit A  
Receive A  
ReframeD1  
ReframeD0  
Reframe C1  
ReframeC0  
Reframe B1  
ReframeB0  
Reframe A1  
Reframe A0  
Transmit PLL Clock Multiplier  
CYP15G0403DX Receive Data Path  
Each Transmit PLL Clock Multiplier accepts a character-rate  
or half-character-rate external clock for REFCLKx input, and  
that clock is multiplied by 10 or 20, as selected by TXRATE, to  
generate a bit-rate clock for use by the transmit shifter. It also  
provides a character-rate clock used by the transmit paths,  
and outputs this character rate clock as TXCLKOx.  
Serial Line Receivers  
Two differential line receivers, INx1± and INx2±, are available  
on each channel for accepting serial data streams. The active  
line receiver on a channel is selected using the associated  
INSELx input. The serial line receiver inputs are differential  
and only require is a 200mV peak-to-peak signal. It can be DC-  
or AC-coupled to +3.3V powered fiber-optic interface modules  
Each clock multiplier PLL can accept a REFCLKx input  
between 10 MHz and 150 MHz, however, this clock range is  
limited by the operating mode of the CYP15G0403DX clock  
multiplier TXRATE and by the level on the associated  
SPDSEL[A:D] input.  
with  
a PECL output. 5V optical modules should be  
AC-coupled. The common-mode tolerance of these line  
receivers will accommodates a wide range of input signal  
voltages. For AC-coupled signals the receiver provides an  
average value DC restoration.  
SPDSEL[A:D] inputs that selects one of three operating  
ranges for the serial data outputs and inputs of the associated  
channel. The operating serial signaling-rate and allowable  
range of REFCLKx frequencies are listed in Table 5.  
The local internal loopback allows the serial transmit data  
outputs to be routed internally back to the Clock and Data  
Recovery circuit associated with each channel. When  
configured for local loopback, all transmit serial driver outputs  
are forced to output a differential logic-1. This prevents local  
diagnostic patterns from being broadcast to attached remote  
receivers.  
Table 5. Operating Speed Settings  
REFCLKx  
Frequency  
(MHz)  
Signaling  
Rate  
(MBaud)  
SPDSELx  
TXRATE  
Signal Detect/Link Fault  
LOW  
1
0
1
0
1
0
20  
200400  
400800  
8001500  
Each selected Line Receiver is simultaneously monitored for  
analog amplitude  
transition density  
range controls reporting the received data stream inside a  
normal frequency range (±200 ppm)  
2040  
2040  
4080  
4075  
80150  
MID (Open)  
HIGH  
receive channel enabled.  
All of these conditions must be valid for the Signal Detect block  
to indicate a valid signal is present. This status is presented  
on the LFIx (Link Fault Indicator) output associated with each  
receive channel, which changes synchronous to the selected  
receive interface clock.  
The REFCLKx± inputs are differential inputs with each input  
internally biased to VCC/2. The REFCLKx input interfaces  
directly to TTL, LVTTL, or LVCMOS clock source.  
Analog Amplitude  
When both the REFCLKx+ and REFCLKxinputs are  
connected, the clock source must be a differential clock. This  
can be a differential LVPECL clock that is DC-or AC-coupled.  
The analog amplitude level detection is adjustable to allow  
operation with highly attenuated signals, or in high-noise  
environments. This adjustment is made through the SDASEL  
signal, a 3-level select[2] input, which sets the trip point for the  
detection of a valid signal at one of three levels, as listed in  
Table 6. This control input effects the analog monitors for all  
receive channels.  
By connecting the REFCLKxinput to an external voltage  
source, it is possible to adjust the reference point of the  
REFCLKx+ input for alternate logic levels.  
Document #: 38-02033 Rev. *A  
Page 17 of 39  
CYP15G0403DX  
PRELIMINARY  
Receive Channel Enabled  
Table 6. Analog Amplitude Detect Valid Signal Levels  
The CYP15G0403DX contains four receive channels that can  
be independently enabled and disabled. Each channel can be  
enabled or disabled separately through the BOE[6,4,2,0]  
inputs, as controlled by the RLE latch-enable signal. When  
RLE is HIGH, the signals present on the BOE[] inputs are  
passed through the Receive Channel Enable latch to control  
the PLLs and logic of the associated receive channel. The  
BOE[] input associated with a specific receive channel is listed  
in Table 4.  
SDASEL  
Typicalsignalwithpeakamplitudesabove  
LOW  
140 mV p-p differential  
MID (Open) 280 mV p-p differential  
HIGH 420 mV p-p differential  
The Signal Detect monitors are active for the present line  
receiver, as selected by the associated INSELx input. When  
configured for local loopback, no input receivers are selected,  
and the LFI output for each channel reports only the receive  
VCO frequency out-of-range and transition density status of  
the associated transmit signal. In local loopback the  
associated analog amplitude monitor is disabled.  
When RLE is HIGH and BOE[x] is HIGH, the associated  
receive channel enabled to receive and decode a serial  
stream. When RLE is HIGH and BOE[x] is LOW, the  
associated receive channel is disabled and powered down.  
Any disabled channel will indicate a constant link fault  
condition on the LFIx output. When RLE returns LOW, the  
values present on the BOE[6,4,2,0] inputs are latched in the  
Receive Channel Enable Latch, and remain there until RLE  
returns HIGH to to resample the input again. Note. When a  
disabled receive channel is re-enabled, the status of the  
associated LFIx output and data on the parallel outputs for the  
associated channel may be indeterminate for up to 10ms.  
Transition Density  
The transition detection logic checks for the absence of transi-  
tions spanning greater than six transmission characters or 60  
bits. If no transitions are present in the data received, the  
transition detection logic for that channel will assert LFIx. The  
LFIx output remains asserted until at least one transition is  
detected in each of three adjacent received characters.  
Clock and Data Recovery  
The extraction of a bit-rate clock and recovery of bits from each  
received serial stream is performed by a separate CDR block  
within each receive channel. The clock extraction function is  
performed by embedded phase-locked loops that track the  
frequency and phase of the transitions in the incoming bit  
streams.  
Range Controls  
The receive-VCO range-control monitors report the frequency  
status of the received signal. They also determine if the  
receive CDR circuits should align the receive VCO clock to the  
data stream or to the associated REFCLKx input. This function  
prevents the receive VCO from tracking an out-of-specification  
received signal.  
Each CDR accepts a character-rate or half-character-rate  
reference clock from the associated REFCLKx input. This  
REFCLKx input is used  
to ensure that the VCO in each CDR is operating at the  
correct frequency.  
to improve PLL acquisition time.  
to limit unlocked frequency excursions of the VCO when no  
data is present at the selected serial inputs.  
When the range-control monitor for a channel indicates that  
the signaling rate is within specification, the phase detector in  
the receive PLL is configured to track the transitions in the  
received data stream. In this mode the LFIx output for the  
associated channel is HIGH. If the range-control monitor  
indicates that the received data stream signaling-rate is out of  
specification, the phase detector is configured to track the  
local REFCLKx input, and the associated LFIx output is  
asserted LOW.  
Regardless of the type of signal present, the CDR will attempt  
to recover a data stream from it. If the frequency of the  
recovered data stream is outside the limits set by the range  
control monitors, the CDR PLL will track REFCLKx instead of  
the data stream. When the frequency of the selected data  
stream returns to a valid frequency, the CDR PLL is allowed to  
track the received data stream. The frequency of REFCLKx is  
required to be within ±200 ppm of the frequency of the clock  
that drives the REFCLK input of the remote transmitter to  
ensure a lock to the incoming data stream.  
The specific trip points for this compare function are listed in  
Table 7. Because the compare function operates with two  
asynchronous clocks, there is a small uncertainty in the  
measurement. The switch points are asymmetric to provide  
operational hysteresis.  
Table 7. Receive Signaling Rate Range Control criteria  
Frequency  
Difference  
For systems using multiple or redundant connections, the LFIx  
output can be used to select an alternate data stream. When  
an LFIx indication is detected, external logic can toggle  
selection INx1± and INx2± inputs. When a port switch takes  
place, the receive PLL must reacquire the new serial stream  
and frame to the incoming character boundaries.  
Between  
Next RX PLL  
Tracking  
Source  
Current RX PLL TransmitCharacter  
Tracking Source  
Clock & RX VCO  
Selected data  
stream  
(LFIx = HIGH)  
< 1708 ppm  
Data Stream  
Indeterminate  
REFCLKx  
17081953 ppm  
> 1953 ppm  
Deserializer/Framer  
Each CDR circuit extracts bits from the associated serial data  
stream and clocks these bits into the Shifter/Framer at the  
bit-clock rate. When enabled, the Framer examines the data  
stream looking for one or more COMMA or K28.5 characters  
at all possible bit positions. The location of this character in the  
data stream is used to determine the character boundaries of  
all following characters.  
REFCLKx  
(LFIx = LOW)  
< 488 ppm  
Data Stream  
Indeterminate  
REFCLKx  
488732 ppm  
> 732 ppm  
Document #: 38-02033 Rev. *A  
Page 18 of 39  
CYP15G0403DX  
PRELIMINARY  
Framing Character  
When BOE(x,x-1) = 01, the alternate-mode multi-byte framer  
is enabled. Like the Cypress-mode multi-byte framer, multiple  
framing characters must be detected before the character  
boundary is adjusted. In this mode, the data stream must  
contain a minimum of four of the selected framing characters,  
received as consecutive characters, on identical 10-bit bound-  
aries, before character framing is adjusted.  
The CYP15G0403DX allows selection of different framing  
characters on each channel. Three combinations of framing  
characters are supported to meet the requirements of different  
interfaces. The selection of the framing character is made  
through the FRAMCHARx inputs.  
The FRAMCHARx signals are 3-level select [2] inputs that  
allow selection of one of three different framing characters or  
character combinations. The specific bit combinations of these  
framing characters are listed in Table 8. When the specific bit  
combination of the selected framing character is detected by  
the framer, the boundaries of the characters present in the  
received data stream are known.  
10B/8B Decoder Block  
The decoder logic block performs three primary functions:  
decoding the received transmission characters to Data and  
Special Character codes  
comparing generated BIST patterns with received  
characters to permit at-speed link testing.  
Table 8. Framing Character Selector  
Bits detected in framer  
10B/8B Decoder  
The framed parallel output of each deserializer shifter is  
passed to the 10B/8B decoder where the input data is trans-  
formed from a 10-bit transmission character back to the  
original Data and Special Character code. This block uses the  
10B/8B decoder patterns in Table 14 and Table 15. Received  
Special Code characters are decoded using Table 15. Valid  
data characters are indicated by a 000b bit-combination on the  
associated RXSTx[2:0] status bits, and Special Character codes  
are indicated by a 001b bit-combination of these status bits.  
Framing characters, invalid patterns, disparity errors, and synchro-  
nization status are presented as alternate combinations of these  
status bits.  
FRAMCHARx  
LOW  
Character Name  
Bits Detected  
COMMA+  
00111110XX [4]  
MID  
COMMA+  
COMMA−  
00111110XX [4]  
or 11000001XX  
HIGH  
K28.5  
+K28.5  
0011111010 or  
1100000101  
Note:  
4. The standard definition of a COMMA contains only seven bits. However,  
since all valid COMMA characters within the 8B/10B character set also  
have the eighth bit as an inversion of the seventh bit, the compare pattern  
is extended to a full 8 bits to reduce the possibility of a framing error.  
The 10B/8B decoder uses one of two look-up tables, and it  
could be bypassed.  
Framer  
Receive BIST Operation  
The framer on each channel operates in one of three different  
modes. The framer is controlled by RFENx. When the framer  
is disabled, no combination of received bits will alter the frame  
information.  
The receiver interfaces contain internal pattern generators that  
can be used to validate system operation. These generators  
are enabled by the associated BOE[x] signals listed in Table 4  
when the BISTLE latch enable input is HIGH. When enabled,  
a register in the associated receive channel becomes a  
signature pattern generator and checker by logically  
converting to a Linear Feedback Shift Register (LFSR). This  
LFSR generates a 511-character sequence that includes all  
Data and Special Character codes, including the explicit  
When the low-latency framer is selected (BOE[x,x-1] = 00), the  
framer operates by stretching the recovered character clock  
until it aligns with the received character boundaries. In this  
mode the framer starts its alignment process on the first  
detection of the selected framing character. To reduce the  
impact on external circuits that use the recovered clock, the  
clock period is not stretched by more than two bit-periods.  
When operated with a character-rate output clock, the output  
of properly framed characters may be delayed by up to nine  
character-clock cycles from the detection of the selected  
framing character. When operated with a half-character-rate  
output clock, the output of properly framed characters may be  
delayed by up to 14 character-clock cycles from the detection  
of the framing character.  
violation symbols. This provides  
a
predictable yet  
pseudo-random sequence that can be matched to an identical  
LFSR in the attached Transmitter. When synchronized with the  
received data stream, the associated receiver checks each  
character in the Decoder with each character generated by the  
LFSR and indicates compare errors and BIST status at the  
RXSTx[2:0] bits of the output register.  
When the BISTLE signal is HIGH, any BOE[x] input that is  
LOW enables the BIST generator/checker in the selected  
receive channel. When BISTLE returns LOW, the values of all  
BOE[x] signals are captured in the BIST Enable Latch. These  
values remain in the BIST Enable Latch until BISTLE is  
returned high to sample input again. All captured signals in the  
BIST Enable Latch are set HIGH and BIST is disabled  
following a device reset by TRSTZ.  
When BOE(x,x-1) = 1x, the Cypress-mode multi-byte framer is  
selected. The required detection of multiple framing  
characters makes the associated link much more robust. In  
this mode, the framer does not adjust the character clock  
boundary, but instead aligns the character to the already  
recovered character clock. This ensures that the recovered  
clock will not contain any phase changes during normal  
operation. This process allows the recovered clock to be repli-  
cated and distributed to other external circuits. In this framing  
mode the character boundaries are only adjusted if the  
selected framing character is detected at least twice within a  
span of 50 bits, with both instances on identical 10-bit  
character boundaries.  
The LFSR is initialized by the BIST hardware once the BIST  
enabled for that receive channel. This sets the BIST LFSR to  
the BIST-loop start-code of D0.0. The code D0.0 is sent only  
once per BIST loop. The status of the BIST and any character  
mismatches are presented on the RXSTx[2:0] status outputs.  
Document #: 38-02033 Rev. *A  
Page 19 of 39  
CYP15G0403DX  
PRELIMINARY  
Code rule violations or running disparity errors that occur as  
part of the BIST loop do not cause an error indication.  
RXSTx[2:0] indicates 010b or 100b for one character period per  
BIST loop to indicate loop completion. This status signal can be  
used to check BIST pattern progress. These same status values  
are presented even when the decoder is bypassed and BIST is  
enabled on a receive channel.  
The insertion of a K28.5 or deletion of a framing character can  
occur at any time on any channel, however, the actual timing  
on these insertions and deletions is controlled in part by the  
how the transmitter sends its data. Insertion of a K28.5  
character can only occur when the receiver has a framing  
character in the Elasticity Buffer. Likewise, to delete a framing  
character, one must also be in the Elasticity Buffer. To prevent  
a buffer overflow or underflow on a receive channel, a  
minimum density of framing characters must be present in the  
received data streams.  
The specific status reported by the BIST state machine are  
listed in Table 11. These same codes are reported on the  
receive status outputs.  
The Elasticity buffer may be reset by a device reset operation  
initiated through the TRSTZ input, however, following such an  
event the CYP15G0403DX will normally require a framing  
event before it will correctly decode characters.  
The specific patterns checked by each receiver are described  
in detail in the Cypress application note HOTLink Built-In  
Self-Test.The sequence compared by the CYP15G0403DX  
is identical to that in the CY7B933, CY7C924DX and  
CYP15G0401DX allowing interoperable systems to be built  
when used at compatible serial signaling rates.  
When the receive channel output register is clocked by a  
recovered clock, no characters are added or deleted; the  
receiver Elasticity Buffer is bypassed.  
If the number of invalid characters received ever exceeds the  
number of valid characters by 16, the receive BIST state  
machine aborts the compare operations and resets the LFSR  
to the D0.0 state.  
Each receive channel presents an 11-signal output bus  
consisting of an 8-bit data bus and a 3-bit status bus.  
The signals present on this output bus are modified by the  
present operating mode of the CYP15G0403DX as selected  
BYPASSLE. This mapping is shown in Table 9.  
When the receive paths are configured for common clock  
operation, each pass must be preceded by a 16-character  
Word Sync Sequence to allow output buffer alignment and  
management of clock frequency variations.  
Table 9. Output Register Bit Assignments  
Signal Name  
RXSTx[2] (LSB)  
RXSTx[1]  
RXSTx[0]  
RXDx[0]  
BYPASS ACTIVE  
COMDETx  
DOUTx[0] [5]  
DOUTx[1]  
DOUTx[2]  
DOUTx[3]  
DOUTx[4]  
DOUTx[5]  
DOUTx[6]  
DOUTx[7]  
DOUTx[8]  
DOUTx[9]  
DECODER  
RXSTx[2]  
RXSTx[1]  
RXSTx[0]  
RXDx[0]  
RXDx[1]  
RXDx[2]  
RXDx[3]  
RXDx[4]  
RXDx[5]  
RXDx[6]  
RXDx[7]  
The BIST state machine requires the characters to be correctly  
framed for it to detect the BIST sequence. If the framer is  
enabled and configured for low-latency operation, the framer  
can align to characters within the BIST sequence. If either of  
the multi-byte framers are enabled, it is generally necessary to  
frame the receiver before BIST is enabled, and then disable  
framing. If the receive outputs are clocked relative to  
REFCLKx, the transmitter precedes every 511 character BIST  
sequence with a 16-character Word Sync Sequence.  
RXDx[1]  
RXDx[2]  
RXDx[3]  
Receive Elasticity Buffer  
RXDx[4]  
Each receive channel contains an Elasticity Buffer that is  
designed to support clock tolerance management. These  
buffers allow data to be read using an Elasticity Buffer Read  
clock that is asynchronous in both frequency and phase from  
the Elasticity Buffer Write clock.  
RXDx[5]  
RXDx[6]  
RXDx[7] (MSB)  
Note:  
5. LSB received first.  
If the chip is configured for operation with a recovered clock,  
the elasticity buffer is bypassed.  
Each Elasticity Buffer is a minimum of 5 characters deep, and  
supports a 11-bit-wide data path. It is capable of supporting a  
decoded character and three status bits for each character  
present in the buffer. The Write clock for these buffers is  
always the recovered clock for the associated Read channel.  
When the 10B/8B decoder is bypassed, the framed 10-bit  
value is presented to the associated output register, along with  
a status output indicating if the character in the output register  
is one of the selected framing characters. The bit usage and  
mapping of the external signals to the raw 10B coded  
character is shown in Table 10.  
The Read clock for the Elasticity Buffers may come from two  
selectable sources:  
The COMDETx status outputs operate the same regardless of  
the bit combination selected for character framing by the  
FRAMCHARx input. They are HIGH when the character in the  
output register contains the selected framing character at the  
proper character boundary, and LOW for all other bit combina-  
tions.  
a character-rate REFCLKx↑  
a recovered clock from the receive channel.  
Receive Modes  
When the receive channel is clocked by REFCLKx, the  
RXCLKx± outputs present a buffered and delayed form of  
REFCLKx. In this mode, the receive Elasticity Buffers are  
enabled. For REFCLKx clocking, for example, the Elasticity  
Buffers are enabled to insert K28.5 characters and delete  
framing characters as appropriate.  
When the low-latency framer and half-rate receive port  
clocking are also enabled, the framer stretches the recovered  
clock to the nearest 20-bit boundary such that the rising edge  
of RXCLKx+ occurs when COMDETx is present on the  
associated output bus.  
Document #: 38-02033 Rev. *A  
Page 20 of 39  
CYP15G0403DX  
PRELIMINARY  
Table 10. Decoder Bypass Mode  
reported as a valid data character. It is instead reported as a  
decoder violation of some specific type. This implies a  
hierarchy or priority level to the various status bit combina-  
tions. The hierarchy and value of each status are listed in  
Table 11.  
Signal Name  
RXSTx[2] (LSB)  
RXSTx[1]  
RXSTx[0]  
RXDx[0]  
Bus Weight  
10B Name  
COMDETx  
20 [5]  
21  
22  
a [5]  
A second status mapping, listed in Table 11, is used when the  
receive channel is configured for BIST operation. This status  
is used to report receive BIST status and progress.  
b
c
d
e
i
RXDx[1]  
23  
BIST Status State Machine  
RXDx[2]  
24  
When a receive path is enabled to look for and compare the  
received data stream with the BIST pattern, the RXSTx[2:0]  
bits identify the present state of the BIST compare operation.  
RXDx[3]  
25  
RXDx[4]  
26  
f
The BIST state machine has multiple states, as shown in  
Figure 2 and Table 11. When the receive PLL detects an  
out-of-lock condition, the BIST state is forced to the  
Start-of-BIST state, regardless of the present state of the BIST  
state machine. If the number of detected errors ever exceeds  
the number of valid matches by greater than 16, the state  
machine is forced to the WAIT_FOR_BIST state where it  
monitors the interface for the first character of the next BIST  
sequence (D0.0). Also, if the Elasticity Buffer ever hits and  
overflow/underflow condition, the status is forced to the  
BIST_START until the buffer is re centered (approximately  
nine character periods).  
RXDx[5]  
27  
28  
29  
g
h
j
RXDx[6]  
RXDx[7] (MSB)  
When the standard framer is enabled and half-rate receive  
port clocking is also enabled, the output clock is not modified  
when framing is detected, but a single pipeline stage may be  
added or subtracted from the data stream by the framer logic  
such that the rising edge of RXCLKx+ occurs when COMDET  
is present on the associated output bus.  
This adjustment only occurs when the framer is enabled.  
When the framer is disabled, the clock boundaries are not  
adjusted, and COMDETx may be active during the rising edge  
of RXCLKx(if an odd number of characters were received  
following the initial framing).  
JTAG Support  
The CYP15G0403DX contains a JTAG port to allow system  
level diagnosis of device interconnect. Only JTAG boundary  
scan is supported. This capability is present on the LVTTL  
inputs and outputs and the REFCLKx± clock input. The  
high-speed serial ports are not supported.  
Receive Status Bits  
When the 10B/8B decoder is enabled, each character  
presented at the output register includes three associated  
status bits. These bits are used to identify  
3-Level Select Inputs  
Each 3-level select input reports as two bits in the scan  
register. These bits report the LOW, MID, and HIGH state of  
the associated input as 00, 10, and 11 respectively  
if the contents of the data bus are valid,  
the type of character present,  
the state of receive BIST operations,  
character violations.  
JTAG ID  
The JTAG device ID for the CYP15G0403DX is 0C810069x.”  
These conditions normally overlap; for example, a valid data  
character received with incorrect running disparity is not  
Document #: 38-02033 Rev. *A  
Page 21 of 39  
CYP15G0403DX  
PRELIMINARY  
Monitor Data  
Received  
Receive BIST  
Detected LOW  
RXSTx =  
RX PLL  
Out of Lock  
BIST_START (101)  
RXSTx =  
BIST_START (101)  
RXSTx =  
BIST_WAIT (111)  
Elasticity  
Buffer Error  
Yes  
Start of  
BIST Detected  
No  
No  
Yes, RXSTx =  
BIST_DATA_COMPARE (000) / BIST_COMMAND_COMPARE (001)  
Compare  
Next Character  
RXSTx =  
Mismatch  
BIST_COMMAND_COMPARE (001)  
Match  
Command  
Data or  
Command  
Auto-Abort  
Condition  
Yes  
RXSTx =  
No  
BIST_DATA_COMPARE (000)  
Data  
End-of-BIST  
State  
End-of-BIST  
State  
No  
Yes, RXSTx =  
BIST_LAST_BAD (100)  
Yes, RXSTx =  
BIST_LAST_GOOD (010)  
No, RXSTx =  
BIST_ERROR (110)  
Figure 2. Receive BIST State Machine  
Table 11. Receive Character Status Bits  
RXSTx[2:0] Priority  
Description  
Receive BIST Status  
(Receive BIST = Enabled)  
Normal Status  
000  
7
Normal Character Received. The valid Data character on the output BIST Data Compare.  
bus meets all the formatting requirements of Data characters listed in Character compared correctly  
Table 14.  
001  
7
Special Code Detected. The valid special character on the output bus BIST Command Compare.  
meets all the formatting requirements of Special Code characters listed Character compared correctly  
in Table 15, but is not the presently selected framing character or a  
decoder violation indication.  
Document #: 38-02033 Rev. *A  
Page 22 of 39  
CYP15G0403DX  
PRELIMINARY  
Table 11. Receive Character Status Bits (continued)  
010  
011  
100  
101  
2
5
4
1
Receive Elasticity Buffer Underrun/Overrun Error. The receive buffer BIST Last Good. Last  
was not able to add/drop a K28.5 or framing character  
Character of BIST sequence  
detected and valid.  
Framing Character Detected. This indicates that a character matching  
thepatternsidentifiedas aframingcharacterwasdetected. Thedecoded  
value of this character is present in the associated output bus.  
Codeword Violation. The character on the output bus is a C0.7. This BIST Last Bad. Last Character  
indicates that the received character cannot be decoded into any valid of BIST sequence detected  
character.  
invalid.  
Loss of Sync. This indicates a PLL Out of Lock condition  
BIST Start. Receive BIST is  
enabled on this channel, but  
character compares have not  
yet commenced. This also  
indicates a PLL Out of Lock  
condition, and Elasticity Buffer  
overflow/underflow conditions.  
110  
111  
6
3
Running Disparity Error. The character on the output bus is a C4.7, BIST Error. While comparing  
C1.7, or C2.7.  
characters, a mismatch was  
found in one or more of the  
decoded character bits.  
Reserved  
BIST Wait. The receiver is  
comparing characters. but has  
not yet found the start of BIST  
character to enable the LFSR.  
Document #: 38-02033 Rev. *A  
Page 23 of 39  
CYP15G0403DX  
PRELIMINARY  
the patterns most similar to the encoded bit patterns of the Special  
Character.  
X3.230 Codes and Notation Conventions  
Information to be transmitted over a serial link is encoded eight  
bits at a time into a 10-bit Transmission Character and then  
sent serially. Information received over a serial link is collected  
ten bits at a time, and those Transmission Characters that are  
used for data characters are decoded into the correct eight-bit  
codes. The 10-bit Transmission Code supports all 256 8-bit  
combinations. Some of the Special Transmission Characters  
are used for other than data functions.  
Under the above conventions, the Transmission Character  
used for the examples above, is referred to by the name D5.2.  
The Special Character K29.7 is so named because the first six  
bits (abcdei) of this character make up a bit pattern similar to  
that resulting from the encoding of the unencoded 11101  
pattern (29), and because the second four bits (fghj) make up  
a bit pattern similar to that resulting from the encoding of the  
unencoded 111 pattern (7).  
The primary use of a Transmission Code is to improve the  
transmission characteristics of a serial link. The encoding  
defined by the Transmission Code ensures that sufficient  
transitions are present in the serial bit stream to recover the  
clock at the Receiver. Such encoding increases the likelihood  
of detecting bit errors that may occur. Some Special  
Characters of the Transmission Code used by Fibre Channel  
Standard consist of an easily recognizable bit pattern that  
assists a Receiver in achieving word alignment.  
Note. This definition of the 10-bit Transmission Code is based  
on (and is in basic agreement with) the following references,  
which describe the same 10-bit transmission code.  
A.X. Widmer and P.A. Franaszek. A DC-Balanced, Parti-  
tioned-Block, 8B/10B Transmission CodeIBM Journal of  
Research and Development, 27, No. 5: 440451 (September,  
1983).  
U.S. Patent 4,486,739. Peter A. Franaszek and Albert X.  
Widmer. Byte-Oriented DC Balanced (0.4) 8B/10B Parti-  
tioned Block Transmission Code(December 4, 1984).  
Notation Conventions  
The documentation for the 8B/10B Transmission Code uses  
letter notation for the bits in an 8-bit byte. Fibre Channel  
Standard notation uses a bit notation of A, B, C, D, E, F, G, H  
for the 8-bit byte for the raw 8-bit data, and the letters a, b, c,  
d, e, i, f, g, h, j for encoded 10-bit data. There is a correspon-  
dence between bit A and bit a, B and b, C and c, D and d, E  
and e, F and f, G and g, and H and h. Bits i and j are derived,  
respectively, from (A,B,C,D,E) and (F,G,H).  
Fibre Channel Physical and Signaling Interface (ANS  
X3.2301994 ANSI FCPH Standard).  
IBM Enterprise Systems Architecture/390 ESCON I/O  
Interface (document number SA227202).  
8B/10B Transmission Code  
The following information describes how the tables shall be  
used for both generating valid Transmission Characters  
(encoding) and checking the validity of received Transmission  
Characters (decoding). It also specifies the ordering rules to  
be followed when transmitting the bits within a character and  
the characters within the higher-level constructs specified by  
the standard.  
The bit labeled A in the description of the 8B/10B Transmission  
Code corresponds to bit 0 in the numbering scheme of the  
FC-2 specification, B corresponds to bit 1, as shown below.  
FC-2 bit designation—  
HOTLink D/Q designation7  
8B/10B bit designation—  
7
6
6
G F  
5
5
4
4
E
3
3
D
2
2
C
1
1
B
0
0
A
H
Transmission Order  
To clarify this correspondence, the following example shows  
the conversion from an FC-2 Valid Data Byte to a Transmission  
Character (using 8B/10B Transmission Code notation).  
Within the definition of the 8B/10B Transmission Code, the bit  
positions of the Transmission Characters are labeled a, b, c,  
d, e, i, f, g, h, j. Bit ashall be transmitted first followed by bits  
b, c, d, e, i, f, g, h, and j in that order. (Note. Bit i shall be  
transmitted between bit e and bit f, rather than in alphabetical  
order.)  
FC-2 45  
Bits: 7654 3210  
0100 0101  
Converted to 8B/10B notation. (Note (carefully). The order of  
bits is reversed.)  
Valid and Invalid Transmission Characters  
Data Byte Name  
D5.2  
Bits:ABCDEFGH  
10100 010  
The following tables define the valid Data Characters and valid  
Special Characters (K characters), respectively. The tables  
are used for both generating valid Transmission Characters  
(encoding) and checking the validity of received Transmission  
Characters (decoding). In the tables, each Valid-Data-byte or  
Special-Character-code entry has two columns that represent  
two (not necessarily different) Transmission Characters. The  
two columns correspond to the current value of the running  
disparity (Current RDor Current RD+). Running disparity  
is a binary parameter with either the value negative () or the  
value positive (+).  
Translated to a transmission Character in the 8B/10B Trans-  
mission Code.  
Bits: abcdeifghj  
1010010101  
Each valid Transmission Character of the 8B/10B Trans-  
mission Code has been given a name using the following  
convention: cxx.y, where c is used to show whether the Trans-  
mission Character is a Data Character (c is set to D, and SC/D  
= LOW) or a Special Character (c is set to K, and SC/D = HIGH).  
When c is set to D, xx is the decimal value of the binary number  
composed of the bits E, D, C, B, and A in that order, and the y is the  
decimal value of the binary number composed of the bits H, G, and  
F inthat order. Whenc is set to K, xx and y are derived by comparing  
the encoded bit patterns of the Special Character to those patterns  
derived from encoded Valid Data bytes and selecting the names of  
After powering on, the Transmitter may assume either a  
positive or negative value for its initial running disparity. Upon  
transmission of any Transmission Character, the transmitter  
will select the proper version of the Transmission Character  
based on the current running disparity value, and the Trans-  
mitter shall calculate a new value for its running disparity  
based on the contents of the transmitted character. Special  
Document #: 38-02033 Rev. *A  
Page 24 of 39  
CYP15G0403DX  
PRELIMINARY  
Character codes C1.7 and C2.7 can be used to force the trans-  
mission of a specific Special Character with a specific running  
disparity as required for some special sequences in X3.230.  
disparity for the next Valid Data byte or Special Character byte  
to be encoded and transmitted. Table 12 shows naming  
notations and examples of valid transmission characters.  
After powering on, the Receiver may assume either a positive  
or negative value for its initial running disparity. Upon reception  
of any Transmission Character, the Receiver shall decide  
whether the Transmission Character is valid or invalid  
according to the following rules and tables and shall calculate  
a new value for its Running Disparity based on the contents of  
the received character.  
Use of the Tables for Checking the Validity of Received  
Transmission Characters  
The column corresponding to the current value of the  
Receivers running disparity shall be searched for the received  
Transmission Character. If the received Transmission  
Character is found in the proper column, then the Trans-  
mission Character is valid and the associated Data byte or  
Special Character code is determined (decoded). If the  
received Transmission Character is not found in that column,  
then the Transmission Character is invalid. This is called a  
code violation. Independent of the Transmission Characters  
validity, the received Transmission Character shall be used to  
calculate a new value of running disparity. The new value shall  
be used as the Receivers current running disparity for the next  
received Transmission Character.  
The following rules for running disparity shall be used to  
calculate the new running-disparity value for Transmission  
Characters that have been transmitted (Transmitters running  
disparity) and that have been received (Receivers running  
disparity).  
Running disparity for a Transmission Character shall be calcu-  
lated from sub-blocks, where the first six bits (abcdei) form one  
sub-block and the second four bits (fghj) form the other  
sub-block. Running disparity at the beginning of the 6-bit  
sub-block is the running disparity at the end of the previous  
Transmission Character. Running disparity at the beginning of  
the 4-bit sub-block is the running disparity at the end of the  
6-bit sub-block. Running disparity at the end of the Trans-  
mission Character is the running disparity at the end of the  
4-bit sub-block.  
Table 12. Valid Transmission Characters  
Data  
DIN or QOUT  
Byte Name  
765  
43210  
Hex Value  
D0.0  
000  
00000  
00  
Running disparity for the sub-blocks shall be calculated as  
follows:  
D1.0  
D2.0  
000  
000  
00001  
00010  
01  
02  
1. Running disparity at the end of any sub-block is positive if  
the sub-block contains more ones than zeros. It is also pos-  
itive at the end of the 6-bit sub-block if the 6-bit sub-block  
is 000111, and it is positive at the end of the 4-bit sub-block  
if the 4-bit sub-block is 0011.  
.
.
.
.
.
.
.
.
2. Running disparity at the end of any sub-block is negative if  
the sub-block contains more zeros than ones. It is also neg-  
ative at the end of the 6-bit sub-block if the 6-bit sub-block  
is 111000, and it is negative at the end of the 4-bit sub-block  
if the 4-bit sub-block is 1100.  
D5.2  
010  
00010  
1
45  
.
.
.
.
.
.
.
.
3. Otherwise, running disparity at the end of the sub-block is  
the same as at the beginning of the sub-block.  
D30.7  
D31.7  
111  
111  
11110  
11111  
FE  
FF  
Use of the Tables for Generating Transmission Characters  
The appropriate entry in the table shall be found for the Valid  
Data byte or the Special Character byte for which a Trans-  
mission Character is to be generated (encoded). The current  
value of the Transmitters running disparity shall be used to  
select the Transmission Character from its corresponding  
column. For each Transmission Character transmitted, a new  
value of the running disparity shall be calculated. This new  
value shall be used as the Transmitters current running  
Detection of a code violation does not necessarily show that  
the Transmission Character in which the code violation was  
detected is in error. Code violations may result from a prior  
error that altered the running disparity of the bit stream which  
did not result in a detectable error at the Transmission  
Character in which the error occurred. Table 13 shows an  
example of this behavior.  
Document #: 38-02033 Rev. *A  
Page 25 of 39  
CYP15G0403DX  
PRELIMINARY  
DC Input Voltage  
0.5V to VCC+0.5V  
> 2000 V  
Maximum Ratings  
Static Discharge Voltage  
(per MIL-STD-883, Method 3015)  
Above which the useful life may be impaired.  
Storage Temperature  
65°C to +150°C  
Latch-Up Current  
> 200 ma  
Ambient Temperature with  
Power Applied  
Operating Range  
55°C to +125°C  
0.5V to +3.8V  
Range  
Ambient Temperature  
0°C to +70°C  
VCC  
Maximum Supply Voltage  
Commercial  
Industrial  
+3.3V ± 5%  
+3.3V ± 5%  
Output Current  
into LVTTL Outputs (LOW)  
40°C to +85°C  
30 mA  
CYP15G0403DX DC Electrical Characteristics  
Parameter Description  
LVTTL-compatible Outputs  
Test Conditions  
Min.  
Max.  
Unit  
VOHT  
VOLT  
IOST  
IOZL  
Output HIGH Voltage  
IOH = 4 mA, VCC = Min.  
2.4  
0.5  
15  
20  
VCC  
0.8  
45  
20  
V
V
Output LOW Voltage  
IOL = 4 mA, VCC = Min.  
VOUT = 0V [6]  
Output Short Circuit Current  
High-Z Output Leakage Current  
mA  
µA  
LVTTL-compatible Inputs  
VIHT  
VILT  
IIHT  
Input HIGH Voltage  
2.0  
VCC + 0.3  
0.8  
V
Input LOW Voltage  
Input HIGH Current  
0.5  
V
REFCLK Input, VIN = VCC  
Other Inputs, VIN = VCC  
REFCLK Input, VIN = 0.0V  
Other Inputs, VIN = 0.0V  
1.5  
ma  
µA  
ma  
µA  
µA  
+40  
IILT  
Input LOW Current  
−1.5  
40  
IIHPDT  
IILPUT  
Input HIGH Current with internal VIN = VCC  
pull-down  
+200  
Input LOW Current with internal VIN = 0.0V  
pull-up  
200  
µA  
LVDIFF Inputs: REFCLKx±  
[7]  
VDIFF  
VIHHP  
VILLP  
VCOM  
Input Differential Voltage  
400  
1.0  
VCC  
VCC  
mV  
V
Highest Input HIGH Voltage  
Lowest Input LOW voltage  
Common Mode Range  
GND  
1.0  
VCC/2  
V
[8]  
V
CC 1.2V  
V
3-Level Inputs  
VIHH  
VIMM  
VILL  
IIHH  
IIMM  
IILL  
3-Level Input HIGH Voltage  
Min. VCC Max.  
Min. VCC Max.  
Min. VCC Max.  
VIN = VCC  
0.87 * VCC  
0.47 * VCC  
0.0  
VCC  
V
V
3-Level Input MID Voltage  
3-Level Input LOW Voltage  
Input HIGH Current  
0.53 * VCC  
0.13 * VCC  
200  
V
µA  
µA  
µA  
Input MID current  
VIN = VCC/2  
50  
50  
Input LOW current  
VIN = GND  
200  
Differential CML Serial Outputs: OUTA1±, OUTA2±, OUTB1±, OUTB2±, OUTC1±, OUTC2±, OUTD1±, OUTD2±  
VOHC  
VOLC  
Output HIGH Voltage  
100differential load  
150differential load  
100differential load  
150differential load  
100differential load  
150differential load  
V
CC 0.5  
CC 0.5  
CC 1.1  
CC 1.1  
V
CC 0.2  
CC 0.2  
CC 0.7  
CC 0.7  
V
V
V
V
Output LOW Voltage  
V
V
V
V
V
V
VODIF  
Output Differential Voltage  
|(OUT+) (OUT)|  
450  
560  
800  
mV  
mV  
1000  
Notes:  
6. Tested one output at a time, output shorted for less than one second, less than 10% duty cycle.  
7. This is the minimum difference in voltage between the true and complement inputs required to ensure detection of a logic-1 or logic-0.  
8. The common mode range defines the allowable input voltage range of both input signal. The input signals must be different by the 100 mv and in this voltage  
range. This is the voltage range in which zero-crossing detection operates between true and complement inputs.  
Document #: 38-02033 Rev. *A  
Page 26 of 39  
CYP15G0403DX  
PRELIMINARY  
CYP15G0403DX DC Electrical Characteristics (continued)  
Parameter  
Description  
Test Conditions  
Min.  
100  
Max.  
Unit  
Differential Serial Line Receiver Inputs: INA1±, INA2±, INB1±, INB2±, INC1±, INC2±, IND1±, IND2±  
VDIFF[7]  
Input Differential Voltage  
|(IN+) (IN)|  
1200  
VCC  
mV  
VIHE  
VILE  
Highest Input HIGH Voltage  
Lowest Input LOW Voltage  
Input HIGH Current  
V
V
V
CC 2.0  
IIHE  
VIN = VIHE Max.  
1000  
µA  
µA  
V
IILE  
Input LOW Current  
VIN = VILE Min.  
700  
+1.25  
Typ.  
860  
VICOM[8]  
Common Mode Input Range  
((VCC 2.0V) + 0.5) min.,((VCC 0.5V)max.  
+3.25  
Max.  
1000  
TBD  
Miscellaneous  
[9]  
ICC  
Power Supply Current  
Freq. = Max.  
Commercial  
Industrial  
mA  
mA  
TBD  
3.3V  
R1  
R2  
OUTPUT  
R1 = 360Ω  
R2 = 270Ω  
L
R = 100Ω  
C
L
L
C < 5 pF  
C
7 pF  
L
C
Total capacitance  
L
R
L
Total capacitance  
LVTTL Input AC Test Load[10]  
CML Input Test Load  
[11]  
(a)  
(b)  
V
IHE  
3.0V  
Note 6  
V
IHE  
2.0V  
0.8V  
2.0V  
0.8V  
80%  
80%  
V
= 1.4V  
V
= 1.4V  
th  
th  
20%  
270 ps  
20%  
270 ps  
V
ILE  
GND  
<1.0 ns  
V
ILE  
< 1.0 ns  
(c) LVTTL Input Test Waveform  
(d) PECL Input Test Waveform  
OUTPUT  
R =100Ω  
C 7 pF  
Total capacitance  
C
L
L
L
C < 5 pF  
L
C
Total capacitance  
L
R
L
LVTTL Output AC Test Load[10]  
CML Input Test Load[11]  
(a)  
(b)  
V
IHE  
3.0V  
Note 6  
V
IHE  
2.0V  
0.8V  
2.0V  
0.8V  
80%  
80%  
V
= 1.4V  
V
= 1.4V  
th  
th  
20%  
270 ps  
20%  
270 ps  
V
ILE  
V
ILE  
< 1.7  
< 1.7 ns  
ns  
(c) LVTTL Output Test Waveform  
(d) PECL Output Test Waveform  
Notes:  
9. Maximum ICC is measured with VCC = 3.465V, frequency = 150 MHz, RFENx = LOW, TA = 45°C. Typical ICC is measured under similar conditions except with  
CC = 3.3V, TA = 25°C. The serial channels sending a constant 01 pattern and the outputs unloaded.  
V
10. Cypress uses constant current (ATE) load configurations and forcing functions. This figure is for reference only.  
11. The LVTTL switching threshold is 1.4V. All timing references are made where the signal edges cross the threshold voltage.  
Document #: 38-02033 Rev. *A  
Page 27 of 39  
CYP15G0403DX  
PRELIMINARY  
CYP15G0403DX Transmitter LVTTL Switching Characteristics Over the Operating Range  
Parameter  
Description  
TXCLKx Clock Cycle Frequency  
Min.  
20  
Max.  
150  
50  
Unit  
MHz  
ns  
fTS  
tTXCLK  
tTXCLKH  
tTXCLKL  
tTXCLKR  
tTXCLKF  
tTXDS  
TXCLKx Period  
6.66  
2.2  
TXCLKx HIGH Time  
ns  
TXCLKx LOW Time  
2.2  
ns  
[12, 14, 15]  
[12, 14, 15]  
TXCLKx Rise Time  
1.7  
1.7  
ns  
TXCLKx Fall Time  
ns  
Transmit Data Set-up Time to TXCLKx↑  
Transmit Data Hold Time from TXCLKx↑  
TXCLKOx Clock Cycle Frequency = 1x or 2x REFCLKx Frequency  
TXCLKOx Period  
2
1
ns  
tTXDH  
ns  
fTOS  
20  
150  
50  
MHz  
ns  
tTXCLKO  
6.66  
40  
tTXCLKOD  
tTXclk0d+  
tTXclk0d-  
TXCLKOx Duty Cycle  
60  
%
TXCLKO+ Duty Cycle Centered with 60% HIGH Time  
TXCLKODuty Cycle Centered with 40% HIGH Time  
0.7  
0.0  
+0.7  
+1.5  
ns  
ns  
CYP15G0403DX Receiver LVTTL Switching Characteristics Over the Operating Range  
Parameter  
fRS  
tRXCLKP  
tRXCLKH  
Description  
RXCLKx Clock Output Frequency  
Min.  
20  
Max.  
150  
50  
Unit  
MHz  
ns  
RXCLKx Period  
6.66  
1.5  
5
RXCLKx HIGH Time (RXRATE = LOW)  
RXCLKx HIGH Time (RXRATE = HIGH)  
RXCLKx LOW Time (RXRATE = LOW)  
RXCLKx LOW Time (RXRATE = HIGH)  
RXCLKx Duty Cycle Centered at 50%  
RXCLKx Rise Time  
24  
ns  
25  
ns  
tRXCLKL  
1.5  
5
24  
ns  
25  
ns  
tRXCLKD  
1.0  
+1.0  
1.2  
1.2  
ns  
[12]  
tRXCLKR  
ns  
[12]  
tRXCLKF  
RXCLKx Fall Time  
ns  
[13]  
tRXDv-  
Status and Data Valid Time to RXCLKX with RXCSEL MID or HIGH  
Status and Data Valid Time to RXCLDX  
Status and Data Valid Time to RXCLDX with half rate recovered clock  
Status and Data Valid Time to RXCLDX with half rate recovered clock  
5UI 1.5  
5UI 1.8  
5UI 1.0  
5UI 1.8  
ns  
[13]  
tRXDv+  
ns  
[13]  
tRXDv-  
ns  
[13]  
tRXDv+  
ns  
CYP15G0403DX REFCLKx Switching Characteristics Over the Operating Range  
Parameter  
fREF  
tREFCLK  
tREFH  
Description  
Min.  
20  
Max.  
150  
50  
35  
35  
35  
35  
70  
2
Unit  
MHz  
ns  
REFCLKx Clock Frequency  
REFCLKx Period  
6.6  
5.9  
2.9  
5.9  
2.9  
30  
REFCLKx HIGH Time (TXRATE = HIGH)  
REFCLKx HIGH Time (TXRATE = LOW)  
REFCLKx LOW Time (TXRATE = HIGH)  
REFCLKx LOW Time (TXRATE = LOW)  
REFCLKx Duty Cycle  
ns  
ns  
tREFL  
ns  
ns  
[11]  
tREFD  
%
[12, 14, 15]  
tREFR  
REFCLKx Rise Time (20%80%)  
REFCLKx Fall Time (20%80%)  
ns  
[12, 14, 15]  
tREFF  
2
ns  
Notes:  
12. Tested initially and after any design or process changes that may affect these parameters, but not 100% tested.  
13. Parallel data output specifications are only valid if all outputs are loaded with similar DC and AC loads.  
14. The ratio of rise time to falling time must not vary by greater than 2:1.  
15. For a given operating frequency, neither rise or fall specification can be greater than 20% of the clock-cycle period or the data sheet maximum time.  
Document #: 38-02033 Rev. *A  
Page 28 of 39  
CYP15G0403DX  
PRELIMINARY  
CYP15G0403DX REFCLKx Switching Characteristics Over the Operating Range (continued)  
Parameter  
tTREFDS  
Description  
Min.  
Max.  
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
%
Transmit Data Setup Time to REFCLKx (TXCKSEL = LOW)  
Transmit Data Hold Time from REFCLKx (TXCKSEL= LOW)  
Receive Data Access Time to REFCLKx (RXCKSEL = LOW)  
Receive Data Valid Time from REFCLKx (RXCKSEL = LOW)  
Receive Data Valid Time to REFCLKx (RXCKSEL = LOW)  
Receive Data Valid Time from REFCLKx  
2
1
tTREFDH  
tRREFDA  
tRREFDV  
tREFADV-  
tREFADV+  
tREFCDV-  
tREFCDV+  
tREFRX  
9.5  
4.0  
1.5  
1.5  
3
Received Data Valid Time to RXCLKx  
Received Data valid Time from RXCLKx  
REFCLKx Frequency Referenced to Received Clock Period[20]  
0.5  
0.02  
+0.02  
CYP15G0403DX Transmit Serial Outputs and TX PLL Characteristics Over the Operating Range  
Parameter  
Description  
Condition  
Min.  
5000  
50  
Max.  
660  
270  
500  
1000  
270  
500  
1000  
0.1  
Unit  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
UI  
tB  
tRISE  
Bit Time  
CML Output Rise Time 2080% (CML Test Load)[12]  
SPDSELx = HIGH  
SPDSELx = MID  
SPDSELx =LOW  
SPDSELx = HIGH  
SPDSELx = MID  
SPDSELx =LOW  
100  
200  
50  
tFALL  
CML Output Fall Time 8020% (CML Test Load)[12]  
100  
200  
tDJ  
tTJ  
Deterministic Jitter (peak-peak)[12, 18]  
Total Jitter (σ)[12, 19]  
0.21.0 Gbps  
1.01.5 Gbps  
0.2  
UI  
192  
TBD  
ps  
tTXLOCK  
Transmit PLLx lock to REFCLKx  
TBD  
CYP15G0403DX Receive Serial Inputs and CDR PLL Characteristics Over the Operating Range  
Parameter  
tRXLOCK  
Description  
Receive PLL lock to input data stream (cold start)  
Receive PLL lock to input data stream  
Receive PLL Unlock Rate  
Static Alignment[12, 16]  
Error Free Window [12, 17, 18]  
Min.  
Max.  
10  
Unit  
ms  
UI  
2500  
TBD  
tRXUNLOCK  
tSA  
TBD  
0.75  
ns  
ps  
tEFW  
UI  
Capacitance[12]  
Parameter  
CINTTL  
Description  
TTL Input Capacitance  
PECL input Capacitance  
Test Conditions  
TA = 25°C, f0 = 1 MHz, VCC = 3.3V  
TA = 25°C, f0 = 1 MHz, VCC = 3.3V  
Max.  
Unit  
7
4
pF  
pF  
CINPECL  
Notes:  
16. Static alignment is a measure of the alignment of the Receiver sampling point to the center of a bit. Static alignment is measured by sliding one bit edge in  
3,000 nominal transitions until a character error occurs.  
17. Receiver Unit Interval (UI) is calculated as 1/(fREF * 20) (when RXRATE = HIGH) or 1/(fREF * 10) (when RXRATE = LOW) if no data is being received, or  
1/(fREF * 20) (when RXRATE = HIGH) or 1/(fREF * 10) (when RXRATE = LOW) of the remote transmitter if data is being received. In an operating link this is  
equivalent to tB.  
18. Error-free Window (EFW) is a measure of the time window between bit centers where a transition may occur without causing a bit sampling error. EFW is  
measured over the operating range, input jitter < 50% Dj.  
19. The duty cycle specification is a simultaneous condition with the tREFH and tREFL parameters. This means that at faster character rates the REFCLKx duty  
cycle cannot be as large as 30%70%,  
20. REFCLKx has no phase or frequency relationship with the recovered clock(s) and only acts as a centering reference to reduce clock synchronization time.  
REFCLKx must be within ±200 PPM (±0.02%) of the transmitter PLL reference (REFCLKx) frequency, necessitating a ±100-PPM crystal.  
21. While sending continuous K28.5s, outputs loaded to a balanced 100load, over the operating range.  
22. While sending continuous K28.7s, after 100,000 samples measured at the cross point of differential outputs, time referenced to REFCLKx input, over the  
operating range.  
Document #: 38-02033 Rev. *A  
Page 29 of 39  
CYP15G0403DX  
PRELIMINARY  
CYP15G0403DX HOTLink II Transmitter Switching Waveforms  
Transmit Interface  
Write Timing  
TXCLKx selected  
TXRATE = LOW  
TXCKSEL = HIGH  
tTXCLK  
tTXCLKH  
tTXCLKL  
TXCLKx  
tTXDS  
tTXDH  
TXDx[7:0],  
TXCTx[1:0],  
Transmit Interface  
Write Timing  
REFCLKx selected  
TXRATE = LOW  
TXCKSEL = LOW  
REFCLKx  
tREFCLK  
tREFH  
tREFL  
tTREFDS  
tTREFDH  
TXDx[7:0],  
TXCTx[1:0],  
Transmit Interface  
Write Timing  
tREFCLK  
REFCLKx selected  
TXRATE = HIGH  
TXCKSEL = LOW  
tREFH  
tREFL  
REFCLKx  
Note 23  
tTREFDS  
tTREFDH  
tTREFDS  
tTREFDH  
TXDx[7:0],  
TXCTx[1:0],  
Transmit Interface  
TXCLKOx Timing  
TXCKSEL = LOW  
TXRATE = HIGH  
tREFCLK  
tREFH  
tREFL  
REFCLKx  
Note 24  
tTXCLKO  
tTXOH  
tTXOL  
Note 25  
TXCLKOx  
(internal)  
Note:  
23. When REFCLKx is configured for half-rate operation (TXRATE = HIGH) and data is captured using REFCLKx instead of a TXCLKx clock. Data is captured  
using both the rising and falling edges of REFCLKx.  
24. The TXCLKOx output remains at the character rate regardless of the state of TXRATE and does not follow the duty cycle of REFCLKx.  
25. The rising edge of TXCLKOx output has no direct phase relationship to the REFCLKx input.  
Document #: 38-02033 Rev. *A  
Page 30 of 39  
CYP15G0403DX  
PRELIMINARY  
CYP15G0403DX HOTLink II Transmitter Switching Waveforms (continued)  
Transmit Interface  
TXCLKOx Timing  
tREFCLK  
tREFH  
tREFL  
TXCKSEL = LOW  
TXRATE = LOW  
Note 24  
REFCLKx  
tTXCLKO  
tTXOH  
t
TXOL  
Note 25  
TXCLKOx  
Receive Interface  
Read Timing  
RXCKSEL = LOW  
RXRATE = LOW  
tREFCLK  
tREFH  
tREFL  
REFCLKx  
tRREFDA  
tRREFDH  
RXDx[7:0],  
RXSTx[2:0]  
tREFDH  
tREFDS  
RXCLKx  
Receive Interface  
Read Timing  
RXCKSEL = LOW  
RXRATE = HIGH  
tREFCLK  
tREFH  
tREFL  
REFCLKx  
tRREFDA  
tRREFDH  
tRREFDA  
RXDx[7:0],  
RXSTx[2:0],  
tREFDH  
tREFDS  
Note 26  
RXCLKx  
Note 26  
Note:  
26. When operated with a half-rate REFCLKx, the set-up and hold specifications for data relative to RXCLKx are relative to both rising and falling edges of the  
respective clock output.  
Document #: 38-02033 Rev. *A  
Page 31 of 39  
CYP15G0403DX  
PRELIMINARY  
Receive Interface  
Read Timing  
Recovered Clock selected  
RXRATE = LOW  
tRXCLKP  
tRXCLKH  
tRXCLKL  
RXCLKx+  
RXCLKx-  
RXDx[7:0],  
RXSTx[2:0],  
tRXDS  
tRXDH  
Receive Interface  
Read Timing  
Recovered Clock selected  
RXRATE = HIGH  
tRXCLKP  
tRXCLKH  
tRXCLKL  
RXCLKx+  
RXCLKx-  
tRXDS  
RXDx[7:0],  
RXSTx[2:0]  
tRXDH  
Static Alignment  
Error-Free Window  
t /2t  
B
SA  
t /2t  
B
SA  
t
EFW  
INA±  
INB±  
INA± ,  
INB±  
t
B
BIT CENTER  
BIT CENTER  
SAMPLE WINDOW  
Table 13. Code Violations Resulting from Prior Errors  
RD  
Character  
D21.1  
RD  
Character  
D10.2  
RD  
Character  
D23.5  
RD  
+
Transmitted data character  
Transmitted bit stream  
Bit stream after error  
101010 1001  
101010 1011  
D21.0  
010101 0101  
010101 0101  
D10.2  
111010 1010  
111010 1010  
Code Violation  
+
+
+
+
Decoded data character  
+
+
+
Document #: 38-02033 Rev. *A  
Page 32 of 39  
CYP15G0403DX  
PRELIMINARY  
Table 14. Valid Data Characters (TXCTx[0] = 0, RXSTx[2:0] = 000)  
Data  
Byte  
Data  
Byte  
Name HGF EDCBA  
Bits  
Current RD−  
Current RD+  
abcdei fghj  
Bits  
Current RD−  
abcdei fghj  
Current RD+  
abcdei fghj  
Name HGF EDCBA  
abcdei fghj  
D0.0  
D1.0  
000 00000  
000 00001  
000 00010  
000 00011  
000 00100  
000 00101  
000 00110  
000 00111  
000 01000  
000 01001  
000 01010  
000 01011  
000 01100  
000 01101  
000 01110  
000 01111  
000 10000  
000 10001  
000 10010  
000 10011  
000 10100  
000 10101  
000 10110  
000 10111  
000 11000  
000 11001  
000 11010  
000 11011  
000 11100  
000 11101  
000 11110  
000 11111  
010 00000  
010 00001  
010 00010  
100111 0100 011000 1011  
011101 0100 100010 1011  
101101 0100 010010 1011  
110001 1011 110001 0100  
110101 0100 001010 1011  
101001 1011 101001 0100  
011001 1011 011001 0100  
111000 1011 000111 0100  
111001 0100 000110 1011  
100101 1011 100101 0100  
010101 1011 010101 0100  
110100 1011 110100 0100  
001101 1011 001101 0100  
101100 1011 101100 0100  
011100 1011 011100 0100  
010111 0100 101000 1011  
011011 0100 100100 1011  
100011 1011 100011 0100  
010011 1011 010011 0100  
110010 1011 110010 0100  
001011 1011 001011 0100  
101010 1011 101010 0100  
011010 1011 011010 0100  
111010 0100 000101 1011  
110011 0100 001100 1011  
100110 1011 100110 0100  
010110 1011 010110 0100  
110110 0100 001001 1011  
001110 1011 001110 0100  
101110 0100 010001 1011  
011110 0100 100001 1011  
101011 0100 010100 1011  
100111 0101 011000 0101  
011101 0101 100010 0101  
101101 0101 010010 0101  
D0.1  
D1.1  
001 00000  
001 00001  
001 00010  
001 00011  
001 00100  
001 00101  
001 00110  
001 00111  
001 01000  
001 01001  
001 01010  
001 01011  
001 01100  
001 01101  
001 01110  
001 01111  
001 10000  
001 10001  
001 10010  
001 10011  
001 10100  
001 10101  
001 10110  
001 10111  
001 11000  
001 11001  
001 11010  
001 11011  
001 11100  
001 11101  
001 11110  
001 11111  
011 00000  
011 00001  
011 00010  
100111 1001 011000 1001  
011101 1001 100010 1001  
101101 1001 010010 1001  
110001 1001 110001 1001  
110101 1001 001010 1001  
101001 1001 101001 1001  
011001 1001 011001 1001  
111000 1001 000111 1001  
111001 1001 000110 1001  
100101 1001 100101 1001  
010101 1001 010101 1001  
110100 1001 110100 1001  
001101 1001 001101 1001  
101100 1001 101100 1001  
011100 1001 011100 1001  
010111 1001 101000 1001  
011011 1001 100100 1001  
100011 1001 100011 1001  
010011 1001 010011 1001  
110010 1001 110010 1001  
001011 1001 001011 1001  
101010 1001 101010 1001  
011010 1001 011010 1001  
111010 1001 000101 1001  
110011 1001 001100 1001  
100110 1001 100110 1001  
010110 1001 010110 1001  
110110 1001 001001 1001  
001110 1001 001110 1001  
101110 1001 010001 1001  
011110 1001 100001 1001  
101011 1001 010100 1001  
100111 0011 011000 1100  
011101 0011 100010 1100  
101101 0011 010010 1100  
D2.0  
D2.1  
D3.0  
D3.1  
D4.0  
D4.1  
D5.0  
D5.1  
D6.0  
D6.1  
D7.0  
D7.1  
D8.0  
D8.1  
D9.0  
D9.1  
D10.0  
D11.0  
D12.0  
D13.0  
D14.0  
D15.0  
D16.0  
D17.0  
D18.0  
D19.0  
D20.0  
D21.0  
D22.0  
D23.0  
D24.0  
D25.0  
D26.0  
D27.0  
D28.0  
D29.0  
D30.0  
D31.0  
D0.2  
D10.1  
D11.1  
D12.1  
D13.1  
D14.1  
D15.1  
D16.1  
D17.1  
D18.1  
D19.1  
D20.1  
D21.1  
D22.1  
D23.1  
D24.1  
D25.1  
D26.1  
D27.1  
D28.1  
D29.1  
D30.1  
D31.1  
D0.3  
D1.2  
D1.3  
D2.2  
D2.3  
Document #: 38-02033 Rev. *A  
Page 33 of 39  
CYP15G0403DX  
PRELIMINARY  
Table 14. Valid Data Characters (TXCTx[0] = 0, RXSTx[2:0] = 000) (continued)  
Data  
Byte  
Data  
Byte  
Bits  
Current RD−  
Current RD+  
abcdei fghj  
Bits  
Current RD−  
abcdei fghj  
Current RD+  
abcdei fghj  
Name HGF EDCBA  
abcdei fghj  
Name HGF EDCBA  
D3.2  
D4.2  
010 00011  
010 00100  
010 00101  
010 00110  
010 00111  
010 01000  
010 01001  
010 01010  
010 01011  
010 01100  
010 01101  
010 01110  
010 01111  
010 10000  
010 10001  
010 10010  
010 10011  
010 10100  
010 10101  
010 10110  
010 10111  
010 11000  
010 11001  
010 11010  
010 11011  
010 11100  
010 11101  
010 11110  
010 11111  
110001 0101 110001 0101  
110101 0101 001010 0101  
101001 0101 101001 0101  
011001 0101 011001 0101  
111000 0101 000111 0101  
111001 0101 000110 0101  
100101 0101 100101 0101  
010101 0101 010101 0101  
110100 0101 110100 0101  
001101 0101 001101 0101  
101100 0101 101100 0101  
011100 0101 011100 0101  
010111 0101 101000 0101  
011011 0101 100100 0101  
100011 0101 100011 0101  
010011 0101 010011 0101  
110010 0101 110010 0101  
001011 0101 001011 0101  
101010 0101 101010 0101  
011010 0101 011010 0101  
111010 0101 000101 0101  
110011 0101 001100 0101  
100110 0101 100110 0101  
010110 0101 010110 0101  
110110 0101 001001 0101  
001110 0101 001110 0101  
101110 0101 010001 0101  
011110 0101 100001 0101  
101011 0101 010100 0101  
D3.3  
D4.3  
011 00011  
011 00100  
011 00101  
011 00110  
011 00111  
011 01000  
011 01001  
011 01010  
011 01011  
011 01100  
011 01101  
011 01110  
011 01111  
011 10000  
011 10001  
011 10010  
011 10011  
011 10100  
011 10101  
011 10110  
011 10111  
011 11000  
011 11001  
011 11010  
011 11011  
011 11100  
011 11101  
011 11110  
011 11111  
110001 1100 110001 0011  
110101 0011 001010 1100  
101001 1100 101001 0011  
011001 1100 011001 0011  
111000 1100 000111 0011  
111001 0011 000110 1100  
100101 1100 100101 0011  
010101 1100 010101 0011  
110100 1100 110100 0011  
001101 1100 001101 0011  
101100 1100 101100 0011  
011100 1100 011100 0011  
010111 0011 101000 1100  
011011 0011 100100 1100  
100011 1100 100011 0011  
010011 1100 010011 0011  
110010 1100 110010 0011  
001011 1100 001011 0011  
101010 1100 101010 0011  
011010 1100 011010 0011  
111010 0011 000101 1100  
110011 0011 001100 1100  
100110 1100 100110 0011  
010110 1100 010110 0011  
110110 0011 001001 1100  
001110 1100 001110 0011  
101110 0011 010001 1100  
011110 0011 100001 1100  
101011 0011 010100 1100  
D5.2  
D5.3  
D6.2  
D6.3  
D7.2  
D7.3  
D8.2  
D8.3  
D9.2  
D9.3  
D10.2  
D11.2  
D12.2  
D13.2  
D14.2  
D15.2  
D16.2  
D17.2  
D18.2  
D19.2  
D20.2  
D21.2  
D22.2  
D23.2  
D24.2  
D25.2  
D26.2  
D27.2  
D28.2  
D29.2  
D30.2  
D31.2  
D10.3  
D11.3  
D12.3  
D13.3  
D14.3  
D15.3  
D16.3  
D17.3  
D18.3  
D19.3  
D20.3  
D21.3  
D22.3  
D23.3  
D24.3  
D25.3  
D26.3  
D27.3  
D28.3  
D29.3  
D30.3  
D31.3  
Document #: 38-02033 Rev. *A  
Page 34 of 39  
CYP15G0403DX  
PRELIMINARY  
Table 14. Valid Data Characters (TXCTx[0] = 0, RXSTx[2:0] = 000) (continued)  
Data  
Byte  
Data  
Byte  
Bits  
Current RD−  
Current RD+  
abcdei fghj  
Bits  
Current RD−  
abcdei fghj  
Current RD+  
abcdei fghj  
Name HGF EDCBA  
abcdei fghj  
Name HGF EDCBA  
D0.4  
D1.4  
100 00000  
100 00001  
100 00010  
100 00011  
100 00100  
100 00101  
100 00110  
100 00111  
100 01000  
100 01001  
100 01010  
100 01011  
100 01100  
100 01101  
100 01110  
100 01111  
100 10000  
100 10001  
100 10010  
100 10011  
100 10100  
100 10101  
100 10110  
100 10111  
100 11000  
100 11001  
100 11010  
100 11011  
100 11100  
100 11101  
100 11110  
100 11111  
110 00000  
110 00001  
110 00010  
100111 0010 011000 1101  
011101 0010 100010 1101  
101101 0010 010010 1101  
110001 1101 110001 0010  
110101 0010 001010 1101  
101001 1101 101001 0010  
011001 1101 011001 0010  
111000 1101 000111 0010  
111001 0010 000110 1101  
100101 1101 100101 0010  
010101 1101 010101 0010  
110100 1101 110100 0010  
001101 1101 001101 0010  
101100 1101 101100 0010  
011100 1101 011100 0010  
010111 0010 101000 1101  
011011 0010 100100 1101  
100011 1101 100011 0010  
010011 1101 010011 0010  
110010 1101 110010 0010  
001011 1101 001011 0010  
101010 1101 101010 0010  
011010 1101 011010 0010  
111010 0010 000101 1101  
110011 0010 001100 1101  
100110 1101 100110 0010  
010110 1101 010110 0010  
110110 0010 001001 1101  
001110 1101 001110 0010  
101110 0010 010001 1101  
011110 0010 100001 1101  
101011 0010 010100 1101  
100111 0110 011000 0110  
011101 0110 100010 0110  
101101 0110 010010 0110  
D0.5  
D1.5  
101 00000  
101 00001  
101 00010  
101 00011  
101 00100  
101 00101  
101 00110  
101 00111  
101 01000  
101 01001  
101 01010  
101 01011  
101 01100  
101 01101  
101 01110  
101 01111  
101 10000  
101 10001  
101 10010  
101 10011  
101 10100  
101 10101  
101 10110  
101 10111  
101 11000  
101 11001  
101 11010  
101 11011  
101 11100  
101 11101  
101 11110  
101 11111  
111 00000  
111 00001  
111 00010  
100111 1010 011000 1010  
011101 1010 100010 1010  
101101 1010 010010 1010  
110001 1010 110001 1010  
110101 1010 001010 1010  
101001 1010 101001 1010  
011001 1010 011001 1010  
111000 1010 000111 1010  
111001 1010 000110 1010  
100101 1010 100101 1010  
010101 1010 010101 1010  
110100 1010 110100 1010  
001101 1010 001101 1010  
101100 1010 101100 1010  
011100 1010 011100 1010  
010111 1010 101000 1010  
011011 1010 100100 1010  
100011 1010 100011 1010  
010011 1010 010011 1010  
110010 1010 110010 1010  
001011 1010 001011 1010  
101010 1010 101010 1010  
011010 1010 011010 1010  
111010 1010 000101 1010  
110011 1010 001100 1010  
100110 1010 100110 1010  
010110 1010 010110 1010  
110110 1010 001001 1010  
001110 1010 001110 1010  
101110 1010 010001 1010  
011110 1010 100001 1010  
101011 1010 010100 1010  
100111 0001 011000 1110  
011101 0001 100010 1110  
101101 0001 010010 1110  
D2.4  
D2.5  
D3.4  
D3.5  
D4.4  
D4.5  
D5.4  
D5.5  
D6.4  
D6.5  
D7.4  
D7.5  
D8.4  
D8.5  
D9.4  
D9.5  
D10.4  
D11.4  
D12.4  
D13.4  
D14.4  
D15.4  
D16.4  
D17.4  
D18.4  
D19.4  
D20.4  
D21.4  
D22.4  
D23.4  
D24.4  
D25.4  
D26.4  
D27.4  
D28.4  
D29.4  
D30.4  
D31.4  
D0.6  
D10.5  
D11.5  
D12.5  
D13.5  
D14.5  
D15.5  
D16.5  
D17.5  
D18.5  
D19.5  
D20.5  
D21.5  
D22.5  
D23.5  
D24.5  
D25.5  
D26.5  
D27.5  
D28.5  
D29.5  
D30.5  
D31.5  
D0.7  
D1.6  
D1.7  
D2.6  
D2.7  
Document #: 38-02033 Rev. *A  
Page 35 of 39  
CYP15G0403DX  
PRELIMINARY  
Table 14. Valid Data Characters (TXCTx[0] = 0, RXSTx[2:0] = 000) (continued)  
Data  
Byte  
Data  
Byte  
Bits  
Current RD−  
Current RD+  
abcdei fghj  
Bits  
Current RD−  
abcdei fghj  
Current RD+  
abcdei fghj  
Name HGF EDCBA  
abcdei fghj  
Name HGF EDCBA  
D3.6  
D4.6  
110 00011  
110 00100  
110 00101  
110 00110  
110 00111  
110 01000  
110 01001  
110 01010  
110 01011  
110 01100  
110 01101  
110 01110  
110 01111  
110 10000  
110 10001  
110 10010  
110 10011  
110 10100  
110 10101  
110 10110  
110 10111  
110 11000  
110 11001  
110 11010  
110 11011  
110 11100  
110 11101  
110 11110  
110 11111  
110001 0110 110001 0110  
110101 0110 001010 0110  
101001 0110 101001 0110  
011001 0110 011001 0110  
111000 0110 000111 0110  
111001 0110 000110 0110  
100101 0110 100101 0110  
010101 0110 010101 0110  
110100 0110 110100 0110  
001101 0110 001101 0110  
101100 0110 101100 0110  
011100 0110 011100 0110  
010111 0110 101000 0110  
011011 0110 100100 0110  
100011 0110 100011 0110  
010011 0110 010011 0110  
110010 0110 110010 0110  
001011 0110 001011 0110  
101010 0110 101010 0110  
011010 0110 011010 0110  
111010 0110 000101 0110  
110011 0110 001100 0110  
100110 0110 100110 0110  
010110 0110 010110 0110  
110110 0110 001001 0110  
001110 0110 001110 0110  
101110 0110 010001 0110  
011110 0110 100001 0110  
101011 0110 010100 0110  
D3.7  
D4.7  
111 00011  
111 00100  
111 00101  
111 00110  
111 00111  
111 01000  
111 01001  
111 01010  
111 01011  
111 01100  
111 01101  
111 01110  
111 01111  
111 10000  
111 10001  
111 10010  
111 10011  
111 10100  
111 10101  
111 10110  
111 10111  
111 11000  
111 11001  
111 11010  
111 11011  
111 11100  
111 11101  
111 11110  
111 11111  
110001 1110 110001 0001  
110101 0001 001010 1110  
101001 1110 101001 0001  
011001 1110 011001 0001  
111000 1110 000111 0001  
111001 0001 000110 1110  
100101 1110 100101 0001  
010101 1110 010101 0001  
110100 1110 110100 1000  
001101 1110 001101 0001  
101100 1110 101100 1000  
011100 1110 011100 1000  
010111 0001 101000 1110  
011011 0001 100100 1110  
100011 0111 100011 0001  
010011 0111 010011 0001  
110010 1110 110010 0001  
001011 0111 001011 0001  
101010 1110 101010 0001  
011010 1110 011010 0001  
111010 0001 000101 1110  
110011 0001 001100 1110  
100110 1110 100110 0001  
010110 1110 010110 0001  
110110 0001 001001 1110  
001110 1110 001110 0001  
101110 0001 010001 1110  
011110 0001 100001 1110  
101011 0001 010100 1110  
D5.6  
D5.7  
D6.6  
D6.7  
D7.6  
D7.7  
D8.6  
D8.7  
D9.6  
D9.7  
D10.6  
D11.6  
D12.6  
D13.6  
D14.6  
D15.6  
D16.6  
D17.6  
D18.6  
D19.6  
D20.6  
D21.6  
D22.6  
D23.6  
D24.6  
D25.6  
D26.6  
D27.6  
D28.6  
D29.6  
D30.6  
D31.6  
D10.7  
D11.7  
D12.7  
D13.7  
D14.7  
D15.7  
D16.7  
D17.7  
D18.7  
D19.7  
D20.7  
D21.7  
D22.7  
D23.7  
D24.7  
D25.7  
D26.7  
D27.7  
D28.7  
D29.7  
D30.7  
D31.7  
Document #: 38-02033 Rev. *A  
Page 36 of 39  
CYP15G0403DX  
PRELIMINARY  
Table 15. Valid Special Character Codes and Sequences (TXCTx = special character code or RXSTx[2:0] = 001)[27, 28]  
S.C. Byte Name  
Cypress  
Alternate  
S.C. Byte  
Bits  
S.C. Byte  
Bits  
Current RD−  
Current RD+  
abcdei fghj  
S.C. Code Name  
K28.0  
K28.1 [30]  
K28.2 [30]  
K28.3  
K28.4 [30]  
K28.5 [30, 31]  
K28.6 [30]  
K28.7 [30, 32]  
K23.7  
Name[29]  
C0.0  
HGF EDCBA  
Name[29]  
HGF EDCBA  
abcdei fghj  
(C00)  
(C01)  
(C02)  
(C03)  
(C04)  
(C05)  
(C06)  
(C07)  
(C08)  
(C09)  
(C0A)  
(C0B)  
000 00000 C28.0  
000 00001 C28.1  
000 00010 C28.2  
000 00011 C28.3  
000 00100 C28.4  
000 00101 C28.5  
000 00110 C28.6  
000 00111 C28.7  
000 01000 C23.7  
000 01001 C27.7  
000 01010 C29.7  
000 01011 C30.7  
(C1C)  
(C3C)  
(C5C)  
(C7C)  
(C9C)  
(CBC)  
(CDC)  
(CFC)  
(CF7)  
(CFB)  
(CFD)  
(CFE)  
000_11100  
001_11100  
010_11100  
011_11100  
100_11100  
101_11100  
110_11100  
111_11100  
111_10111  
111_11011  
111_11101  
111_11110  
001111 0100  
001111 1001  
001111 0101  
001111 0011  
001111 0010  
001111 1010  
001111 0110  
001111 1000  
111010 1000  
110110 1000  
101110 1000  
011110 1000  
110000 1011  
110000 0110  
110000 1010  
110000 1100  
110000 1101  
110000 0101  
110000 1001  
110000 0111  
000101 0111  
001001 0111  
010001 0111  
100001 0111  
C1.0  
C2.0  
C3.0  
C4.0  
C5.0  
C6.0  
C7.0  
C8.0  
C9.0  
C10.0  
C11.0  
K27.7  
K29.7  
K30.7  
End of Frame Sequence  
EOFxx C2.1  
(C22)  
001 00010 C2.1  
(C22)  
001 00010  
K28.5,Dn.xxx0[33] +K28.5,Dn.xxx1[33]  
Code Rule Violation and SVS Tx Pattern  
Exception [32, 34] C0.7  
(CE0)  
(CE1)  
(CE2)  
111 00000 C0.7  
111 00001 C1.7  
111 00010 C2.7  
(CE0)  
(CE1)  
(CE2)  
111 00000  
111 00001  
111 00010  
100111 1000  
001111 1010  
110000 0101  
011000 0111  
001111 1010  
110000 0101  
K28.5[35]  
C1.7  
C2.7  
+K28.5 [36]  
Running Disparity Violation Pattern  
Exception [37]  
C4.7  
(CE4)  
111 00100 C4.7  
(CE4)  
111 00100  
110111 0101  
001000 1010  
Notes:  
27. All codes not shown are reserved.  
28. Notation for Special Character Code Name is consistent with Fibre Channel and ESCON naming conventions. Special Character Code Name is intended to  
describe binary information present on I/O pins. Common usage for the name can either be in the form used for describing Data patterns (i.e., C0.0 through  
C31.7), or in hex notation (i.e., Cnn where nn = the specified value between 00 and FF).  
29. Both the Cypress and alternate encodings may be used for data transmission to generate specific Special Character Codes. The decoding process for received  
characters generates Cypress codes or Alternate codes as selected by the BOE[7:0] configuration inputs.  
30. These characters are used for control of ESCON interfaces. They can be sent as embedded commands or other markers when not operating using ESCON  
protocols.  
31. The K28.5 character is used for framing operations by the receiver. It is also the pad or fill character transmitted to maintain the serial link when no user data  
is available.  
32. Care must be taken when using this Special Character code. When a C7.0 is followed by a D11.x or D20.x, or when an SVS (C0.7) is followed by a D11.x, an  
alias K28.5 sync character is created. These sequences can cause erroneous framing and should be avoided while RFENx = HIGH.  
33. C2.1 = Transmit either K28.5+ or +K28.5as determined by Current RD and modify the Transmission Character that follows, by setting its least significant bit  
to 1 or 0. If Current RD at the start of the following character is plus (+) the LSB is set to 0, and if Current RD is minus () the LSB becomes 1. This modification  
allows construction of X3.230 EOFframe delimiters wherein the second data byte is determined by the Current RD.  
For example, to send EOFdtthe controller could issue the sequence C2.1D21.4D21.4D21.4, and the HOTLink Transmitter will send either  
K28.5D21.4D21.4D21.4 or K28.5D21.5D21.4D21.4 based on Current RD. Likewise to send EOFdtithe controller could issue the sequence  
C2.1D10.4D21.4D21.4, and the HOTLink Transmitter will send either K28.5D10.4D21.4D21.4 or K28.5D10.5D21.4D21.4 based on Current RD.  
The receiver will never output this Special Character, since K28.5 is decoded as C5.0, C1.7, or C2.7, and the subsequent bytes are decoded as data.  
34. C0.7 = Transmit a deliberate code rule violation. The code chosen for this function follows the normal Running Disparity rules. Transmission of this Special  
Character has the same effect as asserting TXSVS = HIGH. The receiver will only output this Special Character if the Transmission Character being decoded  
is not found in the tables.  
35. C1.7 = Transmit Negative K28.5 (K28.5+) disregarding Current RD. The receiver will only output this Special Character if K28.5 is received with the wrong  
running disparity. The receiver will output C1.7 if K28.5 is received with RD+, otherwise K28.5 is decoded as C5.0 or C2.7.  
36. C2.7 = Transmit Positive K28.5 (+K28.5) disregarding Current RD. The receiver will only output this Special Character if K28.5 is received with the wrong  
running disparity. The receiver will output C2.7 if +K28.5 is received with RD, otherwise K28.5 is decoded as C5.0 or C1.7.  
37. C4.7 = Transmit a deliberate code rule violation to indicate a Running Disparity violation. The receiver will only output this Special Character if the Transmission  
Character being decoded is found in the tables, but Running Disparity does not match. This might indicate that an error occurred in a prior byte.  
Document #: 38-02033 Rev. *A  
Page 37 of 39  
PRELIMINARY  
CYP15G0403DX  
Ordering Information  
Operating  
Range  
Speed  
Standard  
Standard  
Ordering Code  
Package Name  
Package Type  
CYP15G0403DX-BGC  
CYP15G0403DX-BGI  
BG256  
BG256  
256-lead Thermally Enhanced Ball Grid Array Commercial  
256-lead Thermally Enhanced Ball Grid Array Industrial  
Package Diagram  
256-Lead PBGA (27 x 27 x 2.33 mm) BG256  
51-85097-*A  
HOTLink, HOTLink II, and MultiFrame are either trademarks or registered trademarks of Cypress Semiconductor. IBM, ESCON,  
and FICON are either trademarks or registered trademarks of International Business Machines. All product and company names  
mentioned in this document may be the trademarks of their respective holders.  
Document #: 38-02033 Rev. *A  
Page 38 of 39  
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize  
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.  
CYP15G0403DX  
PRELIMINARY  
Document Title: CYP15G0403DXA Quad HOTLink II Transceiver (Preliminary)  
Document Number: 38-02033  
Issue  
Date  
Orig. of  
Change  
REV.  
**  
ECN NO.  
113238  
114539  
Description of Change  
03/18/02  
03/26/02  
TPS  
BSS  
New Data Sheet  
*A  
Rev ** has the incorrect package drawing in the datasheet. It should be *A  
for spec 51-85097  
Document #: 38-02033 Rev. *A  
Page 39 of 39  
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