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CYK256K16MCCB-60BVI

型号：

CYK256K16MCCB-60BVI

品牌：

CYPRESS[ CYPRESS ]

页数：

10 页

PDF大小：

178 K

下载PDF手册
CYK256K16MCCB  
MoBL3™  
4-Mbit (256K x 16) Pseudo Static RAM  
can be put into standby mode when deselected (CE HIGH or  
both BHE and BLE are HIGH). The input/output pins (I/O0  
through I/O15) are placed in a high-impedance state when:  
deselected (CE HIGH), outputs are disabled (OE HIGH), both  
Byte High Enable and Byte Low Enable are disabled (BHE,  
BLE HIGH), or during a write operation (CE LOW and WE  
LOW).  
Features  
• Wide voltage range: 2.70V–3.30V  
• Access time: 55 ns, 60 ns and 70 ns  
• Ultra-low active power  
— Typical active current: 1 mA @ f = 1 MHz  
— Typical active current: 8 mA @ f = fmax (70-ns speed)  
• Ultra low standby power  
Writing to the device is accomplished by taking Chip Enable  
(CE LOW) and Write Enable (WE) input LOW. If Byte Low  
Enable (BLE) is LOW, then data from I/O pins (I/O0 through  
I/O7) is written into the location specified on the address pins  
(A0 through A17). If Byte High Enable (BHE) is LOW, then data  
from I/O pins (I/O8 through I/O15) is written into the location  
specified on the address pins (A0 through A17).  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
• Offered in a 48-ball BGA package  
Reading from the device is accomplished by taking Chip  
Enable (CE LOW) and Output Enable (OE) LOW while forcing  
the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is  
LOW, then data from the memory location specified by the  
address pins will appear on I/O0 to I/O7. If Byte High Enable  
(BHE) is LOW, then data from memory will appear on I/O8 to  
I/O15. Refer to the truth table for a complete description of read  
and write modes.  
Functional Description[1]  
The CYK256K16MCCB is a high-performance CMOS Pseudo  
static RAM organized as 256K words by 16 bits that supports  
an asynchronous memory interface. This device features  
advanced circuit design to provide ultra-low active current.  
This is ideal for providing More Battery Life™ (MoBL®) in  
portable applications such as cellular telephones. The device  
Logic Block Diagram  
DATA IN DRIVERS  
A10  
A 9  
A 8  
A 7  
A 6  
A 5  
A 4  
256K × 16  
RAM Array  
I/O0 – I/O7  
I/O8 – I/O15  
A 3  
A 2  
A 1  
A 0  
COLUMN DECODER  
BHE  
WE  
CE  
OE  
BLE  
Power-Down  
Circuit  
BHE  
BLE  
CE  
Note:  
1. For best practice recommendations, please refer to the CY application note System Design Guidelines on http://www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05585 Rev. *D  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Revised January 27, 2005  
CYK256K16MCCB  
MoBL3™  
Pin Configuration[2, 3, 4]  
VFBGA  
Top View  
1
4
3
2
5
6
A
A
A
2
NC  
I/O  
OE  
BLE  
0
1
A
B
I/O BHE  
A
CE  
I/O  
A
0
8
3
4
I/O  
A
A
6
I/O  
I/O  
2
C
D
E
F
5
10  
9
1
A
V
SS  
Vcc  
Vss  
I/O  
I/O  
3
A17  
7
11  
DNU  
A
16  
V
CC  
I/O  
I/O  
12  
4
A
A
15  
I/O  
I/O  
I/O  
I/O  
14  
13  
5
14  
6
A
A
G
NC  
I/O  
WE  
I/O  
13  
12  
15  
7
A
A
A
NC  
H
A
10  
9
11  
NC  
8
Product Portfolio  
Power Dissipation  
Operating ICC(mA)  
f = 1MHz f = fmax Standby ISB2(µA)  
V
CC Range (V)  
Speed  
(ns)  
Product  
Min.  
2.70  
Typ.[5]  
Max.  
3.30  
Typ.[5]  
Max.  
Typ.[5]  
Max.  
Typ.[5]  
Max.  
CYK256K16MCCB  
3.0  
55  
60  
70  
1
5
14  
8
22  
17  
40  
15  
Notes:  
2. Ball H1, G2 and ball H6 for the VFBGA package can be used to upgrade to an 8-Mbit, 16-Mbit and 32-Mbit density, respectively.  
3. NC “no connect” – not connected internally to the die.  
4.DNU (Do Not Use) pins have to be left floating or tied to Vss to ensure proper application.  
5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V  
, T = 25°C.  
A
CC  
CC(typ.)  
Document #: 38-05585 Rev. *D  
Page 2 of 10  
CYK256K16MCCB  
MoBL3™  
DC Input Voltage[6, 7, 8] ....................................–0.4V to 3.7V  
Output Current into Outputs (LOW) ............................ 20 mA  
Maximum Ratings  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
Static Discharge Voltage ......................................... > 2001V  
(per MIL-STD-883, Method 3015)  
Storage Temperature ................................–65°C to + 150°C  
Latch-up Current ....................................................> 200 mA  
Ambient Temperature with  
Power Applied ...........................................–55°C to + 125°C  
Operating Range  
Supply Voltage to Ground Potential ................ –0.4V to 4.6V  
Range  
Ambient Temperature  
VCC  
DC Voltage Applied to Outputs  
Industrial  
–25°C to +85°C  
2.70V to 3.30V  
in High-Z State[6, 7, 8] ....................................... –0.4V to 3.7V  
Electrical Characteristics Over the Operating Range  
CYK256K16MCCB -55, 60, 70  
Parameter  
VCC  
Description  
Test Conditions  
Min.  
Typ.[5]  
Max.  
Unit  
V
Supply Voltage  
2.7  
VCC = 2.70V VCC –0.4  
VCC = 2.70V  
3.0  
3.3  
VOH  
Output HIGH Voltage IOH = –0.1 mA  
V
VOL  
Output LOW  
Voltage  
IOL = 0.1 mA  
0.4  
V
VIH  
VIL  
IIX  
Input HIGH Voltage  
Input LOW Voltage  
0.8 * Vcc  
–0.4  
VCC + 0.4V  
V
V
0.4  
+1  
Input Leakage  
Current  
GND < VIN < VCC  
–1  
µA  
IOZ  
ICC  
Output Leakage  
Current  
GND < VOUT < VCC, Output Disabled  
–1  
+1  
µA  
VCC Operating  
Supply Current  
f = fMAX = 1/tRC  
VCC  
VCCmax  
=
14 for 55-ns speed 22 for 55-ns speed mA  
14 for 60-ns speed 22 for 60-ns speed  
8 for 70-ns speed 15 for 70-ns speed  
IOUT = 0 mA  
CMOS levels  
f = 1 MHz  
1 for all speeds  
150  
5 for all speeds mA  
ISB1  
Automatic CE  
Power-Down  
Current—CMOS  
Inputs  
CE > VCC−0.2V  
VCC = 3.3V  
250  
µA  
V
IN > VCC–0.2V, VIN <  
0.2V) f = fMAX  
(Address and Data  
Only), f = 0 (OE, WE,  
BHE and BLE), VCC  
=
3.30V  
ISB2  
Automatic CE  
Power-Down  
Current—CMOS  
Inputs  
CE > VCC – 0.2V  
VCC = 3.3V  
17  
40  
µA  
V
V
IN > VCC – 0.2V or  
IN < 0.2V,  
f = 0, VCC = 3.30V  
Thermal Resistance[9]  
Parameter  
Description  
Test Conditions  
BGA  
Unit  
°C/W  
°C/W  
ΘJA  
ΘJC  
Thermal Resistance (Junction to Ambient)  
Thermal Resistance (Junction to Case)  
Test conditions follow standard test methods  
and procedures for measuring thermal  
impedence, per EIA / JESD51.  
55  
17  
Capacitance[9]  
Parameter  
Description  
Input Capacitance  
Output Capacitance  
Test Conditions  
TA = 25°C, f = 1 MHz,  
CC = VCC(typ)  
Max.  
Unit  
CIN  
8
8
pF  
pF  
V
COUT  
Notes:  
6. V  
7. V  
= –0.5V for pulse durations less than 20 ns.  
IL(MIN)  
= V + 0.5V for pulse durations less than 20 ns.  
IH(Max)  
CC  
8. Overshoot and undershoot specifications are characterized and are not 100% tested.  
9. Tested initially and after any design or process changes that may affect these parameters.  
Document #: 38-05585 Rev. *D  
Page 3 of 10  
CYK256K16MCCB  
MoBL3™  
AC Test Loads and Waveforms  
R1  
ALL INPUT PULSES  
90%  
10%  
VCC  
OUTPUT  
VCC  
GND  
90%  
10%  
Fall Time = 1 V/ns  
R2  
30 pF  
Rise Time = 1 V/ns  
Equivalentto:  
INCLUDING  
JIG AND  
SCOPE  
THÉVENINEQUIVALENT  
RTH  
OUTPUT  
VTH  
Parameters  
3.0V VCC  
22000  
22000  
11000  
1.50  
Unit  
Ω
R1  
R2  
Ω
RTH  
VTH  
Ω
V
Switching Characteristics Over the Operating Range [10]  
55 ns[14]  
60 ns  
Max.  
70 ns  
Max.  
Parameter  
Read Cycle  
Description  
Min.  
Max.  
Min.  
60  
Min.  
70  
Unit  
tRC  
Read Cycle Time  
55[14]  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tAA  
Address to Data Valid  
55  
60  
70  
tOHA  
tACE  
tDOE  
tLZOE  
tHZOE  
tLZCE  
tHZCE  
tDBE  
tLZBE  
tHZBE  
Data Hold from Address Change  
CE LOW to Data Valid  
5
8
10  
55  
25  
60  
25  
70  
35  
OE LOW to Data Valid  
OE LOW to LOW Z[11, 13]  
OE HIGH to High Z[11, 13]  
CE LOW to Low Z[11, 13]  
CE HIGH to High Z[11, 13]  
BLE / BHE LOW to Data Valid  
BLE / BHE LOW to Low Z[11, 13]  
BLE / BHE HIGH to HIGH Z[11, 13]  
Address Skew  
5
2
5
2
5
5
25  
25  
25  
25  
55  
25  
60  
25  
70  
5
5
5
10  
0
10  
5
25  
10  
[14]  
tSK  
Write Cycle[12]  
tWC  
tSCE  
tAW  
tHA  
Write Cycle Time  
55  
45  
45  
0
60  
45  
45  
0
70  
60  
55  
0
ns  
ns  
ns  
ns  
ns  
ns  
CE LOW to Write End  
Address Set-Up to Write End  
Address Hold from Write End  
Address Set-Up to Write Start  
WE Pulse Width  
tSA  
0
0
0
tPWE  
40  
40  
45  
Notes:  
10. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 ns/V, timing reference levels of V  
/2, input pulse levels  
CC(typ)  
of 0V to V  
, and output loading of the specified I /I as shown in the “AC Test Loads and Waveforms” section.  
CC(typ.)  
OL OH  
11. t  
, t  
, t  
, and t  
transitions are measured when the outputs enter a high impedance state.  
HZOE HZCE HZBE  
HZWE  
12. The internal Write time of the memory is defined by the overlap of WE, CE = V , BHE and/or BLE = V . All signals must be ACTIVE to initiate a write and any  
IL  
IL  
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates  
the write.  
13. High-Z and Low-Z parameters are characterized and are not 100% tested.  
14. To achieve 55-ns performance, the read access should be CE controlled. In this case t  
is the critical parameter and t is satisfied when the addresses are  
SK  
ACE  
stable prior to chip enable going active. For the 70-ns cycle, the addresses must be stable within 10 ns after the start of the read cycle.  
Document #: 38-05585 Rev. *D  
Page 4 of 10  
CYK256K16MCCB  
MoBL3™  
Switching Characteristics Over the Operating Range (continued)[10]  
55 ns[14]  
60 ns  
Max.  
70 ns  
Parameter  
Description  
BLE / BHE LOW to Write End  
Data Set-Up to Write End  
Data Hold from Write End  
WE LOW to High-Z[11, 13]  
WE HIGH to Low-Z[11, 13]  
Min.  
50  
25  
0
Max.  
Min.  
50  
25  
0
Min.  
55  
25  
0
Max.  
Unit  
ns  
tBW  
tSD  
tHD  
ns  
ns  
tHZWE  
tLZWE  
25  
25  
25  
ns  
5
5
5
ns  
Switching Waveforms  
Read Cycle 1 (Address Transition Controlled)[14, 15, 16]  
tRC  
ADDRESS  
tAA  
tSK  
tOHA  
DATA OUT  
PREVIOUS DATA VALID  
DATA VALID  
Read Cycle 2 (OE Controlled)[14, 16]  
ADDRESS  
tRC  
t
SK  
CE  
tHZCE  
tACE  
BHE/BLE  
tDBE  
tHZBE  
tLZBE  
OE  
tHZOE  
tDOE  
tLZOE  
HIGH IMPEDANCE  
HIGH  
IMPEDANCE  
DATA OUT  
DATA VALID  
tLZCE  
ICC  
ISB  
V
CC  
50%  
50%  
SUPPLY  
CURRENT  
Notes:  
15. Device is continuously selected. OE, CE = V .  
IL  
16. WE is HIGH for Read Cycle.  
Document #: 38-05585 Rev. *D  
Page 5 of 10  
CYK256K16MCCB  
MoBL3™  
Switching Waveforms (continued)  
Write Cycle 1 (WE Controlled)[12, 13, 17, 18, 19]  
tWC  
ADDRESS  
CE  
tSCE  
tAW  
tHA  
tSA  
tPWE  
WE  
tBW  
BHE/BLE  
OE  
tSD  
tHD  
VALID DATA  
DATA I/O  
DON’T CARE  
tHZOE  
Write Cycle 2 (CE Controlled)[12, 13, 17, 18, 19]  
t WC  
ADDRESS  
tSCE  
CE  
t
SA  
tHA  
tAW  
tPWE  
WE  
tBW  
BHE/BLE  
OE  
tSD  
tHZOE  
tHD  
VALID DATA  
DATA I/O  
DON’T CARE  
Notes:  
17. Data I/O is high-impedance if OE > V  
.
IH  
18. If Chip Enable goes INACTIVE with WE = V , the output remains in a high-impedance state.  
IH  
19. During this period in the DATA I/O waveform, the I/Os could be in the output state and input signals should not be applied.  
Document #: 38-05585 Rev. *D  
Page 6 of 10  
CYK256K16MCCB  
MoBL3™  
Switching Waveforms (continued)  
Write Cycle 3 (WE Controlled, OE LOW)[18, 19]  
tWC  
ADDRESS  
CE  
tSCE  
tBW  
BHE/BLE  
tAW  
tHA  
tSA  
tPWE  
WE  
tSD  
tHD  
DON’T CARE  
DATAI/O  
VALID DATA  
tLZWE  
tHZWE  
Write Cycle 4 (BHE/BLE Controlled, OE LOW)[18, 19]  
tWC  
ADDRESS  
CE  
tSCE  
tAW  
tHA  
tBW  
BHE/BLE  
WE  
tSA  
tPWE  
tSD  
tHD  
DON’T CARE  
VALID DATA  
DATA I/O  
Document #: 38-05585 Rev. *D  
Page 7 of 10  
CYK256K16MCCB  
MoBL3™  
Truth Table [20]  
CE  
H
X
WE  
X
OE  
X
BHE  
X
BLE  
X
Inputs/Outputs  
High Z  
Mode  
Power  
Deselect/Power-Down  
Deselect/Power-Down  
Read  
Standby (ISB  
Standby (ISB  
Active (ICC  
Active (ICC  
)
X
X
H
H
High Z  
)
L
H
L
L
L
Data Out (I/O0 – I/O15)  
)
L
H
L
H
L
Data Out (I/O0 – I/O7);  
High Z (I/O8 – I/O15)  
Read  
)
L
H
L
L
H
High Z (I/O0 – I/O7);  
Data Out (I/O8 – I/O15)  
Read  
Active (ICC)  
L
L
L
L
L
H
H
H
L
H
H
H
X
X
L
H
L
H
L
L
L
L
High Z  
Output Disabled  
Output Disabled  
Output Disabled  
Write  
Active (ICC  
Active (ICC  
Active (ICC  
Active (ICC  
Active (ICC  
)
High Z  
)
High Z  
)
L
Data In (I/O0 – I/O15)  
)
L
H
Data In (I/O0 – I/O7);  
High Z (I/O8 – I/O15)  
Write  
)
L
L
X
L
H
High Z (I/O0 – I/O7);  
Data In (I/O8 – I/O15)  
Write  
Active (ICC)  
Ordering Information  
Speed  
Package  
Operating  
Range  
(ns)  
Ordering Code  
Name  
BV48A  
BV48A  
BV48A  
BV48A  
BV48A  
Package Type  
55  
CYK256K16MCCB-55BVI  
CYK256K16MCCB-60BVI  
CYK256K16MCCB-70BVI  
CYK256K16MCB-55BVXI  
CYK256K16MCB-70BVXI  
48-ball Fine Pitch BGA (6 mm × 8mm × 1.0 mm)  
48-ball Fine Pitch BGA (6 mm × 8mm × 1.0 mm)  
48-ball Fine Pitch BGA (6 mm × 8mm × 1.0 mm)  
Industrial  
Industrial  
Industrial  
60  
70  
55  
48-ball Fine Pitch BGA (6 mm × 8mm × 1.0 mm) (Pb-Free) Industrial  
48-ball Fine Pitch BGA (6 mm × 8mm × 1.0 mm) (Pb-Free) Industrial  
70  
Note:  
20. H = Logic HIGH, L = Logic LOW, X = Don’t Care.  
Document #: 38-05585 Rev. *D  
Page 8 of 10  
CYK256K16MCCB  
MoBL3™  
Package Diagram  
48-Lead VFBGA (6 x 8 x 1 mm) BV48A  
51-85150-*B  
MoBL is a registered trademark, and More Battery Life and MoBL3 are trademarks, of Cypress Semiconductor Corporation. All  
product and company names mentioned in this document may be the trademarks of their respective holders.  
Document #: 38-05585 Rev. *D  
Page 9 of 10  
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be  
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its  
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
CYK256K16MCCB  
MoBL3™  
Document History Page  
Document Title: CYK256K16MCCB MoBL3™4-Mbit (256K x 16) Pseudo Static RAM  
Document Number: 38-05585  
Orig. of  
REV.  
**  
ECN NO. Issue Date Change  
Description of Change  
223482  
234474  
260330  
298651  
314013  
See ECN  
See ECN  
See ECN  
See ECN  
See ECN  
REF  
SYT  
PCI  
New data sheet  
*A  
Changed ball E3 on package pinout from NC to DNU  
Changed from preliminary to final  
*B  
*C  
PCI  
Added 60-ns speed bin  
*D  
RKF  
Added Pb-Free parts to the Ordering information  
Document #: 38-05585 Rev. *D  
Page 10 of 10  
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