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8N4S271FC-1080CDI8

型号：

8N4S271FC-1080CDI8

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

18 页

PDF大小：

495 K

下载PDF手册
LVDS Frequency-Programmable  
Crystal Oscillator  
IDT8N4S271  
DATA SHEET  
General Description  
Features  
The IDT8N4S271 is a Factory Frequency-Programmable Crystal  
Oscillator with very flexible frequency programming capabilities. The  
device uses IDT’s fourth generation FemtoClock® NG technology for  
an optimum of high clock frequency and low phase noise  
performance. The device accepts 2.5V or 3.3V supply and is  
packaged in a small, lead-free (RoHS 6) 6-lead ceramic 5mm x 7mm  
x 1.55mm package.  
• Fourth generation FemtoClock® NG technology  
• Factory-programmable clock output frequency from 15.476MHz to  
866.67MHz and from 975MHz to 1,300MHz  
• Frequency programming resolution is 218Hz and better  
• One 2.5V, 3.3V LVDS clock output  
• Output enable control (positive polarity), LVCMOS/LVTTL  
compatible  
The device can be factory programmed to any in the range from  
15.476MHz to 866.67MHz and from 975MHz to 1,300MHz and  
supports a very high degree of frequency precision of 218Hz or  
better. The extended temperature range supports wireless  
infrastructure, telecommunication and networking end equipment  
requirements.  
• RMS phase jitter @ 231.25MHz (12kHz - 20MHz):  
0.48ps (typical), integer PLL feedback configuration  
• RMS phase jitter @ 231.25MHz (1kHz - 40MHz):   
0.50ps (typical), integer PLL feedback configuration  
• 2.5V or 3.3V supply  
• -40°C to 85°C ambient operating temperature  
• Available in a lead-free (RoHS 6) 6-pin ceramic package  
Block Diagram  
Pin Assignment  
DNU 1  
OE 2  
6 V  
DD  
FemtoClock® NG  
VCO  
1950-2600MHz  
PFD  
&
LPF  
Q  
nQ  
5 nQ  
4 Q  
÷P  
OSC  
÷N  
GND 3  
fXTAL  
IDT8N4S271  
6-lead ceramic 5mm x 7mm x 1.55mm  
package body  
÷MINT, MFRAC  
2
CD Package  
Top View  
7
25  
Configuration Register (ROM)  
Pullup  
OE  
IDT8N4S271CCD REVISION A NOVEMBER 29, 2012  
1
©2012 Integrated Device Technology, Inc.  
IDT8N4S271 Data Sheet  
LVDS FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR  
Pin Description and Characteristic Tables  
Table 1. Pin Descriptions  
Number  
Name  
DNU  
OE  
Type  
Description  
1
2
Do not use (factory use only).  
Input  
Power  
Output  
Power  
Pullup  
Output enable pin. See Table 3A for function. LVCMOS/LVTTL interface levels.  
Power supply ground.  
3
GND  
Q, nQ  
VDD  
4, 5  
6
Differential clock output pair. LVDS interface levels.  
Power supply pin.  
NOTE: Pullup refers to an internal input resistor. See Table 2, Pin Characteristics, for typical values.  
Table 2. Pin Characteristics  
Symbol  
CIN  
Parameter  
Test Conditions  
Minimum  
Typical  
5.5  
Maximum  
Units  
pF  
Input Capacitance  
Input Pullup Resistor  
RPULLUP  
50  
k  
Function Tables  
Table 3A. OE Configuration  
Input  
OE  
Output Enable  
0
Outputs Q, nQ are in high-impedance state  
Outputs are enabled  
1 (default)  
NOTE: OE is an asynchronous control.  
Table 3B. Output Frequency Range  
15.476MHz to 866.67MHz  
975MHz to 1,300MHz  
NOTE: Supported output frequency range. The output frequency can be programmed to any frequency in this range and to a precision of  
218Hz or better.  
IDT8N4S271CCD REVISION A NOVEMBER 29, 2012  
2
©2012 Integrated Device Technology, Inc.  
 
IDT8N4S271 Data Sheet  
LVDS FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR  
Principles of Operation  
The block diagram consists of the internal 3rd overtone crystal and  
oscillator which provide the reference clock fXTAL of either  
18-bit fractional portion (MFRAC) and provides the means for  
high-resolution frequency generation. The output frequency fOUT is  
calculated by:  
114.285MHz or 100MHz. The PLL includes the FemtoClock NG VCO  
along with the Pre-divider (P), the feedback divider (M) and the post  
divider (N). The P, M, and N dividers determine the output frequency  
based on the fXTAL reference. The feedback divider is fractional  
supporting a huge number of output frequencies. The configuration  
of the feedback divider to integer-only values results in an improved  
output phase noise characteristics at the expense of the range of  
output frequencies. Internal registers are used to hold one factory  
pre-set P, M, and N configuration setting. The P, M, and N frequency  
configuration supports an output frequency range from 15.476MHz to  
866.67MHz and from 975MHz to 1,300MHz.  
1
P N  
MFRAC + 0.5  
------------  
f
= f  
MINT + -------------------------------------  
OUT  
XTAL  
18  
2
Frequency Configuration  
An order code is assigned to each frequency configuration  
programmed by the factory (default frequencies). For more  
information on the available default frequencies and order codes,  
please see the Ordering Information section in this document. For  
available order codes, see the FemtoClock NG Ceramic-Package XO  
and VCXO Ordering Product Information document.  
The devices use the fractional feedback divider with a delta-sigma  
modulator for noise shaping and robust frequency synthesis  
capability. The relatively high reference frequency minimizes phase  
noise generated by frequency multiplication and allows more efficient  
shaping of noise by the delta-sigma modulator.  
For more information on programming capabilities of the device for  
custom frequency and pull-range configurations, see the FemtoClock  
NG Ceramic 5x7 Module Programming Guide.  
The output frequency is determined by the 2-bit pre-divider (P), the  
feedback divider (M) and the 7-bit post divider (N). The feedback  
divider (M) consists of both a 7-bit integer portion (MINT) and an  
IDT8N4S271CCD REVISION A NOVEMBER 29, 2012  
3
©2012 Integrated Device Technology, Inc.  
IDT8N4S271 Data Sheet  
LVDS FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR  
Absolute Maximum Ratings  
NOTE: Stresses beyond those listed under Absolute Maximum  
Ratings may cause permanent damage to the device. These ratings  
are stress specifications only. Functional operation of product at  
these conditions or any conditions beyond those listed in the DC  
Characteristics or AC Characteristics is not implied. Exposure to  
absolute maximum rating conditions for extended periods may affect  
product reliability.  
Item  
Rating  
Supply Voltage, VDD  
Inputs, VI  
3.63V  
-0.5V to VDD + 0.5V  
Outputs, IO (LVDS)  
Continuous Current  
Surge Current  
10mA  
15mA  
Package Thermal Impedance, JA  
49.4C/W (0 mps)  
-65C to 150C  
Storage Temperature, TSTG  
DC Electrical Characteristics  
Table 4A. Power Supply DC Characteristics, VDD =3.3V 5%, TA = -40°C to 85°C  
Symbol  
VDD  
Parameter  
Test Conditions  
Minimum  
Typical  
3.3  
Maximum  
3.465  
Units  
V
Power Supply Voltage  
Power Supply Current  
3.135  
IDD  
134  
160  
mA  
Table 4B. Power Supply DC Characteristics, VDD = 2.5V 5%, TA = -40°C to 85°C  
Symbol  
VDD  
Parameter  
Test Conditions  
Minimum  
Typical  
2.5  
Maximum  
2.625  
Units  
V
Power Supply Voltage  
Power Supply Current  
2.375  
IDD  
129  
155  
mA  
Table 4C. LVCMOS/LVTTL DC Characteristic, VDD = 3.3V 5% or 2.5V 5%, TA = -40°C to 85°C  
Symbol Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
VDD + 0.3  
VDD + 0.3  
0.8  
Units  
V
VDD = 3.3V  
VDD = 2.5V  
VDD = 3.3V  
2
VIH  
VIL  
Input High Voltage  
OE  
OE  
1.7  
-0.3  
-0.3  
V
V
Input Low Voltage  
VDD = 2.5V  
0.7  
V
IIH  
IIL  
Input High Current  
Input Low Current  
OE  
OE  
VDD = VIN = 3.465V or 2.625V  
VDD = 3.465V or 2.625V, VIN = 0V  
10  
µA  
µA  
-150  
IDT8N4S271CCD REVISION A NOVEMBER 29, 2012  
4
©2012 Integrated Device Technology, Inc.  
IDT8N4S271 Data Sheet  
LVDS FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR  
Table 4D. LVDS DC Characteristics, VDD = 3.3V 5%, TA = -40°C to 85°C  
Symbol  
VOD  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
454  
Units  
mV  
mV  
V
Differential Output Voltage  
VOD Magnitude Change  
Offset Voltage  
247  
370  
VOD  
VOS  
50  
1.125  
1.22  
1.375  
50  
VOS  
VOS Magnitude Change  
mV  
Table 4E. LVDS DC Characteristics, VDD = 2.5V 5%, TA = -40°C to 85°C  
Symbol  
VOD  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
454  
Units  
mV  
mV  
V
Differential Output Voltage  
VOD Magnitude Change  
Offset Voltage  
247  
360  
VOD  
VOS  
50  
1.125  
1.21  
1.375  
50  
VOS  
VOS Magnitude Change  
mV  
AC Electrical Characteristics  
Table 5. AC Characteristics, VDD = 3.3V 5% or 2.5V 5%, TA = -40°C to 85°C  
Symbol  
fOUT  
fI  
Parameter  
Test Conditions  
Minimum  
15.476  
975  
Typical  
Maximum  
Units  
866.67  
1,300  
10  
MHz  
MHz  
ppm  
ppm  
ppm  
ppm  
ppm  
ppm  
ppm  
ppm  
ppm  
ps  
Output Frequency  
Initial Accuracy  
Measured @ 25°C  
Option code = A or B  
100  
50  
fS  
fA  
fT  
Temperature Stability  
Aging  
Option code = E or F  
Option code = K or L  
20  
Frequency drift over 10 year life  
Frequency drift over 15 year life  
Option code A, B (10 year life)  
Option code E, F (10 year life)  
Option code K, L (10 year life)  
3
5
113  
63  
Total Stability  
33  
tjit(cc)  
Cycle-to-Cycle Jitter; NOTE 1  
RMS Period Jitter; NOTE 1  
20  
tjit(per)  
3
5
ps  
IDT8N4S271CCD REVISION A NOVEMBER 29, 2012  
5
©2012 Integrated Device Technology, Inc.  
IDT8N4S271 Data Sheet  
LVDS FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR  
Table 5 (continued). AC Characteristics, VDD = 3.3V 5% or 2.5V 5%, TA = -40°C to 85°C  
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
RMS Phase Jitter (Random);  
Fractional PLL feedback and  
17MHz fOUT 1300MHz,  
0.497  
0.882  
ps  
f
XTAL=100.000MHz (2xxx order Integration range: 12kHz-20MHz  
codes), NOTES 2, 3, 4  
500MHz fOUT 1300MHz,  
Integration range: 12kHz-20MHz  
0.232  
0.250  
0.275  
0.242  
0.476  
0.275  
0.504  
0.322  
0.450  
0.405  
0.311  
0.680  
0.359  
0.700  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
125MHz fOUT 500MHz,  
Integration range: 12kHz-20MHz  
17MHz fOUT 125MHz,  
Integration range: 12kHz-20MHz  
RMS Phase Jitter (Random);  
Integer PLL feedback and  
fOUT 156.25MHz,  
Integration range: 12kHz-20MHz  
tjit(Ø)  
fXTAL=100.00MHz   
(1xxx order codes),   
NOTES 2, 3, 5  
fOUT 231.25MHz,  
Integration range: 12kHz-20MHz  
fOUT 156.25MHz,  
Integration range: 12kHz-20MHz  
fOUT 231.25MHz,  
Integration range: 12kHz-20MHz  
RMS Phase Jitter (Random)  
Fractional PLL feedback and  
17MHz fOUT 1300MHz,  
Integration range: 12kHz-20MHz  
0.474  
0.986  
ps  
f
XTAL=114.285MHz (0xxx order  
codes), NOTES 2, 3, 6  
Single-side Band Phase Noise,   
100Hz from Carrier  
N(100)  
N(1k)  
fOUT 231.25MHz  
fOUT 231.25MHz  
fOUT 231.25MHz  
fOUT 231.25MHz  
fOUT 231.25MHz  
-88  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
Single-side Band Phase Noise,   
1kHz from Carrier  
-110  
-123  
-125  
-137  
-141  
Single-side Band Phase Noise,   
10kHz from Carrier  
N(10k)  
N(100k)  
N(1M)  
N(10M)  
Single-side Band Phase Noise,   
100kHz from Carrier  
Single-side Band Phase Noise,   
1MHz from Carrier  
Single-side band phase noise,   
10MHz from Carrier  
fOUT 231.25MHz  
tR / tF  
odc  
Output Rise/Fall Time  
Output Duty Cycle  
20% to 80%  
50  
47  
450  
53  
ps  
%
Device Startup Time After  
Power Up  
tSTARTUP  
20  
ms  
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is  
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium  
has been reached under these conditions.  
NOTE: XTAL parameters (initial accuracy, temperature stability, aging and total stability) are guaranteed by manufacturing.  
NOTE 1: This parameter is defined in accordance with JEDEC standard 65.  
NOTE 2: Refer to the phase noise plot.  
NOTE 3: See the FemtoClock NG Ceramic 5x7 Modules Programming guide for more information on PLL feedback modes and the optimum  
configuration for phase noise. Integer PLL feedback is the default operation for the dddd = 1xxx order codes.  
NOTE 4: Applies to output frequencies: 81MHz, 122.88MHz, 231.25MHz, 622.08MHz, 866.67MHz and 1124MHz.  
NOTE 5: Applies to output frequencies: 75MHz, 100MHz, 106.25MHz, 125MHz, 156.25MHz, 425MHz, 500MHz, 625MHz, 975MHz   
and 1300MHz.  
NOTE 6: Applies to output frequencies: 15.4762MHz, 38.88MHz, 114.285MHz, 496MHz, 669.32MHz and 658MHz.  
IDT8N4S271CCD REVISION A NOVEMBER 29, 2012  
6
©2012 Integrated Device Technology, Inc.  
IDT8N4S271 Data Sheet  
LVDS FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR  
Typical Phase Noise at 231.25MHz (12kHz - 20MHz)  
Offset Frequency (Hz)  
IDT8N4S271CCD REVISION A NOVEMBER 29, 2012  
7
©2012 Integrated Device Technology, Inc.  
IDT8N4S271 Data Sheet  
LVDS FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR  
Parameter Measurement Information  
SCOPE  
SCOPE  
Q
Q
V
V
DD  
DD  
3.3V 5%  
POWER SUPPLY  
2.5V 5%  
POWER SUPPLY  
+
Float GND –  
+
Float GND –  
nQ  
nQ  
2.5V LVDS Output Load Test Circuit  
3.3V LVDS Output Load Test Circuit  
Phase Noise Plot  
VOH  
VREF  
VOL  
1σ contains 68.26% of all measurements  
2σ contains 95.4% of all measurements  
3σ contains 99.73% of all measurements  
4σ contains 99.99366% of all measurements  
6σ contains (100-1.973x10-7)% of all measurements  
Offset Frequency  
f1  
Histogram  
f2  
Reference Point  
(Trigger Edge)  
RMS Phase Jitter =  
Mean Period  
(First edge after trigger)  
1
*
Area Under Curve Defined by the Offset Frequency Markers  
2 * * ƒ  
RMS Phase Jitter  
RMS Period Jitter  
nQ  
nQ  
Q
Q
tPW  
tPERIOD  
➤
➤
tcycle n  
tcycle n+1  
➤
➤
tPW  
tjit(cc) = tcycle n – tcycle n+1  
|
|
odc =  
x 100%  
1000 Cycles  
tPERIOD  
Cycle-to-Cycle Jitter  
Output Duty Cycle/Pulse Width/Period  
IDT8N4S271CCD REVISION A NOVEMBER 29, 2012  
8
©2012 Integrated Device Technology, Inc.  
IDT8N4S271 Data Sheet  
LVDS FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR  
Parameter Measurement Information, continued  
VDD  
out  
nQ  
80%  
tF  
80%  
tR  
DC Input  
VOD  
20%  
LVDS  
20%  
Q
out  
VOS/Δ VOS  
ä
Output Rise/Fall Time  
Offset Voltage Setup  
VDD  
out  
DC Input  
100  
LVDS  
out  
Differential Output Voltage Setup  
IDT8N4S271CCD REVISION A NOVEMBER 29, 2012  
9
©2012 Integrated Device Technology, Inc.  
IDT8N4S271 Data Sheet  
LVDS FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR  
Applications Information  
LVDS Driver Termination  
For a general LVDS interface, the recommended value for the  
termination impedance (ZT) is between 90and 132. The actual  
value should be selected to match the differential impedance (Z0) of  
your transmission line. A typical point-to-point LVDS design uses a  
100parallel resistor at the receiver and a 100differential  
transmission-line environment. In order to avoid any  
transmission-line reflection issues, the components should be  
surface mounted and must be placed as close to the receiver as  
possible. IDT offers a full line of LVDS compliant devices with two  
types of output structures: current source and voltage source. The  
standard termination schematic as shown in Figure 1A can be used  
with either type of output structure. Figure 1B, which can also be  
used with both output types, is an optional termination with center tap  
capacitance to help filter common mode noise. The capacitor value  
should be approximately 50pF. If using a non-standard termination, it  
is recommended to contact IDT and confirm if the output structure is  
current source or voltage source type. In addition, since these  
outputs are LVDS compatible, the input receiver’s amplitude and  
common-mode input range should be verified for compatibility with  
the output.  
ZO ZT  
LVDS  
Driver  
LVDS  
Receiver  
ZT  
Figure 1A. Standard Termination  
ZT  
ZO ZT  
LVDS  
Driver  
2
ZT  
2
LVDS  
Receiver  
C
Figure 1B. Optional Termination  
Figure 1. Typical LVDS Driver Termination  
IDT8N4S271CCD REVISION A NOVEMBER 29, 2012  
10  
©2012 Integrated Device Technology, Inc.  
IDT8N4S271 Data Sheet  
LVDS FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR  
Schematic Layout  
Figure 2 shows an example IDT8N4S271 application schematic. The  
schematic example focuses on functional connections and is  
intended as an example only and may not represent the exact user  
configuration. Refer to the pin description and functional tables in the  
datasheet to ensure the logic control inputs are properly set. For  
example OE can be configured from an FPGA instead of set with pull  
up and pull down resistors as shown.  
capacitor on the VDD pin must be placed on the device side with direct  
return to the ground plane though vias. The remaining filter  
components can be on the opposite side of the PCB.  
Power supply filter component recommendations are a general  
guideline to be used for reducing external noise from coupling into  
the devices. The filter performance is designed for a wide range of  
noise frequencies. This low-pass filter starts to attenuate noise at  
approximately 10kHz. If a specific frequency noise component is  
known, such as switching power supplies frequencies, it is  
recommended that component values be adjusted and if required,  
additional filtering be added. Additionally, good general design  
practices for power plane voltage stability suggests adding bulk  
capacitance in the local area of all devices.  
As with any high speed analog circuitry, the power supply pins are  
vulnerable to random noise, so to achieve optimum jitter performance  
isolation of the VDD pin from power supply is required. In order to  
achieve the best possible filtering, it is recommended that the  
placement of the filter components be on the device side of the PCB  
as close to the power pins as possible. If space is limited, the 0.1µF  
Logic Control Input Examples  
Set Logic  
Input to '1'  
Set Logic  
Input to '0'  
VDD  
VDD  
RU1  
1K  
RU2  
Not Ins tall  
To Logic  
Input  
pins  
To Logic  
Input  
pins  
RD1  
Not Install  
RD2  
1K  
3.3V  
FB1  
2
1
VDD  
C4  
10uF  
BLM18BB221SN1  
C5  
0.1uF  
Place 0.1uF bypass cap  
directly adjacent to  
the VDD pin.  
U3  
DNU VDD  
C3  
0.1uF  
1
2
3
6
5
4
Zo = 50 Ohm  
OE  
OE  
nQ  
Q
+
R1  
100  
GND  
Zo = 50 Ohm  
-
IDT8N4S271CCD  
LVDS Receiv er  
Figure 2. IDT8N4S271 Schematic Example  
IDT8N4S271CCD REVISION A NOVEMBER 29, 2012  
11  
©2012 Integrated Device Technology, Inc.  
IDT8N4S271 Data Sheet  
LVDS FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR  
Power Considerations  
This section provides information on power dissipation and junction temperature for the IDT8N4S271.  
Equations and example calculations are also provided.  
1. Power Dissipation.  
The total power dissipation for the IDT8N4S271 is the sum of the core power plus the output power dissipated due to the loading. The following  
is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.  
•
Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 160mA = 554.4mW  
2. Junction Temperature.  
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The  
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond  
wire and bond pad temperature remains below 125°C.  
The equation for Tj is as follows: Tj = JA * Pd_total + TA  
Tj = Junction Temperature  
JA = Junction-to-Ambient Thermal Resistance  
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)  
TA = Ambient Temperature  
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and  
a multi-layer board, the appropriate value is 49.4°C/W per Table 6 below.  
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:  
85°C + 0.554W * 49.4°C/W = 112.4°C. This is below the limit of 125°C.  
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of  
board (multi-layer).  
Table 6. Thermal Resistance JA for 6 Lead Ceramic 5mm x 7mm Package, Forced Convection  
JA by Velocity  
Meters per Second  
0
1
2.5  
Multi-Layer PCB, JEDEC Standard Test Boards  
49.4°C/W  
44.2°C/W  
42.1°C/W  
IDT8N4S271CCD REVISION A NOVEMBER 29, 2012  
12  
©2012 Integrated Device Technology, Inc.  
IDT8N4S271 Data Sheet  
LVDS FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR  
Reliability Information  
Table 7. JA vs. Air Flow Table for a 6-lead Ceramic 5mm x 7mm Package  
JA vs. Air Flow  
Meters per Second  
0
1
2.5  
Multi-Layer PCB, JEDEC Standard Test Boards  
49.4°C/W  
44.2°C/W  
42.1°C/W  
Transistor Count  
The transistor count for IDT8N4S271 is: 47,511  
IDT8N4S271CCD REVISION A NOVEMBER 29, 2012  
13  
©2012 Integrated Device Technology, Inc.  
IDT8N4S271 Data Sheet  
LVDS FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR  
Package Outline and Package Dimensions  
IDT8N4S271CCD REVISION A NOVEMBER 29, 2012  
14  
©2012 Integrated Device Technology, Inc.  
IDT8N4S271 Data Sheet  
LVDS FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR  
Ordering Information for FemtoClock NG Ceramic-Package XO and VCXO Products  
The programmable VCXO and XO devices support a variety of  
devices options such as the output type, number of default frequen-  
cies, internal crystal frequency, power supply voltage, ambient  
temperature range and the frequency accuracy. The device options,  
default frequencies and default VCXO pull range must be specified at  
the time of order and are programmed by IDT before the shipment.  
The table below specifies the available order codes, including the  
device options and default frequency configurations. Example part  
number: the order code 8N3QV01FG-0001CDI specifies a  
contains a 114.285MHz internal crystal as frequency source,  
industrial temperature range, a lead-free (6/6 RoHS) 6-lead ceramic  
5mm x 7mm x 1.55mm package and is factory-programmed to the  
default frequencies of 100MHz, 122.88MHz, 125MHz and  
156.25MHz and to the VCXO pull range of min. 100ppm.  
Other default frequencies and order codes are available from IDT on  
request. For more information on available default frequencies, see  
the FemtoClock NG Ceramic-Package XO and VCXO Ordering  
Product Information document.  
programmable, quad default-frequency VCXO with a voltage supply  
of 2.5V, a LVPECL output, a 50ppm crystal frequency accuracy,  
Part/Order Numbers  
8N X X XXX X X - dddd XX X X  
Shipping Package  
8: Tape & Reel  
(no letter): Tray  
FemtoClock NG  
I/O Identifier  
Ambient Temperature Range  
“I”: Industrial: (TA = -40°C to 85°C)  
(no letter) : (TA = 0°C to 70°C)  
0: LVCMOS  
3: LVPECL  
4: LVDS  
Package Code  
CD: Lead-Free, 6/10-lead ceramic 5mm x 7mm x 1.55mm  
Number of Default Frequencies  
S: 1: Single  
D: 2: Dual  
Q: 4: Quad  
Default-Frequency and VCXO Pull Range  
See document FemtoClock NG Ceramic-Package XO and VCXO  
Ordering Product Information.  
dddd  
fXTAL (MHz) PLL Feedback  
Use for  
VCXO, XO  
XO  
Part Number  
0000 to 0999  
1000 to 1999  
2000 to 2999  
114.285  
Fractional  
Integer  
OEfct. at  
Function #pins  
pin  
100.000  
Fractional  
XO  
001  
003  
V01  
V03  
V75  
V76  
V85  
085  
270  
271  
272  
273  
XO  
XO  
10  
10  
10  
10  
6
OE@2  
OE@1  
OE@2  
OE@1  
OE@2  
nOE@2  
—
Last digit = L: configuration pre-programmed and not changeable  
VCXO  
VCXO  
VCXO  
VCXO  
VCXO  
XO  
Die Revision  
C
6
6
Option Code (Supply Voltage and Frequency-Stability)  
6
OE@1  
OE@1  
OE@2  
nOE@2  
nOE@1  
A: VCC = 3.3V 5%, 100ppm  
B: VCC = 2.5V 5%, 100ppm  
XO  
6
XO  
6
E: VCC = 3.3V 5%,  
F: VCC = 2.5V 5%,  
K: VCC = 3.3V 5%,  
L: VCC = 2.5V 5%,  
50ppm  
50ppm  
20ppm  
20ppm  
XO  
6
XO  
6
IDT8N4S271CCD REVISION A NOVEMBER 29, 2012  
15  
©2012 Integrated Device Technology, Inc.  
IDT8N4S271 Data Sheet  
LVDS FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR  
Table 9. Device Marking  
Industrial Temperature Range (TA = -40°C to 85°C)  
Commercial Temperature Range (TA = 0°C to 70°C)  
IDT8N4S271yC-  
ddddCDI  
IDT8N4S271yC-  
ddddCD  
Marking  
y = Option Code, dddd=Default-Frequency and VCXO Pull Range  
IDT8N4S271CCD REVISION A NOVEMBER 29, 2012  
16  
©2012 Integrated Device Technology, Inc.  
IDT8N4S271 Data Sheet  
LVDS FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR  
Revision History Sheet  
Rev  
Table  
Page  
Description of Change  
Date  
15  
16  
Ordering Information Table - corrected Die Revision from “G” to “C”.  
Marking Table - corrected marking.  
A
11/29/2012  
T9  
IDT8N4S271CCD REVISION A NOVEMBER 29, 2012  
17  
©2012 Integrated Device Technology, Inc.  
IDT8N4S271Data Sheet  
LVDS FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR  
We’ve Got Your Timing Solution  
6024 Silver Creek Valley Road Sales  
Technical Support  
800-345-7015 (inside USA)  
netcom@idt.com  
San Jose, California 95138  
+408-284-8200 (outside USA) +480-763-2056  
Fax: 408-284-2775  
www.IDT.com/go/contactIDT  
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,  
including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not  
guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the  
suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any  
license under intellectual property rights of IDT or any third parties.  
IDT’s products are not intended for use in applications involving extreme invironmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to signifi-  
cantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.  
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third  
party owners.  
Copyright 2012. All rights reserved.  
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