ICS8OSK270
27 MHZ FIXED AND SPREAD CLOCK GENERATOR
SSCG
External Components
Decoupling Capacitor
PCB Layout Recommendations
As with any high-performance mixed-signal IC, the
ICS8OSK270 must be isolated from system power
supply noise to perform optimally.
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
A decoupling capacitor of 0.01µF must be connected
between each VDD and the PCB ground plane.
1) The 0.01µF decoupling capacitors should be
mounted on the component side of the board as close
to the VDD pin as possible. No vias should be used
between the decoupling capacitors and VDD pins. The
PCB trace to VDD pins should be kept as short as
possible, as should the PCB trace to the ground via.
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50Ω trace (a
commonly used trace impedance), place a 33Ωresistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20Ω.
2) The external crystal should be mounted just next to
the device with short traces. The X1 and X2 traces
should not be routed next to each other with minimum
spaces, instead they should be separated and away
from other traces.
Crystal Load Capacitors
3) To minimize EMI, the 33Ωseries termination resistor
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to
ground. These capacitors are used to adjust the stray
capacitance of the board to match the nominally
required crystal load capacitance. Because load
capacitance can only be increased in this trimming
process, it is important to keep stray capacitance to a
minimum by using very short PCB traces (and no vias)
between the crystal and device. Crystal capacitors must
be connected from each of the pins X1 and X2 to
ground.
(if needed) should be placed close to the clock output.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers. Other signal traces should be routed away
from the ICS8OSK270. This includes signal traces just
underneath the device, or on layers adjacent to the
ground plane layer used by the device.
The value (in pF) of these crystal caps should equal (C
L
-6 pF)*2. In this equation, C = crystal load capacitance
L
in pF. Example: For a crystal with a 16 pF load
capacitance, each crystal capacitor would be 20 pF
[(16-6) x 2 = 20].
IDT™ / ICS™ 27 MHZ FIXED AND SPREAD CLOCK GENERATOR
3
ICS8OSK270 REV C 051006
