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CYM26KAH24AV33-12BGI

型号：

CYM26KAH24AV33-12BGI

品牌：

CYPRESS[ CYPRESS ]

页数：

8 页

PDF大小：

160 K

下载PDF手册
PRELIMINARY  
CYM26KAH24AV33  
256K x 24 Static RAM Module  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. Data from I/O pins  
(I/O0 through I/O23), is written into the location specified on the  
address pins (A0 through A17).  
Features  
• High-density 6-Megabit SRAM Module  
• High-speed CMOS SRAMs  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing the  
Write Enable (WE) HIGH. Then data from the memory location  
specified by the address pins will appear on I/O0 to I/O23. See  
the truth table at the back of this data sheet for a complete  
description of Read and Write modes.  
— tAA = 10 ns  
• Single 3.3V power supply  
• Low active power(648 W at 10 ns)  
• TTL-compatible Inputs and Outputs  
• Available in standard 119-ball BGA  
The input/output pins (I/O0 through I/O23) are placed in a  
high-impedance state when the device is deselected  
(CEHIGH), and the outputs are disabled (OE HIGH), or during  
a Write operation (CE LOW, and WE LOW).  
Functional Description  
The CYM26KAH24AV33 is  
a
3.3V high-performance  
6-Megabit static RAM organized as a 256K words by 24 bits.  
This module is constructed from two SRAM dies mounted on  
a multilayer laminate substrate combined to form a 24-bit  
SRAM.  
The CYM26KAH24AV33 is available in a standard 119 BGA.  
Functional Block Diagram  
A[17:0]  
I/O0-11  
I/O0-11  
CE0/  
WE0/  
OE0/  
A[17:0]  
A[17:0]  
I/O12-23  
I/O0-23  
I/O12-23  
CE/  
WE/  
OE/  
CE1/  
WE1/  
OE1/  
Selection Guide  
-10  
10  
-12  
12  
Unit  
ns  
Maximum Access Time  
Maximum Operating Current  
Commercial  
Industrial  
180  
200  
20  
170  
190  
20  
mA  
mA  
mA  
Maximum Standby Current  
Commercial  
Industrial  
Cypress Semiconductor Corporation  
Document #: 38-05324 Rev. **  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Revised January 17, 2003  
CYM26KAH24AV33  
PRELIMINARY  
Pin Configurations  
119 BGA  
Top View  
1
2
3
A
4
5
A
6
7
A
NC  
A
A
A
NC  
B
C
D
E
F
NC  
A
A
CE  
A
A
A
NC  
I/O12  
I/O13  
I/O14  
I/O15  
I/O16  
I/O17  
VCC  
NC  
VCC  
NC  
VCC  
NC  
VCC  
VSS  
VCC  
NC  
VCC  
NC  
VCC  
NC  
A
NC[1]  
VSS  
VCC  
VSS  
VCC  
VSS  
VCC  
VSS  
VCC  
VSS  
VCC  
VSS  
NC  
A
NC[1]  
VSS  
VCC  
VSS  
VCC  
VSS  
VCC  
VSS  
VCC  
VSS  
VCC  
VSS  
NC  
A
NC  
VCC  
NC  
VCC  
NC  
VCC  
VSS  
VCC  
NC  
VCC  
NC  
VCC  
NC  
A
I/011  
I/O10  
I/O9  
I/O8  
I/O7  
I/O6  
VDD  
I/O5  
I/O4  
I/O3  
I/O2  
I/O1  
I/O0  
NC  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
NC  
WE  
OE  
G
H
J
K
L
I/O18  
I/O19  
I/O20  
I/O21  
I/O22  
I/O23  
NC  
M
N
P
R
T
U
NC  
A
A
A
A
NC  
Note:  
1. Bumps 3C and 5C are actually NC’s but they should be wired 3C to VCC and 5C to Vss to assure compatibility with future versions.  
Document #: 38-05324 Rev. **  
Page 2 of 8  
CYM26KAH24AV33  
PRELIMINARY  
Current into Outputs (LOW)......................................... 20 mA  
Maximum Ratings  
Static Discharge Voltage...........................................> 2001V  
(per MIL-STD-883, Method 3015)  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
Latch-up Current.....................................................> 200 mA  
Storage Temperature ................................ –65°C to +150°C  
Ambient Temperature with Power Applied..–55°C to +125°C  
Supply Voltage on VCC to Relative GND[2] ...... –0.5V to 4.6V  
Operating Range  
Range  
Commercial  
Industrial  
Ambient Temperature  
0°C to +70°C  
VCC  
DC Voltage Applied to Outputs  
3.3V ±5%  
3.3V ±5%  
in High-Z State[2] ....................................–0.5V to VCC + 0.5V  
–40°C to +85°C  
DC Input Voltage[2].................................–0.5V to VCC + 0.5V  
Electrical Characteristics Over the Operating Range  
-10  
-12  
Parameter  
VOH  
Description  
Output HIGH Voltage  
Output LOW Voltage  
Input HIGH Voltage  
Test Conditions  
Min.  
Max.  
Min.  
Max.  
Unit  
VCC = Min., IOH = –4.0 mA  
2.4  
2.4  
V
V
V
VOL  
VCC = Min., IOL = 8.0 mA  
0.4  
0.4  
VIH  
2.0  
VCC  
0.3  
+
2.0  
VCC  
0.3  
+
VIL  
IIX  
Input LOW Voltage[2]  
Input Load Current  
–0.3  
–2  
0.8  
+2  
+2  
-0.3  
-2  
0.8  
+2  
+2  
V
GND < VI < VCC  
µA  
µA  
IOZ  
Output Leakage Current GND < VI < VCC  
,
–2  
-2  
Output Disabled  
ICC  
VCC Operating Supply VCC = Max.  
Commercial  
Industrial  
180  
200  
80  
170  
190  
80  
mA  
mA  
mA  
Current  
f = fMAX = 1/tRC  
ISB1  
Automatic CE  
Power-down Current  
—TTL Inputs  
Max. VCC, CE > VIH  
VIN > VIH or  
VIN < VIL, f = fMAX  
ISB2  
Automatic CE  
Power-down Current  
—CMOS Inputs  
Max. VCC  
,
Commercial/  
Industrial  
20  
20  
mA  
CE > VCC – 0.3V,  
VIN > VCC – 0.3V,  
or VIN < 0.3V, f = 0  
Capacitance[2]  
Parameter  
Description  
Test Conditions  
Max.  
Unit  
CIN  
Input Capacitance  
Output Capacitance  
TA = 25°C, f = 1 MHz,  
VCC = 3.3V  
10  
8
pF  
pF  
COUT  
AC Test Loads and Waveforms  
R1 317Ω  
ALL INPUT PULSES  
90%  
UTPUT  
3.3V  
OUTPUT  
3.0V  
GND  
90%  
Z = 50Ω  
0
R = 50Ω  
10%  
10%  
L
R2  
351Ω  
5 pF  
≤ 3 ns  
≤ 3 ns  
= 1.5V  
VTH  
INCLUDING  
JIG AND  
SCOPE  
(a)  
(b)  
Note:  
2. VIL (min.) = –2.0V for pulse durations of less than 20 ns.  
Document #: 38-05324 Rev. **  
Page 3 of 8  
CYM26KAH24AV33  
PRELIMINARY  
AC Switching Characteristics[3] Over the Operating Range  
-10  
-12  
Parameter  
Read Cycle  
Description  
Min.  
Max.  
Min.  
Max.  
Unit  
tRC  
Read Cycle Time  
10  
3
12  
3
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tAA  
Address to Data Valid  
Data Hold from Address Change  
CE active to Data Valid  
OE LOW to Data Valid  
OE LOW to Low Z  
OE HIGH to High Z[4, 5]  
CE active to Low Z[5]  
CE inactive to High Z[4, 5]  
CE active to Power-Up  
CE inactive to Power-Down  
10  
12  
tOHA  
tACE  
10  
5
12  
6
tDOE  
tLZOE  
0
3
0
0
3
0
tHZOE  
tLZCE  
tHZCE  
tPU  
5
5
6
6
tPD  
10  
12  
Write Cycle[6, 7]  
tWC  
tSCE  
tAW  
Write Cycle Time  
10  
7
12  
8
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
CE active to Write End  
Address Set-Up to Write End  
Address Hold from Write End  
Address Set-Up to Write Start  
WE Pulse Width  
7
8
tHA  
0
0
tSA  
0
0
tPWE  
tSD  
7
8
Data Set-Up to Write End  
Data Hold from Write End  
WE HIGH to Low Z[5]  
5
6
tHD  
0
0
tLZWE  
tHZWE  
3
3
WE LOW to High Z[4, 5]  
4
5
Switching Waveforms  
Read Cycle No. 1[8, 9]  
t
RC  
ADDRESS  
t
AA  
t
OHA  
DATA OUT  
PREVIOUS DATA VALID  
DATA VALID  
Notes:  
3. Tested initially and after any design or process changes that may affect these parameters.  
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified  
OL/IOH  
I
.
5. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.  
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.  
7. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these  
signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.  
8. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD  
9. Device is continuously selected. OE, CE = VIL.  
.
Document #: 38-05324 Rev. **  
Page 4 of 8  
CYM26KAH24AV33  
PRELIMINARY  
Switching Waveforms (continued)  
Read Cycle No. 2 (OE Controlled)[10, 11]  
ADDRESS  
CE  
t
RC  
t
ACE  
OE  
t
HZOE  
t
DOE  
t
HZCE  
t
LZOE  
HIGH  
IMPEDANCE  
HIGH IMPEDANCE  
DATA OUT  
DATA VALID  
t
LZCE  
t
PD  
I
t
PU  
CC  
V
CC  
50%  
50%  
SUPPLY  
CURRENT  
I
SB  
Write Cycle No. 1 (CE Controlled)[12, 13]  
t
WC  
ADDRESS  
CE  
t
SCE  
t
SA  
t
SCE  
t
t
HA  
AW  
t
PWE  
WE  
t
t
HD  
SD  
DATA I/O  
DATA VALID  
Notes:  
10. WE is HIGH for read cycle.  
11. Address valid prior to or coincident with CE transition LOW.  
12. Data I/O is high impedance if OE = VIH  
.
13. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.  
Document #: 38-05324 Rev. **  
Page 5 of 8  
CYM26KAH24AV33  
PRELIMINARY  
Switching Waveforms (continued)  
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)  
t
WC  
ADDRESS  
t
SCE  
CE  
t
t
HA  
AW  
t
SA  
t
PWE  
WE  
OE  
t
t
SD  
HD  
DATA VALID  
DATA I/O  
IN  
Note 14  
t
HZOE  
Write Cycle No. 3 (WE Controlled, OE LOW)  
t
WC  
ADDRESS  
CE  
t
SCE  
t
t
HA  
AW  
t
SA  
t
PWE  
WE  
t
t
HD  
SD  
Note 14  
DATA I/O  
DATA VALID  
t
t
LZWE  
HZWE  
Ordering Information  
Operating  
Range  
Speed (ns)  
Ordering Code  
Package Name  
BG119  
Package Type  
119-Ball BGA  
119-Ball BGA  
119-Ball BGA  
119-Ball BGA  
10  
10  
12  
CYM26KAH24AV33-10BGC  
CYM26KAH24AV33-10BGI  
CYM26KAH24AV33-12BGC  
CYM26KAH24AV33-12BGI  
Commercial  
Industrial  
BG119  
BG119  
Commercial  
Industrial  
12  
BG119  
Note:  
14. During this period the I/Os are in the output state and input signals should not be applied.  
Document #: 38-05324 Rev. **  
Page 6 of 8  
PRELIMINARY  
CYM26KAH24AV33  
Package Diagram  
119-lead PBGA (14 x 22 x 2.4 mm) BG119  
51-85115-*B  
All product and company names mentioned in this document are the trademarks of their respective holders.  
Document #: 38-05324 Rev. **  
Page 7 of 8  
© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize  
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.  
CYM26KAH24AV33  
PRELIMINARY  
Document History Page  
Document Title: CYM26KAH24AV33 256K x 24 Static RAM Module  
Document Number: 38-05324  
Issue  
Date  
Orig. of  
Change  
REV.  
ECN NO.  
Description of Change  
**  
123014  
01/22/03  
CS  
New Data Sheet  
Document #: 38-05324 Rev. **  
Page 8 of 8  
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