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CYM1821PZ-35C

型号：

CYM1821PZ-35C

品牌：

CYPRESS[ CYPRESS ]

页数：

7 页

PDF大小：

137 K

下载PDF手册
1CYM1821  
fax id: 2010  
CYM1821  
16K x 32 Static RAM Module  
constructed from eight 16K x 4 SRAM SOJ packages mount-  
ed on an epoxy laminate board with pins. Four chip selects  
Features  
• High-density 512-Kbit SRAM module  
(CS , CS , CS , and CS ) are used to independently enable  
1 2 3 4  
the four bytes. Reading or writing can be executed on individ-  
ual bytes or any combination of multiple bytes through proper  
use of selects.  
• 32-bit standard footprint supports densities from 16K  
x 32 through 1M x 32  
• High-speed CMOS SRAMs  
— Access time of 12 ns  
• Low active power  
Writing to each byte is accomplished when the appropriate  
chip selects (CS ) and write enable (WE) inputs are both  
N
LOW. Data on the input/output pins (I/O ) is written into the  
X
— 4W (max.)  
memory location specified on the address pins (A through  
0
A
).  
• SMD technology  
13  
• TTL-compatible inputs and outputs  
• Low profile  
Reading the device is accomplished by taking the chip selects  
(CS ) LOW, while write enable (WE) remains HIGH. Under  
N
these conditions the contents of the memory location specified  
on the address pins will appear on the data input/output pins  
— Max. height of .50 in.  
• Small PCB footprint  
— 1.0 sq. in.  
(I/O ).The data input/output pins stay in the high-impedance  
X
state when write enable (WE) is LOW, or the appropriate chip  
selects are HIGH.  
• JEDEC-compatible pinout  
Two pins (PD and PD ) are used to identify module memory  
density in applications where alternate versions of the JEDEC  
standard modules can be interchanged.  
0
1
Functional Description  
The CYM1821 is a high-performance 512-Kbit static RAM  
module organized as 16K words by 32 bits. This module is  
Logic Block Diagram  
Pin Configuration  
ZIP  
Top View  
PD - GND  
0
GND  
PD1  
I/O8  
1
3
PD  
0
0
I/O  
1
PD - OPEN  
2
1
I/O  
A - A  
4
5
0
13  
14  
6
7
I/O9  
OE  
I/O  
8
9
2
I/O10  
I/O11  
I/O  
3
WE  
10  
11  
12  
13  
15  
16  
17  
19  
20  
21  
V
A
CC  
7
A
0
1
14  
A
16K x 4  
SRAM  
16K x 4  
I/O – I/O  
0
I/O – I/O  
A
8
3
4
7
A
2
SRAM  
4
4
4
4
4
4
4
4
18  
A
9
I/O  
I/O  
I/O  
I/O  
12  
13  
14  
15  
I/O  
I/O  
I/O  
I/O  
4
5
6
7
CS  
1
22  
23  
24  
25  
27  
28  
29  
26  
GND  
NC  
CS  
2
16K x 4  
SRAM  
16K x 4  
SRAM  
I/O – I/O  
8
I/O – I/O  
WE  
NC  
CS  
1
11  
12  
15  
23  
31  
30  
31  
32  
33  
CS  
CS  
CS  
2
3
4
CS  
4
CS  
3
34  
35  
NC  
OE  
I/O  
NC  
36  
16K x 4  
SRAM  
16K x 4  
SRAM  
37  
I/O – I/O  
16  
I/O – I/O  
20  
19  
GND  
38  
39  
24  
I/O  
I/O  
I/O  
I/O  
A
A
A
16  
17  
18  
19  
10  
11  
12  
13  
20  
21  
22  
23  
40  
41  
I/O  
I/O  
I/O  
25  
26  
27  
42  
43  
44  
45  
46  
A
47  
3
48  
49  
16K x 4  
SRAM  
16K x 4  
SRAM  
I/O – I/O  
28  
I/O – I/O  
24  
A
4
A
5
27  
50  
51  
52  
53  
V
CC  
A
54  
55  
A
6
I/O  
I/O  
I/O  
I/O  
56  
57  
I/O  
I/O  
I/O  
I/O  
28  
29  
30  
31  
1821–1  
58  
59  
60  
61  
62  
63  
GND  
64  
1821–2  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
November 1988 – Revised January 1995  
CYM1821  
Selection Guide  
1821-12  
12  
1821-15  
15  
1821-20  
20  
1821-25  
25  
1821-35  
1821-45  
45  
Maximum Access Time (ns)  
35  
Maximum Operating Current (mA)  
Maximum Standby Current (mA)  
960  
960  
720  
720  
720  
160  
720  
450  
450  
160  
160  
160  
DC Input Voltage ............................................–0.5V to +7.0V  
Output Current into Outputs (LOW)............................. 20 mA  
Maximum Ratings  
(Above which the useful life may be impaired.)  
Storage Temperature ................................. –65°C to +150°C  
Operating Range  
Ambient Temperature with  
Power Applied............................................... –10°C to +85°C  
Ambient  
Temperature  
Range  
V
CC  
Supply Voltage to Ground Potential............... –0.5V to +7.0V  
Commercial  
0°C to +70°C  
5V ± 10%  
DC Voltage Applied to Outputs  
in High Z State ............................................... –0.5V to +7.0V  
Electrical Characteristics Over the Operating Range  
1821-20  
1821-25  
1821-35  
1821-45  
1821-12  
1821-15  
Parameter  
Description  
Output HIGH Voltage  
Output LOW Voltage  
Input HIGH Voltage  
Test Conditions  
= Min., I = –4.0 mA  
Min.  
Max.  
Min.  
Max. Unit  
V
V
V
V
V
V
2.4  
2.4  
V
OH  
OL  
IH  
CC  
CC  
OH  
= Min., I = 8.0 mA  
0.4  
0.4  
V
V
OL  
2.2  
–0.5  
–20  
–20  
V
2.2  
–0.5  
–20  
–20  
V
CC  
CC  
Input LOW Voltage  
0.8  
+20  
+20  
–350  
960  
0.8  
V
IL  
I
I
I
I
Input Load Current  
GND < V < V  
CC  
+20  
+20  
µA  
µA  
mA  
mA  
IX  
I
Output Leakage Current  
Output Short Circuit Current  
GND < V < V , Output Disabled  
OZ  
OS  
CC  
O
CC  
[1]  
V
= Max., V  
= GND  
–350  
720  
CC  
OUT  
V
Operating Supply Current  
V
= Max., I  
= 0 mA,  
CC  
CC  
OUT  
CS < V  
IL  
I
I
Automatic CS  
Power-Down Current  
Max. V , CS > V ,  
Min. Duty Cycle = 100%  
450  
160  
160  
160  
mA  
mA  
SB1  
SB2  
CC  
IH  
[2]  
[2]  
Automatic CS  
Power-Down Current  
Max. V , CS > V – 0.3V,  
CC  
N
CC  
V
> V – 0.3V or V < 0.3V  
IN CC IN  
Capacitance[3]  
Parameter  
Description  
Test Conditions  
T = 25°C, f = 1 MHz,  
Max.  
Unit  
C
C
C
Input Capacitance (ADDR, OE, WE)  
Input Capacitance (CS)  
70  
35  
20  
pF  
pF  
pF  
INA  
INB  
OUT  
A
V
= 5.0V  
CC  
Output Capacitance  
Notes:  
1. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.  
2. A pull-up resistor to VCC on the CS input is required to keep the device deselected during VCC power-up, otherwise ISB will exceed values given.  
3. Tested on a sample basis.  
2
CYM1821  
AC Test Loads and Waveforms  
481Ω  
481Ω  
ALL INPUT PULSES  
90%  
10%  
5V  
5V  
OUTPUT  
3.0V  
GND  
90%  
10%  
OUTPUT  
255Ω  
255Ω  
30 pF  
5 pF  
< 5 ns  
< 5 ns  
INCLUDING  
JIG AND  
SCOPE  
INCLUDING  
JIG AND  
SCOPE  
1821–3  
1821–4  
(a)  
(b)  
Equivalent to:  
OUTPUT  
THÉ VENIN EQUIVALENT  
167Ω  
1.73V  
]
[4]  
Switching Characteristics Over the Operating Range  
1821-12  
1821-15  
1821-20  
Parameter  
Description  
Min.  
12  
2
Max.  
Min.  
15  
2
Max.  
Min.  
Max.  
Unit  
READ CYCLE  
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time  
20  
2
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
RC  
Address to Data Valid  
Data Hold from Address Change  
CS LOW to Data Valid  
OE LOW to Data Valid  
OE LOW to Low Z  
12  
15  
20  
AA  
OHA  
ACS  
DOE  
LZOE  
HZOE  
LZCS  
HZCS  
PU  
12  
10  
15  
10  
20  
10  
2
3
0
2
3
0
3
5
0
OE HIGH to High Z  
8
8
8
8
8
8
[5]  
CS LOW to Low Z  
[5, 6]  
CS HIGH to High Z  
CS LOW to Power-Up  
CS HIGH to Power-Down  
12  
15  
20  
PD  
[7]  
WRITE CYCLE  
t
t
t
t
t
t
t
t
t
t
Write Cycle Time  
12  
10  
10  
2
15  
12  
12  
2
20  
15  
15  
2
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
WC  
CS LOW to Write End  
Address Set-Up to Write End  
Address Hold from Write End  
Address Set-Up to Write Start  
WE Pulse Width  
SCS  
AW  
HA  
0
0
2
SA  
10  
10  
2
12  
10  
2
15  
10  
2
PWE  
SD  
Data Set-Up to Write End  
Data Hold from Write End  
WE HIGH to Low Z  
HD  
3
3
3
LZWE  
[6]  
WE LOW to High Z  
0
7
0
7
0
7
HZWE  
Notes:  
4. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified  
OL/IOH and 30-pF load capacitance.  
I
5. At any given temperature and voltage condition, tHZCS is less than tLZCS for anygiven device. These parametersare guaranteed bydesign and not 100% tested.  
6. tHZCS and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured ±500 mV from steady-state voltage.  
7. The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can  
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.  
3
CYM1821  
[4]  
Switching Characteristics Over the Operating Range (continued)  
1821-25  
1821-35  
1821-45  
Parameter  
Description  
Min.  
25  
3
Max.  
Min.  
Max.  
Min.  
Max.  
Unit  
READ CYCLE  
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time  
35  
3
45  
3
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
RC  
Address to Data Valid  
Data Hold from Address Change  
CS LOW to Data Valid  
OE LOW to Data Valid  
OE LOW to Low Z  
25  
35  
45  
AA  
OHA  
ACS  
DOE  
LZOE  
HZOE  
LZCS  
HZCS  
PU  
25  
15  
35  
25  
45  
30  
3
5
0
3
10  
0
3
10  
0
OE HIGH to High Z  
15  
10  
25  
20  
15  
35  
20  
20  
45  
[5]  
CS LOW to Low Z  
[5, 6]  
CS HIGH to High Z  
CS LOW to Power-Up  
CS HIGH to Power-Down  
PD  
[7]  
WRITE CYCLE  
t
t
t
t
t
t
t
t
t
t
Write Cycle Time  
25  
20  
20  
2
35  
25  
25  
2
45  
35  
35  
2
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
WC  
CS LOW to Write End  
Address Set-Up to Write End  
Address Hold from Write End  
Address Set-Up to Write Start  
WE Pulse Width  
SCS  
AW  
HA  
2
2
2
SA  
20  
13  
2
25  
15  
2
30  
20  
2
PWE  
SD  
Data Set-Up to Write End  
Data Hold from Write End  
WE HIGH to Low Z  
HD  
3
5
5
LZWE  
HZWE  
[6]  
WE LOW to High Z  
0
7
0
10  
0
15  
4
CYM1821  
Switching Waveforms  
[8,9]  
Read Cycle No. 1  
t
RC  
ADDRESS  
t
AA  
t
OHA  
DATA OUT  
PREVIOUS DATA VALID  
DATA VALID  
1821–5  
[8,10]  
Read Cycle No. 2 (WE Controlled)  
t
CS  
RC  
t
ACS  
OE  
t
HZOE  
t
DOE  
t
HZCS  
t
LZOE  
HIGH  
IMPEDANCE  
HIGH IMPEDANCE  
DATA VALID  
DATA OUT  
t
LZCS  
t
PD  
t
PU  
ICC  
V
CC  
50%  
50%  
SUPPLY  
CURRENT  
ISB  
1821–6  
[7]  
Write Cycle No. 1 (WE Controlled)  
t
WC  
ADDRESS  
t
SCS  
CS  
t
t
HA  
AW  
t
t
SA  
PWE  
WE  
t
t
HD  
SD  
DATA IN  
DATA VALID  
t
t
LZWE  
HZWE  
HIGH IMPEDANCE  
DATA OUT  
DATA UNDEFINED  
1821–7  
Notes:  
8. WE is HIGH for read cycle.  
9. Device is continuously selected, CS = VIL and OE= VIL  
.
10. Address valid prior to or coincident with CS transition LOW.  
5
CYM1821  
Switching Waveforms (continued)  
[7,11]  
Write Cycle No. 2 (CS Controlled)  
t
WC  
ADDRESS  
t
SA  
t
SCS  
CS  
t
t
HA  
AW  
t
PWE  
WE  
t
t
HD  
SD  
DATA IN  
DATA VALID  
t
HZWE  
HIGH IMPEDANCE  
DATA OUT  
DATA UNDEFINED  
1821–8  
Note:  
11. If CS goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.  
Truth Table  
CS  
H
L
WE OE Inputs/Outputs  
Mode  
Deselect/Power-Down  
Read  
N
X
H
L
X
L
High Z  
Data Out  
Data In  
High Z  
L
X
H
Write  
L
H
Deselect  
Ordering Information  
Package  
Name  
Package  
Type  
Operating  
Range  
Speed  
Ordering Code  
12  
CYM1821PM-12C  
CYM1821PZ-12C  
CYM1821PM-15C  
CYM1821PZ-15C  
CYM1821PM-20C  
CYM1821PZ-20C  
CYM1821PM-25C  
CYM1821PZ-25C  
CYM1821PM-35C  
CYM1821PZ-35C  
CYM1821PM-45C  
CYM1821PZ-45C  
PM01  
PZ01  
PM01  
PZ01  
PM01  
PZ01  
PM01  
PZ01  
PM01  
PZ01  
PM01  
PZ01  
64-Pin Plastic SIMM Module  
64-Pin Plastic ZIP Module  
64-Pin Plastic SIMM Module  
64-Pin Plastic ZIP Module  
64-Pin Plastic SIMM Module  
64-Pin Plastic ZIP Module  
64-Pin Plastic SIMM Module  
64-Pin Plastic ZIP Module  
64-Pin Plastic SIMM Module  
64-Pin Plastic ZIP Module  
64-Pin Plastic SIMM Module  
64-Pin Plastic ZIP Module  
Commercial  
Commercial  
Commercial  
Commercial  
Commercial  
Commercial  
15  
20  
25  
35  
45  
Document #: 38-M-00015-E  
6
CYM1821  
a
Package Diagrams  
64-Pin Plastic SIMM Module PM01  
0.125 DIA.  
+.001 2 PLCS  
3.845  
3.855  
0.330  
MAX  
3.580  
3.588  
0.525  
0.400  
0.250  
MAX  
0.145 REF  
0.050  
TYP  
0.62 R + .001  
0.250  
PIN 1  
0.080  
PIN 64  
3.35 (64 PINS)  
0.250  
64-Pin Plastic ZIP Module PZ01  
Bottom View  
0.330  
MAX  
3.640  
3.660  
0.050  
0.050  
0.500  
MAX  
0.120  
0.150  
0.008  
0.014  
0.250  
TYP  
0.100  
TYP  
0.050  
TYP  
0.135  
0.165  
0.015  
0.025  
0.100  
TYP  
Pin 1  
DIMENSIONS IN  
INCHES  
MIN.  
MAX.  
© Cypress Semiconductor Corporation, 1995. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of anycircuitry other than circuitry embodied in a CypressSemiconductor product. Nor does it conveyor imply any license under patent or other rights. CypressSemiconductor does not authorize  
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.  
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