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CYM1730PZ-30C

型号:

CYM1730PZ-30C

品牌:

CYPRESS[ CYPRESS ]

页数:

6 页

PDF大小:

105 K

1CYM1730  
CYM1730  
64K x 24 Static RAM Module  
using six 32K x 8 static RAMs in SOJ packages mounted onto  
an epoxy laminate board with pins.  
Features  
• High-density 1.5M SRAM module  
• High-speed CMOS SRAMs  
— Access time of 25 ns  
Writing to the device is accomplished when the chip select  
(CS) and write enable (WE) inputs are both LOW. Data on the  
input/output pins (I/O through I/O ) of the device is written  
0
23  
into the memory location specified on the address pins (A  
0
• 56-pin, 0.5-inch-high ZIP package  
• Low active power  
through A ).  
15  
Reading the device is accomplished by taking the chip select  
(CS) and output enable (OE) LOW while write enable (WE)  
remains HIGH. Under these conditions, the contents of the  
memory location specified on the address pins will appear on  
the input/output pins.  
— 2.8W (max. for t = 25 ns)  
AA  
• SMD technology  
• TTL-compatible inputs and outputs  
• Commercial temperature range  
• Small PCB footprint  
The input/output pins remain in a high-impedance state unless  
the module is selected, outputs are enabled, and write enable  
is HIGH.  
— 1.05 sq. in.  
Functional Description  
The CYM1730 is a high-performance 1.5M static RAM module  
organized as 64K words by 24 bits. This module is constructed  
Logic Block Diagram  
Pin Configuration  
A – A  
0
14  
15  
ZIP  
Top View  
OE  
WE  
V
CC  
1
3
V
CC  
2
I/O  
I/O  
I/O  
I/O  
0
2
4
6
I/O  
I/O  
I/O  
I/O  
1
3
5
7
4
5
32K x 8  
SRAM  
32K x 8  
SRAM  
6
7
8
9
10  
12  
14  
16  
18  
20  
22  
24  
26  
28  
30  
32  
34  
36  
38  
40  
42  
44  
46  
48  
50  
52  
54  
56  
11  
13  
15  
17  
19  
21  
23  
25  
27  
29  
31  
GND  
GND  
A
0
A
1
3
5
A
2
A
A
4
6
A
15  
A
I/O – I/O  
16  
23  
A
1 OF 2  
DECODER  
8
A
7
CS  
NC  
I/O  
I/O  
I/O  
I/O  
GND  
WE  
NC  
GND  
I/O  
I/O  
I/O  
I/O  
NC  
OE  
A
A
A
A
CS  
8
32K x 8  
SRAM  
32K x 8  
SRAM  
9
10  
12  
14  
11  
13  
15  
33  
35  
37  
39  
41  
43  
45  
47  
49  
51  
53  
55  
A
8
9
I/O – I/O  
8
15  
A
10  
8
11  
13  
15  
A
12  
A
14  
GND  
I/O  
I/O  
18  
I/O  
I/O  
22  
V
CC  
32K x 8  
SRAM  
32K x 8  
SRAM  
GND  
16  
I/O  
I/O  
I/O  
17  
19  
21  
23  
20  
I/O  
V
CC  
I/O – I/O  
0
7
1730-2  
8
1730-1  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
July 1991 – Revised January 1995  
408-943-2600  
CYM1730  
Selection Guide  
1730–25  
25  
1730–30  
30  
1730–35  
35  
Maximum Access Time (ns)  
Maximum Operating Current (mA)  
Maximum Standby Current (mA)  
510  
510  
510  
180  
180  
180  
Maximum Ratings  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
DC Input Voltage ........................................... –0.5V to +7.0V  
Operating Range  
Storage Temperature ................................. –55°C to +125°C  
Ambient Temperature with  
Power Applied............................................... –10°C to +85°C  
Ambient  
Temperature  
Range  
V
CC  
Commercial  
0°C to +70°C  
5V ± 10%  
Supply Voltage to Ground Potential............... –0.5V to +7.0V  
DC Voltage Applied to Outputs  
in High Z State ............................................... –0.5V to +7.0V  
Electrical Characteristics Over the Operating Range  
Parameter  
Description  
Output HIGH Voltage  
Output LOW Voltage  
Input HIGH Voltage  
Input LOW Voltage  
Input Load Current  
Output Leakage Current  
Test Conditions  
Min.  
Max.  
Unit  
V
V
V
= Min., I = –4.0 mA  
OH  
2.4  
V
V
OH  
OL  
IH  
CC  
CC  
V
V
V
= Min., I = 8.0 mA  
0.4  
OL  
2.2  
–0.3  
–20  
–10  
V
+ 0.3  
V
CC  
0.8  
+20  
+10  
V
IL  
I
I
GND < V < V  
CC  
µA  
µA  
IX  
I
GND < V < V ,  
CC  
OZ  
O
Output Disabled  
I
I
V
Operating Supply Current  
V
= Max., I  
= 0 mA, CS < V  
IL  
510  
180  
mA  
mA  
CC  
CC  
CC  
OUT  
Automatic CS Power-Down  
Current  
Max. V , CS > V ,  
CC IH  
Min. Duty Cycle = 100%  
SB1  
[1]  
I
Automatic CS Power-Down  
Current  
Max. V , CS > V – 0.2V,  
180  
mA  
SB2  
CC  
CC  
[1]  
V
> V – 0.2V or V < 0.2V  
IN  
CC  
IN  
Capacitance[2]  
Parameter  
Description  
Input Capacitance  
Output Capacitance  
Test Conditions  
Max.  
50  
Unit  
pF  
C
C
T = 25°C, f = 1 MHz,  
A
IN  
V
= 5.0V  
CC  
20  
pF  
OUT  
Notes:  
1. A pull-up resistor to VCC on the CS input is required to keep the device deselected during VCC power-up, otherwise ISB will exceed values given.  
2. Tested on a sample basis.  
2
CYM1730  
AC Test Loads and Waveforms  
481  
481Ω  
ALL INPUT PULSES  
90%  
10%  
5V  
5V  
OUTPUT  
3.0V  
GND  
90%  
10%  
OUTPUT  
255Ω  
255Ω  
100 pF  
5 pF  
< 5 ns  
< 5 ns  
INCLUDING  
JIG AND  
SCOPE  
INCLUDING  
JIG AND  
SCOPE  
1730-5  
1730-3  
1730-4  
(a)  
(b)  
Equivalent to:  
OUTPUT  
THÉVENIN EQUIVALENT  
167Ω  
1.73V  
[3]  
Switching Characteristics Over the Operating Range  
1730–25  
1730–30  
1730–35  
Parameter  
Description  
Min.  
25  
5
Max.  
Min.  
Max.  
Min.  
Max.  
Unit  
READ CYCLE  
t
t
t
t
t
t
t
t
t
Read Cycle Time  
30  
5
35  
5
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
RC  
Address to Data Valid  
Output Hold from Address Change  
CS LOW to Data Valid  
OE LOW to Data Valid  
OE LOW to Low Z  
25  
30  
35  
AA  
OHA  
ACS  
DOE  
LZOE  
HZOE  
LZCS  
HZCS  
25  
12  
30  
15  
35  
20  
3
5
3
5
3
5
OE HIGH to High Z  
10  
10  
15  
15  
20  
15  
[4]  
CS LOW to Low Z  
[4, 5]  
CS HIGH to High Z  
[6]  
WRITE CYCLE  
t
t
t
t
t
t
t
t
t
t
Write Cycle Time  
25  
20  
22  
2
30  
25  
25  
2
35  
30  
30  
2
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
WC  
CS LOW to Write End  
Address Set-Up to Write End  
Address Hold from Write End  
Address Set-Up to Write Start  
WE Pulse Width  
SCS  
AW  
HA  
2
2
2
SA  
20  
13  
2
23  
15  
2
25  
20  
2
PWE  
SD  
Data Set-Up to Write End  
Data Hold from Write End  
WE HIGH to Low Z  
HD  
3
3
5
LZWE  
[5]  
WE LOW to High Z  
0
10  
0
10  
0
15  
HZWE  
Notes:  
3. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified  
OL/IOH and 30-pF load capacitance.  
4. At any given temperature and voltage condition, tHZCS is less than tLZCS for any given device.  
5. HZOE, tHZCS, and tLZCEare specified with CL = 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured ±500 mV from steady-state voltage.  
I
t
6. The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can  
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.  
3
CYM1730  
Switching Waveforms  
[7, 8]  
Read Cycle No. 1  
t
RC  
ADDRESS  
t
AA  
t
OHA  
DATA OUT  
PREVIOUS DATA VALID  
DATA VALID  
1730-6  
[7, 9]  
Read Cycle No. 2  
t
RC  
CS  
t
ACS  
OE  
t
HZOE  
t
DOE  
t
t
HZCS  
LZOE  
HIGH  
IMPEDANCE  
HIGH IMPEDANCE  
DATA VALID  
DATA OUT  
t
LZCS  
t
PD  
t
PU  
ICC  
V
CC  
50%  
50%  
SUPPLY  
CURRENT  
ISB  
1730-7  
[6, 10]  
Write Cycle No. 1 (WE Controlled)  
t
WC  
ADDRESS  
t
SCS  
CS  
t
t
HA  
AW  
t
SA  
t
PWE  
WE  
t
t
HD  
SD  
DATA IN  
DATA VALID  
t
t
LZWE  
HZWE  
HIGH IMPEDANCE  
DATA UNDEFINED  
DATAOUT  
1730-8  
Notes:  
7. WE is HIGH for read cycle.  
8. Device is continuously selected, CS = VIL and OE= VIL  
.
9. Address valid prior to or coincident with CS transition LOW.  
10. Data I/O will be high impedance if OE = VIH  
.
4
CYM1730  
Switching Waveforms (continued)  
[6, 10, 11]  
Write Cycle No. 2 (CS Controlled)  
t
WC  
ADDRESS  
t
SA  
t
SCS  
CS  
WE  
t
t
HA  
AW  
t
PWE  
t
t
HD  
SD  
DATA IN  
DATA VALID  
t
HZWE  
HIGH IMPEDANCE  
DATAOUT  
DATA UNDEFINED  
1730-9  
Note:  
11. If CS goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.  
Truth Table  
CS WE OE Input/Outputs  
Mode  
Deselect/Power-Down  
Read Word  
H
L
L
L
X
H
L
X
L
High Z  
Data Out  
Data In  
High Z  
X
H
Write Word  
H
Deselect  
Ordering Information  
Speed  
Package  
Operating  
Range  
(ns)  
Ordering Code  
CYM1730PZ–25C  
CYM1730PZ–30C  
CYM1730PZ–35C  
Name  
PZ07  
PZ07  
PZ07  
Package Type  
25  
56-Pin ZIP Module  
56-Pin ZIP Module  
56-Pin ZIP Module  
Commercial  
Commercial  
Commercial  
30  
35  
Document #: 38–M–00049–A  
5
CYM1730  
Package Diagram  
56-Pin ZIP Module PZ07  
2.990/3.010  
.350 MAX.  
.485/.495  
.125/.175  
.100 REF  
2.750 REF  
© Cypress Semiconductor Corporation, 1995. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of anycircuitry other than circuitry embodied in a CypressSemiconductor product. Nor does it conveyor imply any license under patent or other rights. CypressSemiconductor does not authorize  
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.  
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