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CYM1861AV33PM-25C

型号：

CYM1861AV33PM-25C

品牌：

CYPRESS[ CYPRESS ]

页数：

7 页

PDF大小：

109 K

下载PDF手册
CYM1861AV33  
2,048K x 32 3.3V Static RAM Module  
chip selects are used to independently enable the four bytes.  
Reading or writing can be executed on individual bytes or any  
combination of multiple bytes through proper use of selects.  
Features  
• High-density 3.3V 64-megabit SRAM module  
• 32-bit Standard Footprint supports densities from  
16K × 32 through 2M × 32  
• High-speed SRAMs  
— Access time of 20 ns  
• 72 pins  
The CYM1861AV33 is designed for use with standard 72-pin  
SIMM sockets. The pinout is downward compatible with the  
64-pin JEDEC SIMM module family (CYM1821, CYM1831,  
CYM1836, and CYM1841). Thus, a single motherboard  
design can be used to accommodate memory depth ranging  
from 16K words (CYM1821) to 2,048K words  
(CYM1861AV33). The CYM1861AV33 is offered in vertical  
SIMM configuration and is available with tin-lead edge  
contacts.  
• Available in SIMM format  
Functional Description  
The CYM1861AV33 is a high-performance 3.3V 64-megabit  
static RAM module organized as 2,048K words by 32 bits. This  
module is constructed from sixteen 1,024K × four SRAMs in  
SOJ packages mounted on an epoxy laminate substrate. Four  
Presence detect pins (PD0–PD3) are used to identify module  
memory density in applications where modules with alternate  
word depths can be interchanged.  
Logic Block Diagram  
Pin Configuration  
ZIP/SIMM  
Top View  
NC  
PD  
1
3
5
NC  
3
PD  
0
2
4
2
PD  
GND  
6
8
7
9
PD  
1
8
I/O  
0
I/O  
I/O  
1
10  
12  
14  
16  
18  
20  
22  
24  
26  
28  
30  
32  
11  
13  
15  
17  
19  
21  
23  
25  
27  
29  
31  
I/O  
I/O  
I/O  
9
10  
11  
I/O  
2
I/O  
3
V
CC  
7
8
A
0
A –A  
PD – OPEN  
0
19  
0
A
A
1
2
PD – GND  
A
1
A
PD – GND  
A
2
9
I/O  
I/O  
I/O  
I/O  
12  
13  
14  
15  
20  
Buffer  
I/O  
I/O  
I/O  
I/O  
PD – OPEN  
4
5
6
7
3
OE  
WE  
I/O – I/O  
I/O –I/O  
GND  
4
7
4
7
WE  
4
4
1M x 4  
SRAM  
1M x 4  
SRAM  
33  
35  
A
15  
A
14  
I/O – I/O  
I/O –I/O  
34  
36  
0
3
0
3
4
4
CS  
CS  
2
CS  
1
37  
39  
41  
43  
45  
47  
49  
51  
53  
55  
57  
59  
61  
63  
65  
67  
69  
71  
4
CS  
3
38  
40  
42  
44  
46  
48  
50  
52  
54  
56  
58  
60  
62  
64  
66  
68  
70  
72  
A
17  
A
16  
–
–
I/O  
I/O  
I/O  
I/O  
OE  
12  
15  
12  
15  
GND  
4
4
4
1M x 4  
SRAM  
1M x 4  
SRAM  
I/O  
I/O  
I/O  
I/O  
24  
25  
26  
27  
I/O – I/O  
I/O – I/O  
8 11  
I/O  
8
11  
16  
4
I/O  
17  
I/O  
18  
I/O  
19  
–CS  
CS  
A
1
3
4
A
10  
–
–
–
I/O  
20  
I/O  
I/O  
I/O  
23  
A
4
A
5
20  
23  
4
4
4
A
1M x 4  
SRAM  
1M x 4  
SRAM  
11  
MUX  
4:8  
I/O  
I/O  
I/O –I/O  
16  
19  
16  
19  
A
12  
A
4
V
CC  
A
20  
13  
A
6
I/O  
20  
I/O  
I/O  
I/O  
I/O  
28  
29  
30  
31  
I/O  
21  
I/O  
I/O –I/O  
I/O –I/O  
22  
28  
31  
28  
31  
4
4
1M x 4  
SRAM  
1M x 4  
SRAM  
I/O  
23  
–
–
I/O  
I/O  
I/O  
I/O  
24  
27  
24  
27  
GND  
4
4
A
18  
20  
A
19  
A
NC  
Selection Guide  
CY1861AV33-20  
CY1861AV33-25  
Unit  
ns  
Maximum Access Time  
20  
25  
Maximum Operating Current  
Maximum Standby Current  
2400  
1050  
2400  
1050  
mA  
mA  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
Document #: 38-05297 Rev. **  
Revised August 20, 2002  
CYM1861AV33  
DC Voltage Applied to Outputs  
in High-Z State................................................ –0.5V to +VCC  
Maximum Ratings  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
DC Input Voltage ............................................–0.5V to +4.6V  
Storage Temperature .................................–55°C to +125°C  
Operating Range  
Ambient Temperature with  
Power Applied...............................................–10°C to +85°C  
Range  
Ambient Temperature  
VCC  
Commercial  
0°C to +70°C  
3.3 V  
+ 10% –5%  
Supply Voltage to Ground Potential............... –0.5V to +4.6V  
Electrical Characteristics Over the Operating Range  
Parameter  
VOH  
VOL  
Description  
Output HIGH Voltage  
Test Conditions  
VCC = Min., IOH = –4.0 mA  
VCC = Min., IOL = 4.0 mA  
Min.  
Max.  
0.4  
Unit  
V
2.4  
Output LOW Voltage  
Input HIGH Voltage  
V
VIH  
2.2  
–0.3V  
–10  
VCC + 0.3  
0.8  
V
V
VIL  
Input LOW Voltage  
IIX  
Input Load Current  
GND < VI < VCC  
+10  
µA  
µA  
mA  
IOZ  
Output Leakage Current  
VCC Operating Supply Current  
GND < VO < VCC, Output Disabled  
–20  
+20  
ICC  
VCC = Max., IOUT = 0 mA,  
CSN < VIL  
2400  
ISB1  
ISB2  
Automatic CS Power-down Current[1] Max. VCC, CS > VIH,  
1050  
500  
mA  
mA  
Min. Duty Cycle = 100%  
Automatic CS Power-down Current[1] Max. VCC  
,
CS > VCC − 0.2V,  
VIN > VCC − 0.2V, or  
VIN < 0.2V  
Capacitance[2]  
Parameter  
CIN  
Description  
Input Capacitance  
Output Capacitance  
Test Conditions  
Max.  
Unit  
pF  
TA = 25°C, f = 1 MHz,  
VCC = 3.3V  
7
COUT  
14  
pF  
AC Test Loads and Waveforms  
R1 589 Ω  
R1 589 Ω  
ALL INPUT PULSES  
90%  
3.3V  
3.3V  
OUTPUT  
3.3V  
GND  
90%  
10%  
OUTPUT  
R2  
434 Ω  
R2  
434 Ω  
10%  
30 pF  
5 pF  
< 5 ns  
< 5 ns  
INCLUDING  
JIG AND  
SCOPE  
INCLUDING  
JIG AND  
SCOPE  
(a)  
(b)  
Equivalent to:  
THÉVENIN EQUIVALENT  
250 Ω  
1.40V  
OUTPUT  
Notes:  
1. A pull-up resistor to VCC on the CS input is required to keep the device deselected during VCC power-up, otherwise ISB will exceed values given.  
2. Tested on a sample basis.  
Document #: 38-05297 Rev. **  
Page 2 of 7  
CYM1861AV33  
Switching Characteristics Over the Operating Range[3]  
CY1861AV33-20  
CY1861AV33-25  
Parameter  
Description  
Min.  
Max.  
Min.  
25  
3
Max.  
Unit  
Read Cycle  
tRC  
Read Cycle Time  
20  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tAA  
Address to Data Valid  
Data Hold from Address Change  
CS LOW to Data Valid  
OE LOW to Data Valid  
OE LOW to Low-Z  
20  
25  
tOHA  
tACS  
3
20  
12  
25  
15  
tDOE  
tLZOE  
tHZOE  
tLZCS  
tHZCS  
tPD  
0
3
4
7
OE HIGH to High-Z  
CS LOW to Low-Z[4]  
CS HIGH to High-Z[4, 5]  
10  
12  
10  
20  
12  
25  
CS HIGH to Power-down  
Write Cycle[6]  
tWC  
Write Cycle Time  
20  
17  
17  
3
25  
20  
20  
3
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tSCS  
CS LOW to Write End  
Address Set-up to Write End  
Address Hold from Write End  
Address Set-up to Write Start  
WE Pulse Width  
tAW  
tHA  
tSA  
2
2
tPWE  
tSD  
15  
12  
2
20  
15  
2
Data Set-up to Write End  
Data Hold from Write End  
WE HIGH to Low-Z  
tHD  
tLZWE  
tHZWE  
3
3
WE LOW to High-Z[5]  
0
12  
0
12  
Switching Waveforms  
Read Cycle No. 1[7, 8]  
t
RC  
ADDRESS  
t
AA  
t
OHA  
DATA OUT  
PREVIOUS DATA VALID  
DATA VALID  
Notes:  
3. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified  
IOL/IOH and 30-pF load capacitance.  
4. At any given temperature and voltage condition, tHZCS is less than tLZCS for any given device. These parameters are guaranteed and not 100% tested.  
5. tHZCS and tHZWE are specified with CL = 5 pF as in (b) of AC Test Loads and Waveforms. Transition is measured ± 500 mV from steady-state voltage.  
6. The internal Write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a Write and either signal can  
terminate a Write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the Write.  
7. WE is HIGH for Read cycle.  
Document #: 38-05297 Rev. **  
Page 3 of 7  
CYM1861AV33  
Switching Waveforms (continued)  
Read Cycle No. 2[7, 9]  
t
RC  
CS  
t
ACS  
OE  
t
HZOE  
t
DOE  
t
HZCS  
t
LZOE  
HIGH  
IMPEDANCE  
HIGH IMPEDANCE  
DATA VALID  
DATA OUT  
t
LZCS  
t
PD  
t
PU  
ICC  
V
CC  
50%  
50%  
SUPPLY  
CURRENT  
ISB  
Write Cycle No. 1 (WE Controlled) [6]  
t
WC  
ADDRESS  
CS  
t
SCS  
t
t
HA  
AW  
t
SA  
t
PWE  
WE  
t
t
HD  
SD  
DATA IN  
DATA VALID  
t
t
LZWE  
HZWE  
HIGH IMPEDANCE  
DATA OUT  
DATA UNDEFINED  
Notes:  
8. Device is continuously selected, CS = VIL, and OE = VIL  
.
9. Address valid prior to or coincident with CS transition LOW.  
Document #: 38-05297 Rev. **  
Page 4 of 7  
CYM1861AV33  
Switching Waveforms (continued)  
Write Cycle No. 2 (CS Controlled)[6,10]  
t
WC  
ADDRESS  
t
SA  
t
SCS  
CS  
t
t
HA  
AW  
t
PWE  
WE  
t
t
HD  
SD  
DATA IN  
DATA VALID  
t
HZWE  
HIGH IMPEDANCE  
DATA OUT  
DATA UNDEFINED  
Truth Table  
CS  
H
L
WE  
X
OE  
X
Inputs/Output  
Mode  
High-Z  
Deselect/Power-down  
H
L
Data Out  
Data In  
High-Z  
Read  
L
L
X
Write  
L
H
H
Deselect  
Ordering Information  
Speed  
Package  
Type  
Operating  
Range  
(ns)  
Ordering Code  
CYM1861AV33PM-20C  
CYM1861AV33PM-25C  
Package Type  
20  
PM48  
PM48  
72-pin Plastic SIMM Module  
72-pin Plastic SIMM Module  
Commercial  
Commercial  
25  
Note:  
10. If CS goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.  
Document #: 38-05297 Rev. **  
Page 5 of 7  
CYM1861AV33  
Package Diagram  
72-pin Plastic SIMM Module  
51-41322-*D  
All product and company names mentioned in this document are the trademarks of their respective holders.  
Document #: 38-05297 Rev. **  
Page 6 of 7  
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize  
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.  
CYM1861AV33  
Document Title: CYM1861AV33 2,048K x 32 3.3V Static RAM Module  
Document Number: 38-05297  
Issue  
Date  
Orig. of  
Change  
REV.  
ECN NO.  
Description of Change  
**  
117909  
08/22/02  
MEG  
New Data Sheet  
Document #: 38-05297 Rev. **  
Page 7 of 7  
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