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CYM1465PD-100C

型号：

CYM1465PD-100C

品牌：

CYPRESS[ CYPRESS ]

页数：

6 页

PDF大小：

137 K

下载PDF手册
1CYM1465  
CYM1465  
512K x 8 SRAM Module  
Features  
Functional Description  
• High-density 4-megabit SRAM module  
• High-speed CMOS SRAMs  
— Access time of 70 ns  
• Low active power  
The CYM1465 is a high-performance 4-megabit static RAM  
module organized as 512K words by 8 bits. This module is  
constructed using four 128K x 8 RAMs mounted on a substrate  
with pins. A decoder is used to interpret the higher-order ad-  
dresses (A and A ) and to select one of the four RAMs.  
17  
18  
— 605 mW (max.)  
Writing to the module is accomplished when the chip select  
(CS) and write enable (WE) inputs are both LOW. Data on the  
eight input/output pins (I/O through I/O ) of the device is writ-  
• 2V data retention (L Version)  
• JEDEC-compatible pinout  
• 32-pin, 0.6-inch-wide DIP package  
• TTL-compatible inputs and outputs  
• Low profile  
0
7
ten into the memory location specified on the address pins (A  
0
through A ). Reading the device is accomplished by taking  
18  
chip select and output enable (OE) LOW while write enable  
remains inactive or HIGH. Under these conditions, the con-  
tents of the memory location specified on the address pins (A  
— Max. height of 0.27 in.  
• Small PCB footprint  
0
through A ) will appear on the eight appropriate data in-  
18  
put/output pins (I/O through I/O ).  
0
7
— 0.98 sq. in.  
The input/output pins remain in a high-impedance state unless  
the module is selected, outputs are enabled, and write enable  
is HIGH.  
Logic Block Diagram  
Pin Configuration  
DIP  
Top View  
A − A  
0
16  
1
2
3
4
32  
31  
30  
29  
A
18  
A
16  
A
14  
A
12  
V
CC  
S
WE  
OE  
A
15  
A
17  
WE  
5
6
7
8
9
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
A
A
7
13  
128K x 8  
SRAM  
128K x 8  
SRAM  
A
A
6
8
A
A
A
5
9
11  
A
4
A
OE  
3
A
10  
10  
11  
12  
13  
14  
15  
16  
A
2
A
CS  
1
A
I/O  
I/O  
I/O  
I/O  
I/O  
0
7
6
5
4
3
I/O  
I/O  
I/O  
0
1
2
A
A
17  
1 OF 4  
DECODER  
18  
128K x 8  
SRAM  
128K x 8  
SRAM  
GND  
CS  
1465–2  
I/O0 − I/O7  
1465–1  
Selection Guide  
1465-70  
1465-85  
85  
1465-100  
100  
1465-120  
120  
1465-150  
150  
Maximum Access Time (ns)  
70  
110  
12  
Maximum Operating Current (mA)  
Maximum Standby Current (mA)  
110  
110  
110  
110  
12  
12  
12  
12  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
January 1991 – Revised January 1995  
CYM1465  
DC Input Voltage .............................................-0.5V to +7.0V  
Maximum Ratings  
(Above which the useful life may be impaired.)  
Operating Range  
Storage Temperature ................................. –55°C to +150°C  
Ambient  
Range  
Commercial  
Industrial  
Temperature  
0°C to +70°C  
–40°C to +85°C  
V
CC  
Ambient Temperature with  
Power Applied............................................... –10°C to +85°C  
5V ± 10%  
5V ± 10%  
Supply Voltage to Ground Potential............... –0.5V to +7.0V  
DC Voltage Applied to Outputs  
in High Z State ............................................... –0.5V to +7.0V  
Electrical Characteristics Over the Operating Range  
1465  
Max.  
Parameter  
Description  
Output HIGH Voltage  
Output LOW Voltage  
Input HIGH Voltage  
Input LOW Voltage  
Input Load Current  
Output Leakage Current  
Test Conditions  
Min.  
Unit  
V
V
V
V
V
V
= Min., I = – 1.0 mA  
2.4  
V
V
OH  
OL  
IH  
CC  
CC  
OH  
= Min., I = 2.1 mA  
0.4  
+ 0.3  
OL  
2.2  
–0.3  
–10  
–20  
V
V
CC  
0.8  
+10  
+20  
110  
V
IL  
I
I
I
GND < V < V  
CC  
µA  
µA  
mA  
IX  
I
GND < V < V , Output Disabled  
OZ  
CC  
O
CC  
V
Operating Supply  
V
= Max., I  
= 0 mA, CS < V  
OUT IL  
CC  
CC  
Current  
I
I
Automatic CS Power-Down Max. V , CS > V ,  
12  
mA  
SB1  
SB2  
CC  
IH  
Current  
Min. Duty Cycle = 100%  
Automatic CS Power-Down Max. V , CS > V - 0.2V,  
Standard Version  
L Version  
8
mA  
CC  
CC  
Current  
V
> V - 0.2V or V < 0.2V  
IN CC IN  
420  
µA  
Capacitance[1]  
Parameter  
Description  
Input Capacitance  
Output Capacitance  
Test Conditions  
T = 25°C, f = 1 MHz,  
Max.  
Unit  
pF  
C
C
45  
45  
IN  
A
V
= 5.0V  
CC  
pF  
OUT  
AC Test Loads and Waveforms  
1.847kΩ  
1.847k Ω  
5 pF  
ALL INPUT PULSES  
90%  
5V  
5V  
OUTPUT  
3.0V  
GND  
90%  
OUTPUT  
10%  
10%  
1kΩ  
1kΩ  
[2]  
C
L
< 10 ns  
< 10 ns  
INCLUDING  
JIG AND  
SCOPE  
INCLUDING  
JIG AND  
SCOPE  
(b)  
(a)  
1465–3  
1465–4  
Equivalent to:  
THÉVENIN EQUIVALENT  
648Ω  
OUTPUT  
1.76V  
Notes:  
1. Tested on a sample basis.  
2
CYM1465  
[2]  
Switching Characteristics Over the Operating Range  
1465-70  
1465-85  
1465-100  
1465-120  
1465-150  
Parameter  
Description  
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit  
READ CYCLE  
t
t
t
t
t
t
t
t
t
Read Cycle Time  
Address to Data Valid  
70  
85  
10  
100  
10  
120  
10  
150  
10  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
RC  
70  
85  
100  
120  
150  
AA  
Data Hold from Address Change 10  
CS LOW to Data Valid  
OHA  
ACS  
DOE  
LZOE  
HZOE  
LZCS  
HZCS  
70  
35  
85  
45  
100  
50  
120  
60  
150  
75  
OE LOW to Data Valid  
OE LOW to Low Z  
OE HIGH to High Z  
CS LOW to Low Z  
5
5
5
5
5
[3]  
25  
30  
30  
30  
35  
35  
45  
45  
55  
60  
10  
10  
10  
10  
10  
[3]  
CS HIGH to High Z  
[4]  
WRITE CYCLE  
t
t
t
t
t
t
t
t
t
t
Write Cycle Time  
70  
65  
65  
0
85  
75  
75  
5
100  
90  
90  
5
120  
100  
100  
5
150  
115  
110  
5
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
WC  
CS LOW to Write End  
SCS  
AW  
Address Set-Up to Write End  
Address Hold from Write End  
Address Set-Up to Write Start  
WE Pulse Width  
HA  
0
5
5
5
5
SA  
55  
30  
0
65  
35  
0
75  
40  
0
85  
45  
0
95  
50  
0
PWE  
SD  
Data Set-Up to Write End  
Data Hold from Write End  
WE HIGH to Low Z  
HD  
5
5
5
5
5
LZWE  
HZWE  
[3]  
WE LOW to High Z  
25  
30  
35  
40  
45  
Data Retention Characteristics Over the Operating Range (L Version Only)  
Commercial  
Industrial  
Min. Max.  
Parameter  
Description  
for Retention Data  
Test Conditions  
Min.  
Max.  
Unit  
V
V
V
CS > V – 0.2V  
2
2
DR  
CC  
CC  
I
t
t
Data Retention Current  
V
= 3.0V,  
50  
150  
µA  
ns  
CCDR3  
DR  
CS > V – 0.2V,  
[5]  
CC  
Chip Deselect to Data Retention Time  
Operation Recovery Time  
0
5
0
5
CDR  
V
V
> V – 0.2V or  
IN  
IN  
CC  
[5]  
< 0.2V  
ms  
R
Notes:  
2. Test conditions assume signal transition times of 10 ns or less, timing reference levels of 1.5V, input levels of 0 to 3.0V, and output loading of the specified  
IOL/IOH and 100-pF load capacitance for 85-, 100-, 120-, and 150-ns speeds. CL = 30 pF for 70-ns speed.  
3. CL = 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured ±500 mV from steady-state voltage.  
4. The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can  
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.  
5. Guaranteed, not tested.  
Data Retention Waveform  
DATA RETENTION MODE  
V
CC  
4.5V  
4.5V  
V
DR  
> 2V  
t
t
R
CDR  
V
DR  
V
IH  
V
IH  
CS  
1465–5  
3
CYM1465  
Switching Waveforms  
[6,7]  
Read Cycle No. 1  
t
RC  
ADDRESS  
t
AA  
t
OHA  
DATA OUT  
PREVIOUS DATA VALID  
DATA VALID  
1465–6  
[6,8]  
Read Cycle No. 2  
t
RC  
CS  
t
ACS  
OE  
t
HZOE  
t
DOE  
t
HZCS  
t
LZOE  
HIGH  
IMPEDANCE  
HIGH IMPEDANCE  
DATA VALID  
DATA OUT  
t
LZCS  
1465–7  
[4]  
(WE  
Write Cycle No. 1  
Controlled)  
t
WC  
ADDRESS  
t
SCS  
CS  
WE  
t
t
HA  
AW  
t
SA  
t
PWE  
t
t
HD  
SD  
DATA IN  
DATA VALID  
t
t
LZWE  
HZWE  
HIGH IMPEDANCE  
DATAOUT  
DATA UNDEFINED  
1465–8  
Notes:  
6. WE is HIGH for read cycle.  
7. Device is continuously selected, CS = VIL  
8. Address valid prior to or coincident with CS transition LOW.  
.
4
CYM1465  
Switching Waveforms (continued)  
[4,9]  
Write Cycle No. 2 (CS Controlled)  
t
WC  
ADDRESS  
t
SA  
t
SCS  
CS  
t
t
HA  
AW  
t
PWE  
WE  
t
t
HD  
SD  
DATA IN  
DATA VALID  
t
HZWE  
HIGH IMPEDANCE  
DATA OUT  
DATA UNDEFINED  
1465–9  
Note:  
9. If CS goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.  
Truth Table  
Inputs  
CS  
H
L
WE  
X
OE  
X
Output  
High Z  
Mode  
Deselect/Power-Down  
Read Word  
H
L
Data Out  
Data In  
High Z  
L
L
X
Write Word  
L
H
H
Deselect  
5
CYM1465  
Ordering Information  
Speed  
Package  
Name  
Operating  
Range  
(ns)  
Ordering Code  
CYM1465PD-70C  
CYM1465LPD-70C  
CYM1465PD-85C  
CYM1465LPD-85C  
CYM1465PD-85I  
Package Type  
70  
PD03  
PD03  
PD03  
PD03  
PD03  
PD03  
PD03  
PD03  
PD03  
32-Pin DIP Module  
Commercial  
Commercial  
Industrial  
85  
32-Pin DIP Module  
32-Pin DIP Module  
32-Pin DIP Module  
32-Pin DIP Module  
32-Pin DIP Module  
32-Pin DIP Module  
32-Pin DIP Module  
32-Pin DIP Module  
CYM1465LPD-85I  
CYM1465PD-100C  
CYM1465LPD-100C  
CYM1465PD-100I  
CYM1465LPD-100I  
CYM1465PD-120C  
CYM1465LPD-120C  
CYM1465PD-120I  
CYM1465LPD-120I  
CYM1465PD-150C  
CYM1465LPD-150C  
CYM1465PD-150I  
CYM1465LPD-150I  
100  
120  
150  
Commercial  
Industrial  
Commercial  
Industrial  
Commercial  
Industrial  
Document #: 38-M-00036-D  
Package Diagrams  
32–Pin DIP Module PD03  
© Cypress Semiconductor Corporation, 1995. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of anycircuitry other than circuitry embodied in a CypressSemiconductor product. Nor does it conveyor imply any license under patent or other rights. CypressSemiconductor does not authorize  
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.  
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