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Data Sheet, Rev. 1.0, Sep. 2004

HYS64T256020HU–[3.7/5]–A

HYS72T256020HU–[3.7/5]–A

240-Pin Unbuffered DDR2 SDRAM Modules

DDR2 SDRAM

UDIMM SDRAM RoHS Compliant

Memory Products

N e v e r s t o p t h i n k i n g .

The information in this document is subject to change without notice.

Edition 2004-09

Published by Infineon Technologies AG,

St.-Martin-Strasse 53,

81669 München, Germany

Attention please!

The information herein is given to describe certain components and shall not be considered as a guarantee of

characteristics.

Terms of delivery and rights to technical change reserved.

We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding

circuits, descriptions and charts stated herein.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest

Infineon Technologies Office (www.infineon.com).

Warnings

Due to technical requirements components may contain dangerous substances. For information on the types in

question please contact your nearest Infineon Technologies Office.

Infineon Technologies Components may only be used in life-support devices or systems with the express written

approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure

of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support

devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain

and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may

be endangered.

Data Sheet, Rev. 1.0, Sep. 2004

HYS64T256020HU–[3.7/5]–A

HYS72T256020HU–[3.7/5]–A

240-Pin Unbuffered DDR2 SDRAM Modules

DDR2 SDRAM

UDIMM SDRAM RoHS Compliant

Memory Products

N e v e r s t o p t h i n k i n g .

HYS64T256020HU–[3.7/5]–A HYS72T256020HU–[3.7/5]–A HYS72T256020HU–[3.7/5]–A

Revision History:

Rev. 1.0

2004-09

Previous Revision:

Rev. 0.22

2003-09

Page

Subjects (major changes since last revision)

We Listen to Your Comments

Any information within this document that you feel is wrong, unclear or missing at all?

Your feedback will help us to continuously improve the quality of this document.

Please send your proposal (including a reference to this document) to:

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Template: mp_a4_v2.3_2004-01-14.fm

HYS[64/72]T256020HU–[3.7/5]–A

Unbuffered Double-Data-Rate-Two SDRAM Modules

Table of Contents

1

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.1

1.2

2

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1

Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3

I

_DDSpecifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.1

3.2

I

_DDTest Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

ODT (On Die Termination) Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.1

Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5

6

7

SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Product Type Nomenclature (DDR2 DRAMs and DIMMs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Data Sheet

5

Rev. 1.0, 2004-09

02182004-TRHM-8N4H

HYS[64/72]T256020HU–[3.7/5]–A

Unbuffered Double-Data-Rate-Two SDRAM Modules

Overview

1

Overview

This chapter gives an overview of the 240-Pin Unbuffered DDR2 SDRAM Modules product family and describes

its main characteristics.

1.1

Features

•

240-pin PC2-4200 and PC2-3200 DDR2 SDRAM

memory modules for use as main memory when

installed in systems such as mobile personal

computers.

•

Programmable CAS Latencies (3, 4 and 5), Burst

Length (8 & 4) and Burst Type

•

Burst Refresh, Distributed Refresh and Self Refresh

All inputs and outputs SSTL_18 compatible

OCD (Off-Chip Driver Impedance Adjustment) and

ODT (On-Die Termination)

•

256M × 64, 256M × 72 module organisation, and

128M × 8 chip organisation

JEDEC standard Double-Data-Rate-Two

Synchronous DRAMs (DDR2 SDRAM) with a single

+ 1.8 V (± 0.1 V) power supply

•

Serial Presence Detect with E²PROM

UDIMM Dimensions (nominal):

30 mm high, 133.35 mm wide

•

Built with 1Gb DDR2 SDRAMs in and P-TFBGA-68

chipsize packages

•

Based on JEDEC standard reference layouts Raw

Card “B“

RoHS Compliant Products¹⁾

Table 1

Performance

Product Type Speed Code

Speed Grade

max. Clock Frequency

–3.7

PC2–4200 4–4–4

f_CK5266

f_CK4266

f_CK3200

t_RCD15

–5

Units

—

MHz

ns

PC2–3200 3–3–3

@CL5

@CL4

@CL3

200

15

40

min. RAS-CAS-Delay

min. Row Pre charge Time

min. Row Active Time

min. Row Cycle Time

t_RP

t_RAS45

t_RC60

15

55

1.2

Description

The INFINEON HYS[64/72]T256020HU–[3.7/5]–A Rate (DDR2) Synchronous DRAMs for ECC and Non-

module family are low profile Unbuffered DIMM ECC applications. Decoupling capacitors are mounted

modules with 30,0 mm height based on DDR2 on the PCB board. The DIMMs feature serial presence

technology. DIMMs are available as non-ECC modules detect based on a serial E²PROM device using the 2-

in 256M × 64 (2GB), and as ECC-modules in pin I²C protocol. The first 128 bytes are programmed

256M × 72 (2GB) organisation and density, intended with configuration data and the second 128 bytes are

for mounting into 240 pin connector sockets.

available to the customer.

The memory array is designed with 1Gb Double Data

1)RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and

electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council

of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated

biphenyls and polybrominated biphenyl ethers.

Data Sheet

6

Rev. 1.0, 2004-09

02182004-TRHM-8N4H

HYS[64/72]T256020HU–[3.7/5]–A

Unbuffered Double-Data-Rate-Two SDRAM Modules

Overview

Table 2

Ordering Information

Product Type¹⁾

Compliance Code²⁾

Description

SDRAM Technology

PC2-3200

HYS64T256020HU–5–A

HYS72T256020HU–5–A

PC2–4200

2GB 2R×8 PC2–3200U–333–11–B1 2 Ranks, Non-ECC 1 Gbit (×8

2GB 2R×8 PC2–3200E–333–11–B1 2 Ranks, ECC 1 Gbit (×8)

HYS64T256020HU–3.7–A 2GB 2R×8 PC2–4200U–444–11–B1 2 Ranks, Non-ECC 1 Gbit (×8

HYS72T256020HU–3.7–A 2GB 2R×8 PC2–4200E–444–11–B1 2 Ranks, ECC 1 Gbit (×8)

1) All part numbers end with a place code, designating the silicon die revision. Example: HYS64T256020HU–3.7–A, indicating

Rev. “A” dies are used for DDR2 SDRAM components. For all INFINEON DDR2 module and component nomenclature see

Chapter 7 of this data sheet.

2) The Compliance Code is printed on the module label and describes the speed grade, e.g. “PC2–4200U–444–11–B”, where

4200U means Unbuffered DIMM modules with 4.26 GB/sec Module Bandwidth and “444-11” means Column Address

Strobe (CAS) latency = 4, Row Column Delay (RCD) latency = 4 and Row Pre charge (RP) latency = 4 using the latest

JEDEC SPD Revision 1.1 and produced on the Raw Card “B”.

Data Sheet

7

Rev. 1.0, 2004-09

02182004-TRHM-8N4H

HYS[64/72]T256020HU–[3.7/5]–A

Unbuffered Double-Data-Rate-Two SDRAM Modules

Overview

Table 3

DIMM

Address Format

Module

Memory

Ranks

ECC/

# of

# of row/bank/columns bits

Raw

Density Organization

Non-ECC

SDRAMs

Card

2 GB

256M × 64

256M × 72

2

Non-ECC

ECC

16

18

14/3/10

B

Table 4

Components on Modules ¹⁾

Part Number

DRAM components

DRAM Density

DRAM Organisation

reference data sheet

HYB18T1G800AF²⁾

HYS64T256020HU²⁾

HYS72T256020HU²⁾

1 Gbit

128Mb ×8

1) For a detailed description of all functions of the DRAM components on these modules see the referenced component data

sheet.

2) Green products

Data Sheet

8

Rev. 1.0, 2004-09

02182004-TRHM-8N4H

HYS[64/72]T256020HU–[3.7/5]–A

Unbuffered Double-Data-Rate-Two SDRAM Modules

Pin Configuration

2

Pin Configuration

The pin configuration of the Unbuffered DDR2 SDRAM DIMM is listed by function in Table 5 (240 pins). The

abbreviations used in columns Pin and Buffer Type are explained in Table 6 and Table 7 respectively. The pin

numbering is depicted in Figure 1 for non-ECC modules (×64) and Figure 2 for ECC modules (×72).

Table 5

Pin#

Pin Configuration of UDIMM

Name Pin Buffer Function

Typ Type

e

Clock Signals

185

137

220

186

138

221

52

CK0

CK1

CK2

CK0

CK1

CK2

CKE0

CKE1

I

SSTL Clock Signals 2:0, Complement Clock Signals 2:0

Note: The system clock inputs. All address and command lines are

sampled on the cross point of the rising edge of CK and the

falling edge of CK. A Delay Locked Loop (DLL) circuit is driven

from the clock inputs and output timing for read operations is

synchronized to the input clock.

SSTL

SSTL Clock Enable Rank 1:0

Note: Activates the DDR2 SDRAM CK signal when HIGH and

171

SSTL

deactivates the CK signal when LOW. By deactivating the

clocks, CKE LOW initiates the Power Down Mode or the Self

Refresh Mode.

Note: 2 Ranks module

Note: 1 Rank module

NC

—

Control Signals

193

76

S0

S1

I

SSTL Chip Select Rank 1:0

Note: Enables the associated DDR2 SDRAM command decoder

SSTL

when LOW and disables the command decoder when HIGH.

When the command decoder is disabled, new commands are

ignored but previous operations continue. Rank 0 is selected by

S0; Rank 1 is selected by S1. Ranks are also called "Physical

banks".

Note: 2 Ranks module

Note: 1 Rank module

SSTL Row Address Strobe

NC

RAS

NC

I

—

192

Note: When sampled at the cross point of the rising edge of CK,and

falling edge of CK, RAS, CAS and WE define the operation to

be executed by the SDRAM.

74

73

CAS

WE

I

SSTL Column Address Strobe

SSTL Write Enable

Address Signals

71

190

BA0

BA1

I

SSTL Bank Address Bus 1:0

Note: Selects which DDR2 SDRAM internal bank of four or eight is

activated.

SSTL Bank Address Bus 2

Note: greater than 512Mb DDR2 SDRAMS

SSTL

54

BA2

NC

I

NC

—

Note: less than 1Gb DDR2 SDRAMS

Data Sheet

9

Rev. 1.0, 2004-09

02182004-TRHM-8N4H

HYS[64/72]T256020HU–[3.7/5]–A

Unbuffered Double-Data-Rate-Two SDRAM Modules

Pin Configuration

Table 5

Pin#

Pin Configuration of UDIMM (cont’d)

Name Pin Buffer Function

Typ Type

e

188

183

63

182

61

60

180

58

A0

A1

A2

A3

A4

A5

A6

A7

I

SSTL Address Bus 12:0

Note: During a Bank Activate command cycle, defines the row

SSTL

address when sampled at the crosspoint of the rising edge of CK

and falling edge of CK. During a Read or Write command cycle,

defines the column address when sampled at the cross point of

the rising edge of CK and falling edge of CK. In addition to the

column address, AP is used to invoke autoprecharge operation

at the end of the burst read or write cycle. If AP is HIGH,

autoprecharge is selected and BA0-BAn defines the bank to be

precharged. If AP is LOW, autoprecharge is disabled. During a

Precharge command cycle, AP is used in conjunction with BA0-

BAn to control which bank(s) to precharge. If AP is HIGH, all

banks will be precharged regardless of the state of BA0-BAn

inputs. If AP is LOW, then BA0-BAn are used to define which

bank to precharge.

179

177

70

A8

A9

A10

AP

A11

A12

A13

57

176

196

SSTL Address Signal 13

Note: 1 Gbit based module and 512M ×4/×8

Note:

NC

—

1. Module based on 1 Gbit ×16

2. Module based on 512 Mbit ×16 or smaller

174

A14

NC

I

SSTL Address Signal 14

Note: Modules based on 2 Gbit

NC

—

Note: Modules based on 1 Gbit or smaller

Data Sheet

10

Rev. 1.0, 2004-09

02182004-TRHM-8N4H

HYS[64/72]T256020HU–[3.7/5]–A

Unbuffered Double-Data-Rate-Two SDRAM Modules

Pin Configuration

Table 5

Pin#

Pin Configuration of UDIMM (cont’d)

Name Pin Buffer Function

Typ Type

e

Data Signals

3

4

9

10

122

123

128

129

12

13

21

22

131

132

140

141

24

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9

DQ10 I/O

DQ11 I/O

DQ12 I/O

DQ13 I/O

DQ14 I/O

DQ15 I/O

DQ16 I/O

I/O

SSTL Data Bus 63:0

Note: Data Input/Output pins

SSTL

Data Sheet

11

Rev. 1.0, 2004-09

02182004-TRHM-8N4H

HYS[64/72]T256020HU–[3.7/5]–A

Unbuffered Double-Data-Rate-Two SDRAM Modules

Pin Configuration

Table 5

Pin#

Pin Configuration of UDIMM (cont’d)

Name Pin Buffer Function

Typ Type

e

25

30

31

143

144

149

150

33

34

39

40

152

153

158

159

80

81

86

87

199

200

205

206

89

90

95

96

208

209

214

215

98

DQ17 I/O

DQ18 I/O

DQ19 I/O

DQ20 I/O

DQ21 I/O

DQ22 I/O

DQ23 I/O

DQ24 I/O

DQ25 I/O

DQ26 I/O

DQ27 I/O

DQ28 I/O

DQ29 I/O

DQ30 I/O

DQ31 I/O

DQ32 I/O

DQ33 I/O

DQ34 I/O

DQ35 I/O

DQ36 I/O

DQ37 I/O

DQ38 I/O

DQ39 I/O

DQ40 I/O

DQ41 I/O

DQ42 I/O

DQ43 I/O

DQ44 I/O

DQ45 I/O

DQ46 I/O

DQ47 I/O

DQ48 I/O

DQ49 I/O

DQ50 I/O

DQ51 I/O

DQ52 I/O

DQ53 I/O

DQ54 I/O

DQ55 I/O

DQ56 I/O

SSTL Data Bus 63:0

SSTL

99

107

108

217

218

226

227

110

Data Sheet

12

Rev. 1.0, 2004-09

02182004-TRHM-8N4H

HYS[64/72]T256020HU–[3.7/5]–A

Unbuffered Double-Data-Rate-Two SDRAM Modules

Pin Configuration

Table 5

Pin#

Pin Configuration of UDIMM (cont’d)

Name Pin Buffer Function

Typ Type

e

111

116

117

229

230

235

236

DQ57 I/O

DQ58 I/O

DQ59 I/O

DQ60 I/O

DQ61 I/O

DQ62 I/O

DQ63 I/O

SSTL Data Bus 63:0

SSTL

Check Bit Signal

42

CB0

I/O

SSTL Check Bit 0

Note: ECC type module only

Note: Non-ECC module

SSTL Check Bit 1

Note: ECC type module only

Note: Non-ECC module

SSTL Check Bit 2

Note: ECC type module only

Note: Non-ECC module

SSTL Check Bit 3

Note: ECC type module only

Note: Non-ECC module

SSTL Check Bit 4

Note: ECC type module only

Note: Non-ECC module

SSTL Check Bit 5

Note: ECC type module only

Note: Non-ECC module

SSTL Check Bit 6

Note: ECC type module only

Note: Non-ECC module

SSTL Check Bit 7

Note: ECC type module only

NC

CB1

NC

I/O

—

43

NC

CB2

NC

I/O

—

48

NC

CB3

NC

I/O

—

49

NC

CB4

NC

I/O

—

161

162

167

168

NC

CB5

NC

I/O

—

NC

CB6

NC

I/O

—

NC

CB7

NC

I/O

—

NC

—

Note: Non-ECC module

Data Sheet

13

Rev. 1.0, 2004-09

02182004-TRHM-8N4H

HYS[64/72]T256020HU–[3.7/5]–A

Unbuffered Double-Data-Rate-Two SDRAM Modules

Pin Configuration

Table 5

Pin#

Pin Configuration of UDIMM (cont’d)

Name Pin Buffer Function

Typ Type

e

Data Strobe Bus

7

DQS0 I/O

DQS1 I/O

DQS2 I/O

DQS3 I/O

DQS4 I/O

DQS5 I/O

DQS6 I/O

DQS7 I/O

DQS8 I/O

SSTL Data Strobe Bus 8:0

Note: The data strobes, associated with one data byte, sourced with

data transfers. In Write mode, the data strobe is sourced by the

controller and is centered in the data window. In Read mode the

data strobe is sourced by the DDR2 SDRAM and is sent at the

leading edge of the data window. DQS signals are

complements, and timing is relative to the crosspoint of

respective DQS and DQS. If the module is to be operated in

single ended strobe mode, all DQS signals must be tied on the

system board to V_SSand DDR2 SDRAM mode registers

programmed appropriately.

16

28

37

84

93

105

114

46

SSTL

Note: See block diagram for corresponding DQ signals

6

15

27

36

83

92

104

113

DQS0 I/O

DQS1 I/O

DQS2 I/O

DQS3 I/O

DQS4 I/O

DQS5 I/O

DQS6 I/O

DQS7 I/O

DQS8 I/O

SSTL Complement Data Strobe Bus 8:0

Note: See block diagram for corresponding DQ signals

SSTL

45

Data Mask Signals

125

134

146

155

202

211

223

232

DM0

I

SSTL Data Mask Bus 8:0

Note: The data write masks, associated with one data byte. In Write

DM1

DM2

DM3

DM4

DM5

DM6

DM7

DM8

SSTL

mode, DM operates as a byte mask by allowing input data to be

written if it is LOW but blocks the write operation if it is HIGH. In

Read mode, DM lines have no effect.

Note: See block diagram for corresponding DQ M signals

164

EEPROM

120

SCL

SDA

I

CMOS Serial Bus Clock

Note: This signal is used to clock data into and out of the SPD

EEPROM.

119

I/O

OD

Serial Bus Data

Note: This is a bidirectional pin used to transfer data into or out of the

SPD EEPROM. A resistor must be connected from SDA to to

V

_DDSPDon the motherboard to act as a pull-up.

Data Sheet

14

Rev. 1.0, 2004-09

02182004-TRHM-8N4H

HYS[64/72]T256020HU–[3.7/5]–A

Unbuffered Double-Data-Rate-Two SDRAM Modules

Pin Configuration

Table 5

Pin#

Pin Configuration of UDIMM (cont’d)

Name Pin Buffer Function

Typ Type

e

239

240

101

SA0

SA1

SA2

I

CMOS Serial Address Select Bus 2:0

Note: Address pins used to select the Serial Presence Detect base

CMOS

address.

CMOS

Power Supplies

1

V_REF

AI

—

I/O Reference Voltage

Note: Reference voltage for the SSTL-18 inputs.

EEPROM Power Supply

Note: Power supplies for core, I/O, Serial Presence Detect, and

ground for the module.

238

V_DDSPDPW

R

51,56,62,72,75,

78,170,175,181,

191,194

53,59,64,67,69,

172,178,184,187,

189,197

V_DDQPW

—

I/O Driver Power Supply

R

V_DD

V_SS

PW

R

Power Supply

Note: Power supplies for core, I/O, Serial Presence Detect, and

ground for the module.

Ground Plane

2,5,8,11,14,17,

20,23,26,29,32,

35,38,41,44,47,

50,65,66,79,82,

85,88,91,94,97,

100,103,106,

GND —

Note: Power supplies for core, I/O, Serial Presence Detect, and

ground for the module.

109,112,115,118,

121,124,127,

130,133,136,139,

142,145,148,

151,154,157,160,

163,166,169,

198,201,204,207,

210,213,216,

219,222,225,228,

231,234,237

Other Pins

195

77

ODT0

ODT1

I

SSTL On-Die Termination Control 0

SSTL On-Die Termination Control 1

Note: Asserts on-die termination for DQ, DM, DQS, and DQS signals

if enabled via the DDR2 SDRAM mode register.

Note: 2 Rank modules

NC

—

Note: 1 Rank modules

Not connected

Note: Pins not connected on Infineon UDIMMs

18,19,55,68,102, NC

126,135,147,

156,165,173,203,

212, 224,233

Data Sheet

15

Rev. 1.0, 2004-09

02182004-TRHM-8N4H

HYS[64/72]T256020HU–[3.7/5]–A

Unbuffered Double-Data-Rate-Two SDRAM Modules

Pin Configuration

Table 6

Abbreviations for Pin Type

Abbreviation

Description

I

O

Standard input-only pin. Digital levels.

Output. Digital levels.

I/O is a bidirectional input/output signal.

Input. Analog levels.

Power

I/O

AI

PWR

GND

NC

Ground

Not Connected

Table 7

Abbreviation

SSTL

LV-CMOS

CMOS

Abbreviations for Buffer Type

Description

Serial Stub Terminated Logic (SSTL_18)

Low Voltage CMOS

CMOS Levels

OD

Open Drain. The corresponding pin has 2 operational states, active low and

tristate, and allows multiple devices to share as a wire-OR.

Data Sheet

16

Rev. 1.0, 2004-09

02182004-TRHM-8N4H

HYS[64/72]T256020HU–[3.7/5]–A

Unbuffered Double-Data-Rate-Two SDRAM Modules

Pin Configuration

VREF - Pin 001

DQ0 - Pin 003

V_SS- Pin 005

DQS0 - Pin 007

DQ2 - Pin 009

V_SS- Pin 011

DQ9 - Pin 013

DQS1 - Pin 015

V_SS- Pin 017

Pin 121 - V_SS

Pin 122 - DQ4

Pin 123 - DQ5

Pin 124 - V_SS

V_SS

- Pin 002

- Pin 004

DQ1

Pin 125 - DM0

Pin 126 - NC

DQS0 - Pin 006

Pin 127 - V_SS

V_SS

- Pin 008

- Pin 010

- Pin 012

- Pin 014

Pin 128 - DQ6

Pin 129 - DQ7

Pin 130 - V_SS

DQ3

DQ8

V_SS

Pin 131 - DQ12

Pin 132 - DQ13

Pin 133 - V_SS

Pin 134 - DM1

Pin 135 - NC

DQS1 - Pin 016

Pin 136 - V_SS

Pin 137 - CK1

Pin 138 - CK1

Pin 139 - V_SS

NC

- Pin 018

- Pin 020

NC

- Pin 019

-

V_SS

Pin 140 - DQ14

Pin 141 - DQ15

DQ10 Pin 021

-

Pin 142 V_SS

DQ11

DQ16

V_SS

Pin 022

-

V_SS

Pin 023

Pin 143 - DQ20

Pin 145 - V_SS

Pin 147 - NC

Pin 149 - DQ22

Pin 151 - V_SS

Pin 153 - DQ29

Pin 155 - DM3

Pin 157 - V_SS

Pin 159 - DQ31

Pin 161 - NC

Pin 163 - V_SS

Pin 165 - NC

Pin 167 - NC

Pin 169 - V_SS

Pin 171 - CKE1

Pin 173 - NC

Pin 175 - V_DDQ

Pin 177 - A9

-

Pin 144 DQ21

Pin 024

DQ17 - Pin 025

DQS2 - Pin 027

-

Pin 146 DM2

Pin 026

Pin 028

Pin 030

Pin 032

-

Pin 148 V_SS

DQS2

DQ18

V_SS

- Pin 029

-

Pin 150 DQ23

DQ19 - Pin 031

DQ24 - Pin 033

-

Pin 152 DQ28

DQ25 - Pin 034

DQS3 - Pin 036

Pin 154 - V_SS

Pin 156 - NC

Pin 158 - DQ30

Pin 160 - V_SS

V_SS

- Pin 035

DQS3 - Pin 037

DQ26 - Pin 039

V_SS

- Pin 038

DQ27 - Pin 040

V_SS

NC

V_SS

NC

- Pin 041

- Pin 043

- Pin 045

- Pin 047

- Pin 049

-

Pin 162 NC

NC

- Pin 042

-

Pin 164 NC

V_SS

NC

Pin 044

Pin 046

Pin 048

Pin 050

Pin 052

-

Pin 166 V_SS

-

Pin 168 NC

NC

-

Pin 170 V_DDQ

V_SS

CKE0

V_DDQ- Pin 051

V_DD- Pin 053

-

Pin 172 V_DD

-

Pin 174 A14

NC/BA2 Pin 054

NC

- Pin 055

-

Pin 176 A12

V_DDQ

A7

Pin 056

Pin 058

Pin 060

Pin 062

A11 - Pin 057

V_DD- Pin 059

-

Pin 178 V_DD

Pin 179 - A8

-

Pin 180 A6

A5

A4

A2

- Pin 061

- Pin 063

Pin 181 - V_DDQ

Pin 183 - A1

-

V_DDQ

V_DD

Pin 182 A3

- Pin 064

Pin 184 - V_DD

V_SS

- Pin 065

Pin 185 - CK0

Pin 187 - V_DD

Pin 189 - V_DD

Pin 191 - V_DDQ

Pin 193 - S0

-

Pin 186 CK0

V_SS

NC

- Pin 066

- Pin 068

V_DD- Pin 067

V_DD- Pin 069

BA0 - Pin 071

-

Pin 188 A0

A10/AP - Pin 070

Pin 190 - BA1

-

Pin 192 RAS

V_DDQ

CAS

Pin 072

Pin 074

Pin 076

Pin 078

Pin 080

Pin 082

Pin 084

Pin 086

WE

- Pin 073

-

Pin 194 V_DDQ

V_DDQ- Pin 075

ODT1 - Pin 077

Pin 195 - ODT0

Pin 197 - V_DD

Pin 199 - DQ36

Pin 201 - V_SS

Pin 203 - NC

Pin 205 - DQ38

Pin 207 - V_SS

Pin 209 - DQ45

Pin 211 - DM5

Pin 213 - V_SS

Pin 215 - DQ47

Pin 217 - DQ52

Pin 219 - V_SS

Pin 221 - CK2

Pin 223 - DM6

Pin 225 - V_SS

Pin 227 - DQ55

Pin 229 - DQ60

Pin 231 - V_SS

Pin 233 - NC

Pin 235 - DQ62

Pin 237 V_SS

Pin 239 SA0

-

Pin 196 NC/A13

NC/S1

V_DDQ

DQ32

V_SS

-

Pin 198 V_SS

V_SS

- Pin 079

-

Pin 200 DQ37

DQ33 - Pin 081

DQS4 - Pin 083

-

Pin 202 DM4

-

Pin 204 V_SS

DQS4

DQ34

V_SS

- Pin 085

-

Pin 206 DQ39

DQ35 - Pin 087

DQ40 - Pin 089

- Pin 088

Pin 208 - DQ44

Pin 210 - V_SS

Pin 212 - NC

DQ41 - Pin 090

DQS5 - Pin 092

V_SS

- Pin 091

DQS5 - Pin 093

DQ42 - Pin 095

V_SS

- Pin 094

Pin 214 - DQ46

-

Pin 216 V_SS

DQ43 - Pin 096

DQ48 - Pin 098

V_SS

- Pin 097

-

Pin 218 DQ53

DQ49 - Pin 099

SA2 - Pin 101

-

Pin 220 CK2

V_SS

Pin 100

Pin 102

Pin 104

Pin 106

Pin 108

Pin 110

Pin 112

Pin 114

Pin 116

-

Pin 222 V_SS

NC

V_SS

- Pin 103

-

Pin 224 NC

DQS6

V_SS

DQS6 - Pin 105

DQ50 - Pin 107

-

Pin 226 DQ54

-

Pin 228 V_SS

DQ51

DQ56

V_SS

- Pin 109

-

Pin 230 DQ61

DQ57 - Pin 111

DQS7 - Pin 113

-

Pin 232 DM7

-

Pin 234 V_SS

DQS7

DQ58

V_SS

- Pin 115

-

Pin 236 DQ63

DQ59 - Pin 117

SDA - Pin 119

- Pin 118

- Pin 120

Pin 238 V_DDSPD

Pin 240 SA1

SCL

MPPT0150

Figure 1

Pin Configuration UDIMM ×64 (240 Pin)

Data Sheet

17

Rev. 1.0, 2004-09

02182004-TRHM-8N4H

HYS[64/72]T256020HU–[3.7/5]–A

Unbuffered Double-Data-Rate-Two SDRAM Modules

Pin Configuration

VREF - Pin 001

DQ0 - Pin 003

V_SS- Pin 005

DQS0 - Pin 007

DQ2 - Pin 009

V_SS- Pin 011

DQ9 - Pin 013

DQS1 - Pin 015

V_SS- Pin 017

Pin 121 - V_SS

Pin 122 - DQ4

Pin 123 - DQ5

Pin 124 - V_SS

V_SS

- Pin 002

- Pin 004

DQ1

Pin 125 - DM0

Pin 126 - NC

DQS0 - Pin 006

Pin 127 - V_SS

V_SS

- Pin 008

- Pin 010

- Pin 012

- Pin 014

Pin 128 - DQ6

Pin 129 - DQ7

Pin 130 - V_SS

DQ3

DQ8

V^SS

Pin 131 - DQ12

Pin 132 - DQ13

Pin 133 - V_SS

Pin 134 - DM1

Pin 135 - NC

DQS1 - Pin 016

Pin 136 - NC

Pin 137 - CK1

Pin 138 - CK1

Pin 139 - V_SS

NC

- Pin 018

- Pin 020

NC

- Pin 019

-

V_SS

Pin 140 - DQ14

Pin 141 - DQ15

DQ10 Pin 021

-

Pin 142 V_SS

DQ11

DQ16

V_SS

Pin 022

-

V_SS

Pin 023

Pin 143 - DQ20

Pin 145 - V_SS

Pin 147 - NC

Pin 149 - DQ22

Pin 151 - V_SS

Pin 153 - DQ29

Pin 155 - DM3

Pin 157 - V_SS

Pin 159 - DQ31

Pin 161 - CB4

Pin 163 - V_SS

Pin 165 - NC

Pin 167 - CB6

Pin 169 - V_SS

Pin 171 - CKE1

Pin 173 - NC

Pin 175 - V_DDQ

Pin 177 - A9

-

Pin 144 DQ21

Pin 024

DQ17 - Pin 025

DQS2 - Pin 027

-

Pin 146 DM2

Pin 026

Pin 028

Pin 030

Pin 032

-

Pin 148 V_SS

DQS2

V_SS

- Pin 029

-

Pin 150 DQ23

DQ19 - Pin 031

DQ24 - Pin 033

-

V_SS

Pin 152 DQ28

DQ25 - Pin 034

DQS3 - Pin 036

Pin 154 - V_SS

Pin 156 - NC

Pin 158 - DQ30

Pin 160 - V_SS

V_SS

- Pin 035

DQS3 - Pin 037

DQ26 - Pin 039

V_SS

- Pin 038

DQ27 - Pin 040

V_SS

- Pin 041

-

Pin 162 CB5

CB0

V_SS

- Pin 042

CB1 - Pin 043

DQS8 - Pin 045

-

Pin 164 DM8

Pin 044

Pin 046

Pin 048

Pin 050

Pin 052

-

Pin 166 V_SS

DQS8

CB2

V_SS

- Pin 047

-

Pin 168 CB7

CB3 - Pin 049

V_DDQ- Pin 051

V_DD- Pin 053

-

Pin 170 V_DDQ

-

Pin 172 V_DD

CKE0

-

Pin 174 A14

NC/BA2 Pin 054

NC

- Pin 055

-

Pin 176 A12

V_DDQ

A7

Pin 056

Pin 058

Pin 060

Pin 062

A11 - Pin 057

V_DD- Pin 059

-

Pin 178 V_DD

Pin 179 - A8

-

Pin 180 A6

A5

A4

A2

- Pin 061

- Pin 063

Pin 181 - V_DDQ

Pin 183 - A1

-

V_DDQ

V_DD

Pin 182 A3

- Pin 064

Pin 184 - V_DD

V_SS

- Pin 065

Pin 185 - CK0

Pin 187 - V_DD

Pin 189 - V_DD

Pin 191 - V_DDQ

Pin 193 - S0

-

Pin 186 CK0

V_SS

NC

- Pin 066

- Pin 068

V_DD- Pin 067

V_DD- Pin 069

BA0 - Pin 071

-

Pin 188 A0

A10/AP - Pin 070

Pin 190 - BA1

-

Pin 192 RAS

V_DDQ

CAS

Pin 072

Pin 074

Pin 076

Pin 078

Pin 080

Pin 082

Pin 084

Pin 086

WE

- Pin 073

-

Pin 194 V_DDQ

V_DDQ- Pin 075

ODT1 - Pin 077

Pin 195 - ODT0

Pin 197 - V_DD

Pin 199 - DQ36

Pin 201 - V_SS

Pin 203 - NC

Pin 205 - DQ38

Pin 207 - V_SS

Pin 209 - DQ45

Pin 211 - DM5

Pin 213 - V_SS

Pin 215 - DQ47

Pin 217 - DQ52

Pin 219 - V_SS

Pin 221 - CK2

Pin 223 - DM6

Pin 225 - V_SS

Pin 227 - DQ55

Pin 229 - DQ60

Pin 231 - V_SS

Pin 233 - NC

Pin 235 - DQ62

Pin 237 V_SS

Pin 239 SA0

-

Pin 196 NC/A13

NC/S1

V_DDQ

DQ32

V_SS

-

Pin 198 V_SS

V_SS

- Pin 079

-

Pin 200 DQ37

DQ33 - Pin 081

DQS4 - Pin 083

-

Pin 202 DM4

-

Pin 204 V_SS

DQS4

DQ34

V_SS

- Pin 085

-

Pin 206 DQ39

DQ35 - Pin 087

DQ40 - Pin 089

- Pin 088

Pin 208 - DQ44

Pin 210 - V_SS

Pin 212 - NC

DQ41 - Pin 090

DQS5 - Pin 092

V_SS

- Pin 091

DQS5 - Pin 093

V_SS

- Pin 094

Pin 214 - DQ46

V_SS

- Pin 095

- Pin 097

-

Pin 216 V_SS

DQ43 - Pin 096

DQ48 - Pin 098

-

Pin 218 DQ53

DQ49 - Pin 099

SA2 - Pin 101

-

Pin 220 CK2

V_SS

Pin 100

Pin 102

Pin 104

Pin 106

Pin 108

Pin 110

Pin 112

Pin 114

Pin 116

-

Pin 222 V_SS

NC

V_SS

- Pin 103

-

Pin 224 NC

DQS6

V_SS

DQS6 - Pin 105

DQ50 - Pin 107

-

Pin 226 DQ54

-

Pin 228 V_SS

DQ51

DQ56

V_SS

- Pin 109

-

Pin 230 DQ61

DQ57 - Pin 111

DQS7 - Pin 113

-

Pin 232 DM7

-

Pin 234 V_SS

DQS7

DQ58

V_SS

- Pin 115

-

Pin 236 DQ63

DQ59 - Pin 117

SDA - Pin 119

- Pin 118

- Pin 120

Pin 238 V_DDSPD

Pin 240 SA1

SCL

MPPT0160

Figure 2

Pin Configuration UDIMM ×72 (240 Pin)

Data Sheet

18

Rev. 1.0, 2004-09

02182004-TRHM-8N4H

HYS[64/72]T256020HU–[3.7/5]–A

Unbuffered Double-Data-Rate-Two SDRAM Modules

Pin Configuration

2.1

Block Diagrams

BA0 - BA2

A0 - An

RAS

BA0 - BA2: SDRAMs D0 - D15

A0 - An: SDRAMs D0 - D15

RAS: SDRAMs D0 - D15

CAS: SDRAMs D0 - D15

WE: SDRAMs D0 - D15

CKE 0: SDRAMs D0 - D7

CKE 1: SDRAMs D8 - D15

ODT 0: SDRAMs D0 - D7

ODT 0: SDRAMs D8 - D15

CAS

WE

E0

V_DD,SPD

SCL

CKE 0

CKE 1

ODT 0

ODT 1

SCL

V_DD: SPD EEPROM E0

V

/V

SDA

A0

SDA

SA0

SA1

DD DDQ

V_DD/V_DDQ: SDRAMs D0 - D15

V_REF: SDRAMs D0 - D15

V

REF

A1

V

SS

V

: SDRAMs D0 - D15

A2

SS

WP

V_SS

S0

S1

D0

D8

D4

D12

D13

D14

D15

DM0

DQS0

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DM

CS

DM

CS

DM4

DQS4

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DM

CS

DM

CS

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D1

D2

D3

D9

D5

D6

D7

DM1

DQS1

DQ8

DM

CS

DM5

DQS5

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DM

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

D10

DM2

DQS2

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DM

DM6

DQS6

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DM

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D11

DM3

DQS3

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DM

DM7

DQS7

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DM

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

MPBT0130

Figure 3

Notes

Block Diagram Raw Card B UDIMM (×64, 2 Ranks, ×8)

1. DQ,DQS,DQS,DM,CB resistors are 22 Ω ± 5 %

2. BAn, An, RAS, CAS, WE resistors are 7.5 Ω ± 5 %

3. ODT,CKE,S capacitors are 24 pF

4. All CK lines have resistor termination between CK

an CK.

Table 8

Clock Signal Loads

Clock Input

CK0,CK0

CK1,CK1

CK2,CK3

SDRAMs

Note

4

6

Data Sheet

19

Rev. 1.0, 2004-09

02182004-TRHM-8N4H

HYS[64/72]T256020HU–[3.7/5]–A

Unbuffered Double-Data-Rate-Two SDRAM Modules

Pin Configuration

aw Card B ×72

CKE 0

CKE 0: SDRAMs D0 - D8

CKE 1: SDRAMs D9 - D17

ODT 0: SDRAMs D0 - D8

ODT 0: SDRAMs D9 - D17

BA0 - BA2

A0 - An

RAS

BA0 - BA2: SDRAMs D0 - D17

A0 - An: SDRAMs D0 - D17

RAS: SDRAMs D0 - D17

CAS: SDRAMs D0 - D17

WE: SDRAMs D0 - D17

CKE 1

ODT 0

ODT 1

CAS

WE

V

SS

S0

S1

D0

D8

D4

D5

D6

D7

D12

D13

D14

DM0

DQS0

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DM

CS

DM

CS

DM4

DM

CS

DM

CS

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS4

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D1

D2

D3

D8

D9

DM1

DQS1

DQ8

DM

DM5

DQS5

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DM

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

D10

D11

D17

DM2

DQS2

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DM

DM6

DQS6

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DM

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D15

DM3

DQS3

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DM

DM7

DQS7

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DM

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

E0

SCL

SDA

A0

SCL

DM8

DQS8

CB0

DM

SDA

SA0

SA1

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

A1

A2

CB1

WP

V_DD,SPD

V_SS

CB2

V_DD: SPD EEPROM E0

V_DD/V_DDQ: SDRAMs D0 - D17

V_REF: SDRAMs D0 - D17

V_SS: SDRAMs D0 - D17

CB3

V_DD/V_DDQ

CB4

V

REF

CB5

V

SS

CB6

CB7

MPBT0140

Figure 4

Notes

Block Diagram Raw Card B UDIMM (×72, 2 Ranks, ×8)

1. DQ,DQS,DQS,DM,CB resistors are 22 Ω ± 5 %

2. BAn, An, RAS, CAS, WE resistors are 7.5 Ω ± 5 %

3. ODT,CKE, S capacitors are 24 pF

4. All CK lines have resistor termination between CK

and CK.

Table 9

Clock Signal Loads

Clock Input

CK0,CK0

CK1,CK1

CK2,CK3

SDRAMs

Note

6

Data Sheet

20

Rev. 1.0, 2004-09

02182004-TRHM-8N4H

HYS[64/72]T256020HU–[3.7/5]–A

Unbuffered Double-Data-Rate-Two SDRAM Modules

I_DDSpecifications and Conditions

3

I_DDSpecifications and Conditions

Table 10

Parameter

I

_DDMeasurement Conditions^1)2)3)4)5)6)

Symbol

Operating Current 0

I_DD0

One bank Active - Precharge; t_CK= t_CK.MIN, t_RC= t_RC.MIN, t_RAS= t_RAS.MIN, CKE is HIGH, CS is HIGH

between valid commands. Address and control inputs are SWITCHING, Databus inputs are

SWITCHING^.

Operating Current 1

I_DD1

One bank Active - Read - Precharge; I_OUT= 0 mA, BL = 4, t_CK= t_CK.MIN, t_RC= t_RC.MIN, t_RAS= t_RAS.MIN

,

t

_RCD= t_RCD.MIN, AL = 0, CL = CL_.MIN; CKE is HIGH, CS is HIGH between valid commands. Address and

control inputs are SWITCHING, Databus inputs are SWITCHING.

Precharge Power-Down Current

I_DD2P

I_DD2N

Other control and address inputs are STABLE, Data bus inputs are FLOATING^.

Precharge Standby Current

All banks idle; CS is HIGH; CKE is HIGH; t_CK= t_CK.MIN; Other control and address inputs are

SWITCHING, Data bus inputs are SWITCHING.

Precharge Quiet Standby Current

I_DD2Q

All banks idle; CS is HIGH; CKE is HIGH; t_CK= t_CK.MIN; Other control and address inputs are STABLE,

Data bus inputs are FLOATING.

Active Power-Down Current

I_DD3P(0)

I_DD3P(1)

I_DD3N

All banks open; t_CK= t_CK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus

inputs are FLOATING. MRS A12 bit is set to LOW (Fast Power-down Exit);

Active Power-Down Current

All banks open; t_CK= t_CK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus

inputs are FLOATING. MRS A12 bit is set to HIGH (Slow Power-down Exit);

Active Standby Current

Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL_.MIN; t_CK= t_CK.MIN

;

t

_RAS= t_RAS.MAX, t_RP= t_RP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address inputs are

SWITCHING; Data Bus inputs are SWITCHING; I_OUT= 0 mA.

Operating Current

I_DD4R

Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL_.MIN; t_CK= t_CK.MIN

t

_RAS= t_RAS.MAX., t_RP= t_RP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address inputs are

SWITCHING; Data Bus inputs are SWITCHING; I_OUT= 0 mA.

Operating Current

I_DD4W

Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CL_.MIN; t_CK= t_CK.MIN

;

t

_RAS= t_RAS.MAX., t_RP= t_RP.MAX; CKE is HIGH, CS is HIGH between valid commands. Address inputs are

SWITCHING; Data Bus inputs are SWITCHING;

Burst Refresh Current

I_DD5B

t

_CK= t_CKmin., Refresh command every t_RFC= t_RFC.MINinterval, CKE is HIGH, CS is HIGH between valid

commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.

Distributed Refresh Current

I_DD5D

t

_CK= t_CKmin., Refresh command every t_RFC= t_REFIinterval, CKE is LOW and CS is HIGH between valid

commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.

Data Sheet

21

Rev. 1.0, 2004-09

02182004-TRHM-8N4H

HYS[64/72]T256020HU–[3.7/5]–A

Unbuffered Double-Data-Rate-Two SDRAM Modules

I_DDSpecifications and Conditions

Table 10

I

_DDMeasurement Conditions^1)2)3)4)5)6)

Parameter

Symbol

Self-Refresh Current

I_DD6

CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING,

Data bus inputs are FLOATING. I_DD6current values are guaranteed up to T_CASEof 85 °C max.

All Bank Interleave Read Current

I_DD7

All banks are being interleaved at minimum t_RCwithout violating t_RRDusing a burst length of 4. Control

and address bus inputs are STABLE during DESELECTS. I_out= 0 mA.

1) V_DDQ= 1.8 V ± 0.1 V; V_DD= 1.8 V ± 0.1 V

2) I_DDspecifications are tested after the device is properly initialized and I_DDparameter are specified with ODT disabled.

3) Definitions for I_DD

:

LOW is defined as V_IN≤ V_IL(ac).MAX, HIGH is defined as V_IN≥ V_IH(ac).MIN

STABLE is defined as: inputs are stable at a HIGH or LOW level

FLOATING is defined as: inputs are V_REF= V_DDQ/2

SWITCHING is defined as: inputs are changing between HIGH and LOW every other clock (once per 2 cycles)

for address and control signals, and inputs changing between HIGH and LOW every other data transfer

(once per cycle) for DQ signals not including mask or strobes.

4) I_DD1, I_DD4Rand I_DD7current measurements are defined with the outputs disabled (I_OUT= 0 mA). To achieve this on module

level the output buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to

HIGH.

5) For two rank modules: for all active current measurements the other rank is in Precharge Power-Down Mode I_DD2P

6) For details and notes see the relevant INFINEON component data sheet

Data Sheet

22

Rev. 1.0, 2004-09

02182004-TRHM-8N4H

HYS[64/72]T256020HU–[3.7/5]–A

Unbuffered Double-Data-Rate-Two SDRAM Modules

I_DDSpecifications and Conditions

Table 11

Product Type

I_DDSpecification for HYS64T256020HU–3.7–A

HYS64T256020HU–3.7–A

HYS72T256020HU–3.7–A

Unit Notes¹⁾

Organization

2 GB

2 Ranks

×64

2 GB

2 Ranks

×72

–37

Symbol

I_DD0

I_DD1

I_DD2P

I_DD2N

Max.

640

720

80

740

510

270

100

800

920

960

1520

110

80

Max.

720

810

90

830

580

310

110

900

1040

1080

1710

130

90

1890

2)

mA

2)

3)

I_DD2Q

3)

I_{DD3P( MRS = 0)}

I_{DD3P( MRS = 1)}

I_DD3N

I_DD4R

I_DD4W

I_DD5B

I_DD5D

I_DD6

I_DD7

3)

2)

3)

2)

1680

1) Calculated values from component data. ODT disabled. I_DD1, I_DD4Rand I_DD7are defined with the outputs disabled

2) The other rank is in I_DD2PPre charge Power-Down Standby Current mode

3) Both ranks are in the same I_DDcurrent mode

Data Sheet

23

Rev. 1.0, 2004-09

02182004-TRHM-8N4H

HYS[64/72]T256020HU–[3.7/5]–A

Unbuffered Double-Data-Rate-Two SDRAM Modules

I_DDSpecifications and Conditions

Table 12

Product Type

I_DDSpecification for HYS64T256020HU–5–A

HYS64T256020HU–5–A

HYS72T256020HU–5–A

Unit

Notes¹⁾

Organization

2 GB

2 Ranks

×64

–5

2 GB

2 Ranks

×72

–5

Symbol

I_DD0

I_DD1

I_DD2P

I_DD2N

Max.

600

680

80

560

450

210

80

640

760

800

1480

110

80

Max.

680

770

90

630

500

230

90

720

860

900

1670

130

90

2)

3)

2)

3)

2)

mA

I_DD2Q

I_{DD3P( MRS = 0)}

I_{DD3P( MRS = 1)}

I_DD3N

I_DD4R

I_DD4W

I_DD5B

I_DD5D

I_DD6

I_DD7

1600

1800

1) Calculated values from component data. ODT disabled. I_DD1, I_DD4Rand I_DD7are defined with the outputs disabled

2) The other rank is in I_DD2PPre charge Power-Down Standby Current mode

3) Both ranks are in the same I_DDcurrent mode

Data Sheet

24

Rev. 1.0, 2004-09

02182004-TRHM-8N4H

HYS[64/72]T256020HU–[3.7/5]–A

Unbuffered Double-Data-Rate-Two SDRAM Modules

I_DDSpecifications and Conditions

3.1

I_DDTest Conditions

For testing the I_DDparameters, the following timing parameters are used:

Table 13

I_DDMeasurement Test Conditions

Parameter

Symbol

–3.7

–5

Unit

PC2-4200-4-4-4 PC2-3200-3-3-3

CAS Latency

Clock Cycle Time

CL_(IDD)

t_CK(IDD)

t_RCD(IDD)

t_RC(IDD)

4

3

5

15

55

7.5

10

40

70000

15

127.5

7.8

t_CK

ns

µs

3.75

15

60

7.5

10

Active to Read or Write delay

Active to Active / Auto-Refresh command period

Active bank A to Active bank B command delay ×8¹⁾t_RRD(IDD)

×16²⁾t_RRD(IDD)

Active to Precharge Command

Precharge Command Period

Auto-Refresh to Active / Auto-Refresh command period t_RFC(IDD)

Average periodic Refresh interval

t_RAS.MIN(IDD)45

t_RAS.MAX(IDD)70000

t_RP(IDD)

15

127.5

7.8

t_REFI

1) For modules based on ×8 components

2) For modules based on ×16 components

3.2

ODT (On Die Termination) Current

The ODT function adds additional current consumption to the DDR2 SDRAM when enabled by the EMRS(1).

Depending on address bits A6 & A2 in the EMRS(1) a “weak” or “strong” termination can be selected. The current

consumption for any terminated input pin, depends on the input pin is in tristate or driving 0 or 1, as long a ODT

is enabled during a given period of time.

Table 14

Parameter

ODT current per terminated pin:

Symbol min.

Type.

max.

Unit

EMRS(1)

State

Enabled ODT current per DQ

added IDDQ current for ODT enabled;

ODT is HIGH; Data Bus inputs are

FLOATING

I_ODTO

5

2.5

6

3

7.5

3.75

mA/DQ A6 = 0, A2 = 1

mA/DQ A6 = 1, A2 = 0

Active ODT current per DQ

I_ODTT

10

5

12

6

15

7.5

mA/DQ A6 = 0, A2 = 1

mA/DQ A6 = 1, A2 = 0

added IDDQ current for ODT enabled;

ODT is HIGH; worst case of Data Bus inputs

are STABLE or SWITCHING.

Note:For power consumption calculations the ODT duty cycle has to be taken into account

Data Sheet

25

Rev. 1.0, 2004-09

02182004-TRHM-8N4H

HYS[64/72]T256020HU–[3.7/5]–A

Unbuffered Double-Data-Rate-Two SDRAM Modules

Electrical Characteristics

4

Electrical Characteristics

4.1

Operating Conditions

Table 15

Absolute Maximum Ratings

Parameter

Symbol

Limit Values

Unit Note/Test Condition

min.

V_IN, V_OUT– 0.5

max.

2.3

95

1)

Voltage on any pins relative to V_SS

Voltage on V_DDrelative to V_SS

Voltage on V_{DD Q}relative to V_SS

Storage Humidity (without condensation)

V

%

1)

V_DD

– 1.0

– 0.5

5

1)

V_DDQ

H_STG

1)

1) Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This

is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the

operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended

periods may affect reliability.

Table 16

Operating Conditions

Parameter

Symbol

Limit Values

Unit Notes

min.

0

max.

+55

DIMM Module Operating Temperature Range (ambient)

DRAM Component Case Temperature Range

Storage Temperature

Barometric Pressure (operating & storage)

Operating Humidity (relative)

T_OPR

T_CASE

T_STG

PBar

H_OPR

°C

kPa

1)2)3)4)

0

+95

– 50

+69

10

+100

+105

90

5)

%

1) DRAM Component Case Temperature is the surface temperature in the center on the top side of any of the DRAMs

2) Within the DRAM Component Case Temperature range all DRAM specification will be supported.

3) Above 85°C DRAM case temperature the Auto-Refresh command interval has to be reduced to t_REFI= 3.9 µs.

4) Self-Refresh period is hard-coded in the DRAMs and therefore it is imperative that the system ensures the DRAM is below

85°C case temperature before initiating self-refresh operation.

5) Up to 3000 m.

Table 17

Supply Voltage Levels and DC Operating Conditions

Parameter

Symbol

Limit Values

Unit

Notes

min.

1.7

nom.

1.8

max.

1.9

Device Supply Voltage

Output Supply Voltage

Input Reference Voltage

SPD Supply Voltage

DC Input Logic High

DC Input Logic Low

V_DD

V_DDQ

V_REF

V_DDSPD

V_{IH (DC)}

V_{IL (DC)}

V

-

1)

1.7

0.49 x V_DDQ

1.7

1.8

0.5 x V_DDQ

–

1.9

0.51 x V_DDQ

3.6

2)

V

_REF+ 0.125

V

_DDQ+ 0.3

_REF– 0.125

– 0.30

1) Under all conditions, V_DDQmust be less than or equal to V_DD

2) Peak to peak AC noise on V_REFmay not exceed ± 2% V_REF(DC).V_REFis also expected to track noise variations

in V_DDQ

.

Data Sheet

26

Rev. 1.0, 2004-09

02182004-TRHM-8N4H

HYS[64/72]T256020HU–[3.7/5]–A

Unbuffered Double-Data-Rate-Two SDRAM Modules

Electrical Characteristics

Table 18

Speed Grade Definition Speed Bins

Speed Grade

DDR2–533C

–3.7

4–4–4

DDR2–400B

–5

3–3–3

Unit

Notes

IFX Sort Name

CAS-RCD-RP latencies

Parameter

t_CK

—

ns

Symbol

t_CK

Min.

5

Max.

8

Min.

5

Max.

8

1)2)3)4)

1)2)3)4)5)

1)2)3)4)

Clock Frequency

@ CL = 3

@ CL = 4

@ CL = 5

3.75

45

8

5

8

t_CK

5

8

Row Active Time

Row Cycle Time

RAS-CAS-Delay

Row Precharge Time

t_RAS

t_RC

t_RCD

t_RP

70000

—

40

55

15

70000

—

60

15

—

15

—

1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a

differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are

further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) only.

2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS,

RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode

3) Inputs are not recognized as valid until V_REFstabilizes. During the period before V_REFstabilizes, CKE = 0.2 x V_DDQis

recognized as low.

4) The output timing reference voltage level is V_TT.

5) t_RAS.MAXis calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is

equal to 9 x t_REFI

.

Data Sheet

27

Rev. 1.0, 2004-09

02182004-TRHM-8N4H

HYS[64/72]T256020HU–[3.7/5]–A

Unbuffered Double-Data-Rate-Two SDRAM Modules

Electrical Characteristics

Table 19

Parameter

Timing Parameter by Speed Grade - DDR2-400B & DDR2-533C

Symbol –3.7

–5

Unit Notes¹⁾

DDR2–533 4–4–4

DDR2–400 3–3–3

Min.

Max.

Min.

Max.

DQ output access time from CK / t_AC

–500

+500

–600

+600

ps

CK

CAS A to CAS B command period t_CCD

2

0.45

3

—

0.55

—

2

0.45

3

—

0.55

—

t_CK

CK, CK high-level width

t_CH

CKE minimum high and low pulse t_CKE

width

CK, CK low-level width

t_CL

t_DAL

0.45

WR + t_RP

0.55

—

0.45

WR + t_RP

0.55

—

t_CK

Auto-Precharge write recovery +

precharge time

Minimum time clocks remain ON

after CKE asynchronously drops

LOW

t_DELAY

t_IS+ t_CK

+

––

t_IS+ t_CK

+

—

ns

t_IH

DQ and DM input hold time

t_DH(base) 225

––

275

25

––

ps

t_CK

ps

t_CK

ps

(differential data strobe)

DQ and DM input hold time (single t_DH1(base) –25

—

ended data strobe)

DQ and DM input pulse width (each t_DIPW

0.35

–450

0.35

—

0.35

–500

0.35

—

input)

DQS output access time from CK / t_DQSCK

+450

—

+500

—

CK

DQS input low (high) pulse width t_DQSL,H

(write cycle)

DQS-DQ skew (for DQS &

t_DQSQ

t_DQSS

t_DS(base) 100

_DS1(base) –25

300

350

associated DQ signals)

Write command to 1st DQS

latching transition

WL – 0.25 WL + 0.25 WL – 0.25 WL + 0.25 t_CK

DQ and DM input setup time

—

150

25

—

ps

t_CK

(differential data strobe)

DQ and DM input setup time

(single ended data strobe)

t

DQS falling edge hold time from

t_DSH

0.2

CK (write cycle)

DQS falling edge to CK setup time t_DSS

(write cycle)

2)3)

4)

Four Activate Window period

t_FAW

37.5

50

—

37.5

50

—

ns

Clock half period

Data-out high-impedance time

from CK / CK

t_HP

t_HZ

MIN. (t_CL,t_CH)

t_AC.MAX

MIN. (t_CL,t_CH)

—

t_AC.MAX

ps

Address and control input hold time t_IH(base) 375

—

475

0.6

—

ps

t_CK

Address and control input pulse

t_IPW

0.6

width

(each input)

Data Sheet

28

Rev. 1.0, 2004-09

02182004-TRHM-8N4H

HYS[64/72]T256020HU–[3.7/5]–A

Unbuffered Double-Data-Rate-Two SDRAM Modules

Electrical Characteristics

Table 19

Parameter

Timing Parameter by Speed Grade - DDR2-400B & DDR2-533C (cont’d)

Symbol –3.7

–5

Unit Notes¹⁾

DDR2–533 4–4–4

DDR2–400 3–3–3

Min.

Max.

Min.

Max.

Address and control input setup

time

t_IS(base) 250

—

350

—

ps

DQ low-impedance time from CK / t_LZ(DQ)

2 × t_AC.MINt_AC.MAX

CK

DQS low-impedance from CK / CK t_LZ(DQS)

t_AC.MIN

2

t_AC.MAX

—

t_AC.MIN

2

t_AC.MAX

—

ps

t_CK

Mode register set command cycle t_MRD

time

OCD drive mode output delay

Data output hold time from DQS

Data hold skew factor

t_OIT

t_QH

t_QHS

0

12

—

400

7.8

3.9

—

0

12

—

450

7.8

3.9

—

ns

t

_HP– t_QHS

t

_HPQ– t_QHS

—

127.5

—

127.5

ps

µs

ns

5)

Average periodic refresh Interval t_REFI

6)

Auto-Refresh to Active/Auto-

Refresh command period

t_RFC

Precharge-All (8 banks) command t_RP

15 + 1t_CK

—

15 + 1t_CK

—

ns

period

Read preamble

Read postamble

t_RPRE

t_RPST

t_RRD

0.9

0.40

7.5

10

1.1

0.60

—

0.9

0.40

7.5

10

1.1

0.60

—

t_CK

ns

Active bank A to Active bank B

command period

Internal Read to Precharge

command delay

t_RTP

7.5

Write preamble

Write postamble

t_WPRE

t_WPST

t_WR

0.35xt_CK

0.40

15

—

0.60

—

0.35xt_CK

0.40

15

—

0.60

—

t_CK

ns

Write recovery time for write

without Auto-Precharge

Write recovery time for write with

Auto-Precharge

WR

t

_WR/t_CK

t

_WR/t_CK

t_CK

ns

Internal Write to Read command

t_WTR

t_XARD

7.5

2

—

10

2

—

delay

Exit power down to any valid

command

t_CK

(other than NOP or Deselect)

Exit active power-down mode to

Read command (slow exit, lower

power)

Exit precharge power-down to any t_XP

valid command (other than NOP or

Deselect)

t_XARDS

6 – AL

2

—

6 – AL

2

—

t_CK

Exit Self-Refresh to non-Read

t_XSNR

t

_RFC+10

—

t

_RFC+10

—

ns

command

Exit Self-Refresh to Read

command

t_XSRD

200

t_CK

Data Sheet

29

Rev. 1.0, 2004-09

02182004-TRHM-8N4H

HYS[64/72]T256020HU–[3.7/5]–A

Unbuffered Double-Data-Rate-Two SDRAM Modules

Electrical Characteristics

1) For details and notes see the relevant INFINEON component data sheet

2) ×4 & ×8 (1k page size)

3) 8 bank device Sequential Activation Restriction. No more than 4 banks may be activated in a rolling t_FAWwindow.

4) ×16 (2k page size), not on 256 Mbit component

5) 0 ≤ T_CASE≤ 85 °C

6) 85 °C < T_CASE≤ 95 °C

Table 20

ODT AC Electrical Characteristics and Operating Conditions

Symbol Parameter / Condition

Values

Min.

2

Unit

Notes

Max.

2

t_AOND

t_AON

ODT turn-on delay

ODT turn-on

t_CK

ns

1)

t_AC.MIN

t_AC.MAX+ 1 ns

t_AONPD

t_AOFD

t_AOF

t_AOFPD

t_ANPD

t_AXPD

ODT turn-on (Power-Down Modes)

ODT turn-off delay

ODT turn-off

ODT turn-off (Power-Down Modes)

ODT to Power Down Mode Entry Latency 3

ODT Power Down Exit Latency

t

_AC.MIN+ 2 ns 2 t_CK+ t_AC.MAX+ 1 ns ns

2.5

t_AC.MIN

2.5

t_CK

2)

t_AC.MAX+ 0.6 ns

ns

t_AC.MIN+ 2 ns 2.5 t_CK+t_AC.MAX+ 1 ns ns

—

t_CK

8

1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time

max is when the ODT resistance is fully on. Both are measure from t_AOND

2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high

impedance. Both are measured from t_AOFD

.

Data Sheet

30

Rev. 1.0, 2004-09

02182004-TRHM-8N4H

HYS[64/72]T256020HU–[3.7/5]–A

Unbuffered Double-Data-Rate-Two SDRAM Modules

SPD Codes

5

SPD Codes

Table 21

SPD Codes for HYS64T256020HU–3.7–A

Product Type

Organization

2 GByte

×64

2 GByte

×72

2 Ranks (×8)

Label Code

PC2–4200U–444 PC2–4200E–444

JEDEC SPD Revision

Rev. 1.1

HEX

80

08

Rev. 1.1

HEX

80

08

Byte#

0

Description

Programmed SPD Bytes in EEPROM

Total number of Bytes in EEPROM

Memory Type (DDR2)

1

2

3

4

5

6

Number of Row Addresses

Number of Column Addresses

DIMM Rank and Stacking Information

Data Width

0E

0A

61

0E

0A

61

40

48

7

Not used

00

8

Interface Voltage Level

05

9

t

_CK@ CL_max(Byte 18) [ns]

_ACSDRAM @ CL_max(Byte 18) [ns]

3D

50

00

82

08

00

0C

08

38

00

02

00

01

3D

50

3D

50

02

82

08

00

0C

08

38

00

02

00

01

3D

50

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

Error Correction Support (non-ECC, ECC)

Refresh Rate and Type

Primary SDRAM Width

Error Checking SDRAM Width

Not used

Burst Length Supported

Number of Banks on SDRAM Device

Supported CAS Latencies

DIMM Mechanical Characteristics

DIMM Type Information

DIMM Attributes

Component Attributes

t

_CK@ CL_max-1 (Byte 18) [ns]

_ACSDRAM @ CL_max-1 [ns]

_CK@ CL_max-2 (Byte 18) [ns]

Data Sheet

31

Rev. 1.0, 2004-09

02182004-TRHM-8N4H

HYS[64/72]T256020HU–[3.7/5]–A

Unbuffered Double-Data-Rate-Two SDRAM Modules

SPD Codes

Table 21

SPD Codes for HYS64T256020HU–3.7–A (cont’d)

Product Type

Organization

2 GByte

×64

2 GByte

×72

2 Ranks (×8)

Label Code

PC2–4200U–444 PC2–4200E–444

JEDEC SPD Revision

Rev. 1.1

HEX

60

3C

1E

3C

2D

01

25

37

10

22

3C

1E

00

3C

7F

80

1E

28

00

51

Rev. 1.1

HEX

60

3C

1E

3C

2D

01

25

37

10

22

3C

1E

00

3C

7F

80

1E

28

00

51

Byte#

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

Description

t

_ACSDRAM @ CL_max-2 [ns]

_RP.min[ns]

_RRD.min[ns]

_RCD.min[ns]

_RAS.min[ns]

Module Density per Rank

t

_AS.minand t_CS.min[ns]

_AH.minand t_CH.min[ns]

_DS.min[ns]

_DH.min[ns]

_WR.min[ns]

_WTR.min[ns]

_RTP.min[ns]

Analysis Characteristics

t

_RCand t_RFCExtension

_RC.min[ns]

_RFC.min[ns]

_CK.max[ns]

_DQSQ.max[ns]

_QHS.max[ns]

PLL Relock Time

T

_CASE.maxDelta / ∆T_4R4WDelta

Psi(T-A) DRAM

∆T₀(DT0)

∆T_2N(DT2N, UDIMM) or ∆T_{2Q (}(DT2Q, RDIMM)

∆T_2P(DT2P)

∆T_3N(DT3N)

60

36

2A

1E

1F

60

36

2A

1E

1F

∆T_3P.fast(DT3P fast)

Data Sheet

32

Rev. 1.0, 2004-09

02182004-TRHM-8N4H

HYS[64/72]T256020HU–[3.7/5]–A

Unbuffered Double-Data-Rate-Two SDRAM Modules

SPD Codes

Table 21

SPD Codes for HYS64T256020HU–3.7–A (cont’d)

Product Type

Organization

2 GByte

×64

2 GByte

×72

2 Ranks (×8)

Label Code

PC2–4200U–444 PC2–4200E–444

JEDEC SPD Revision

Rev. 1.1

HEX

16

32

22

Rev. 1.1

HEX

16

32

22

Byte#

54

Description

∆T_3P.slow(DT3P slow)

∆T_4R(DT4R) / ∆T_{4R4W S}Sign (DT4R4W)

∆T_5B(DT5B)

55

56

57

∆T₇(DT7)

25

58

Psi(ca) PLL

00

59

Psi(ca) REG

00

60

∆T_PLL(DTPLL)

00

61

62

∆T_REG(DTREG) / Toggle Rate

SPD Revision

00

11

00

11

63

64

65 - 71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

Checksum of Bytes 0-62

JEDEC ID Code of Infineon (1)

JEDEC ID Code of Infineon (2 - 8)

Module Manufacturer Location

Product Type, Char 1

Product Type, Char 2

Product Type, Char 3

Product Type, Char 4

Product Type, Char 5

Product Type, Char 6

Product Type, Char 7

Product Type, Char 8

Product Type, Char 9

Product Type, Char 10

Product Type, Char 11

Product Type, Char 12

Product Type, Char 13

Product Type, Char 14

Product Type, Char 15

48

C1

00

xx

36

34

54

32

35

36

30

32

30

48

55

33

2E

37

5A

C1

00

xx

37

32

54

32

35

36

30

32

30

48

55

33

2E

37

86

87

41

Data Sheet

33

Rev. 1.0, 2004-09

02182004-TRHM-8N4H

HYS[64/72]T256020HU–[3.7/5]–A

Unbuffered Double-Data-Rate-Two SDRAM Modules

SPD Codes

Table 21

SPD Codes for HYS64T256020HU–3.7–A (cont’d)

Product Type

Organization

2 GByte

×64

2 GByte

×72

2 Ranks (×8)

Label Code

PC2–4200U–444 PC2–4200E–444

JEDEC SPD Revision

Rev. 1.1

HEX

20

1x

xx

Rev. 1.1

HEX

20

1x

xx

Byte#

88

Description

Product Type, Char 16

Product Type, Char 17

Product Type, Char 18

Module Revision Code

Test Program Revision Code

Module Manufacturing Date Year

Module Manufacturing Date Week

Module Serial Number (1 - 4)

Not used

89

90

91

92

93

94

95 - 98

99 -127

xx

00

xx

00

Data Sheet

34

Rev. 1.0, 2004-09

02182004-TRHM-8N4H

HYS[64/72]T256020HU–[3.7/5]–A

Unbuffered Double-Data-Rate-Two SDRAM Modules

SPD Codes

Table 22

SPD Codes for HYS64T256020HU–5–A

Product Type

Organization

2 GByte

×64

2 GByte

×72

2 Ranks (×8)

Label Code

PC2–3200U–333 PC2–3200E–333

JEDEC SPD Revision

Rev. 1.1

HEX

80

08

Rev. 1.1

HEX

80

08

Byte#

0

Description

Programmed SPD Bytes in EEPROM

Total number of Bytes in EEPROM

Memory Type (DDR2)

1

2

3

4

5

6

Number of Row Addresses

Number of Column Addresses

DIMM Rank and Stacking Information

Data Width

0E

0A

61

0E

0A

61

40

48

7

Not used

00

8

Interface Voltage Level

05

9

t

_CK@ CL_max(Byte 18) [ns]

_ACSDRAM @ CL_max(Byte 18) [ns]

50

60

00

82

08

00

0C

08

38

00

02

00

01

50

60

50

60

02

82

08

00

0C

08

38

00

02

00

01

50

60

50

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

Error Correction Support (non-ECC, ECC)

Refresh Rate and Type

Primary SDRAM Width

Error Checking SDRAM Width

Not used

Burst Length Supported

Number of Banks on SDRAM Device

Supported CAS Latencies

DIMM Mechanical Characteristics

DIMM Type Information

DIMM Attributes

Component Attributes

t

_CK@ CL_max-1 (Byte 18) [ns]

_ACSDRAM @ CL_max-1 [ns]

_CK@ CL_max-2 (Byte 18) [ns]

_ACSDRAM @ CL_max-2 [ns]

_RP.min[ns]

60

3C

60

3C

Data Sheet

35

Rev. 1.0, 2004-09

02182004-TRHM-8N4H

HYS[64/72]T256020HU–[3.7/5]–A

Unbuffered Double-Data-Rate-Two SDRAM Modules

SPD Codes

Table 22

SPD Codes for HYS64T256020HU–5–A (cont’d)

Product Type

Organization

2 GByte

×64

2 GByte

×72

2 Ranks (×8)

Label Code

PC2–3200U–333 PC2–3200E–333

JEDEC SPD Revision

Rev. 1.1

HEX

1E

3C

28

01

35

47

15

27

3C

28

1E

00

37

7F

80

23

2D

00

51

60

32

20

1E

18

12

2A

Rev. 1.1

HEX

1E

3C

28

01

35

47

15

27

3C

28

1E

00

37

7F

80

23

2D

00

51

60

32

20

1E

18

12

2A

Byte#

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

Description

t

_RRD.min[ns]

_RCD.min[ns]

_RAS.min[ns]

Module Density per Rank

t

_AS.minand t_CS.min[ns]

_AH.minand t_CH.min[ns]

_DS.min[ns]

_DH.min[ns]

_WR.min[ns]

_WTR.min[ns]

_RTP.min[ns]

Analysis Characteristics

t

_RCand t_RFCExtension

_RC.min[ns]

_RFC.min[ns]

_CK.max[ns]

_DQSQ.max[ns]

_QHS.max[ns]

PLL Relock Time

T

_CASE.maxDelta / ∆T_4R4WDelta

Psi(T-A) DRAM

∆T₀(DT0)

∆T_2N(DT2N, UDIMM) or ∆T_{2Q (}(DT2Q, RDIMM)

∆T_2P(DT2P)

∆T_3N(DT3N)

∆T_3P.fast(DT3P fast)

∆T_3P.slow(DT3P slow)

∆T_4R(DT4R) / ∆T_{4R4W S}Sign (DT4R4W)

Data Sheet

36

Rev. 1.0, 2004-09

02182004-TRHM-8N4H

HYS[64/72]T256020HU–[3.7/5]–A

Unbuffered Double-Data-Rate-Two SDRAM Modules

SPD Codes

Table 22

SPD Codes for HYS64T256020HU–5–A (cont’d)

Product Type

Organization

2 GByte

×64

2 GByte

×72

2 Ranks (×8)

Label Code

PC2–3200U–333 PC2–3200E–333

JEDEC SPD Revision

Rev. 1.1

HEX

21

Rev. 1.1

HEX

21

Byte#

56

Description

∆T_5B(DT5B)

57

∆T₇(DT7)

24

58

Psi(ca) PLL

00

59

Psi(ca) REG

00

60

∆T_PLL(DTPLL)

00

61

62

∆T_REG(DTREG) / Toggle Rate

SPD Revision

00

11

00

11

63

64

65 - 71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

Checksum of Bytes 0-62

JEDEC ID Code of Infineon (1)

JEDEC ID Code of Infineon (2 - 8)

Module Manufacturer Location

Product Type, Char 1

Product Type, Char 2

Product Type, Char 3

Product Type, Char 4

Product Type, Char 5

Product Type, Char 6

Product Type, Char 7

Product Type, Char 8

Product Type, Char 9

Product Type, Char 10

Product Type, Char 11

Product Type, Char 12

Product Type, Char 13

Product Type, Char 14

Product Type, Char 15

Product Type, Char 16

Product Type, Char 17

99

C1

00

xx

36

34

54

32

35

36

30

32

30

48

55

35

41

AB

C1

00

xx

37

32

54

32

35

36

30

32

30

48

55

35

41

86

87

88

89

20

Data Sheet

37

Rev. 1.0, 2004-09

02182004-TRHM-8N4H

HYS[64/72]T256020HU–[3.7/5]–A

Unbuffered Double-Data-Rate-Two SDRAM Modules

SPD Codes

Table 22

SPD Codes for HYS64T256020HU–5–A (cont’d)

Product Type

Organization

2 GByte

×64

2 GByte

×72

2 Ranks (×8)

Label Code

PC2–3200U–333 PC2–3200E–333

JEDEC SPD Revision

Rev. 1.1

HEX

20

1x

xx

00

Rev. 1.1

HEX

20

1x

xx

00

Byte#

90

Description

Product Type, Char 18

Module Revision Code

Test Program Revision Code

Module Manufacturing Date Year

Module Manufacturing Date Week

Module Serial Number (1 - 4)

Not used

91

92

93

94

95 - 98

99 - 127

Data Sheet

38

Rev. 1.0, 2004-09

02182004-TRHM-8N4H

HYS[64/72]T256020HU–[3.7/5]–A

Unbuffered Double-Data-Rate-Two SDRAM Modules

Package Outlines

6

Package Outlines

0.1

1.27

133.35

0.4

0.1

128.95

C

1.)

1

120

0.1

4

0.1

2.5

5

4 MAX.

0.1

63

55

A

0.1

1.5

121

240

1.)

B

3 MIN.

Detail of contacts

1

0.2

0.8

0.1 A B C

Burr max. 0.4 allowed

GLD09653

Figure 5

Package Outline Raw Card B L-DIM-240-2

Note

1. The chip is only found on ECC modules.

Data Sheet

39

Rev. 1.0, 2004-09

02182004-TRHM-8N4H

HYS[64/72]T256020HU–[3.7/5]–A

Unbuffered Double-Data-Rate-Two SDRAM Modules

Product Type Nomenclature (DDR2 DRAMs and DIMMs)

7

Product Type Nomenclature (DDR2 DRAMs and DIMMs)

Infineon’s nomenclature uses simple coding combined with some proprietary coding. Table 23 provides examples

for module and component product type number as well as the field number. The detailed field description together

with possible values and coding explanation is listed for modules in Table 24 and for components in Table 25.

Table 23

Example for

Nomenclature Fields and Examples

Field Number

1

HYS

HYB

2

64

18

3

T

4

128

1G

5

0

16

6

2

7

0

8

K

A

9

M

C

10

–5

11

–A

Micro-DIMM

DDR2 DRAM

1) Multiplying “Memory Density per I/O” with “Module Data

Width” and dividing by 8 for Non-ECC and 9 for ECC

modules gives the overall module memory density in

MBytes as listed in column “Coding”.

Table 24

Field Description

DDR2 DIMM Nomenclature

Values Coding

1

INFINEON

HYS

Constant

Modul Prefix

2

Module Data

64

72

T

Non-ECC

ECC

DDR2

Table 25

Field Description

DDR2 DRAM Nomenclature

Values Coding

Width [bit]

3

4

DRAM

1

INFINEON

HYB

Constant

Technology

Component Prefix

Memory Density

32

64

128

256

0 .. 9

256 MByte

512 MByte

1 GByte

2 GByte

look up table

2

3

4

Interface Voltage [V] 18

DRAM Technology

Component Density 256

SSTL1.8

DDR2

256 Mbit

512 Mbit

1 Gbit

2 Gbit

×4

per I/O [Mbit];

T

Module Density¹⁾

[Mbit]

512

1G

2G

40

5

6

Raw Card

Generation

Number of Module 0, 2, 4 1, 2, 4

5+6 Number of I/Os

Ranks

80

×8

7

8

Product Variations 0 .. 9

look up table

16

×16

Package,

A .. Z

7

8

Product Variations 0 .. 9

Die Revision

look up table

First

Second

Lead-Free Status

A

B

C

9

Module Type

D

M

R

U

–3.7

–5

–A

–B

SO-DIMM

Micro-DIMM

Registered

Unbuffered

PC2–4200 4–4–4

PC2–3200 3–3–3

First

9

Package,

FBGA,

Lead-Free Status

lead-containing

F

–3.7

–5

FBGA, lead-free

DDR2-533C

DDR2-400B

10

11

Speed Grade

Die Revision

10

11

Speed Grade

N/A for Components

Second

Data Sheet

40

Rev. 1.0, 2004-09

02182004-TRHM-8N4H

w w w . i n f i n e o n . c o m

Published by Infineon Technologies AG

厂商	型号	描述	页数
INFINEON	HYS64-72V2200GU-8	3.3V 2M ×64 /72- 1位BANK SDRAM模块3.3V 4M ×64 /72- 2位BANK SDRAM模块[ 3.3V 2M x 64/72-Bit 1 BANK SDRAM Module 3.3V 4M x 64/72-Bit 2 BANK SDRAM Module ]	17 页
INFINEON	HYS64-74V8200GU	3.3 V 8M ×64 /72- 1位银行SDRAM模块3.3 V 16M ×64 /72- 2位银行SDRAM模块[ 3.3 V 8M x 64/72-Bit 1 Bank SDRAM Module 3.3 V 16M x 64/72-Bit 2 Bank SDRAM Module ]	17 页
INFINEON	HYS6472V16200GU	3.3 V 16M ×64 /72-位SDRAM模块3.3 V 32M ×64 /72-位SDRAM模块3.3 V 64M ×64 /72-位SDRAM模块[ 3.3 V 16M x 64/72-Bit SDRAM Modules 3.3 V 32M x 64/72-Bit SDRAM Modules 3.3 V 64M x 64/72-Bit SDRAM Modules ]	17 页
INFINEON	HYS6472V4200GU	3.3V 4M ×64 /72- 1位BANK SDRAM模块3.3V 8M ×64 /72- 2位BANK SDRAM模块[ 3.3V 4M x 64/72-Bit 1 BANK SDRAM Module 3.3V 8M x 64/72-Bit 2 BANK SDRAM Module ]	15 页
INFINEON	HYS64D128020GBDL-6-A	[ DDR DRAM Module, 128MX64, 0.7ns, CMOS, SO-DIMM-200 ]	11 页
ETC	HYS64D128020GBDL-7-A	？ 1GB （ 1024Mx64 ） PC2100 2银行？\n[ ?1GB (1024Mx64) PC2100 2-bank? ]	11 页
INFINEON	HYS64D128020GU-7-A	2.5 V 184针无缓冲DDR- SDRAM我模块[ 2.5 V 184-pin Unbuffered DDR-I SDRAM Modules ]	18 页
INFINEON	HYS64D128020GU-8-A	2.5 V 184针无缓冲DDR- SDRAM我模块[ 2.5 V 184-pin Unbuffered DDR-I SDRAM Modules ]	18 页
QIMONDA	HYS64D128020GU-8-A	[ DDR DRAM Module, 128MX64, 0.8ns, CMOS, PDMA184 ]	18 页
INFINEON	HYS64D128021	200针的小型双列直插式内存模块[ 200-Pin Small Outline Dual-In-Line Memory Modules ]	23 页