Philips Semiconductors
Product specification
128 macrocell CPLD
PZ5128
FEATURES
Table 1. PZ5128 Features
• Industry’s first TotalCMOS PLD – both CMOS design and
PZ5128
4000
100
process technologies
Usable gates
• Fast Zero Power (FZP ) design technique provides ultra-low
Maximum inputs
Maximum I/Os
power and very high speed
96
• IEEE 1149.1–compliant, JTAG Testing Capability
– 4 pin JTAG interface (TCK, TMS, TDI, TDO)
– IEEE 1149.1 TAP Controller
Number of macrocells
Propagation delay (ns)
128
7.5
84-pin PLCC, 100-pin PQFP,
100-pin TQFP 128-pin LQFP,
160-pin PQFP
– JTAG commands include: Bypass, Sample/Preload, Extest,
Usercode, Idcode, HighZ
Packages
• 5 Volt, In–System Programmable (ISP) using the JTAG interface
– On–chip supervoltage generation
DESCRIPTION
– ISP commands include: Enable, Erase, Program, Verify
– Supported by multiple ISP programming platforms
The PZ5128 CPLD (Complex Programmable Logic Device) is the
third in a family of Fast Zero Power (FZP ) CPLDs from Philips
Semiconductors. These devices combine high speed and zero
power in a 128 macrocell CPLD. With the FZP design technique,
the PZ5128 offers true pin-to-pin speeds of 7.5ns, while
• High speed pin-to-pin delays of 7.5ns
• Ultra-low static power of less than 100µA
simultaneously delivering power that is less than 100µA at standby
without the need for ‘turbo bits’ or other power down schemes. By
replacing conventional sense amplifier methods for implementing
product terms (a technique that has been used in PLDs since the
bipolar era) with a cascaded chain of pure CMOS gates, the
dynamic power is also substantially lower than any competing CPLD
– 70% lower at 50MHz. These devices are the first TotalCMOS
PLDs, as they use both a CMOS process technology and the
patented full CMOS FZP design technique. For 3V applications,
Philips also offers the high speed PZ3128 CPLD that offers these
features in a full 3V implementation.
• Dynamic power that is 70% lower at 50MHz than competing
devices
• 100% routable with 100% utilization while all pins and all
macrocells are fixed
• Deterministic timing model that is extremely simple to use
• 4 clocks with programmable polarity at every macrocell
• Support for asynchronous clocking
• Innovative XPLA architecture combines high speed with
extreme flexibility
The Philips FZP CPLDs introduce the new patent-pending XPLA
(eXtended Programmable Logic Array) architecture. The XPLA
architecture combines the best features of both PLA and PAL type
structures to deliver high speed and flexible logic allocation that
results in superior ability to make design changes with fixed pinouts.
The XPLA structure in each logic block provides a fast 10ns PAL
path with 5 dedicated product terms per output. This PAL path is
joined by an additional PLA structure that deploys a pool of 32
product terms to a fully programmable OR array that can allocate
the PLA product terms to any output in the logic block. This
combination allows logic to be allocated efficiently throughout the
logic block and supports as many as 37 product terms on an output.
The speed with which logic is allocated from the PLA array to an
output is only 2ns, regardless of the number of PLA product terms
• 1000 erase/program cycles guaranteed
• 20 years data retention guaranteed
• Logic expandable to 37 product terms
• PCI compliant
• Advanced 0.5µ E CMOS process
• Security bit prevents unauthorized access
2
• Design entry and verification using industry standard and Philips
CAE tools
• Reprogrammable using industry standard device programmers
• Innovative Control Term structure provides either sum terms or
product terms in each logic block for:
used, which results in worst case t ’s of only 9.5ns from any pin to
PD
– Programmable 3-State buffer
any other pin. In addition, logic that is common to multiple outputs
can be placed on a single PLA product term and shared across
multiple outputs via the OR array, effectively increasing design
density.
– Asynchronous macrocell register preset/reset
• Programmable global 3-State pin facilitates ‘bed of nails’ testing
without using logic resources
The PZ5128 CPLDs are supported by industry standard CAE tools
(Cadence, Exemplar Logic, Minc, Mentor, Synopsys, Synario,
Viewlogic, MINC), using text (Abel, VHDL, Verilog) and/or schematic
entry. Design verification uses industry standard simulators for
functional and timing simulation. Development is supported on
personal computer, Sparc, and HP platforms. Device fitting uses
either MINC or Philips Semiconductors-developed tools.
• Available in PLCC, TQFP, and PQFP packages
• Available in both Commercial and Industrial grades
The PZ5128 CPLD is electrically reprogrammable using industry
standard device programmers from vendors such as Data I/O, BP
Microsystems, SMS, and others. The PZ5128 also includes an
industry-standard, IEEE 1149.1, JTAG interface through which
in-system programming (ISP) and reprogramming of the device is
supported.
PAL is a registered trademark of Advanced Micro Devices, Inc.
2
1998 Jul 23
853–2023 19775
