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HYS64V64220GU-8B

型号：

HYS64V64220GU-8B

品牌：

INFINEON[ Infineon ]

页数：

15 页

PDF大小：

113 K

下载PDF手册
3.3V 32M x 64/72-Bit SDRAM Modules  
3.3V 64M x 64/72-Bit SDRAM Modules  
HYS64/72V32200GU  
HYS64/72V64220GU  
PC100-168 pin unbuffered DIMM Modules  
• 168 Pin unbuffered 8 Byte Dual-In-Line SDRAM Modules for PC main memory applications  
• One bank 32M x 64 and 32M x 72 organisation  
• Two bank 64M x 64 and 64M x 72 organisation  
• Optimized for byte-write non-parity or ECC applications  
• Fully PC board layout compatible to INTEL’s Rev. 1.0 module specification  
• JEDEC standard Synchronous DRAMs (SDRAM)  
• SDRAM Performance:  
-8  
-8A  
100  
-8B  
100  
Units  
MHz  
fCK  
tAC  
Clock frequency (max.)  
Clock access time  
100  
6
6
6
ns  
• Programmed Latencies :  
Product Speed  
CL  
2
tRCD  
tRP  
-8  
PC100  
PC100  
PC100  
2
2
2
2
2
3
-8A  
-8B  
3
3
• Single +3.3V(± 0.3V ) power supply  
• Programmable CAS Latency, Burst Length and Wrap Sequence  
(Sequential & Interleave)  
• Auto Refresh (CBR) and Self Refresh  
• Decoupling capacitors mounted on substrate  
• All inputs, outputs are LVTTL compatible  
2
• Serial Presence Detect with E PROM  
• Uses SIEMENS 256Mbit SDRAM components in 32M x 8 organisation and TSOPII-54 packages  
• Gold contact pad  
• Card Size: 133,35 mm x 31.75 mm x 4,00 mm  
INFINEON Technologies  
1
4.99  
HYS64(72)V32200/64220GU  
SDRAM-Modules  
The HYS64/72V32200 and HYS64/72V64220 are industry standard 168-pin 8-byte Dual in-line Memory Modules  
(DIMMs) which are organised as 32M x 64 and 32M x 72 in 1 bank and 64M x 64 and 64M x 72 in two banks  
high speed memory arrays designed with 256M Synchronous DRAMs (SDRAMs) for non-parity and ECC  
applications. The DIMMs use -8 and -8B speed sort for 32M x 8 SDRAM devices in TSOP54 packages to meet the  
PC100 requirement. Decoupling capacitors are mounted on the PC board. The PC board design is according to  
INTEL’s PC 100 module specification.  
The DIMMs have a serial presence detect, implemented with a serial E2PROM using the two pin I2C protocol. The  
first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes are available to the end user.  
All SIEMENS 168-pin DIMMs provide a high performance, flexible 8-byte interface in a 133,35 mm long footprint,  
with 1,25“ ( 31,75 mm) height.  
Ordering Information  
Type  
Code  
Package  
Descriptions  
Module  
Height  
PC100 32M x 64 1 bank SDRAM module  
PC100 32M x 72 1 bank SDRAM module  
PC100 64M x 64 2 bank SDRAM module  
PC100 64M x 72 2 bank SDRAM module  
PC100 32M x 64 1 bank SDRAM module  
PC100 32M x 72 1 bank SDRAM module  
PC100 64M x 64 2 bank SDRAM module  
PC100 64M x 72 2 bank SDRAM module  
PC100 32M x 64 1 bank SDRAM module  
PC100 32M x 72 1 bank SDRAM module  
PC100 64M x 64 2 bank SDRAM module  
PC100 64M x 72 2 bank SDRAM module  
HYS 64V32200GU-8  
HYS 72V32200GU-8  
HYS 64V64220GU-8  
HYS 72V64220GU-8  
PC100-222-620  
PC100-222-620  
PC100-222-620  
PC100-222-620  
L-DIM-168-30  
L-DIM-168-30  
L-DIM-168-30  
L-DIM-168-30  
L-DIM-168-30  
L-DIM-168-30  
L-DIM-168-30  
L-DIM-168-30  
L-DIM-168-30  
L-DIM-168-30  
L-DIM-168-30  
L-DIM-168-30  
1,25“  
1,25“  
1,25“  
1,25“  
1,25“  
1,25“  
1,25“  
1,25“  
1,25“  
1,25“  
1,25“  
1,25“  
HYS 64V32200GU-8A PC100-222-620  
HYS 72V32200GU-8A PC100-222-620  
HYS 64V64220GU-8A PC100-222-620  
HYS 72V64220GU-8A PC100-222-620  
HYS 64V32200GU-8B PC100-323-620  
HYS 72V32200GU-8B PC100-323-620  
HYS 64V64220GU-8B PC100-323-620  
HYS 72V64220GU-8B PC100-323-620  
Pin Names  
A0-A12  
BA0, BA1  
DQ0 - DQ63  
CB0-CB7  
Address Inputs  
Bank Selects  
CLK0 - CLK3  
Clock Input  
DQMB0 - DQMB7 Data Mask  
Data Input/Output  
CS0 - CS3  
Vcc  
Chip Select  
Check Bits (x72 organisation  
only)  
Power (+3.3 Volt)  
RAS  
CAS  
WE  
Row Address Strobe  
Column Address Strobe  
Read / Write Input  
Vss  
SCL  
SDA  
Ground  
Clock for Presence Detect  
Serial Data Out for Presence  
Detect  
CKE0, CKE1  
Clock Enable  
N.C. / DU  
No Connection  
Address Format:  
Part Number  
Rows  
13  
Columns Banks  
Refresh  
8k  
Period  
64 ms  
64 ms  
Interval  
7,8 µs  
7,8 µs  
32M x 64/72 HYS64/72V32200GU  
64M x 64/72 HYS64/72V64220GU  
10  
10  
2
2
13  
8k  
INFINEON Technologies  
2
HYS64(72)V32200/64220GU  
SDRAM-Modules  
Pin Configuration  
PIN #  
Symbol  
PIN #  
Symbol  
PIN #  
Symbol  
PIN #  
Symbol  
1
VSS  
DQ0  
DQ1  
DQ2  
DQ3  
VCC  
DQ4  
DQ5  
DQ6  
DQ7  
DQ8  
VSS  
DQ9  
DQ10  
DQ11  
DQ12  
DQ13  
VCC  
DQ14  
DQ15  
NC (CB0)  
NC (CB1)  
VSS  
NC  
43  
VSS  
85  
VSS  
127  
VSS  
2
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
DU  
86  
DQ32  
DQ33  
DQ34  
DQ35  
VCC  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
139  
140  
141  
142  
143  
144  
145  
146  
147  
148  
149  
150  
151  
152  
153  
154  
155  
156  
157  
158  
159  
160  
161  
162  
163  
164  
165  
166  
167  
168  
CKE0  
CS3  
3
CS2  
87  
4
DQMB2  
DQMB3  
DU  
88  
DQMB6  
DQMB7  
NC  
5
89  
6
90  
7
VCC  
91  
DQ36  
DQ37  
DQ38  
DQ39  
DQ40  
VSS  
VCC  
NC  
8
NC  
92  
9
NC  
93  
NC  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
NC (CB2)  
NC (CB3)  
VSS  
94  
CB6  
95  
CB7  
96  
VSS  
DQ16  
DQ17  
DQ18  
DQ19  
VCC  
97  
DQ41  
DQ42  
DQ43  
DQ44  
DQ45  
VCC  
DQ48  
DQ49  
DQ50  
DQ51  
VCC  
DQ52  
NC  
98  
99  
100  
101  
102  
103  
104  
105  
106  
107  
108  
109  
110  
111  
112  
113  
114  
115  
116  
117  
118  
119  
120  
121  
122  
123  
124  
125  
126  
DQ20  
NC  
DQ46  
DQ47  
NC (CB4)  
NC (CB5)  
VSS  
DU  
DU  
CKE1  
VSS  
NC  
VSS  
DQ21  
DQ22  
DQ23  
VSS  
DQ53  
DQ54  
DQ55  
VSS  
NC  
NC  
NC  
VCC  
WE  
VCC  
DQ24  
DQ25  
DQ26  
DQ27  
VCC  
CAS  
DQ56  
DQ57  
DQ58  
DQ59  
VCC  
DQ60  
DQ61  
DQ62  
DQ63  
VSS  
DQMB0  
DQMB1  
CS0  
DQMB4  
DQMB5  
CS1  
DU  
RAS  
VSS  
A0  
DQ28  
DQ29  
DQ30  
DQ31  
VSS  
VSS  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
CLK2  
NC  
A9  
CLK3  
NC  
A10  
BA0  
BA1  
WP  
A11  
SA0  
VCC  
VCC  
CLK0  
SDA  
VCC  
SA1  
SCL  
CLK1  
A12  
SA2  
VCC  
VCC  
Note : Pinnames in brackets are for the x72 ECC versions  
INFINEON Technologies  
3
HYS64(72)V32200/64220GU  
SDRAM-Modules  
WE  
CS0  
CS WE  
CS WE  
DQMB0  
DQ(7:0)  
DQMB4  
DQM  
DQM  
DQ(39:32)  
DQ0-DQ7  
DQ0-DQ7  
D0  
CS WE  
D4  
CS WE  
DQM  
DQM  
DQ0-DQ7  
DQMB1  
DQMB5  
DQ0-DQ7  
DQ(15:8)  
DQ(47:40)  
D1  
CS WE  
D5  
DQM  
CB(7:0)  
DQ0-DQ7  
D8  
CS2  
CS WE  
CS WE  
DQMB2  
DQM  
DQM  
DQMB6  
DQ0-DQ7  
DQ0-DQ7  
DQ(55:48)  
DQ(23:16)  
D6  
CS WE  
D2  
CS WE  
DQMB7  
DQM  
DQM  
DQMB3  
DQ(63:56)  
DQ0-DQ7  
DQ0-DQ7  
DQ(31:24)  
D3  
D7  
E2PROM (256wordx8bit)  
D0 - D7,(D8)  
A0-A12, BA0,BA1  
VCC  
VSS  
SA0  
SA1  
SA2  
SCL  
SA0  
SA1  
SA2  
SCL  
D0 - D7,(D8)  
D0 - D7,(D8)  
SDA  
WP  
C
47k  
RAS  
CAS  
CKE0  
D0 - D7,(D8)  
D0 - D7,(D8)  
Clock Wiring  
32M x 64  
CLK0 4 SDRAM+3.3pF 5 SDRAM  
CLK1 Termination Termination  
CLK2 4 SDRAM+3.3pF 4 SDRAM+3.3pF  
CLK3 Termination Termination  
32M x 72  
D0 - D7,(D8)  
Note: D8 is only used in the x72 ECC version  
Block Diagram for 32M x 64/72 one bank SDRAM DIMM modules  
INFINEON Technologies  
4
HYS64(72)V32200/64220GU  
SDRAM-Modules  
CS1  
CS0  
CS  
CS  
CS  
CS  
DQMB0  
DQ(7:0)  
DQM  
DQM  
DQMB4  
DQM  
DQM  
DQ0-DQ7  
D0  
DQ0-DQ7  
D8  
DQ(39:32)  
DQ0-DQ7  
D4  
DQ0-DQ7  
D12  
CS  
CS  
CS  
CS  
DQM  
DQM  
DQM  
DQM  
DQMB1  
DQMB5  
DQ(15:8)  
DQ(47:40)  
DQ0-DQ7  
D1  
DQ0-DQ7  
D9  
DQ0-DQ7  
D5  
DQ0-DQ7  
D13  
CS  
CS  
DQM  
DQM  
DQ0-DQ7  
D16  
DQ0-DQ7  
D17  
CB(7:0)  
CS3  
CS2  
CS  
CS  
CS  
CS  
DQM  
DQM  
DQMB2  
DQM  
DQM  
DQMB6  
DQ(23:16)  
DQ(55:48)  
DQ0-DQ7  
D2  
DQ0-DQ7  
D10  
DQ0-DQ7  
D6  
DQ0-DQ7  
D14  
CS  
CS  
CS  
CS  
DQMB3  
DQM  
DQM  
DQMB7  
DQM  
DQM  
DQ(31:24)  
DQ(63:56)  
DQ0-DQ7  
D3  
DQ0-DQ7  
D11  
DQ0-DQ7  
D7  
DQ0-DQ7  
D15  
E2PROM (256wordx8bit)  
D0 - D15,(D16,D17)  
D0 - D15,(D16,D17)  
A0-A12,BA0,BA1  
VDD  
SA0  
SA1  
SA2  
SCL  
SA0  
SDA  
WP  
SA1  
SA2  
SCL  
C0-C31,(C32..C35)  
VSS  
D0 - D7,(D8)  
47k  
RAS, CAS, WE  
CKE0  
D0 - D15,(D16,D17)  
Clock Wiring  
64M x 64  
D0 - D7,(D16)  
64M x 72  
VDD  
10k  
CLK0 4 SDRAM+3.3pF 5 SDRAM  
CLK1 4 SDRAM+3.3pF 5 SDRAM  
CLK2 4 SDRAM+3.3pF 4 SDRAM+3.3pF  
CLK3 4 SDRAM+3.3pF 4 SDRAM+3.3pF  
CKE1  
D9 - D15,(D17)  
Note: D16 & D17 is only used in the x72 ECC version and all resistor values are 10 Ohms except otherwise noted.  
Block Diagram for 64M x 64/72 two bank SDRAM DIMM modules  
INFINEON Technologies  
5
HYS64(72)V32200/64220GU  
SDRAM-Modules  
DC Characteristics  
TA = 0 to 70 °C; VSS = 0 V; VDD,VDDQ = 3.3 V ± 0.3 V  
Parameter  
Symbol  
Limit Values  
Unit  
min.  
max.  
Vcc+0.3  
0.8  
Input high voltage  
VIH  
VIL  
2.0  
– 0.5  
2.4  
V
Input low voltage  
V
Output high voltage (IOUT = – 4.0 mA)  
Output low voltage (IOUT = 4.0 mA)  
VOH  
VOL  
II(L)  
–
V
–
0.4  
V
Input leakage current, any input  
– 40  
40  
µA  
(0 V < VIN < 3.6 V, all other inputs = 0 V)  
Output leakage current  
IO(L)  
– 40  
40  
µA  
(DQ is disabled, 0 V < VOUT < VCC)  
Capacitance  
TA = 0 to 70 °C; VDD = 3.3 V ± 0.3 V, f = 1 MHz  
Parameter  
Symbol  
Limit Values  
Unit  
max.  
max.  
max  
max.  
32Mx64 32Mx72 64Mx64 64Mx72  
Input capacitance  
CI1  
60  
70  
90  
100  
pF  
(A0 to A11, BA0, BA1, RAS, CAS, WE)  
Input capacitance (CS0 -CS3, )  
Input capacitance (CLK0 - CLK3)  
Input capacitance (CKE0, CKE1)  
Input capacitance (DQMB0 - DQMB7)  
CI2  
CICL  
CI3  
CI4  
CIO  
30  
35  
50  
20  
13  
35  
40  
55  
20  
13  
30  
35  
55  
25  
20  
35  
40  
60  
25  
20  
pF  
pF  
pF  
pF  
pF  
Input / Output capacitance  
(DQ0-DQ63, CB0-CB7)  
Input Capacitance (SCL,SA0-2)  
Input/Output Capacitance  
C
C
8
8
8
8
pF  
pF  
sc  
10  
10  
10  
10  
sd  
INFINEON Technologies  
6
HYS64(72)V32200/64220GU  
SDRAM-Modules  
o
Operating Currents per SDRAM (T = 0 to 70 C, Vdd = 3.3V ± 0.3V 1)  
A
(Recommended Operating Conditions unless otherwise noted)  
Symb.  
Note  
Parameter & Test Condition  
OPERATING CURRENT  
-8/-8A  
max.  
-8B  
max.  
ICC1  
trc=trcmin., tck=tckmin.  
x8  
210  
165  
mA  
2
Ouputs open, Burst Length = 4, CL=3  
All banks operated in random access,  
all banks operated in ping-pong manner  
to maximize gapless data access  
PRECHARGE STANDBY CURRENT in tck = min.  
Power Down Mode  
ICC2P  
ICC2N  
2
2
mA  
mA  
2
2
CS =VIH (min.), CKE<=Vil(max)  
PRECHARGE STANDBY CURRENT in tck = min.  
Non-Power Down Mode  
19  
16  
CS = VIH (min.), CKE>=Vih(min)  
NO OPERATING CURRENT  
CKE>=VIH(min.)  
CKE<=VIL(max.)  
ICC3N  
ICC3P  
ICC4  
45  
10  
40  
10  
mA  
mA  
2
2
tck = min., CS = VIH(min),  
active state ( max. 4 banks)  
BURST OPERATING CURRENT  
tck = min.,  
Read command cycling  
x8  
210  
240  
165  
195  
mA 2,3  
AUTO REFRESH CURRENT  
tck = min.,  
Auto Refresh command cycling  
ICC5  
ICC6  
2
mA  
SELF REFRESH CURRENT  
Self Refresh Mode, CKE=0.2V  
standard version  
2.5  
2.5  
mA  
2
Notes:  
1. All values are shown per one SDRAM component.  
2. These parameters depend on the cycle rate. These values are measured at 100 MHz for -8  
and at 66 MHz for -10 parts. Input signals are changed once during tck, excepts for ICC6 and for standby  
currents when tck=infinity.  
3. These parameters are measured with continuous data stream during read access and all DQ toggling. CL=3  
and BL=4 is assumed and the VDDQ current is excluded.  
INFINEON Technologies  
7
HYS64(72)V32200/64220GU  
SDRAM-Modules  
AC Characteristics 1)2)  
TA = 0 to 70 °C; VSS = 0 V; VCC = 3.3 V ± 0.3 V, tT = 1 ns  
Symbol  
Unit  
Parameter  
Limit Values  
-8  
PC100-  
222  
-8A  
PC100-  
322  
-8B  
PC100-  
323  
min. max. min. max. min. max.  
Clock and Clock Enable  
Clock Cycle Time  
CAS Latency = 3  
CAS Latency = 2  
10  
10  
–
–
10  
12  
–
–
10  
15  
–
–
ns  
ns  
tCK  
tCK  
tAC  
Clock Frequency  
CAS Latency = 3  
CAS Latency = 2  
–
–
100  
100  
–
–
100  
83  
–
–
100 MHz  
66 MHz  
Access Time from Clock  
CAS Latency = 3  
CAS Latency = 2  
Clock High Pulse Width  
2,  
3
–
–
6
6
–
–
6
6
–
–
6
7
ns  
ns  
tCH  
tCL  
tT  
3
3
–
–
3
3
–
–
3
3
–
–
ns  
ns  
Clock Low Pulse Width  
Transition time  
0.5  
10  
0.5  
10  
0.5  
10 ns  
Setup and Hold Times  
Input Setup Time  
4
4
4
4
tIS  
2
1
–
–
–
–
–
8
2
1
–
–
2
1
–
–
–
–
–
ns  
ns  
ns  
ns  
ns  
Input Hold Time  
tIH  
CKE Setup Time  
tCKS  
tCKH  
tRSC  
tSB  
2
2
–
2
CKE Hold Time  
1
1
–
1
Mode Register Set-up time  
Power Down Mode Entry Time  
16  
0
16  
0
–
20  
0
10  
10 ns  
Common Parameters  
Row to Column Delay Time  
Row Precharge Time  
Row Active Time  
5
5
5
5
tRCD  
tRP  
tRAS  
tRC  
20  
20  
48  
70  
–
–
20  
20  
20  
30  
–
–
ns  
ns  
100k  
–
48 100k 60 100k ns  
70 80 ns  
Row Cycle Time  
–
–
INFINEON Technologies  
8
HYS64(72)V32200/64220GU  
SDRAM-Modules  
Symbol  
Unit  
Parameter  
Limit Values  
-8  
PC100-  
222  
-8A  
PC100-  
322  
-8B  
PC100-  
323  
min. max. min. max. min. max.  
5
Activate(a) to Activate(b) Command  
period  
tRRD  
tCCD  
16  
–
16  
20  
–
ns  
CAS(a) to CAS(b) Command period  
1
–
1
–
1
–
CLK  
Refresh Cycle  
Refresh Period (8192 cycles)  
Self Refresh Exit Time  
tREF  
–
64  
–
64  
–
64 ms  
ns  
tSREX  
10  
10  
10  
Read Cycle  
Data Out Hold Time  
tOH  
tLZ  
3
0
3
–
–
–
8
2
3
0
3
–
–
–
8
2
3
0
3
–
–
–
ns  
ns  
2
Data Out to Low Impedance Time  
Data Out to High Impedance Time  
DQM Data Out Disable Latency  
tHZ  
10 ns  
tDQZ  
2
CLK  
Write Cycle  
Data Input to Precharge  
(write recovery)  
tWR  
2
0
–
–
2
0
–
–
2
0
–
–
CLK  
CLK  
DQM Write Mask Latency  
tDQW  
INFINEON Technologies  
9
HYS64(72)V32200/64220GU  
SDRAM-Modules  
Notes:  
1. An initial pause of 100µs is required after power-up, then a Precharge All Banks command must  
be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can  
begin.  
2. AC timing tests have V = 0.4 V and V = 2.4 V with the timing referenced to the 1.4 V crossover  
il  
ih  
point. The transition time is measured between V and V . All AC measurements assume t =1ns  
ih  
il  
T
with the AC output load circuit show. Specified tac and toh parameters are measured with a 50  
pF only, without any resisitve termination and with a input signal of 1V / ns edge rate between  
0.8V and 2.0 V.  
tCH  
+ 1.4 V  
2.4 V  
CLOCK  
50 Ohm  
0.4 V  
tCL  
t
T
Z=50 Ohm  
tSETUP tHOLD  
I/O  
50 pF  
1.4V  
INPUT  
tAC  
tAC  
I/O  
tLZ  
tOH  
50 pF  
Measurement conditions for  
tac and toh  
1.4V  
OUTPUT  
tHZ  
fig.1  
3. If clock rising time is longer than 1ns, a time (t /2 -0.5) ns has to be added to this parameter.  
T
4. Rated at 1.5 V  
5. If t is longen than 1 ns, a time (t -1) ns has to be added to this parameter.  
T
T
6. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh  
commands must be given to “wake-up“ the device.  
7. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after  
CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied  
once the Self Refresh Exit command is registered.  
8. Referenced to the time which the output achieves the open circuit condition, not to output voltage  
levels.  
INFINEON Technologies  
10  
HYS64(72)V32200/64220GU  
SDRAM-Modules  
A serial presence detect storage device - E2PROM - is assembled onto the module. Information about the module  
configuration, speed, etc. is written into the E2PROM device during module production using a serial presence  
detect protocol ( I2C synchronous 2-wire bus).  
SPD-Table for 256MBit SDRAM based PC100 Modules:  
Byte#  
Description  
SPD Entry  
Value  
Hex  
32Mx64 32Mx64 32Mx64 32Mx72 32Mx72 32Mx72  
one  
bank  
-8  
one  
bank  
-8A  
one  
bank  
-8B  
one  
bank  
-8  
one  
bank  
-8A  
one  
bank  
-8B  
0
1
2
3
Number of SPD bytes  
Total bytes in Serial PD  
Memory Type  
128  
256  
80  
08  
04  
0D  
80  
08  
04  
0D  
80  
08  
04  
0D  
80  
08  
04  
0D  
80  
08  
04  
0D  
80  
08  
04  
0D  
SDRAM  
13  
Number of Row Addresses  
(without BS bits)  
4
Number of Column Addres-  
ses (for 32Mx8 SDRAMs)  
10  
0A  
0A  
0A  
0A  
0A  
0A  
5
6
7
8
9
Number of DIMM Banks  
Module Data Width  
1
01  
40  
00  
01  
A0  
60  
01  
40  
00  
01  
A0  
6.0  
01  
40  
00  
01  
A0  
60  
01  
48  
00  
01  
A0  
60  
01  
48  
00  
01  
A0  
60  
01  
48  
00  
01  
A0  
60  
64 / 72  
0
Module Data Width (cont’d)  
Module Interface Levels  
SDRAM Cycle Time at CL=3  
LVTTL  
10.0 ns  
6.0 ns  
10 SDRAM Access time from  
Clock at CL=3  
11 Dimm Config  
none / ECC  
00  
82  
00  
82  
00  
82  
02  
82  
02  
82  
02  
82  
12 Refresh Rate/Type  
Self-Refresh,  
7,8µs  
1 3 S D R A M w i d t h , P r i m a r y  
x 8  
0 8  
00  
0 8  
00  
0 8  
00  
0 8  
08  
0 8  
08  
0 8  
08  
14 Error Checking SDRAM data  
width  
n/a / x8  
15 Minimum clock delay for  
back-to-back random column  
address  
t
ccd = 1 CLK  
01  
01  
01  
01  
01  
01  
16 Burst Length supported  
17 Number of SDRAM banks  
18 Supported CAS Latencies  
1, 2, 4 & 8  
4
0F  
04  
06  
0F  
04  
06  
0F  
04  
06  
0F  
04  
06  
0F  
04  
06  
0F  
04  
06  
CAS latency  
= 2 & 3  
19 CS Latencies  
20 WE Latencies  
CS latency =  
0
01  
01  
00  
0E  
A0  
60  
01  
01  
00  
0E  
F0  
60  
01  
01  
00  
0E  
F0  
70  
01  
01  
00  
0E  
A0  
60  
01  
01  
00  
0E  
F0  
60  
01  
01  
00  
E
Write lat-  
ency = 0  
21 SDRAM DIMM module  
attributes  
non buffered/  
non reg.  
22 SDRAM Device Attributes  
:General  
Vcc tol +/-  
10%  
23 Min. Clock Cycle Time at  
CAS Latency = 2  
10.0 / 15.0  
ns  
F0  
70  
24 Max. data access time from  
Clock for CL=2  
6.0 / 7.0 ns  
INFINEON Technologies  
11  
HYS64(72)V32200/64220GU  
SDRAM-Modules  
Byte#  
Description  
SPD Entry  
Value  
Hex  
32Mx64 32Mx64 32Mx64 32Mx72 32Mx72 32Mx72  
one  
bank  
-8  
one  
bank  
-8A  
one  
bank  
-8B  
one  
bank  
-8  
one  
bank  
-8A  
one  
bank  
-8B  
25 Minimum Clock Cycle Time  
at CL = 1  
not suppor-  
ted  
FF  
FF  
14  
10  
14  
32  
40  
FF  
FF  
14  
14  
14  
32  
40  
FF  
FF  
1E  
14  
14  
3C  
40  
FF  
FF  
14  
10  
14  
32  
40  
FF  
FF  
14  
14  
14  
32  
40  
FF  
FF  
1E  
14  
14  
3C  
40  
26 Maximum Data Access Time not suppor-  
from Clock at CL=1  
ted  
27 Minimum Row Precharge  
Time  
20 / 30 ns  
28 Minimum Row Active to Row  
Active delay tRRD  
16 / 20 ns  
20 ns  
29 Minimum RAS to CAS delay  
tRCD  
30 Minimum RAS pulse width  
tRAS  
50 / 60 ns  
256 MByte  
31 Module Bank Density (per  
bank)  
32 SDRAM input setup time  
33 SDRAM input hold time  
2 ns  
1 ns  
2 ns  
20  
10  
20  
20  
10  
20  
20  
10  
20  
20  
10  
20  
20  
10  
20  
20  
10  
20  
34 SDRAM data input setup  
time  
35 SDRAM data input hold time  
1 ns  
10  
10  
FF  
10  
FF  
10  
FF  
10  
10  
FF  
62-61 Superset information (may  
be used in future)  
FF  
FF  
62 SPD Revision  
Revision 1.2  
12  
99  
12  
ED  
XX  
12  
11  
12  
AB  
XX  
12  
FF  
XX  
12  
F3  
XX  
63 Checksum for bytes 0 - 62  
64- Manufacturers information  
125  
XX  
XX  
126 Frequency Specification  
127 100 MHz support details  
128+ Unused storage locations  
100 MHz  
64  
AF  
FF  
64  
AD  
FF  
64  
AD  
FF  
64  
AF  
FF  
64  
AD  
FF  
64  
AD  
FF  
INFINEON Technologies  
12  
HYS64(72)V32200/64220GU  
SDRAM-Modules  
SPD-Table for 256Mbit SDRAM based PC100 Modules:  
Byte#  
Description  
SPD Entry  
Value  
Hex  
64Mx64 64Mx64 64Mx64 64Mx72 64Mx72 64Mx72  
two  
bank  
-8  
two  
bank  
-8A  
two  
bank  
-8B  
two  
bank  
-8  
two  
bank  
-8A  
two  
bank  
-8B  
0
1
2
3
Number of SPD bytes  
Total bytes in Serial PD  
Memory Type  
128  
256  
80  
08  
04  
0D  
80  
08  
04  
0D  
80  
08  
04  
0D  
80  
08  
04  
0D  
80  
08  
04  
0D  
80  
08  
04  
0D  
SDRAM  
13  
Number of Row Addresses  
(without BS bits)  
4
Number of Column Addres-  
ses (for 32Mx8 SDRAMs)  
10  
0A  
0A  
0A  
0A  
0A  
0A  
5
6
7
8
9
Number of DIMM Banks  
Module Data Width  
2
02  
40  
00  
01  
A0  
60  
02  
40  
00  
01  
A0  
60  
02  
40  
00  
01  
A0  
60  
02  
48  
00  
01  
A0  
60  
02  
48  
00  
01  
A0  
60  
02  
48  
00  
01  
A0  
60  
64 / 72  
0
Module Data Width (cont’d)  
Module Interface Levels  
SDRAM Cycle Time at CL=3  
LVTTL  
10.0 ns  
6.0 ns  
10 SDRAM Access time from  
Clock at CL=3  
11 Dimm Config  
none / ECC  
00  
82  
00  
82  
00  
82  
02  
82  
02  
82  
02  
82  
12 Refresh Rate/Type  
Self-Refresh,  
7.8 µs  
1 3 S D R A M w i d t h , P r i m a r y  
x 8  
0 8  
00  
0 8  
00  
0 8  
00  
0 8  
08  
0 8  
08  
0 8  
08  
14 Error Checking SDRAM data  
width  
n/a / x8  
15 Minimum clock delay for  
back-to-back random column  
address  
t
ccd = 1 CLK  
01  
01  
01  
01  
01  
01  
16 Burst Length supported  
17 Number of SDRAM banks  
18 Supported CAS Latencies  
1, 2, 4 & 8  
4
0F  
04  
06  
0F  
04  
06  
0F  
04  
06  
0F  
04  
06  
0F  
04  
06  
0F  
04  
06  
CAS latency  
= 2 & 3  
19 CS Latencies  
20 WE Latencies  
CS latency =  
0
01  
01  
00  
0E  
A0  
60  
FF  
01  
01  
00  
0E  
F0  
60  
FF  
01  
01  
00  
0E  
F0  
70  
FF  
01  
01  
00  
0E  
A0  
60  
FF  
01  
01  
00  
0E  
F0  
60  
FF  
01  
01  
00  
0E  
F0  
70  
FF  
Write lat-  
ency = 0  
21 SDRAM DIMM module  
attributes  
non buffered/  
non reg.  
22 SDRAM Device Attributes  
:General  
Vcc tol +/-  
10%  
23 Min. Clock Cycle Time at  
CAS Latency = 2  
10.0 / 15.0  
ns  
24 Max. data access time from  
Clock for CL=2  
6.0 / 7.0 ns  
25 Minimum Clock Cycle Time  
at CL = 1  
not suppor-  
ted  
INFINEON Technologies  
13  
HYS64(72)V32200/64220GU  
SDRAM-Modules  
Byte#  
Description  
SPD Entry  
Value  
Hex  
64Mx64 64Mx64 64Mx64 64Mx72 64Mx72 64Mx72  
two  
bank  
-8  
two  
bank  
-8A  
two  
bank  
-8B  
two  
bank  
-8  
two  
bank  
-8A  
two  
bank  
-8B  
26 Maximum Data Access Time not suppor-  
FF  
14  
10  
14  
32  
40  
FF  
14  
14  
14  
32  
40  
FF  
1E  
14  
14  
3C  
40  
FF  
14  
10  
14  
32  
40  
FF  
14  
14  
14  
32  
40  
FF  
1E  
14  
14  
3C  
40  
from Clock at CL=1  
ted  
27 Minimum Row Precharge  
Time  
20 / 30 ns  
28 Minimum Row Active to Row  
Active delay tRRD  
16 / 20 ns  
20 ns  
29 Minimum RAS to CAS delay  
tRCD  
30 Minimum RAS pulse width  
tRAS  
50 / 60 ns  
256 MByte  
31 Module Bank Density (per  
bank)  
32 SDRAM input setup time  
33 SDRAM input hold time  
2 ns  
1 ns  
2 ns  
20  
10  
20  
20  
10  
20  
20  
10  
20  
20  
10  
20  
20  
10  
20  
20  
10  
20  
34 SDRAM data input setup  
time  
35 SDRAM data input hold time  
1 ns  
10  
10  
FF  
10  
FF  
10  
FF  
10  
10  
FF  
36-61 Superset information (may  
be used in future)  
FF  
FF  
62 SPD Revision  
Revision 1.2  
12  
9A  
XX  
12  
EE  
XX  
12  
E2  
XX  
12  
AC  
XX  
12  
00  
12  
24  
XX  
63 Checksum for bytes 0 - 62  
64- Manufacturers information  
125  
XX  
126 Frequency Specification  
127 100 MHz support details  
128+ Unused storage locations  
100 MHz  
64  
FF  
FF  
64  
FD  
FF  
64  
FD  
FF  
64  
FF  
FF  
64  
FD  
FF  
64  
FD  
FF  
INFINEON Technologies  
14  
HYS64(72)V32200/64220GU  
SDRAM-Modules  
L-DIM-168-30  
SDRAM DIMM Module package  
133,35  
127,35  
4,0  
x)  
84  
1
10 11  
40 41  
+ 0.1  
42,18  
1,27  
-
66,68  
A
C
B
85  
94 95  
124 125  
168  
x)  
D
6,35  
6,35  
1,27  
1,0 + 0.5  
-
+
0,2 0,15  
-
2,0  
2,0  
Detail C  
Detail A  
Detail B  
DM168-30.WMF  
2.26  
RADIUS  
x) on ECC modules only  
1.27 + 0.10  
Detail D  
GLD09159  
INFINEON Technologies  
15  
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