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Data Sheet, Rev. 1.20, Mar. 2006

HYS72D64301HBR–[5/6]–C

HYS72D128x00HBR–[5/6]–C

HYS72D128321HBR–[5/6]–C

HYS72D256x20HBR–[5/6]–C

184-Pin Registered Double-Data-Rate SDRAM Module

RDIMM

DDR SDRAM

RoHS Compliant

Memory Products

Edition 2006-03

Published by Infineon Technologies AG,

St.-Martin-Strasse 53,

81669 München, Germany

Attention please!

The information herein is given to describe certain components and shall not be considered as a guarantee of

characteristics.

Terms of delivery and rights to technical change reserved.

We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding

circuits, descriptions and charts stated herein.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest

Infineon Technologies Office (www.infineon.com).

Warnings

Due to technical requirements components may contain dangerous substances. For information on the types in

question please contact your nearest Infineon Technologies Office.

Infineon Technologies Components may only be used in life-support devices or systems with the express written

approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure

of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support

devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain

and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may

be endangered.

HYS72D64301HBR–[5/6]–C, HYS72D128x00HBR–[5/6]–C, HYS72D128321HBR–[5/6]–C,

HYS72D256x20HBR–[5/6]–C

Revision History: 2006-03, Rev. 1.20

Previous Version: Rev. 1.10

Page

8

Subjects (major changes since last revision)

added product types to PC2700R

We Listen to Your Comments

Any information within this document that you feel is wrong, unclear or missing at all?

Your feedback will help us to continuously improve the quality of this document.

Please send us your proposal (including a reference to this document) to:

techdoc.mp@infineon.com

Template: mp_a4_s_rev314 / 3 / 2005-05-02

HYS72D[64/128/256]xxxHBR–[5/6]–C

Registered Double-Data-Rate SDRAM Module

Table of Contents

List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1

1.1

1.2

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3

3.1

3.2

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

AC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4

5

6

SPD Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Application Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Data Sheet

4

Rev. 1.20, 2006-03

07212004-3T0H-0Z61

HYS72D[64/128/256]xxxHBR–[5/6]–C

Registered Double-Data-Rate SDRAM Module

List of Tables

Table 1

Table 2

Table 3

Table 4

Table 5

Table 6

Table 7

Table 8

Table 9

Table 10

Table 11

Table 12

Table 13

Table 14

Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Address Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Pin Configuration of RDIMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Abbreviations for Pin Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Abbreviations for Buffer Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Electrical Characteristics and DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

IDD Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

IDD Specification for HYS72D[64/128/256]xxxHBR–5–C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

I

_DDSpecification for HYS72D[64/128/256]xxxHBR–6–C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

AC Timing - Absolute Specifications for PC3200 and PC2700 . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

SPD Codes for HYS72D[64/128/256]3[00/01/20/21]HBR–5–C . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

SPD Codes for HYS72D[64/128/256]3[00/01/20/21]HBR–6–C . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

SPD Codes for HYS72D[128/256]90x0HBR–6–C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

The function for RESET is as follows: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Data Sheet

5

Rev. 1.20, 2006-03

07212004-3T0H-0Z61

HYS72D[64/128/256]xxxHBR–[5/6]–C

Registered Double-Data-Rate SDRAM Module

List of Figures

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Pin Configuration 184 Pins, Reg. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Block Diagram RDIMM ×72, 1 Rank, ×8, Raw Card A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Block Diagram ×72 1 Rank ×4, ECC, Raw Card C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Block Diagram ×72, 2 Ranks ×8, ECC, Raw Card B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Block Diagram ×72 2 Ranks ×4, ECC, Raw Card F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Package Outline Raw Card A - L-DIM-184-21-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Package Outline Raw Card C - L-DIM-184-22-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Package Outline Raw Card B - L-DIM-184-23-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Package Outline Raw Card F – L-DIM-184-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Data Sheet

6

Rev. 1.20, 2006-03

07212004-3T0H-0Z61

184-Pin Registered Double-Data-Rate SDRAM Module

RDIMM

HYS72D64301HBR–[5/6]–C

HYS72D128x00HBR–[5/6]–C

HYS72D128321HBR–[5/6]–C

HYS72D256x20HBR–[5/6]–C

1

Overview

1.1

Features

•

184-Pin Registered 8-Byte Dual-In-Line DDR SDRAM Module for PC, Workstation and Server main memory

applications

•

One rank 64M ×72, 128M ×72 organization , and two ranks 256M ×72 organization

Standard Double Data Rate Synchronous DRAMs (DDR SDRAM) with a single + 2.5 V (± 0.2 V) power supply

and +2.6 (± 0.1 V) power supply for DDR400

•

Built with DDR SDRAMs in FBGA 60 package

Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave)

Auto Refresh (CBR) and Self Refresh

RAS-lockout supported t_RAP= t_RCD

All inputs and outputs SSTL_2 compatible

Re-drive for all input signals using register and PLL devices.

Serial Presence Detect with E²PROM

Low Profile Modules form factor: 133.35 mm × 28.58 mm (1.1”) × 4.00 mm and 133.35 mm × 30.48 mm (1.2”)

Standard reference card layout Raw Card A, B, C and F

Gold plated contacts

RoHS Compliant Product¹⁾

Table 1

Performance

Part Number Speed Code

–5

–6

Unit

—

Speed Grade

Component

Module

DDR400B

PC3200–3033

200

DDR333B

PC2700–2533

166

—

max. Clock Frequency

@CL3

f_CK3

MHz

@CL2.5

@CL2

f_CK2.5

f_CK2

166

133

1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic

equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January

2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and

polybrominated biphenyl ethers.

Data Sheet

7

Rev. 1.20, 2006-03

07212004-3T0H-0Z61

HYS72D[64/128/256]xxxHBR–[5/6]–C

Registered Double-Data-Rate SDRAM Module

Overview

1.2

Description

The HYS72D[64/128/256]xxxHBR–[5/6]–C are low- register devices and a PLL for the clock distribution.

profile versions of the standard Registered DIMM This reduces capacitive loading to the system bus, but

modules with 1.1-inch (28.58) and 1.2-inch (30,40-mm) adds one cycle to the SDRAM timing. A variety of

height for Server Applications. The low-profile DIMM decoupling capacitors are mounted on the PC board.

versions are available as 64M ×72, 128M ×72 (1 GB), The DIMMs feature serial presence detect based on a

and 256M ×72 (2 GB).

The memory array is designed with Double-Data-Rate first

serial E²PROM device using the 2-pin I²C protocol. The

128 bytes contain factory programmed

Synchronous DRAMs for ECC applications. All control configuration data and the second 128 bytes are made

and address signals are re-driven on the DIMM using available to the customer.

Table 2

Ordering Information

Product Type¹⁾

Compliance Code²⁾Description

SDRAM Technology

PC3200 (CL=3)

HYS72D64301HBR–5–C PC3200R–30331–A0 one rank 512 MByte Reg. ECC DIMM 512 MBit (×8)

HYS72D128300HBR–5–C PC3200R–30331–C0 one rank 1 GByte Reg. ECC DIMM 512 MBit (×4)

HYS72D128321HBR–5–C PC3200R–30331–B0 two ranks 1 GByte Reg. ECC DIMM 512 MBit (×8)

HYS72D256320HBR–5–C PC3200R–30331–F0 two ranks 2 GByte Reg. ECC DIMM 512 MBit (×4)

PC2700 (CL=2.5)

HYS72D64301HBR–6–C PC2700R–25331–A0 one rank 512 MByte Reg. ECC DIMM 512 MBit (×8)

HYS72D128300HBR–6–C PC2700R–25331–C0 one rank 1 GByte Reg. ECC DIMM

HYS72D128900HBR–6–C PC2700R–25331–C0 one rank 1 GByte Reg. ECC DIMM

512 MBit (×4)

HYS72D128321HBR–6–C PC2700R–25331–B0 two ranks 1 GByte Reg. ECC DIMM 512 MBit (×8)

HYS72D256320HBR–6–C PC2700R–25331–F0 two ranks 2 GByte Reg. ECC DIMM 512 MBit (×4)

HYS72D256920HBR–6–C PC2700R–25331–F0 two ranks 2 GByte Reg. ECC DIMM 512 MBit (×4)

1) All product types end with a place code designating the silicon-die revision. Reference information available on request.

Example: HYS72D128300GBR-5-B, indicating Rev.B die are used for SDRAM components.

2) The Compliance Code is printed on the module labels and describes the speed sort (for example “PC2700R”), the latencies

(for example “25331” means CAS latency of 2.5 clocks, Row-Column-Delay (RCD) latency of 3 clocks and Row Precharge

latency of 3 clocks), JEDEC SPD code definition version 1, and the Raw Card used for this module.

Table 3

Address Format

Density Organization Memory

Ranks

SDRAMs # of

SDRAMs

# of row/bank/ Refresh Period Interval

column bits

512 MB 64M ×72

1

2

64M ×8

128M ×4 18

64M ×8 18

128M ×4 36

9

13/2/12

13/2/11

13/2/12

8K

64 ms 7.8 ms

1 GB

2 GB

128M ×72

256M ×72

Data Sheet

8

Rev. 1.20, 2006-03

07212004-3T0H-0Z61

HYS72D[64/128/256]xxxHBR–[5/6]–C

Registered Double-Data-Rate SDRAM Module

Pin Configuration

2

Pin Configuration

The pin configuration of the Registered DDR SDRAM DIMM is listed by function in Table 4 (184 pins). The

abbreviations used in columns Pin and Buffer Type are explained in Table 5 and Table 6 respectively. The pin

numbering is depicted in Chapter 1.

Table 4

Pin# Name Pin

Type Type

Pin Configuration of RDIMM (cont’d)

Table 4

Pin Configuration of RDIMM

Buffer Function

Pin# Name Pin

Buffer Function

Type Type

125 A6

29 A7

122 A8

27 A9

I

SSTL Address Bus 11:0

Clock Signals

137 CK0

SSTL

I

SSTL Clock Signal

SSTL

138 CK0

SSTL Complement Clock

SSTL Clock Enable Rank 0

SSTL Clock Enable Rank 1

Note: 2-rank module

SSTL

21

CKE0

141 A10

AP

SSTL

111 CKE1

SSTL

118 A11

115 A12

SSTL

NC

SSTL Note: 1-rank module

SSTL Address Signal 12

Control Signals

Note:Module based on

256 Mbitorlarger

dies

157 S0

158 S1

I

SSTL Chip Select of Rank 0

SSTL Chip Select of Rank 1

Note: 2-ranks module

NC

I

–

Note:128 Mbit based

module

NC

–

Note: 1-rank module

167 A13

SSTL Address Signal 13

154 RAS

I

SSTL Row Address Strobe

Note:1 Gbit based

module

65

CAS

SSTL Column Address

Strobe

NC

–

Note:Module based on

512 Mbit or

63

10

WE

I

SSTL Write Enable

RESET I

LV-

Register Reset

smaller dies

CMOS Forces registered

inputs low

Data Signals

2

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9

I/O

SSTL Data Bus 63:0

SSTL

Note: For detailed

description of the

Power Up and

Power

Managementsee

the Application

Note at the end of

data sheet

4

6

SSTL

8

SSTL

94

95

98

99

12

13

19

20

SSTL

Address Signals

SSTL

59

52

48

43

41

BA0

BA1

A0

I

SSTL Bank Address Bus

SSTL

1:0

SSTL

SSTL Address Bus 11:0

DQ10 I/O

DQ11 I/O

SSTL

A1

SSTL

A2

105 DQ12 I/O

106 DQ13 I/O

109 DQ14 I/O

SSTL

130 A3

SSTL

37

32

A4

A5

SSTL

Data Sheet

9

Rev. 1.20, 2006-03

07212004-3T0H-0Z61

HYS72D[64/128/256]xxxHBR–[5/6]–C

Registered Double-Data-Rate SDRAM Module

Pin Configuration

Table 4

Pin Configuration of RDIMM (cont’d)

Table 4

Pin Configuration of RDIMM (cont’d)

Pin# Name Pin

Buffer Function

Pin# Name Pin

Buffer Function

Type Type

110 DQ15 I/O

SSTL Data Bus 63:0

SSTL

171 DQ55 I/O

SSTL Data Bus 63:0

23

24

28

31

DQ16 I/O

DQ17 I/O

DQ18 I/O

DQ19 I/O

83

84

87

88

DQ56 I/O

DQ57 I/O

DQ58 I/O

DQ59 I/O

SSTL

114 DQ20 I/O

117 DQ21 I/O

121 DQ22 I/O

123 DQ23 I/O

174 DQ60 I/O

175 DQ61 I/O

178 DQ62 I/O

179 DQ63 I/O

SSTL

33

35

39

40

DQ24 I/O

DQ25 I/O

DQ26 I/O

DQ27 I/O

44

45

49

51

CB0

CB1

CB2

CB3

I/O

SSTL Check Bits 7:0

SSTL

126 DQ28 I/O

127 DQ29 I/O

131 DQ30 I/O

133 DQ31 I/O

134 CB4

135 CB5

142 CB6

144 CB7

SSTL

53

55

57

60

DQ32 I/O

DQ33 I/O

DQ34 I/O

DQ35 I/O

5

DQS0 I/O

DQS1 I/O

DQS2 I/O

DQS3 I/O

DQS4 I/O

DQS5 I/O

DQS6 I/O

DQS7 I/O

DQS8 I/O

SSTL Data Strobes 8:0

14

25

36

56

67

78

86

47

97

SSTL

Note:See block

diagram for

corresponding

DQ signals

146 DQ36 I/O

147 DQ37 I/O

150 DQ38 I/O

151 DQ39 I/O

SSTL Data Strobes 8:0

SSTL

61

64

68

69

DQ40 I/O

DQ41 I/O

DQ42 I/O

DQ43 I/O

SSTL

DM0

I

SSTL Data Mask 0

Note:×8 based module

SSTL Data Strobe 9

Note:×4 based module

SSTL Data Mask 1

Note:×8 based module

SSTL Data Strobe 10

Note:×4 based module

SSTL Data Mask 2

Note:×8 based module

SSTL Data Strobe 11

Note:×4 based module

DQS9

I/O

I

153 DQ44 I/O

155 DQ45 I/O

161 DQ46 I/O

162 DQ47 I/O

107 DM1

DQS10 I/O

72

73

79

80

DQ48 I/O

DQ49 I/O

DQ50 I/O

DQ51 I/O

119 DM2

I

DQS11 I/O

165 DQ52 I/O

166 DQ53 I/O

170 DQ54 I/O

Data Sheet

10

Rev. 1.20, 2006-03

07212004-3T0H-0Z61

HYS72D[64/128/256]xxxHBR–[5/6]–C

Registered Double-Data-Rate SDRAM Module

Pin Configuration

Table 4

Pin# Name Pin

Type Type

SSTL Data Mask 3

Note: ×8 based module

SSTL Data Strobe 12

Note: ×4 based module

SSTL Data Mask 4

Note: ×8 based module

SSTL Data Strobe 13

Note: ×4 based module

SSTL Data Mask 5

Note: ×8 based module

SSTL Data Strobe 14

Note: ×4 based module

SSTL Data Mask 6

Note: ×8 based module

SSTL Data Strobe 15

Note: ×4 based module

SSTL Data Mask 7

Note: ×8 based module

SSTL Data Strobe 16

Note: ×4 based module

SSTL Data Mask 8

Note: ×8 based module

SSTL Data Strobe 17

Note: ×4 based module

Pin Configuration of RDIMM (cont’d)

Table 4

Pin# Name Pin

Type Type

PWR –

Pin Configuration of RDIMM (cont’d)

Buffer Function

129 DM3

I

15, V_DDQ

22,

I/O Driver Power

Supply

30,

54,

62,

77,

DQS12 I/O

149 DM4

I

96,

104,

112,

128,

136,

143,

156,

164,

172,

180

DQS13 I/O

159 DM5

I

DQS14 I/O

169 DM6

I

7,

V_DD

PWR –

Power Supply

DQS15 I/O

38,

46,

70,

85,

108,

120,

148,

168

177 DM7

I

DQS16 I/O

140 DM8

I

3,

V_SS

GND

–

Ground Plane

11,

18,

26,

34,

DQS17 I/O

EEPROM

92

91

SCL

SDA

I

CMOS Serial Bus Clock

OD Serial Bus Data

CMOS Slave Address Select

42,

50,

58,

66,

74,

81,

I/O

181 SA0

182 SA1

183 SA2

I

Bus 2:0

CMOS

Power Supplies

AI

89,

93,

1

V_REF

–

I/O Reference Voltage

100,

116,

124,

132,

139,

145,

152,

160,

176

184 V_DDSPDPWR –

EEPROM Power

Supply

Data Sheet

11

Rev. 1.20, 2006-03

07212004-3T0H-0Z61

HYS72D[64/128/256]xxxHBR–[5/6]–C

Registered Double-Data-Rate SDRAM Module

Pin Configuration

Table 4

Pin# Name Pin

Type Type

Pin Configuration of RDIMM (cont’d)

Table 5

Abbreviations for Pin Type

Buffer Function

Abbreviatio Description

n

Other Pins

I

Standard input-only pin. Digital levels.

82

V_DDID

O

OD

V_DDIdentification

O

Output. Digital levels.

I/O is a bidirectional input/output signal.

Input. Analog levels.

Note: Pin in tristate,

indicating V_DD

and V_DDQnets

connected on

PCB

I/O

AI

PWR

GND

NU

NC

Power

Ground

9,

NC

–

Not connected

Pins not connected on

Infineon RDIMM’s

Not Usable (JEDEC Standard)

Not Connected (JEDEC Standard)

16,

17,

71,

75,

Table 6

Abbreviations for Buffer Type

76,

90,

Abbreviatio Description

n

101,

102,

103,

113,

163,

173

SSTL

Serial Stub Terminalted Logic (SSTL2)

LV-CMOS

CMOS

OD

Low Voltage CMOS

CMOS Levels

Open Drain. The corresponding pin has

2 operational states, active low and

tristate, and allows multiple devices to

share as a wire-OR.

Data Sheet

12

Rev. 1.20, 2006-03

07212004-3T0H-0Z61

HYS72D[64/128/256]xxxHBR–[5/6]–C

Registered Double-Data-Rate SDRAM Module

Pin Configuration

V_SS

Pin 093 -

Pin 094 - DQ04

Pin 095 - DQ05

V

_REF- Pin 001

- Pin 003

DQ00 - Pin 002

DQ01 - Pin 004

DQ02 - Pin 006

DQ03 - Pin 008

RESET - Pin 010

DQ08 - Pin 012

DQS1 - Pin 014

NC - Pin 016

V

SS

V

Pin 096 -

DDQ

DQS0 - Pin 005

Pin 097 - DQ00/DQS9

Pin 099 - DQ07

Pin 101 - NC

Pin 098 - DQ06

V

_DD- Pin 007

V

Pin 100 -

SS

NC - Pin 009

Pin 102 - NC

V

_SS- Pin 011

Pin 103 - NC

V

Pin 104 -

DDQ

DQ09 - Pin 013

Pin 105 - DQ15

Pin 107 - DM1/DQS10

Pin 109 - DQ14

Pin 111 - CKE1/NC

Pin 113 - NC

Pin 106 - DQ13

V

_DDQ- Pin 015

V

Pin 108 -

DD

NC - Pin 017

DQ10 - Pin 019

CKE0 - Pin 021

DQ16 - Pin 023

DQS2 - Pin 025

A9 - Pin 027

V

_SS- Pin 018

Pin 110 - DQ15

V

DQ11 - Pin 020

Pin 112 -

Pin 114 - DQ20

V_SS

DDQ

V

_DDQ- Pin 022

Pin 115 - A12/NC

Pin 117 - DQ21

Pin 119 - DM2/DQS11

Pin 121 - DQ22

Pin 123 - DQ23

Pin 125 - A6

DQ17 - Pin 024

Pin 116 -

Pin 118 - A11

V

_SS- Pin 026

V

DQ18 - Pin 028

Pin 120 -

Pin 122 - A8

DD

A7 - Pin 029

V

_DDQ- Pin 030

DQ19 - Pin 031

DQ24 - Pin 033

DQ25 - Pin 035

A4 - Pin 037

V_SS

A5 - Pin 032

Pin 124 -

V

_SS- Pin 034

Pin 126 - DQ28

Pin 127 - DQ29

Pin 129 - DM3/DQS12

Pin 131 - DQ30

Pin 133 - DQ31

Pin 135 - CB5

V_DDQ

DQS3 - Pin 036

Pin 128 -

Pin 130 - A3

V

_DD- Pin 038

DQ26 - Pin 039

A2 - Pin 041

V

DQ27 - Pin 040

Pin 132 -

Pin 134 - DQ04

V_DDQ

Pin 136 -

SS

V

_SS- Pin 042

A1 - Pin 043

CB00 - Pin 044

CB01 - Pin 045

DQS8 - Pin 047

CB02 - Pin 049

CB03 - Pin 051

Pin 137 - CK0

V

_DD- Pin 046

Pin 138 - CK0

Pin 139 - V_SS

A0 - Pin 048

Pin 140 - DM8/DQS17

Pin 142 - CB06

Pin 144 - CB07

Pin 141 - A10/AP

V

_SS- Pin 050

V

Pin 143 -

DDQ

BA1 - Pin 052

V

-

DQ32 Pin 053

Pin 145

SS

-

Pin 146 DQ36

V

_DDQ- Pin 054

-

DQ33 Pin 055

Pin 147 DQ37

-

Pin 148

V

DD

DQS4

V_SS

- Pin 056

- Pin 058

- Pin 060

-

Pin 149 DM4/DQS13

-

DQ34 Pin 057

-

Pin 150 DQ38

-

Pin 151 DQ39

-

BA0 Pin 059

-

Pin 152 V_SS

DQ35

V

-

Pin 153 DQ44

-

DQ40 Pin 061

-

Pin 154 RAS

_DDQ- Pin 062

-

Pin 155 DQ45

-

WE Pin 063

-

Pin 156 V_DDQ

DQ41

- Pin 064

-

Pin 157 S0

-

CAS Pin 065

-

Pin 158 S1/NC

V

_SS- Pin 066

-

Pin 159 DM5/DQS14

-

DQS5 Pin 067

-

Pin 160

V

SS

DQ42

V_DD

- Pin 068

- Pin 070

- Pin 072

-

Pin 161 DQ46

-

DQ43 Pin 069

-

Pin 162 DQ47

-

Pin 163 NC

-

NC Pin 071

-

Pin 164 V_DDQ

DQ48

V

-

Pin 165 DQ52

-

DQ49 Pin 073

-

Pin 166 DQ53

_SS- Pin 074

-

Pin 167 A13/NC

-

NC Pin 075

-

Pin 168

V

DD

NC

- Pin 076

- Pin 078

- Pin 080

- Pin 082

- Pin 084

- Pin 086

- Pin 088

- Pin 090

- Pin 092

V

-

Pin 169 DM6/DQS15

-

Pin 077

DDQ

-

Pin 170 DQ54

DQS6

-

Pin 171 DQ55

-

DQ50 Pin 079

-

Pin 172

V

DDQ

DQ51

V_DDID

V_SS

-

Pin 173 NC

-

Pin 081

-

Pin 174 DQ60

-

Pin 175 DQ61

-

DQ56 Pin 083

-

Pin 176 V_SS

DQ57

DQS7

DQ59

NC

V_DD

-

Pin 177 DM7/DQS16

-

Pin 085

-

Pin 178 DQ62

-

Pin 179 DQ63

-

DQ58 Pin 087

-

Pin 180

V

DDQ

V

-

Pin 181 SA0

-

Pin 089

SS

-

Pin 182 SA1

-

Pin 183 SA2

-

SDA Pin 091

-

Pin 184

V

DDSPD

SCL

MPPD0020

Figure 1

Pin Configuration 184 Pins, Reg

Data Sheet

13

Rev. 1.20, 2006-03

07212004-3T0H-0Z61

HYS72D[64/128/256]xxxHBR–[5/6]–C

Registered Double-Data-Rate SDRAM Module

Pin Configuration

&.ꢁ

3&.

3//

6ꢁ

56ꢁ

&6ꢌꢋ6'5$0Vꢋ'ꢁꢍꢋ'ꢊ

&.(ꢁ

%$ꢁꢋꢍꢋ%$ꢀ

$ꢁꢋꢍꢋ$Q

5$6

5&.(ꢁ

5%$ꢁꢋꢍꢋ5%$ꢀ

5$ꢁꢍ5$Q

55$6

&.(ꢌꢋ6'5$0Vꢋ'ꢁꢋꢍꢋ'ꢊ

%$ꢁꢋꢍꢋ%$ꢀꢌꢋ6'5$0Vꢋ'ꢁꢋꢍꢋ'ꢊ

$ꢁꢋꢍꢋ$Qꢌꢋ6'5$0Vꢋ'ꢁꢋꢍꢋ'ꢊ

5$6ꢌꢋ6'5$0Vꢋ'ꢁꢋꢍꢋ'ꢊ

&$6ꢌꢋ6'5$0Vꢋ'ꢁꢋꢍꢋ'ꢊ

:(ꢌꢋ6'5$0Vꢋ'ꢁꢋꢍꢋ'ꢊ

5

(

*

,

&$6

5&$6

6

7

(

5

:(

5:(

3&.

5(6(7

6ꢁ

'ꢆ

'ꢂ

'ꢁ

'0ꢁꢃ'46ꢄ

'46ꢁ

'4ꢁ

'0ꢆꢃ'46ꢀꢅ

ꢋ'0ꢋꢋꢋꢋꢋ&6

'0ꢂꢃ'46ꢀꢈ

'46ꢂ

'4ꢇꢊ

ꢋ'0ꢋꢋꢋꢋꢋ&6

'46ꢆ

'4ꢅꢇ

'4ꢅꢈ

'4ꢅꢂ

'4ꢅꢉ

'4ꢅꢊ

'4ꢅꢄ

'4ꢆꢁ

'4ꢆꢀ

ꢋ'46ꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋ

ꢋ,ꢃ2ꢋꢁ

ꢋ'46ꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋ

ꢋ,ꢃ2ꢋꢁ

ꢋ'46ꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋ

ꢋ,ꢃ2ꢋꢁ

'4ꢀ

ꢋ,ꢃ2ꢋꢀꢋꢋꢋꢋꢋꢋꢋ

ꢋ,ꢃ2ꢋꢅ

'4ꢇꢄ

ꢋ,ꢃ2ꢋꢀꢋꢋꢋꢋꢋꢋꢋ

ꢋ,ꢃ2ꢋꢅ

ꢋ,ꢃ2ꢋꢀꢋꢋꢋꢋꢋꢋꢋ

ꢋ,ꢃ2ꢋꢅ

'4ꢅ

'4ꢈꢁ

'4ꢆ

ꢋ,ꢃ2ꢋꢆ

'4ꢈꢀ

ꢋ,ꢃ2ꢋꢆ

'4ꢇ

ꢋ,ꢃ2ꢋꢇ

'4ꢈꢅ

ꢋ,ꢃ2ꢋꢇ

'4ꢈ

ꢋ,ꢃ2ꢋꢈ

'4ꢈꢆ

ꢋ,ꢃ2ꢋꢈ

'4ꢂ

ꢋ,ꢃ2ꢋꢂ

'4ꢈꢇ

ꢋ,ꢃ2ꢋꢂ

'4ꢉ

ꢋ,ꢃ2ꢋꢉ

'4ꢈꢈ

ꢋ,ꢃ2ꢋꢉ

'ꢀ

'ꢇ

'ꢉ

ꢋ'0ꢋꢋꢋꢋꢋ&6

'0ꢇꢃ'46ꢀꢆ

'46ꢇ

'4ꢆꢅ

ꢋ'0ꢋꢋꢋꢋꢋ&6

'0ꢉꢃ'46ꢀꢂ

'46ꢉ

'4ꢈꢂ

ꢋ'0ꢋꢋꢋꢋꢋ&6

ꢋ'46ꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋ

ꢋ,ꢃ2ꢋꢁ

ꢋ'46ꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋ

ꢋ,ꢃ2ꢋꢁ

ꢋ'46ꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋ

ꢋ,ꢃ2ꢋꢁ

ꢋ,ꢃ2ꢋꢀꢋꢋꢋꢋꢋꢋꢋ

ꢋ,ꢃ2ꢋꢅ

'4ꢆꢆ

ꢋ,ꢃ2ꢋꢀꢋꢋꢋꢋꢋꢋꢋ

ꢋ,ꢃ2ꢋꢅ

'4ꢈꢉ

ꢋ,ꢃ2ꢋꢀꢋꢋꢋꢋꢋꢋꢋ

ꢋ,ꢃ2ꢋꢅ

'4ꢆꢇ

'4ꢈꢊ

ꢋ,ꢃ2ꢋꢆ

'4ꢆꢈ

ꢋ,ꢃ2ꢋꢆ

'4ꢈꢄ

ꢋ,ꢃ2ꢋꢆ

ꢋ,ꢃ2ꢋꢇ

'4ꢆꢂ

ꢋ,ꢃ2ꢋꢇ

'4ꢂꢁ

ꢋ,ꢃ2ꢋꢇ

ꢋ,ꢃ2ꢋꢈ

'4ꢆꢉ

ꢋ,ꢃ2ꢋꢈ

'4ꢂꢀ

ꢋ,ꢃ2ꢋꢈ

ꢋ,ꢃ2ꢋꢂ

'4ꢆꢊ

ꢋ,ꢃ2ꢋꢂ

'4ꢂꢅ

ꢋ,ꢃ2ꢋꢂ

ꢋ,ꢃ2ꢋꢉ

'4ꢆꢄ

ꢋ,ꢃ2ꢋꢉ

'4ꢂꢆ

ꢋ,ꢃ2ꢋꢉ

'ꢅ

'ꢈ

'ꢊ

ꢋ'0ꢋꢋꢋꢋꢋ&6

'0ꢈꢃ'46ꢀꢇ

'46ꢈ

'4ꢇꢁ

ꢋ'0ꢋꢋꢋꢋꢋ&6

'0ꢊꢃ'46ꢀꢉ

'46ꢊ

&%ꢁ

ꢋ'0ꢋꢋꢋꢋꢋ&6

ꢋ'46ꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋ

ꢋ,ꢃ2ꢋꢁ

ꢋ'46ꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋ

ꢋ,ꢃ2ꢋꢁ

ꢋ'46ꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋꢋ

ꢋ,ꢃ2ꢋꢁ

ꢋ,ꢃ2ꢋꢀꢋꢋꢋꢋꢋꢋꢋ

ꢋ,ꢃ2ꢋꢅ

'4ꢇꢀ

ꢋ,ꢃ2ꢋꢀꢋꢋꢋꢋꢋꢋꢋ

ꢋ,ꢃ2ꢋꢅ

&%ꢀ

ꢋ,ꢃ2ꢋꢀꢋꢋꢋꢋꢋꢋꢋ

ꢋ,ꢃ2ꢋꢅ

'4ꢇꢅ

&%ꢅ

ꢋ,ꢃ2ꢋꢆ

'4ꢇꢆ

ꢋ,ꢃ2ꢋꢆ

&%ꢆ

ꢋ,ꢃ2ꢋꢆ

ꢋ,ꢃ2ꢋꢇ

'4ꢇꢇ

ꢋ,ꢃ2ꢋꢇ

&%ꢇ

ꢋ,ꢃ2ꢋꢇ

ꢋ,ꢃ2ꢋꢈ

'4ꢇꢈ

ꢋ,ꢃ2ꢋꢈ

&%ꢈ

ꢋ,ꢃ2ꢋꢈ

ꢋ,ꢃ2ꢋꢂ

'4ꢇꢂ

ꢋ,ꢃ2ꢋꢂ

&%ꢂ

ꢋ,ꢃ2ꢋꢂ

ꢋ,ꢃ2ꢋꢉ

'4ꢇꢉ

ꢋ,ꢃ2ꢋꢉ

&%ꢉ

ꢋ,ꢃ2ꢋꢉ

(ꢁ

9_''ꢎ63'

9

_''ꢌꢋ63'ꢋ((3520ꢋ(ꢁ

_''ꢃ9_''4ꢌꢋ6'5$0Vꢋ'ꢁꢋꢍꢋ'ꢊ

₅₍₎ꢌꢋ6'5$0Vꢋ'ꢁꢋꢍꢋ'ꢊ

₆₆ꢌꢋ6'5$0Vꢋ'ꢁꢋꢍꢋ'ꢊ

6&/

6$'

6$ꢁ

6$ꢀ

6$ꢅ

9₆₆

ꢋ6&/ꢋꢋꢋꢋꢋ

9

_''ꢃ9_''4

ꢋ6$'ꢋ

ꢋ$ꢁꢋꢋꢋꢋꢋꢋꢋꢋ

ꢋ$ꢀ

9₅₍₎

9₆₆

ꢋ$ꢅꢋꢋꢋꢋꢋꢋꢋꢋꢋ

ꢋ:3

9_'','

ꢋꢋ

6W

UDSꢌꢋV

HHꢋ1RWHꢋꢀ

03%'ꢀꢀꢁꢀ

Figure 2

Notes

Block Diagram RDIMM ×72, 1 Rank, ×8, Raw Card A

3. BAn, An, RAS, CAS, WE resistors are 22 ohms

±5%

4. For Wire per Clock Loading please see Figure:

“Differential Clock Net Wiring“

1. V_DD= V_DDQ, therefore V_DDIDstrap open

2. DQ, DQS, DM resistors are 22 ohms ±5%

Data Sheet

14

Rev. 1.20, 2006-03

07212004-3T0H-0Z61

HYS72D[64/128/256]xxxHBR–[5/6]–C

Registered Double-Data-Rate SDRAM Module

Pin Configuration

CK0

PCK

PLL

S0

CKE0

BA0 - BA1

A0 - An

RAS

RS0

CS: SDRAMs D0- D17

RCKE0

RBA0 - RBA1

RA0 - RAn

RRAS

CKE: SDRAMs D0 - D17

BA0 - BA1: SDRAMs D0 - D17

A0 - An: SDRAMs D0 - D17

RAS: SDRAMs D0 - D17

CAS: SDRAMs D0 - D17

WE: SDRAMs D0 - D17

R

E

G

I

S

T

E

R

CAS

RCAS

RWE

WE

PCK

RESET

RS0

D0

D1

D2

D3

D4

D5

D6

D12

D13

D14

D15

D16

D17

CS

DQS0

DQ0

DQ1

DQ2

DQ3

DQS

DQS6

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS12

DQ28

DQ29

DQ30

DQ31

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQ48

DQ49

DQ50

DQ51

I/O 0

I/O 1

I/O 2

I/O 3

D7

DQS1

DQ8

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS7

DQ56

DQ57

DQ58

DQ59

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS13

DQ36

DQ37

DQ38

DQ39

DQ9

DQ10

DQ11

D8

DQS2

DQ16

DQ17

DQ18

DQ19

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS8

CB0

CB1

CB2

CB3

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS14

DQ44

DQ45

DQ46

DQ47

DQS

I/O 0

I/O 1

I/O 2

I/O 3

D9

DQS3

DQ24

DQ25

DQ26

DQ27

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS9

DQ4

DQ5

DQ6

DQ7

DQS15

DQ52

DQ53

DQ54

DQ55

D10

D11

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS10

DQ12

DQ13

DQ14

DQ15

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS16

DQ60

DQ61

DQ62

DQ63

DQS4

DQ32

DQ33

DQ34

DQ35

DQS11

DQ20

DQ21

DQ22

DQ23

DQS17

CB4

DQS5

DQ40

DQ41

DQ42

DQ43

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS

I/O 0

I/O 1

I/O 2

I/O 3

CB5

CB6

CB7

E0

V_DD,SPD

V_DD/V_DDQ

V_REF

SCL

SAD

SA0

SA1

SA2

V_SS

SCL

SAD

A0

V_DD: SPD EEPROM E0

V

_DD/V_DDQ: SDRAMs D0 - D17

_REF: SDRAMs D0 - D17

_SS: SDRAMs D0 - D17

A1

V_SS

V_DDID

A2

WP

Strap: see Note 1

MPBD1501

Figure 3

Notes

Block Diagram ×72 1 Rank ×4, ECC, Raw Card C

3. BAn, An, RAS, CAS, WE resistors are 22 ohms

± 5%

4. For Wire per Clock Loading please see Figure:

1. V_DD= V_DDQ, therefore V_DDIDstrap open

2. DQ, DQS, DM resistors are 22 ohms ± 5%

“Differential Clock Net Wiring“

Data Sheet

15

Rev. 1.20, 2006-03

07212004-3T0H-0Z61

HYS72D[64/128/256]xxxHBR–[5/6]–C

Registered Double-Data-Rate SDRAM Module

Pin Configuration

CK0

PCK

PLL

S0

CKE0

S1

RS0

RCKE0

RS1

RCKE1

RBA0 - RBA1

RA0 - RAn

RRAS

R

E

G

I

S

T

E

R

CKE: SDRAMs D0 - D8

CKE1

BA0 - BA1

A0 - An

RAS

CKE: SDRAMs D9 - D17

BA0 - BA1: SDRAMs D0 - D17

A0 - An: SDRAMs D0 - D17

RAS: SDRAMs D0 - D17

CAS: SDRAMs D0 - D17

WE: SDRAMs D0 - D17

E0

SCL

SAD

SA0

SA1

SA2

V_SS

SCL

SAD

A0

CAS

RCAS

RWE

WE

A1

PCK

A2

WP

PCK

RESET

S0

S1

D0

D1

D2

D3

D9

D4

D5

D6

D7

D8

D13

CS

DM

CS

DM0/DQS9

DQS0

DQ0

DM4/DQS13

DM

DQS4

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

DQ1

I/O 1

DQ2

I/O 2

DQ3

I/O 3

DQ4

I/O 4

DQ5

I/O 5

DQ6

I/O 6

DQ7

I/O 7

D10

D11

D12

D14

D15

D16

D17

CS

DM

DM5/DQS14

DQS5

DQ40

DM

DM1/DQS10

DQS1

DQ8

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

DQ41

I/O 1

DQ9

DQ42

I/O 2

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ43

I/O 3

DQ44

I/O 4

DQ45

I/O 5

DQ46

I/O 6

DQ47

I/O 7

CS

DM

DM2/DQS11

DQS2

DQ16

DM6/DQS15

DQS6

DQ48

DM

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

DQ17

DQ49

I/O 1

DQ18

DQ50

I/O 2

DQ19

DQ51

I/O 3

DQ20

DQ52

I/O 4

DQ21

DQ53

I/O 5

DQ22

DQ54

I/O 6

DQ23

DQ55

I/O 7

CS

DM

DM7/DQS16

DQS7

DQ56

DM

DM3/DQS12

DQS3

DQ24

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

DQ57

I/O 1

DQ25

DQ58

I/O 2

DQ26

DQ59

I/O 3

DQ27

DQ60

I/O 4

DQ28

DQ61

I/O 5

DQ29

DQ62

I/O 6

DQ30

DQ63

I/O 7

DQ31

DM8/DQS17

DQS8

CB0

DM

V_DD,SPD

V_DD/V_DDQ

V_REF

V_DD: SPD EEPROM E0

_DD/V_DDQ: SDRAMs D0 - D17

V_REF: SDRAMs D0 - D17

_SS: SDRAMs D0 - D17

DM: SDRAMs D0 - D17

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

V

CB1

CB2

V_SS

V_DDID

V

CB3

CB4

CB5

Strap: see Note 1

CB6

CB7

MPBD1401

Figure 4

Notes

Block Diagram ×72, 2 Ranks ×8, ECC, Raw Card B

3. BAn, An, RAS, CAS, WE resistors are 22 ohms

±5%

4. For Wire per Clock Loading please see Figure:

“Differential Clock Net Wiring“

1. V_DD= V_DDQ, therefore V_DDIDstrap open

2. DQ, DQS, DM resistors are 22 ohms ±5%

Data Sheet

16

Rev. 1.20, 2006-03

07212004-3T0H-0Z61

HYS72D[64/128/256]xxxHBR–[5/6]–C

Registered Double-Data-Rate SDRAM Module

Pin Configuration

CK0

PCK

RS0

RCKE0

RS1

RCKE1

RBA0 - RBA1

RA0-RAn

RRAS

RCAS

RWE

V_DD,SPD

V_DD/V_DDQ

PLL

V_DD: SPD EEPROM E0

V_DD/V_DDQ: SDRAMs D0 - D35

S0

CKE0

S1

V_REF

V_SS

V_DDID

V

_REF: SDRAMs D0 - D35

R

E

G

I

S

T

E

R

V_SS: SDRAMs D0 - D35

DM: SDRAMs D0 - D35

CKE1

BA0 - BA1

A0 - An

RAS

BA0 - BA1: SDRAMs D0 - D35

A0 - An: SDRAMs D0 - D35

RAS: SDRAMs D0 - D35

CAS: SDRAMs D0 - D35

WE: SDRAMs D0 - D35

Strap: see Note 1

E0

SCL

SAD

SA0

SA1

SA2

V_SS

SCL

SAD

A0

CAS

WE

A1

PCK

A2

PCK

WP

RESET

RS0

RCKE0

RS1

RCKE1

D6

D4

D5

D7

CKE CS

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS0

DQ0

DQ1

DQ2

DQ3

DQS7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

DQ56

DQ57

DQ58

DQ59

D2

D0

D1

D3

CKE CS

DQS6

DQ48

DQ49

DQ50

DQ51

DQS1

DQ8

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQ9

DQ10

DQ11

D12

D8

D14

D13

D9

D15

D11

D23

D19

D27

D31

D35

CKE CS

DQS10

DQ12

DQ13

DQ14

DQ15

DQS15

DQ52

DQ53

DQ54

DQ55

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS

I/O 0

I/O 1

I/O 2

I/O 3

D10

D22

D18

D26

D30

D34

CKE CS

DQS9

DQ4

DQ5

DQ6

DQ7

DQS16

DQ60

DQ61

DQ62

DQ63

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS

I/O 0

I/O 1

I/O 2

I/O 3

D20

D16

D24

D28

D32

D21

D17

D25

D28

D33

CKE CS

DQS11

DQ20

DQ21

DQ22

DQ23

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS14

DQ44

DQ45

DQ46

DQ47

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS

I/O 0

I/O 1

I/O 2

I/O 3

CKE CS

DQS2

DQ16

DQ17

DQ18

DQ19

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS5

DQ40

DQ41

DQ42

DQ43

CKE CS

DQS3

DQ24

DQ25

DQ26

DQ27

DQS4

DQ32

DQ33

DQ34

DQ35

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS

I/O 0

I/O 1

I/O 2

I/O 3

CKE CS

DQS17

CB4

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS8

CB0

CB1

CB2

CB3

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS

I/O 0

I/O 1

I/O 2

I/O 3

CB5

CB6

CB7

CKE CS

DQS12

DQ28

DQ29

DQ30

DQ31

DQS13

DQ36

DQ37

DQ38

DQ39

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS

I/O 0

I/O 1

I/O 2

I/O 3

MPBD1061

Figure 5

Notes

Block Diagram ×72 2 Ranks ×4, ECC, Raw Card F

3. BAn, An, RAS, CAS, WE resistors are 22 ohms ± 5%

4. For Wire per Clock Loading please see Figure:

“Differential Clock Net Wiring“

1. V_DD= V_DDQ, therefore V_DDIDstrap open

2. DQ, DQS, DM resistors are 18 ohms ± 5%

Data Sheet

17

Rev. 1.20, 2006-03

07212004-3T0H-0Z61

HYS72D[64/128/256]xxxHBR–[5/6]–C

Registered Double-Data-Rate SDRAM Module

Electrical Characteristics

3

Electrical Characteristics

3.1

Operating Conditions

Table 7

Absolute Maximum Ratings

Parameter

Symbol

Values

Unit Note/ Test

Condition

min.

V_IN, V_OUT–0.5

typ. max.

Voltage on I/O pins relative to V_SS

Voltage on inputs relative to V_SS

Voltage on V_DDsupply relative to V_SS

Voltage on V_DDQsupply relative to V_SS

Operating temperature (ambient)

Storage temperature (plastic)

–

V

_DDQ+ 0.5

V

–

V_IN

–1

0

–

+3.6

+70

+150

–

V

V_DD

V_DDQ

T_A

–

V

–

V

–

°C

W

mA

T_STG

PD

-55

–

Power dissipation (per SDRAM component)

Short circuit output current

1

I_OUT

–

50

–

Attention: Permanent damage to the device may occur if “Absolute Maximum Ratings” are exceeded. This

is a stress rating only, and functional operation should be restricted to recommended operation

conditions. Exposure to absolute maximum rating conditions for extended periods of time may

affect device reliability and exceeding only one of the values may cause irreversible damage to

the integrated circuit.

Table 8

Electrical Characteristics and DC Operating Conditions

Parameter

Symbol

Values

Typ.

Unit Note/Test Condition ¹⁾

Min.

2.3

Max.

2.7

Device Supply Voltage

Output Supply Voltage

EEPROM supply voltage

V_DD

2.5

2.6

2.5

2.6

2.5

V

VDD

V_DDQ

2.5

2.7

V

f

_CK> 166 MHz ²⁾

3)

2.3

VDDQ 2.5

2.7

3.6

f

_CK> 166 MHz ²⁾³⁾

VDDSP 2.3

D

—

Supply Voltage, I/O Supply V_SS,

0

V

—

Voltage

V_SSQ

V_REF

V_TT

4)

5)

Input Reference Voltage

0.49 × V_DDQ0.5 × V_DDQ0.51 × V_DDQ

V

I/O Termination Voltage

(System)

V_REF– 0.04

V_REF+ 0.04 V

6)

Input High (Logic1) Voltage V_IH(DC)

Input Low (Logic0) Voltage V_IL(DC)

V_REF+ 0.15

–0.3

V_DDQ+ 0.3

V

V_REF– 0.15 V

Input Voltage Level,

CK and CK Inputs

V_IN(DC)

–0.3

V_DDQ+ 0.3

V_DDQ+ 0.6

V

6)7)

Input Differential Voltage, V_ID(DC)

CK and CK Inputs

0.36

Data Sheet

18

Rev. 1.20, 2006-03

07212004-3T0H-0Z61

HYS72D[64/128/256]xxxHBR–[5/6]–C

Registered Double-Data-Rate SDRAM Module

Electrical Characteristics

Table 8

Electrical Characteristics and DC Operating Conditions

Parameter

Symbol

Values

Typ.

Unit Note/Test Condition ¹⁾

Min.

Max.

8)

VI-Matching Pull-up

Current to Pull-down

Current

VI_Ratio

0.71

1.4

—

Input Leakage Current

I_I

–2

2

µA Any input 0 V ≤ V_IN≤ V_DD;

All other pins not under test

= 0 V ⁹⁾

Output Leakage Current

I_OZ

I_OH

I_OL

–5

5

µA DQs are disabled;

9)

0 V ≤ V_OUT≤ V_DDQ

Output High Current,

Normal Strength Driver

—

–16.2

—

mA V_OUT

=

1.95 V

Output Low

16.2

mA V_OUT= 0.35 V

Current, Normal Strength

Driver

1) 0 °C ≤ T_A≤ 70 °C; V_DDQ= 2.5 V ± 0.2 V, V_DD= +2.5 V ± 0.2 V; VDDQ = 2.6 V ± 0.1 V, VDD = +2.6 V ± 0.1 V (DDR400);

2) DDR400 conditions apply for all clock frequencies above 166 MHz

3) Under all conditions, V_DDQmust be less than or equal to V_DD

.

4) Peak to peak AC noise on V_REFmay not exceed ± 2% VREF (DC). VREF is also expected to track noise variations in V_DDQ

.

5) V_TTis not applied directly to the device. V_TTis a system supply for signal termination resistors, is expected to be set equal

to V_REF, and must track variations in the DC level of V_REF

6) Inputs are not recognized as valid until V_REFstabilizes.

.

7) V_IDis the magnitude of the difference between the input level on CK and the input level on CK.

8) The ratio of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire

temperature and voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the

maximum difference between pull-up and pull-down drivers due to process variation.

9) Values are shown per pin.

IDD Conditions

Parameter

Symbol

Operating Current 0

I_DD0

one bank; active/ precharge; DQ, DM, and DQS inputs changing once per clock cycle;

address and control inputs changing once every two clock cycles.

Operating Current 1

I_DD1

one bank; active/read/precharge; Burst Length = 4; see component data sheet.

Precharge Power-Down Standby Current

all banks idle; power-down mode; CKE ≤ V_IL,MAX

I_DD2P

I_DD2F

Precharge Floating Standby Current

CS ≥ V_IH,,MIN, all banks idle; CKE ≥ V_IH,MIN

;

address and other control inputs changing once per clock cycle; V_IN= V_REFfor DQ, DQS and DM.

Precharge Quiet Standby Current

I_DD2Q

CS ≥ V_IHMIN, all banks idle; CKE ≥ V_IH,MIN; V_IN= V_REFfor DQ, DQS and DM;

address and other control inputs stable at ≥ V_IH,MINor ≤ V_IL,MAX

.

Active Power-Down Standby Current

I_DD3P

one bank active; power-down mode; CKE ≤ V_ILMAX; V_IN= V_REFfor DQ, DQS and DM.

Data Sheet

19

Rev. 1.20, 2006-03

07212004-3T0H-0Z61

HYS72D[64/128/256]xxxHBR–[5/6]–C

Registered Double-Data-Rate SDRAM Module

Electrical Characteristics

IDD Conditions

Parameter

Symbol

Active Standby Current

I_DD3N

one bank active; CS ≥ V_IH,MIN; CKE ≥ V_IH,MIN; t_RC= t_RAS,MAX

DQ, DM and DQS inputs changing twice per clock cycle;

address and control inputs changing once per clock cycle.

;

Operating Current Read

I_DD4R

one bank active; Burst Length = 2; reads; continuous burst;

address and control inputs changing once per clock cycle;

50% of data outputs changing on every clock edge;

CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B; I_OUT= 0 mA

Operating Current Write

I_DD4W

one bank active; Burst Length = 2; writes; continuous burst;

address and control inputs changing once per clock cycle;

50% of data outputs changing on every clock edge;

CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B

Auto-Refresh Current

I_DD5

I_DD6

I_DD7

t

_RC= t_RFCMIN, burst refresh

Self-Refresh Current

CKE ≤ 0.2 V; external clock on

Operating Current 7

four bank interleaving with Burst Length = 4; see component data sheet.

Data Sheet

20

Rev. 1.20, 2006-03

07212004-3T0H-0Z61

HYS72D[64/128/256]xxxHBR–[5/6]–C

Registered Double-Data-Rate SDRAM Module

Electrical Characteristics

IDD Specification for HYS72D[64/128/256]xxxHBR–5–C

Product Type

Unit

Note ¹⁾²⁾

Organization

512 MB

×72

1 GB

×72

1 GB

×72

2 GB

×72

1 Rank

–5

1 Rank

–5

2 Ranks

–5

2 Ranks

–5

Symbol

I_DD0

Typ.

1050

1270

360

Max.

1240

1470

440

Typ.

1890

2200

670

Max.

2210

2530

780

Typ.

1660

1880

670

Max.

1910

2140

780

Typ.

3120

3430

1290

2410

1870

1670

2770

3610

3700

4510

1270

5680

Max.

3570

3890

1460

2650

2140

1850

3090

3980

4070

5490

1430

6500

3)

mA

3)4)

5)

I_DD1

I_DD2P

I_DD2F

I_DD2Q

I_DD3P

I_DD3N

I_DD4R

I_DD4W

I_DD5

5)

830

940

1360

960

1510

1120

970

1360

960

1510

1120

970

5)

510

600

5)

460

530

860

870

5)

920

1050

1510

1560

2120

390

1540

2380

2470

3280

640

1730

2620

2710

4130

740

1540

1970

2020

2290

640

1730

2190

2240

2800

740

3)4)

3)

1360

1400

1670

330

3)

5)

I_DD6

3)4)

I_DD7

2390

2770

4450

5140

3010

3450

1) Module I_DDis calculated on the basis of component I_DDand includes Register and PLL currents

2) Test condition for maximum values: V_DD= 2.7 V, T_A= 10 °C

3) The module I_DDxvalues are calculated from the component I_DDxdata sheet values as:

m × I_DDx[component] + n × I_DD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules

4) DQ I/O (I_DDQ) currents are not included into calculations: module I_DDvalues will be measured differently depending on load

conditions

5) The module I_DDxvalues are calculated from the corrponent I_DDxdata sheet values as: (m + n) × I_DDx[component]

Data Sheet

21

Rev. 1.20, 2006-03

07212004-3T0H-0Z61

HYS72D[64/128/256]xxxHBR–[5/6]–C

Registered Double-Data-Rate SDRAM Module

Electrical Characteristics

Table 9

I_DDSpecification for HYS72D[64/128/256]xxxHBR–6–C

Product Type

Unit

Note¹⁾²⁾

Organization

512 MB

×72

1 GB

×72

1 GB

×72

2 GB

×72

1 Rank

–6

1 Rank

–6

2 Ranks

–6

2 Ranks

–6

Symbol

I_DD0

Typ.

1000

1160

340

Max.

1140

1360

410

Typ.

1790

2000

600

Max.

2020

2330

700

Typ.

1530

1700

600

Max.

1720

1940

700

Typ.

2860

3060

1120

2060

1630

1460

2440

3150

3240

4000

1110

5040

Max.

3180

3490

1280

2260

1890

1640

2690

3580

3670

4940

1270

5750

3)

mA

3)4)

5)

I_DD1

I_DD2P

I_DD2F

I_DD2Q

I_DD3P

I_DD3N

I_DD4R

I_DD4W

I_DD5

5)

740

840

1180

860

1310

1000

880

1180

860

1310

1000

880

5)

470

560

5)

430

500

770

5)

830

940

1370

2090

2180

2930

580

1520

2420

2510

3780

680

1370

1740

1790

2040

580

1520

1990

2030

2530

680

3)4)

3)

1210

1250

1510

320

1410

1450

1950

390

3)

5)

I_DD6

3)4)

I_DD7

2150

2490

3980

4580

2690

3070

1) Module I_DDis calculated on the basis of component I_DDand includes Register and PLL currents

2) Test condition for maximum values: V_DD= 2.7 V, T_A= 10 °C

3) The module I_DDxvalues are calculated from the component I_DDxdata sheet values as:

m × I_DDx[component] + n × I_DD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules

4) DQ I/O (I_DDQ) currents are not included into calculations: module I_DDvalues will be measured differently depending on load

conditions

5) The module I_DDxvalues are calculated from the corrponent I_DDxdata sheet values as: (m + n) × I_DDx[component]

Data Sheet

22

Rev. 1.20, 2006-03

07212004-3T0H-0Z61

HYS72D[64/128/256]xxxHBR–[5/6]–C

Registered Double-Data-Rate SDRAM Module

Electrical Characteristics

3.2

AC Timing Parameters

Table 10

AC Timing - Absolute Specifications for PC3200 and PC2700

Parameter

Symbol –5

DDR400B

–6

Unit Note/ Test

Condition ¹⁾

DDR333

Min.

Max.

2)3)4)5)

DQ output access time from

CK/CK

t_AC

–0.5

+0.5

–0.7

+0.7

ns

2)3)4)5)

CK high-level width

Clock cycle time

t_CH

t_CK

0.45

5

0.55

8

0.45

6

0.55

12

t_CK

ns

t_CK

CL = 3.0 ^2)3)4)5)

CL = 2.5 ^2)3)4)5)

CL = 2.0 ^2)3)4)5)

6

12

6

12

7.5

0.45

12

7.5

0.45

12

2)3)4)5)

CK low-level width

t_CL

0.55

2)3)4)5)6)

Auto precharge write recovery t_DAL

+ precharge time

(tWR/tCK)+(tRP/tCK)

2)3)4)5)

DQ and DM input hold time

t_DH

0.4

—

0.45

1.75

—

ns

2)3)4)5)6)

DQ and DM input pulse width t_DIPW

(each input)

1.75

2)3)4)5)

DQS output access time from t_DQSCK

CK/CK

–0.6

0.35

—

+0.6

—

–0.6

0.35

—

+0.6

—

ns

DQS input low (high) pulse

width (write cycle)

t_DQSL,H

t_DQSQ

t_DQSS

t_CK

DQS-DQ skew (DQS and

associated DQ signals)

+0.40

1.25

+0.40 ns

TFBGA

2)3)4)5)

Write command to 1^stDQS

0.72

0.75

1.25

t_CK

2)3)4)5)

latching transition

2)3)4)5)

DQ and DM input setup time t_DS

0.4

0.2

—

0.45

0.2

—

ns

DQS falling edge hold time

from CK (write cycle)

t_DSH

t_CK

2)3)4)5)

DQS falling edge to CK setup t_DSS

0.2

—

0.2

—

t_CK

time (write cycle)

2)3)4)5)

Clock Half Period

t_HP

min. (t_CL, t_CH)

—

min. (t_CL, t_CH)

—

ns

2)3)4)5)7)

Data-out high-impedance time t_HZ

—

+0.7

–0.7

+0.7

from CK/CK

Address and control input hold t_IH

time

0.6

0.7

2.2

0.6

0.7

—

0.75

0.8

—

ns

fast slew rate

3)4)5)6)8)

slow slew rate

3)4)5)6)8)

2)3)4)5)9)

Control and Addr. input pulse t_IPW

width (each input)

2.2

Address and control input

setup time

t_IS

0.75

0.8

fast slew rate

3)4)5)6)8)

slow slew rate

3)4)5)6)8)

Data Sheet

23

Rev. 1.20, 2006-03

07212004-3T0H-0Z61

HYS72D[64/128/256]xxxHBR–[5/6]–C

Registered Double-Data-Rate SDRAM Module

Electrical Characteristics

Table 10

AC Timing - Absolute Specifications for PC3200 and PC2700

Parameter

Symbol –5

DDR400B

–6

Unit Note/ Test

Condition ¹⁾

DDR333

Min.

Max.

2)3)4)5)7)

Data-out low-impedance time t_LZ

–0.7

+0.7

–0.7

+0.7

ns

from CK/CK

2)3)4)5)

Mode register set command

cycle time

t_MRD

2

—

2

—

t_CK

2)3)4)5)

DQ/DQS output hold time

Data hold skew factor

t_QH

t

_HP–t_QHS

—

t

_HP–t_QHS

—

ns

t_QHS

—

+0.50

—

+0.50 ns

ns

70E+3 ns

TFBGA ^2)3)4)5)

2)3)4)5)

Active to Autoprecharge delay t_RAP

Active to Precharge command t_RAS

t_RCD

40

t_RCD

—

2)3)4)5)

70E+3 42

Active to Active/Auto-refresh t_RC

55

—

60

—

ns

command period

2)3)4)5)

Active to Read or Write delay t_RCD

15

—

18

—

ns

2)3)4)5)10)

Average Periodic Refresh

Interval

t_REFI

7.8

µs

2)3)4)5)

Auto-refresh to Active/Auto-

refresh command period

t_RFC

70

—

72

—

ns

2)3)4)5)

Precharge command period

Read preamble

t_RP

15

—

18

—

ns

t_CK

ns

t_RPRE

t_RPST

0.9

0.40

10

1.1

0.60

—

0.9

0.40

12

1.1

0.60

—

Read postamble

Active bank A to Active bank B t_RRD

command

2)3)4)5)

Write preamble

t_WPRE

t_WPRES

t_WPST

t_WR

0.25

0

—

0.25

0

—

t_CK

ns

2)3)4)5)11)

2)3)4)5)12)

2)3)4)5)

Write preamble setup time

Write postamble

—

0.40

15

2

0.60

—

0.40

15

1

0.60

—

t_CK

ns

Write recovery time

2)3)4)5)

Internal write to read

command delay

t_WTR

—

t_CK

2)3)4)5)

Exit self-refresh to non-read

command

t_XSNR

t_XSRD

75

—

75

—

ns

Exit self-refresh to read

command

200

t_CK

1) 0 °C ≤ T_A≤ 70 °C; V_DDQ= 2.5 V ± 0.2 V, V_DD= +2.5 V ± 0.2 V (DDR333); _DDQ= 2.6 V ± 0.1 V, _DD= +2.6 V ± 0.1 V (DDR400)

2) Input slew rate ≥ 1 V/ns for DDR400, DDR333

3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference

level for signals other than CK/CK, is V_REF. CK/CK slew rate are ≥ 1.0 V/ns.

4) Inputs are not recognized as valid until V_REFstabilizes.

5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is V_TT.

6) For each of the terms, if not already an integer, round to the next highest integer. t_CKis equal to the actual system clock

cycle time.

7) t_HZand t_LZtransitions occur in the same access time windows as valid data transitions. These parameters are not referred

to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).

8) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns,

measured between V_IH(ac)and V_IL(ac)

.

9) These parameters guarantee device timing, but they are not necessarily tested on each device.

Data Sheet

24

Rev. 1.20, 2006-03

07212004-3T0H-0Z61

HYS72D[64/128/256]xxxHBR–[5/6]–C

Registered Double-Data-Rate SDRAM Module

Electrical Characteristics

10) A maximun of eight Autorefresh commands can be posted to any given DDR SDRAM device

11) The specific requirement is that DQS be valid (HIGH,LOW, or some point on a valid transition) on or before this CK edge.

A valid transition is defined as monotonic and meeting the input slew rate specificationsof the device. When no writes were

previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,

DQS could be HIGH, LOW at this time, depending on t_DQSS

.

12) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but

system performance (bus turnaround) degrades accordingly.

Data Sheet

25

Rev. 1.20, 2006-03

07212004-3T0H-0Z61

HYS72D[64/128/256]xxxHBR–[5/6]–C

Registered Double-Data-Rate SDRAM Module

SPD Contents

4

SPD Contents

Table 11

SPD Codes for HYS72D[64/128/256]3[00/01/20/21]HBR–5–C

Product Type

Organization

Label Code

512 MB

1 GByte

2 GByte

×72

1 Rank (×8) 2 Ranks (×8)

1 Rank (×4) 2 Ranks (×4)

PC3200R–

30331

PC3200R–

30331

PC3200R–

30331

PC3200R–

30331

JEDEC SPD Revision

Description

Rev 1.0

HEX

Rev 1.0

HEX

80

Rev 1.0

HEX

80

Rev 1.0

HEX

80

Byte#

0

Programmed SPD Bytes in E2PROM 80

1

Total number of Bytes in E2PROM

Memory Type (DDR = 07h)

Number of Row Addresses

Number of Column Addresses

Number of DIMM Ranks

Data Width (LSB)

08

07

0D

0B

01

48

00

04

50

70

02

82

08

01

0E

08

2

07

3

0D

0B

02

0D

0C

01

0D

0C

02

4

5

6

48

7

Data Width (MSB)

00

8

Interface Voltage Levels

04

9

t

_CK@ CL_max(Byte 18) [ns]

50

10

11

12

13

14

15

16

17

18

19

20

21

22

23

_ACSDRAM @ CL_max(Byte 18) [ns]

70

Error Correction Support

Refresh Rate

02

82

Primary SDRAM Width

Error Checking SDRAM Width

08

04

08

04

t

_CCD[cycles]

Burst Length Supported

Number of Banks on SDRAM Device 04

01

0E

04

0E

04

0E

04

CAS Latency

1C

01

02

26

C1

60

1C

01

1C

01

1C

01

CS Latency

Write Latency

02

DIMM Attributes

Component Attributes

26

C1

60

C1

60

C1

60

t

_CK@ CL_max-0.5 (Byte 18) [ns]

Data Sheet

26

Rev. 1.20, 2006-03

07212004-3T0H-0Z61

HYS72D[64/128/256]xxxHBR–[5/6]–C

Registered Double-Data-Rate SDRAM Module

SPD Contents

Table 11

SPD Codes for HYS72D[64/128/256]3[00/01/20/21]HBR–5–C (cont’d)

Product Type

Organization

Label Code

512 MB

1 GByte

2 GByte

×72

1 Rank (×8) 2 Ranks (×8)

1 Rank (×4) 2 Ranks (×4)

PC3200R–

30331

PC3200R–

30331

PC3200R–

30331

PC3200R–

30331

JEDEC SPD Revision

Description

Rev 1.0

HEX

70

Rev 1.0

HEX

70

Rev 1.0

HEX

70

Rev 1.0

HEX

70

Byte#

24

t

_ACSDRAM @ CL_max-0.5 [ns]

_CK@ CL_max-1 (Byte 18) [ns]

_ACSDRAM @ CL_max-1 [ns]

_RPmin[ns]

25

75

26

70

27

3C

28

3C

28

3C

28

3C

28

_RRDmin[ns]

29

_RCDmin[ns]

3C

28

3C

28

3C

28

3C

28

30

_RASmin[ns]

31

Module Density per Rank

_CS[ns]

_CH[ns]

_DS[ns]

_DH[ns]

80

01

32

t_AS,

t_AH,

t

60

33

t

60

34

t

40

35

40

36 - 40 not used

00

41

42

43

44

45

46

47

t

_RCmin[ns]

37

_RFCmin[ns]

_CKmax[ns]

_DQSQmax[ns]

_QHSmax[ns]

41

28

50

not used

00

DIMM PCB Height

01

48 - 61 not used

00

62

63

64

SPD Revision

10

Checksum of Byte 0-62

C7

C1

00

C8

C1

00

41

42

JEDEC ID Code of Infineon (1)

C1

00

C1

00

65 - 71 JEDEC ID Code of Infineon (2 - 8)

72

73

Module Manufacturer Location

Part Number, Char 1

xx

37

Data Sheet

27

Rev. 1.20, 2006-03

07212004-3T0H-0Z61

HYS72D[64/128/256]xxxHBR–[5/6]–C

Registered Double-Data-Rate SDRAM Module

SPD Contents

Table 11

SPD Codes for HYS72D[64/128/256]3[00/01/20/21]HBR–5–C (cont’d)

Product Type

Organization

Label Code

512 MB

1 GByte

2 GByte

×72

1 Rank (×8) 2 Ranks (×8)

1 Rank (×4) 2 Ranks (×4)

PC3200R–

30331

PC3200R–

30331

PC3200R–

30331

PC3200R–

30331

JEDEC SPD Revision

Rev 1.0

HEX

32

Rev 1.0

HEX

32

Rev 1.0

HEX

32

Rev 1.0

HEX

32

Byte#

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

Description

Part Number, Char 2

Part Number, Char 3

Part Number, Char 4

Part Number, Char 5

Part Number, Char 6

Part Number, Char 7

Part Number, Char 8

Part Number, Char 9

Part Number, Char 10

Part Number, Char 11

Part Number, Char 12

Part Number, Char 13

Part Number, Char 14

Part Number, Char 15

Part Number, Char 16

Part Number, Char 17

Part Number, Char 18

Module Revision Code

Test Program Revision Code

Module Manufacturing Date Year

Module Manufacturing Date Week

44

36

31

32

34

32

35

33

38

36

30

33

31

32

30

32

48

31

30

42

48

52

42

35

52

43

35

20

43

20

0x

xx

95 - 98 Module Serial Number (1 - 4)

99 - 127 not used

xx

00

Data Sheet

28

Rev. 1.20, 2006-03

07212004-3T0H-0Z61

HYS72D[64/128/256]xxxHBR–[5/6]–C

Registered Double-Data-Rate SDRAM Module

SPD Contents

Table 12

SPD Codes for HYS72D[64/128/256]3[00/01/20/21]HBR–6–C

Product Type

Organization

Label Code

512 MB

×72

1 GByte

2 GByte

×72

1 Rank (×8)

2 Ranks (×8) 1 Rank (×4) 2 Ranks (×4)

PC2700R–

25331

PC2700R–

25331

PC2700R–

25331

PC2700R–

25331

JEDEC SPD Revision

Description

Rev 1.0

HEX

Rev 1.0

HEX

80

Rev 1.0

HEX

80

Rev 1.0

HEX

80

Byte#

0

Programmed SPD Bytes in E2PROM 80

1

Total number of Bytes in E2PROM

Memory Type (DDR = 07h)

Number of Row Addresses

Number of Column Addresses

Number of DIMM Ranks

Data Width (LSB)

08

07

0D

0B

02

48

00

04

60

70

02

82

08

01

0E

08

2

07

3

0D

0B

02

0D

0C

01

0D

0C

02

4

5

6

48

7

Data Width (MSB)

00

8

Interface Voltage Levels

04

9

t_CK@ CL_max(Byte 18) [ns]

60

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

t_ACSDRAM @ CL_max(Byte 18) [ns]

70

Error Correction Support

Refresh Rate

02

82

Primary SDRAM Width

Error Checking SDRAM Width

08

04

08

04

t

_CCD[cycles]

Burst Length Supported

Number of Banks on SDRAM Device 04

01

0E

04

0E

04

0E

04

CAS Latency

0C

01

02

26

C1

75

70

00

0C

01

0C

01

0C

01

CS Latency

Write Latency

02

DIMM Attributes

Component Attributes

26

C1

75

C1

75

C1

75

t_CK@ CL_max-0.5 (Byte 18) [ns]

t_ACSDRAM @ CL_max-0.5 [ns]

t_CK@ CL_max-1 (Byte 18) [ns]

70

00

Data Sheet

29

Rev. 1.20, 2006-03

07212004-3T0H-0Z61

HYS72D[64/128/256]xxxHBR–[5/6]–C

Registered Double-Data-Rate SDRAM Module

SPD Contents

Table 12

SPD Codes for HYS72D[64/128/256]3[00/01/20/21]HBR–6–C (cont’d)

Product Type

Organization

Label Code

512 MB

×72

1 GByte

2 GByte

×72

1 Rank (×8)

2 Ranks (×8) 1 Rank (×4) 2 Ranks (×4)

PC2700R–

25331

PC2700R–

25331

PC2700R–

25331

PC2700R–

25331

JEDEC SPD Revision

Description

Rev 1.0

HEX

00

Rev 1.0

HEX

00

Rev 1.0

HEX

00

Rev 1.0

HEX

00

Byte#

26

t

_ACSDRAM @ CL_max-1 [ns]

27

_RPmin[ns]

48

28

_RRDmin[ns]

30

29

_RCDmin[ns]

48

30

_RASmin[ns]

2A

80

2A

80

2A

01

2A

01

31

Module Density per Rank

32

t

_AS,t_CS[ns]

_AH,t_CH[ns]

_DS[ns]

75

33

75

34

45

35

_DH[ns]

45

36 - 40 not used

00

41

42

43

44

45

46

47

t

_RCmin[ns]

3C

48

3C

48

3C

48

3C

48

_RFCmin[ns]

_CKmax[ns]

_DQSQmax[ns]

_QHSmax[ns]

30

28

50

not used

00

DIMM PCB Height

01

48 - 61 not used

00

62

63

64

SPD Revision

10

Checksum of Byte 0-62

62

DB

C1

00

DC

C1

00

JEDEC ID Code of Infineon (1)

C1

00

C1

00

65 - 71 JEDEC ID Code of Infineon (2 - 8)

72

73

74

75

Module Manufacturer Location

Part Number, Char 1

xx

37

Part Number, Char 2

32

Part Number, Char 3

44

Data Sheet

30

Rev. 1.20, 2006-03

07212004-3T0H-0Z61

HYS72D[64/128/256]xxxHBR–[5/6]–C

Registered Double-Data-Rate SDRAM Module

SPD Contents

Table 12

SPD Codes for HYS72D[64/128/256]3[00/01/20/21]HBR–6–C (cont’d)

Product Type

Organization

Label Code

512 MB

×72

1 GByte

2 GByte

×72

1 Rank (×8)

2 Ranks (×8) 1 Rank (×4) 2 Ranks (×4)

PC2700R–

25331

PC2700R–

25331

PC2700R–

25331

PC2700R–

25331

JEDEC SPD Revision

Rev 1.0

HEX

36

Rev 1.0

HEX

31

Rev 1.0

HEX

31

Rev 1.0

HEX

32

Byte#

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

Description

Part Number, Char 4

Part Number, Char 5

Part Number, Char 6

Part Number, Char 7

Part Number, Char 8

Part Number, Char 9

Part Number, Char 10

Part Number, Char 11

Part Number, Char 12

Part Number, Char 13

Part Number, Char 14

Part Number, Char 15

Part Number, Char 16

Part Number, Char 17

Part Number, Char 18

Module Revision Code

Test Program Revision Code

Module Manufacturing Date Year

Module Manufacturing Date Week

34

32

35

33

38

36

30

33

31

32

30

32

48

31

30

42

48

52

42

36

52

43

36

20

43

20

0x

xx

95 - 98 Module Serial Number (1 - 4)

99 - 127 not used

xx

00

Data Sheet

31

Rev. 1.20, 2006-03

07212004-3T0H-0Z61

HYS72D[64/128/256]xxxHBR–[5/6]–C

Registered Double-Data-Rate SDRAM Module

SPD Contents

Table 13

SPD Codes for HYS72D[128/256]90x0HBR–6–C

Product Type

Organization

Label Code

1 GByte

2 GByte

×72

1 Rank (×4)

2 Ranks (×4)

PC2700R–25331

JEDEC SPD Revision

Rev 1.0

HEX

80

Rev 1.0

HEX

80

Byte#

0

Description

Programmed SPD Bytes in E2PROM

Total number of Bytes in E2PROM

Memory Type (DDR = 07h)

Number of Row Addresses

Number of Column Addresses

Number of DIMM Ranks

Data Width (LSB)

1

08

2

07

3

0D

0C

01

0D

0C

02

4

5

6

48

7

Data Width (MSB)

00

8

Interface Voltage Levels

04

9

t

_CK@ CL_max(Byte 18) [ns]

60

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

_ACSDRAM @ CL_max(Byte 18) [ns]

70

Error Correction Support

Refresh Rate

02

82

Primary SDRAM Width

Error Checking SDRAM Width

04

t

_CCD[cycles]

01

Burst Length Supported

Number of Banks on SDRAM Device

CAS Latency

0E

04

0E

04

0C

01

0C

01

CS Latency

Write Latency

02

DIMM Attributes

26

Component Attributes

C1

75

C1

75

t

_CK@ CL_max-0.5 (Byte 18) [ns]

_ACSDRAM @ CL_max-0.5 [ns]

_CK@ CL_max-1 (Byte 18) [ns]

_ACSDRAM @ CL_max-1 [ns]

70

00

Data Sheet

32

Rev. 1.20, 2006-03

07212004-3T0H-0Z61

HYS72D[64/128/256]xxxHBR–[5/6]–C

Registered Double-Data-Rate SDRAM Module

SPD Contents

Table 13

SPD Codes for HYS72D[128/256]90x0HBR–6–C (cont’d)

Product Type

Organization

Label Code

1 GByte

2 GByte

×72

1 Rank (×4)

2 Ranks (×4)

PC2700R–25331

JEDEC SPD Revision

Description

Rev 1.0

HEX

48

Rev 1.0

HEX

48

Byte#

27

t

_RPmin[ns]

_RRDmin[ns]

_RCDmin[ns]

_RASmin[ns]

28

30

29

48

30

2A

01

2A

01

31

Module Density per Rank

_CS[ns]

_CH[ns]

_DS[ns]

_DH[ns]

32

t_AS,

t_AH,

t

75

33

t

75

34

t

45

35

45

36 - 40

41

not used

00

t

_RCmin[ns]

3C

48

3C

48

42

_RFCmin[ns]

_CKmax[ns]

_DQSQmax[ns]

_QHSmax[ns]

43

30

44

28

45

50

46

not used

00

47

DIMM PCB Height

01

48 - 61

62

not used

00

SPD Revision

10

63

Checksum of Byte 0-62

JEDEC ID Code of Infineon (1)

JEDEC ID Code of Infineon (2 - 8)

Module Manufacturer Location

Part Number, Char 1

Part Number, Char 2

Part Number, Char 3

Part Number, Char 4

Part Number, Char 5

DB

C1

00

DC

C1

00

64

65 - 71

72

xx

73

37

74

32

75

44

76

31

32

77

32

35

Data Sheet

33

Rev. 1.20, 2006-03

07212004-3T0H-0Z61

HYS72D[64/128/256]xxxHBR–[5/6]–C

Registered Double-Data-Rate SDRAM Module

SPD Contents

Table 13

SPD Codes for HYS72D[128/256]90x0HBR–6–C (cont’d)

Product Type

Organization

Label Code

1 GByte

2 GByte

×72

1 Rank (×4)

2 Ranks (×4)

PC2700R–25331

JEDEC SPD Revision

Rev 1.0

HEX

38

Rev 1.0

HEX

36

Byte#

78

Description

Part Number, Char 6

Part Number, Char 7

Part Number, Char 8

Part Number, Char 9

Part Number, Char 10

Part Number, Char 11

Part Number, Char 12

Part Number, Char 13

Part Number, Char 14

Part Number, Char 15

Part Number, Char 16

Part Number, Char 17

Part Number, Char 18

Module Revision Code

Test Program Revision Code

Module Manufacturing Date Year

Module Manufacturing Date Week

Module Serial Number (1 - 4)

not used

79

39

80

30

32

81

30

82

48

83

42

84

52

85

36

86

43

87

20

88

20

89

20

90

20

91

0x

92

xx

93

xx

94

xx

95 - 98

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Data Sheet

34

Rev. 1.20, 2006-03

07212004-3T0H-0Z61

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Data Sheet

35

Rev. 1.20, 2006-03

07212004-3T0H-0Z61

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Data Sheet

36

Rev. 1.20, 2006-03

07212004-3T0H-0Z61

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Data Sheet

37

Rev. 1.20, 2006-03

07212004-3T0H-0Z61

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Data Sheet

38

Rev. 1.20, 2006-03

07212004-3T0H-0Z61

HYS72D[64/128/256]xxxHBR–[5/6]–C

Registered Double-Data-Rate SDRAM Module

Application Note

6

Application Note

Power Up and Power Management on DDR Registered DIMMs

(according to JEDEC ballot JC-42.5 Item 1173)

184-pin Double Data Rate (DDR) Registered DIMMs include two new features to facilitate controlled power-up and

to minimize power consumption during low power mode. One feature is externally controlled via a system-

generated RESET signal; the second is based on module detection of the input clocks. These enhancements

permit the modules to power up with SDRAM outputs in a High-Z state (eliminating risk of high current dissipations

and/or dotted I/Os), and result in the powering-down of module support devices (registers and Phase-Locked

Loop) when the memory is in Self-Refresh mode.

The new RESET pin controls power dissipation on the module’s registers and ensures that CKE and other SDRAM

inputs are maintained at a valid ‘low’ level during power-up and self refresh. When RESET is at a low level, all the

register outputs are forced to a low level, and all differential register input receivers are powered down, resulting

in very low register power consumption. The RESET pin, located on DIMM tab #10, is driven from the system as

an asynchronous signal according to the attached details. Using this function also permits the system and DIMM

clocks to be stopped during memory Self Refresh operation, while ensuring that the SDRAMs stay in Self Refresh

mode.

Table 14

The function for RESET is as follows:¹⁾

Register Inputs

Register Outputs

RESET

CK

Data in (D)

Data out (Q)

H

L

Rising

L or H

High Z

X or Hi-Z

Falling

L or H

High Z

X or Hi-Z

H

L

X

Qo

X

Illegal input conditions

L

X or Hi-Z

1) X : Don’t care, Hi-Z : High Impedance, Qo: Data latched at the previous of CK risning and CK falling

As described in the table above, a low on the RESET input ensures that the Clock Enable (CKE) signal(s) are

maintained low at the SDRAM pins (CKE being one of the 'Q' signals at the register output). Holding CKE low

maintains a high impedance state on the SDRAM DQ, DQS and DM outputs — where they will remain until

activated by a valid ‘read’ cycle. CKE low also maintains SDRAMs in Self Refresh mode when applicable.

The DDR PLL devices automatically detect clock activity above 20MHz. When an input clock frequency of 20MHz

or greater is detected, the PLL begins operation and initiates clock frequency lock (the minimum operating

frequency at which all specifications will be met is 95MHz). If the clock input frequency drops below 20MHz (actual

detect frequency will vary by vendor), the PLL VCO (Voltage Controlled Oscillator) is stopped, outputs are made

High-Z, and the differential inputs are powered down — resulting in a total PLL current consumption of less than

1mA. Use of this low power PLL function makes the use of the PLL RESET (or G pin) unnecessary, and it is tied

inactive on the DIMM.

This application note describes the required and optional system sequences associated with the DDR Registered

DIMM 'RESET' function. It is important to note that all references to CKE refer to both CKE0 and CKE1 for a 2-

bank DIMM. Because RESET applies to all DIMM register devices, it is therefore not possible to uniquely control

CKE to one physical DIMM bank through the use of the RESET pin.

Data Sheet

39

Rev. 1.20, 2006-03

07212004-3T0H-0Z61

HYS72D[64/128/256]xxxHBR–[5/6]–C

Registered Double-Data-Rate SDRAM Module

Application Note

Power-Up Sequence with RESET — Required

1. The system sets RESET at a valid low level. This is the preferred default state during power-up. This input

condition forces all register outputs to a low state independent of the condition on the register inputs (data and

clock), ensuring that CKE is at a stable low-level at the DDR SDRAMs.

2. The power supplies should be initialized according to the JEDEC-approved initialization sequence for DDR

SDRAMs.

3. Stabilization of Clocks to the SDRAM The system must drive clocks to the application frequency (PLL

operation is not assured until the input clock reaches 20MHz). Stability of clocks at the SDRAMs will be

affected by all applicable system clock devices, and time must be allotted to permit all clock devices to settle.

Once a stable clock is received at the DIMM PLL, the required PLL stabilization time (assuming power to the

DIMM is stable) is 100 microseconds. When a stable clock is present at the SDRAM input (driven from the

PLL), the DDR SDRAM requires 200 µsec prior to SDRAM operation.

4. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM

connector). CKE must be maintained low and all other inputs should be driven to a known state. In general

these commands can be determined by the system designer. One option is to apply an SDRAM ‘NOP’

command (with CKE low), as this is the first command defined by the JEDEC initialization sequence (ideally

this would be a ‘NOP Deselect’ command). A second option is to apply low levels on all of the register inputs

to be consistent with the state of the register outputs.

5. The system switches RESET to a logic ‘high’ level. The SDRAM is now functional and prepared to receive

commands. Since the RESET signal is asynchronous, setting the RESET timing in relation to a specific clock

edge is not required (during this period, register inputs must remain stable).

6. The system must maintain stable register inputs until normal register operation is attained. The registers have

an activation time that allows their clock receivers, data input receivers, and output drivers sufficient time to be

turned on and become stable. During this time the system must maintain the valid logic levels described in step

5. It is also a functional requirement that the registers maintain a low state at the CKE outputs to guarantee

that the DDR SDRAMs continue to receive a low level on CKE. Register activation time (t (ACT) ), from

asynchronous switching of RESET from low to high until the registers are stable and ready to accept an input

signal, is specified in the register and DIMM do-umentation.

7. The system can begin the JEDEC-defined DDR SDRAM power-up sequence (according to the JEDEC-

pproved initialization sequence).

Self Refresh Entry (RESET low, clocks powered off) — Optional

Self Refresh can be used to retain data in DDR SDRAM DIMMs even if the rest of the system is powered down

and the clocks are off. This mode allows the DDR SDRAMs on the DIMM to retain data without external clocking.

Self Refresh mode is an ideal time to utilize the RESET pin, as this can reduce register power consumption

(RESET low deactivates register CK and CK, data input receivers, and data output drivers).

•

The system applies Self Refresh entry command. (CKEÆLow, CSÆLow, RAS Æ Low, CASÆ Low, WEÆ

High)

Note:The commands reach the DDR SDRAM one clock later due to the additional register pipelining on a

Registered DIMM. After this command is issued to the SDRAM, all of the address and control and clock input

conditions to the SDRAM are Don’t Cares— with the exception of CKE.

•

The system sets RESET at a valid low level. This input condition forces all register outputs to a low state,

independent of the condition on the registerm inputs (data and clock), and ensures that CKE, and all other

control and address signals, are a stable low-level at the DDR SDRAMs. Since the RESET signal is

asynchronous, setting the RESET timing in relation to a specific clock edge is not required.

Data Sheet

40

Rev. 1.20, 2006-03

07212004-3T0H-0Z61

HYS72D[64/128/256]xxxHBR–[5/6]–C

Registered Double-Data-Rate SDRAM Module

Application Note

•

The system turns off clock inputs to the DIMM. (Optional)

a. In order to reduce DIMM PLL current, the clock inputs to the DIMM are turned off, resulting in High-Z clock

inputs to both the SDRAMs and the registers. This must be done after the RESET deactivate time of the

register (t (INACT) ). The deactivate time defines the time in which the clocks and the control and address

signals must maintain valid levels after RESET low has been applied and is specified in the register and DIMM

documentation.

b. The system may release DIMM address and control inputs to High-Z. This can be done after the RESET

deactivate time of the register. The deactivate time defines the time in which the clocks and the control and the

address signals must maintain valid levels after RESET low has been applied. It is highly recommended that

CKE continue to remain low during this operation.

•

The DIMM is in lowest power Self Refresh mode.

Self Refresh Exit (RESET low, clocks powered off) — Optional

1. Stabilization of Clocks to the SDRAM. The system must drive clocks to the application frequency (PLL

operation is not assured until the input clock reaches ~20MHz). Stability of clocks at the SDRAMs will be

affected by all applicable system clock devices, and time must be allotted to permit all clock devices to settle.

Once a stable clock is received at the DIMM PLL, the required PLL stabilization time (assuming power to the

DIMM is stable) is 100 microseconds.

2. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM

connector). CKE must be maintained low and all other inputs should be driven to a known state. In general

these commands can be determined by the system designer. One option is to apply an SDRAM ‘NOP’

command (with CKE low), as this is the first command defined by the JEDEC Self Refresh Exit sequence

(ideally this would be a ‘NOP Deselect’ command). A second option is to apply low levels on all of the register

inputs, to be consistent with the state of the register outputs.

3. The system switches RESET to a logic ‘high’ level. The SDRAM is now functional and prepared to receive

commands. Since the RESET signal is asynchronous, RESET timing relationship to a specific clock edge is

not required (during this period, register inputs must remain stable).

4. The system must maintain stable register inputs until normal register operation is attained. The registers have

an activation time that allows the clock receivers, input receivers, and output drivers sufficient time to be turned

on and become stable. During this time the system must maintain the valid logic levels described in Step 2. It

is also a functional requirement that the registers maintain a low state at the CKE outputs to guarantee that the

DDR SDRAMs continue to receive a low level on CKE. Register activation time (t (ACT) ), from asynchronous

switching of RESET from low to high until the registers are stable and ready to accept an input signal, is

specified in the register and DIMM do-umentation.

5. System can begin the JEDEC-defined DDR SDRAM Self Refresh Exit Procedure.

Self Refresh Entry (RESET low, clocks running) — Optional

Although keeping the clocks running increases power consumption from the on-DIMM PLL during self refresh, this

is an alternate operating mode for these DIMMs.

1. System enters Self Refresh entry command. (CKEÆ Low, CSÆ Low, RASÆ Low, CASÆ Low, WEÆ High)

Note:The commands reach the DDR SDRAM one clock later due to the additional register pipelining on a

Registered DIMM. After this command is issued to the SDRAM, all of the address and control and clock input

conditions to the SDRAM are Don’t Cares — with the exception of CKE.

Data Sheet

41

Rev. 1.20, 2006-03

07212004-3T0H-0Z61

HYS72D[64/128/256]xxxHBR–[5/6]–C

Registered Double-Data-Rate SDRAM Module

Application Note

•

The system sets RESET at a valid low level. This input condition forces all register outputs to a low state,

independent of the condition on the data and clock register inputs, and ensures that CKE is a stable low-level

at the DDR SDRAMs.

The system may release DIMM address and control inputs to High-Z. This can be done after the RESET

deactivate time of the register (t (INACT) ). The deactivate time describes the time in which the clocks and the

control and the address signals must maintain valid levels after RESET low has been applied. It is highly

recommended that CKE continue to remain low during the operation.

•

The DIMM is in a low power, Self Refresh mode.

Self Refresh Exit (RESET low, clocks running) — Optional

1. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM

connector). CKE must be maintained low and all other inputs should be driven to a known state. In general

these commands can be determined by the system designer. One option is to apply an SDRAM ‘NOP’

command (with CKE low), as this is the first command defined by the Self Refresh Exit sequence (ideally this

would be a ‘NOP Deselect’ command). A second option is to apply low levels on all of the register inputs to be

consistent with the state of the register outputs.

2. The system switches RESET to a logic 'high' level. The SDRAM is now functional and prepared to receive

commands. Since the RESET signal is asynchronous, it does not need to be tied to a particular clock edge

(during this period, register inputs must continue to remain stable).

3. The system must maintain stable register inputs until normal register operation is attained. The registers have

an activation time that allows the clock receivers, input receivers, and output drivers sufficient time to be turned

on and become stable. During this time the system must maintain the valid logic levels described in Step 1. It

is also a functional requirement that the registers maintain a low state at the CKE outputs in order to guarantee

that the DDR SDRAMs continue to receive a low level on CKE. This activation time, from asynchronous

switching of RESET from low to high, until the registers are stable and ready to accept an input signal, is t (ACT

) as specified in the register and DIMM documentation.

4. The system can begin JEDEC defined DDR SDRAM Self Refresh Exit Procedure.

Self Refresh Entry/Exit (RESET high, clocks running) — Optional

As this sequence does not involve the use of the RESET function, the JEDEC standard SDRAM specification

explains in detail the method for entering and exiting Self Refresh for this case.

Self Refresh Entry (RESET high, clocks powered off) — Not Permissible

In order to maintain a valid low level on the register output, it is required that either the clocks be running and the

system drive a low level on CKE, or the clocks are powered off and RESET is asserted low according to the

sequence defined in this application note. In the case where RESET remains high and the clocks are powered off,

the PLL drives a High-Z clock input into the register clock input. Without the low level on RESET an unknown DIMM

state will result.

Data Sheet

42

Rev. 1.20, 2006-03

07212004-3T0H-0Z61

w w w . i n f i n e o n . c o m

Published by Infineon Technologies AG

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