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CYM74P55PM-60

型号：

CYM74P55PM-60

品牌：

CYPRESS[ CYPRESS ]

页数：

7 页

PDF大小：

197 K

下载PDF手册
1CYM74SP54/55  
CYM74BP54  
CYM74P54/55  
CYM74SP54/55  
PRELIMINARY  
Intel® 82430NX Chipset  
Level II Cache Module Family  
dustry standard 5V SRAMs and 3.3V level translators for CPU  
bus speeds up to 66 MHz. The CYM74BP54 is organized as  
32K by 64-bits.  
Features  
• Pin-compatible secondary cache module family  
• Asynchronous (CYM74BP54), synchronous pipelined  
(CYM74P54, CYM74P55), or synchronous  
The synchronous modules are available with low-cost syn-  
chronous pipelined RAMs or higher performance synchronous  
burst RAMs. The synchronous pipelined modules are based  
on a 16Kx64 RAM. The CYM74P54 is a 256-KB module while  
the CYM74P55 is a 512-KB module. Both are modules without  
byte parity.  
(CYM74SP54, CYM74SP55) configurations with pres-  
ence and configuration detect pins  
• Ideal for Intel® P54C-based systems with the 82430NX  
(Neptune) chipset  
• Operates at 60 and 66 MHz  
• Uses cost-effective CMOS asynchronous SRAMs or  
high-performance synchronous SRAMs  
• 160-position Burndy DIMM CELP2X80SC3Z48  
connector  
The CYM74SP54 and CYM74SP55 are synchronous burst  
cache modules that provide zero wait-state performance at a  
bus speed of 66 MHz. The CYM74SP54 is a 256-Kbyte cache  
module with byte parity. The CYM74SP55 is a 512-Kbyte  
cache module with byte parity.  
• 3.3V inputs/outputs  
Multiple ground pins and on-board decoupling capacitors en-  
sure high performance with maximum noise immunity.  
Functional Description  
All components on the cache modules are surface mounted  
on a multi-layer epoxy laminate (multifunctional) substrate.  
The contact pins are plated with 150 micro-inches of nickel  
covered by 10 micro-inches of gold flash.  
This family of secondary cache modules is designed for Intel  
P54C systems with the 82430NX (Neptune) chipset.  
CYM74BP54 is an asynchronous 256-Kbyte cache module  
that provides a low-cost, high-performance solution with in-  
CYM74BP54  
Logic Block Diagram -  
ADDRESS LATCH  
A
17  
-A  
7
D -D  
D -D  
8
0
7
A -A  
6–0 5–0  
LA -LA  
17  
5
15  
D
D
-D  
23  
16  
CALE  
LE  
-D  
24  
31  
32K x 8  
32K x 8  
32K x 8  
32K x 8  
D
A
D
A
D
A
D
A
A -A  
4–0 3–0  
CE  
CE  
OE  
CE  
OE  
CE  
OE  
OE  
WE  
2
WE  
1
WE  
3
WE  
0
CE  
0
OE  
0
3
WE -WE  
0
D
D
-D  
-D  
-D  
-D  
32  
39  
47  
55  
63  
40  
D
48  
D
32K x 8  
D
32K x 8  
D
32K x 8  
D
32K x 8  
D
56  
A
4–1  
-A  
3–1  
A
A
A
A
CE  
OE  
CE  
OE  
CE  
OE  
CE  
OE  
WE  
6
WE  
5
WE  
7
WE  
4
74BP54–1  
CE  
1
OE  
1
WE -WE  
4
7
A
Intel is a registered trademark of Intel Corporation.  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
May 1994 – Revised October 1995  
•
408-943-2600  
CYM74BP54  
CYM74P54/55  
CYM74SP54/55  
PRELIMINARY  
Block Diagram: 5V to 3.3V Level Conversion (CYM74BP54)  
5.0Volts  
100ohms  
Vcc  
4.3Vzener  
5%tolerance  
64BitBusSwitch  
(uses7CYBUS3384)  
5VSRAM  
3.3VcompliantI/O  
D
B
GND  
BE  
[2:1]  
74BP54–2  
PD  
PD  
PD  
0
TBD  
TBD  
Logic Block Diagram - CYM74P54, CYM74P55  
2
1
CYM74P54 TBD  
CYM74P55 TBD  
TBD  
TBD  
CYM74P55ONLY  
D -D  
63  
0
CLK1  
CLK0  
CK  
CK  
CK  
CK  
D
D
D
D
A
-A  
A
A
A
A
A
16  
7
A
-A  
A
A
A
6–0 3–0  
A
-A  
6–1 3–1  
WE -WE  
BE -BE  
0
BE -BE  
0
BE -BE  
BE -BE  
0 7  
7
0
7
7
0
7
8
ADSP0  
ADSC0  
ADV0  
ADSP  
ADSC  
ADV  
ADSP  
ADSC  
ADV  
ADSP1 ADSP  
ADSC1 ADSC  
ADSP  
ADSC  
ADV  
ADV1  
ADV  
CE  
1
1
CE  
CS  
CS  
CS  
OE  
CS  
0
0
0
0
0
OE  
OE  
OE  
OE  
OE  
0
CS  
CS  
CS  
CS  
CS  
CS  
CS  
CS  
CS  
CS  
CS  
CS  
CS  
V
GND  
V
CC  
GND  
GND  
1
4
3
1
4
3
1
2
4
3
1
4
3
CC  
CS  
CS  
CS  
2
V
CC  
V
CC  
GND  
2
2
16Kx64  
16Kx64  
16Kx64  
16Kx64  
A
17  
CYM74P54(GND)  
CYM74P55 (A  
)
18  
74BP54–3  
2
CYM74BP54  
CYM74P54/55  
CYM74SP54/55  
PRELIMINARY  
Logic Block Diagram - CYM74SP54/CYM74SP55  
D -D  
0
15  
DP -DP  
0
1
3
D -D  
16 31  
DP -DP  
2
D -D  
32 47  
DP -DP  
4
5
Note:A isnotusedbyCYM74SP54  
18  
D -D  
48 63  
DP -DP  
6
7
(CYM74SP54)32K x 18  
(CYM74SP55)64Kx18  
D
D
D
D
A
-A  
7
18  
A
A
A
A
A -A  
6–1 3–1  
A
-A  
3–0  
6–0  
ADSP1  
ADSP  
ADSP  
ADSP  
ADSP  
ADSP0  
ADSC1  
ADV1  
ADSC  
ADV  
ADSC  
ADV  
ADSC  
ADV  
ADSC  
ADV  
ADSC0  
ADV0  
CE  
CE  
CE  
CE  
OE  
OE  
OE  
OE  
WE4/5  
WE2/3  
WE6/7  
WE0/1  
CLK0  
CLK1  
CE  
0
OE  
0
1
74BP54–4  
CE  
OE  
1
WE -WE  
0
7
Selection Guide  
Asynchronous Cache Modules  
Part Number  
CYM74BP54-60  
CYM74BP54-66  
Cache Size (KB)  
System Clock (MHz)  
RAM Speed  
256  
60  
66  
t
=15 ns  
t
=12 ns  
AA  
AA  
Synchronous Pipelined Cache Modules  
Part Number  
Cache Size (KB)  
System Clock (MHz)  
RAM Speed  
CYM74P54-60  
CYM74P54-66  
CYM74P55-60  
CYM74P55-66  
66  
256  
256  
512  
60  
60  
66  
t
=10.5 ns  
t
=8.5 ns  
t
=10.5 ns  
t
=8.5 ns  
CDV  
CDV  
CDV  
CDV  
Synchornous Burst Cache Modules  
Part Number  
Cache Size (KB)  
System Clock (MHz)  
RAM Speed  
CYM74SP54-60  
CYM74SP54-66  
CYM74SP55-60  
CYM74SP55-66  
66  
512  
60  
60  
66  
t
=10.5 ns  
t
=8.5 ns  
t
=10.5 ns  
t
=8.5 ns  
CDV  
CDV  
CDV  
CDV  
3
CYM74BP54  
CYM74P54/55  
CYM74SP54/55  
PRELIMINARY  
Pin Configuration  
Dual Read–Out SIMM (DIMM)  
Top View  
GND  
D63  
VCC  
D61  
VCC  
D59  
GND  
81  
82  
83  
84  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
95  
96  
1
2
3
4
5
6
7
8
9
D62  
NC (74BP54) / VCCQ (74P5X, 74SP5X)  
D60  
NC (74BP54) / VCCQ (74P5X, 74SP5X)  
D58  
D57  
GND  
D56  
GND  
NC (74BP54) / DP6 (74P5X, 74SP5X)  
D54  
D52  
(74P5X, 74SP5X)DP7 / (74BP54) NC  
D55  
D53  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
D51  
D50  
GND  
GND  
D49  
D48  
D47  
D45  
D46  
D44  
D43  
D42  
97  
98  
99  
GND  
GND  
D41  
D40  
NC (74BP54) / DP4 (74P5X, 74SP5X)  
(74P5X, 74SP5X)DP5 / (74BP54) NC  
100  
101  
102  
103  
104  
105  
106  
107  
108  
109  
110  
111  
112  
113  
114  
115  
116  
D39  
D37  
D35  
GND  
D33  
D38  
D36  
D34  
GND  
D32  
D31  
D30  
D29  
D28  
D27  
D26  
D25  
GND  
D24  
GND  
NC (74BP54) / DP2 (74P5X, 74SP5X)  
D22  
D20  
NC (74BP54) / VCCQ (74P5X, 74SP5X)  
D18  
GND  
(74P5X, 74SP5X)DP3 / (74BP54) NC  
D23  
D21  
VCC  
D19  
GND  
D17  
VCC  
D15  
D16  
117  
118  
119  
120  
121  
122  
NC (74BP54) / VCCQ (74P5X, 74SP5X)  
D14  
D12  
GND  
D10  
D13  
GND  
D11  
VCC  
D9  
123  
124  
125  
126  
127  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
139  
140  
141  
142  
143  
144  
145  
146  
147  
148  
149  
150  
151  
152  
153  
154  
155  
156  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
NC (74BP54) / VCCQ (74P5X, 74SP5X)  
D8  
(74P5X, 74SP5X)DP1 / (74BP54) NC  
NC (74BP54) / DP0 (74P5X, 74SP5X)  
VCC  
D7  
D5  
D3  
D1  
GND  
NC (74BP54) / VCCQ (74P5X, 74SP5X)  
D6  
D4  
D2  
D0  
GND  
A3–0  
A4–0  
A5–0  
A3–1  
A4–1  
(74P5X, 74SP5X)A5–1 / (74BP54) NC  
A6–0  
(74P5X, 74SP5X)A6–1 / (74BP54) NC  
A7  
GND  
A8  
GND  
A9  
A10  
A11  
A12  
A13  
A14  
A15  
A17  
GND  
A16  
NC (74BP54, 74SP54) / GND (74P54) / A18 (74P55, 74SP55)  
GND  
(ReservedA19) NC  
PD0  
PD1  
PD2  
NC (74BP54, 74P54) / CLK1 (74P55, 74SP5X)  
NC (Reserved CLK3)  
GND  
(74P5X, 74SP5X)CLK0 / (74BP54) NC  
(Reserved CLK2) NC  
GND  
WE7  
WE5  
WE3  
WE1  
GND  
WE6  
WE4  
WE2  
WE0  
GND  
CALE (74BP54) / ADSC0 (74P5X, 74SP5X)  
CE0  
NC (74BP54) / ADV0 (74P5X, 74SP5X)  
OE0  
NC (74BP54) / VCCQ (74P5X, 74SP5X)  
NC (74BP54) / ADSP0 (74P5X, 74SP5X)  
GND  
(74P55, 74SP5X)ADSC1 / (74BP54, 74P54) NC  
CE1  
(74P55, 74SP5X)ADV1 / (74BP54, 74P54) NC  
OE1  
157  
158  
159  
160  
77  
78  
79  
80  
VCC  
(74P55, 74SP5X)ADSP1 / (74BP54, 74P54) NC  
GND  
74BP54–5  
4
CYM74BP54  
CYM74P54/55  
CYM74SP54/55  
PRELIMINARY  
Pin Definitions  
Common Signals  
Description  
V
5V Supply  
CC  
GND  
A –A  
Ground  
Addresses from processor  
7
19  
A
A
, A  
Lower address from chipset, identical to the bank1 addresses  
3–0 4–0  
, A  
Lower address from chipset, identical to the bank0 addresses, A , A not used on  
CYM74P54  
3–1 4–1  
3-1  
4-1  
A
, A  
Lower address from processor (CYM74P5X, CYM74SP5X- identical to the bank1  
addresses)  
5–0  
6–0  
CE , CE  
Chip Enable (same signal), CE not used on CYM74P54  
1
0
1
OE , OE  
Output Enable (same signal), OE not used on CYM74P54  
0
1
1
WE , WE ,WE ,WE  
3
Byte Write Enables  
0
1
2
WE ,WE ,WE ,WE  
4
5
6
7
PD –PD  
Presence Detect pins  
0
2
D –D  
Data lines from processor  
0
63  
NC  
Signal not connected on module.  
Description  
CYM74BP54 Only Signals  
CALE  
CYM74P5X, CYM74SP5X Signals  
Latch Enable  
Description  
V
3.3V Supply  
CCQ  
DP –DP  
Data Parity lines (Optional)  
0
7
ADSP0, ADSP1  
ADSC0,ADSC1  
ADV0, ADV1  
Processor Address Strobe, ADSP1 not used on CYM74P54  
Cache Controller Address Strobe, ADSC1 not used on CYM74P54  
Burst Address Advance, ADV1 not used on CYM74P54  
A
, A  
Lower address from processor, identical to the bank0 addresses, A , A not used on  
5–1  
6–1  
5-1 6-1  
CYM74P54  
CLK0, CLK1, CLK2, CLK3  
Clock signals (each should be given own clk driver); CLK0 used on CYM74P5X,  
CYM74SP5X; CLK1 not used on CYM74P54; CLK2 and CLK3 are RSVD  
Presence Detect Pins  
PD  
PD  
PD  
0
2
1
Asynchronous – CYM74BP54  
NC  
GND  
TBD  
TBD  
GND  
GND  
NC  
TBD  
TBD  
NC  
Synchronous Pipelined – CYM74P54  
Synchronous Pipelined – CYM74P55  
Synchronous Burst – CYM74SP54  
Synchronous Burst – CYM74SP55  
TBD  
TBD  
GND  
GND  
GND  
5
CYM74BP54  
CYM74P54/55  
CYM74SP54/55  
PRELIMINARY  
Output Current into Outputs (LOW)............................. 20 mA  
Maximum Ratings  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.  
Operating Range  
Ambient  
Tempera-  
Storage Temperature ................................. –55°C to +125°C  
Ambient Temperature  
with Power Applied ......................................... –0°C to +70°C  
Range  
ture  
V
V
CCQ  
CC  
Commercial  
(CYM74BP54)  
0°C to  
+70°C  
5V ± 5%  
N/A  
3.3V Supply Voltage to Ground Potential..... –0.5V to +5.25V  
5V Supply Voltage to Ground Potential........ –0.5V to +5.25V  
Commercial  
(CYM74P5X,  
CYM74SP5X)  
0°C to  
+70°C  
5V ± 5%  
5V ± 5%  
3.3V + 10%  
– 5%  
DC Voltage Applied to Outputs  
in High Z State ............................................... –0.5V to +4.6V  
DC Input Voltage............................................ –0.5V to +4.6V  
Electrical Characteristics Over the Operating Range  
Parameter  
Description  
Input HIGH Voltage  
Input LOW Voltage  
Input LOW Voltage  
Output HIGH Voltage  
Output LOW Voltage  
Test Condition  
Min.  
2.2  
Max.  
Unit  
V
V
IH  
V
V
V
V
CYM74BP54  
CYM74P5X, CYM74SP5X  
-0.5  
-0.3  
2.4  
0.8  
0.8  
V
IL  
V
IL  
V
V
V
V
V
V
V
=Min. I = -4 mA  
V
OH  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
OH  
=Min. I = 8 mA  
0.4  
V
OL  
OL  
I
I
I
I
I
V
V
V
V
V
Operating Supply Current  
Operating Supply Current  
Operating Supply Current  
Operating Supply Current  
Operating Supply Current  
=Max., I  
=Max., I  
=Max., I  
=Max., I  
=Max., I  
=0 mA, f=f  
=0 mA, f=f  
=0 mA, f=f  
=0 mA, f=f  
=0 mA, f=f  
=1/t  
=1/t  
=1/t  
=1/t  
=1/t  
1700  
TBD  
TBD  
1100  
1400  
mA  
mA  
mA  
mA  
mA  
CC (74BP54)  
CC (74P54)  
CC (74P55)  
CC (74SP54)  
CC (74SP55)  
CC  
CC  
CC  
CC  
CC  
OUT  
OUT  
OUT  
OUT  
OUT  
MAX  
MAX  
MAX  
MAX  
MAX  
RC  
RC  
RC  
RC  
RC  
Ordering Information  
Speed  
Package  
Name  
Operating  
Range  
(MHz)  
Ordering Code  
CYM74BP54PM-60  
CYM74P54PM-60  
CYM74P55PM-60  
CYM74SP54PM-60  
CYM74SP55PM-60  
CYM74BP54PM-66  
CYM74P54PM-66  
CYM74P55PM-66  
CYM74SP54PM-66  
CYM74SP55PM-66  
Package Type  
Description  
60  
PM36  
TBD  
160-Pin Dual-Readout SIMM  
160-Pin Dual-Readout SIMM  
160-Pin Dual-Readout SIMM  
160-Pin Dual-Readout SIMM  
160-Pin Dual-Readout SIMM  
160-Pin Dual-Readout SIMM  
160-Pin Dual-Readout SIMM  
160-Pin Dual-Readout SIMM  
160-Pin Dual-Readout SIMM  
160-Pin Dual-Readout SIMM  
Asynchronous 256KB  
Synch Pipelined 256KB  
Synch Pipelined 512KB  
Synch Burst 256KB  
Synch Burst 512KB  
Asynchronous 256KB  
Synch Pipelined 256KB  
Synch Pipelined 512KB  
Synch Burst 256KB  
Synch Burst 512KB  
Commercial  
TBD  
PM26  
PM26  
PM36  
TBD  
66  
Commercial  
TBD  
PM26  
PM26  
Document #: 38-M-00070-B  
6
CYM74BP54  
CYM74P54/55  
CYM74SP54/55  
PRELIMINARY  
Package Diagrams  
160-Pin Dual-Readout SIMM PM26  
160-Pin Dual Readout SIMM PM36  
© Cypress Semiconductor Corporation, 1995. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of anycircuitry other than circuitry embodied in a CypressSemiconductor product. Nor does it conveyor imply any license under patent or other rights. CypressSemiconductor does not authorize  
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.  
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ETC

 		CYM1220HD-12C X4 SRAM模块\n[ x4 SRAM Module ] 5 页

ETC

 		CYM1220HD-12MB X4 SRAM模块\n[ x4 SRAM Module ] 5 页

ETC

 		CYM1220HD-15C X4 SRAM模块\n[ x4 SRAM Module ] 5 页

ETC

 		CYM1220HD-15MB X4 SRAM模块\n[ x4 SRAM Module ] 5 页

ETC

 		CYM1220HD-20MB X4 SRAM模块\n[ x4 SRAM Module ] 5 页

CYPRESS

 		CYM1240HD-25C [ SRAM Module, 256KX4, 25ns, CMOS, CDIP28, HERMETIC SEALED, MODULE, DIP-28 ] 1 页

CYPRESS

 		CYM1240HD-25MB [ SRAM Module, 256KX4, 25ns, CMOS, CDIP28, HERMETIC SEALED, MODULE, DIP-28 ] 1 页

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