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HYS72T64001HR-5-A

型号：

HYS72T64001HR-5-A

品牌：

INFINEON[ Infineon ]

页数：

50 页

PDF大小：

729 K

下载PDF手册
Data Sheet, Rev. 1.0, Oct. 2004  
HYS72T32000HR–[3.7/5]–A  
HYS72T64001HR–[3.7/5]–A  
HYS72T64020HR–[3.7/5]–A  
240-Pin Registered DDR2 SDRAM Modules  
DDR2 SDRAM  
RDIMM SDRAM  
RoHS Compliant  
Memory Products  
N e v e r s t o p t h i n k i n g .  
The information in this document is subject to change without notice.  
Edition 2004-10  
Published by Infineon Technologies AG,  
St.-Martin-Strasse 53,  
81669 München, Germany  
© Infineon Technologies AG 2004.  
All Rights Reserved.  
Attention please!  
The information herein is given to describe certain components and shall not be considered as a guarantee of  
characteristics.  
Terms of delivery and rights to technical change reserved.  
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding  
circuits, descriptions and charts stated herein.  
Information  
For further information on technology, delivery terms and conditions and prices please contact your nearest  
Infineon Technologies Office (www.infineon.com).  
Warnings  
Due to technical requirements components may contain dangerous substances. For information on the types in  
question please contact your nearest Infineon Technologies Office.  
Infineon Technologies Components may only be used in life-support devices or systems with the express written  
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure  
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support  
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain  
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may  
be endangered.  
Data Sheet, Rev. 1.0, Oct. 2004  
HYS72T32000HR–[3.7/5]–A  
HYS72T64001HR–[3.7/5]–A  
HYS72T64020HR–[3.7/5]–A  
240-Pin Registered DDR2 SDRAM Modules  
DDR2 SDRAM  
RDIMM SDRAM  
RoHS Compliant  
Memory Products  
N e v e r s t o p t h i n k i n g .  
HYS72T32000HR–[3.7/5]–A, HYS72T64001HR–[3.7/5]–A, HYS72T64020HR–[3.7/5]–A  
Revision History:  
Rev. 1.0  
2004-10  
Previous Version:  
Rev. 0.85 (2004-04-14)  
Page  
23, 24  
38,42  
all  
Subjects (major changes since last revision)  
DD currents are final  
SPD Code Update  
I
Layout update  
all  
Only green products included  
We Listen to Your Comments  
Any information within this document that you feel is wrong, unclear or missing at all?  
Your feedback will help us to continuously improve the quality of this document.  
Please send your proposal (including a reference to this document) to:  
techdoc.mp@infineon.com  
Template: mp_a4_v2.3_2004-01-14.fm  
HYS72T[32/64]0[0/2][0/1]HR–[3.7/5]–A  
Registered Double-Data-Rate-Two SDRAM Modules  
Table of Contents  
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
1.1  
1.2  
2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
2.1  
Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
3
I
DD Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
3.1  
3.2  
I
DD Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25  
On Die Termination (ODT) Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25  
4
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26  
4.1  
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26  
5
6
7
SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30  
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46  
Product Type Nomenclature (DDR2 DRAMs and DIMMs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49  
Data Sheet  
5
Rev. 1.0, 2004-10  
02182004-UN2L-F13U  
240-Pin Registered DDR2 SDRAM Modules  
DDR2 SDRAM  
HYS72T32000HR–[3.7/5]–A  
HYS72T64001HR–[3.7/5]–A  
HYS72T64020HR–[3.7/5]–A  
1
Overview  
This chapter gives an overview of the 1.8 V 240-pin Registered DDR2 SDRAM Modules product family and  
describes its main characteristics.  
1.1  
Features  
•
•
•
•
240-pin PC2-4200 and PC2-3200 DDR2 SDRAM  
memory modules for PC, Workstation and Server  
main memory applications  
•
Programmable CAS Latencies (3, 4 & 5), Burst  
Length (4 & 8) and Burst Type  
•
•
•
Auto Refresh (CBR) and Self Refresh  
All inputs and outputs SSTL_1.8 compatible  
Off-Chip Driver Impedance Adjustment (OCD) and  
On-Die Termination (ODT)  
One rank 32M x 72, 64M x 72 and two ranks  
64M × 72 module organization and 32M × 8,  
64M × 4 chip organization  
JEDEC  
standard  
Double-Data-Rate-Two  
•
•
Serial Presence Detect with E2PROM  
RDIMM Dimensions (nominal):  
Synchronous DRAMs (DDR2 SDRAM) with a single  
+ 1.8 V (± 0.1 V) power supply  
30,00 mm high, 133.35 mm wide  
Built with 256Mb DDR2 SDRAMs in P-TFBGA-60  
chipsize packages.  
•
•
Based on JEDEC standard reference layouts Raw  
Card “F”, “G” & “H”  
RoHS Compliant Products1)  
Table 1  
Performance  
Product Type Speed Code  
Speed Grade  
max. Clock Frequency  
–3.7  
PC2–4200 4–4–4  
fCK5 266  
fCK4 266  
fCK3 200  
tRCD 15  
–5  
Units  
—
MHz  
MHz  
MHz  
ns  
ns  
ns  
ns  
PC2–3200 3–3–3  
@CL5  
@CL4  
@CL3  
200  
200  
200  
15  
15  
40  
min. RAS-CAS-Delay  
min. Row Precharge Time  
min. Row Active Time  
min. Row Cycle Time  
tRP  
tRAS 45  
tRC 60  
15  
55  
1)RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and  
electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council  
of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated  
biphenyls and polybrominated biphenyl ethers.  
Data Sheet  
6
Rev. 1.0, 2004-10  
02182004-UN2L-F13U  
HYS72T[32/64]0[0/2][0/1]HR–[3.7/5]–A  
Registered Double-Data-Rate-Two SDRAM Modules  
Overview  
1.2  
Description  
The INFINEON HYS72T[32/64]0[0/2][0/1]HR–[3.7/5]– using register devices and a PLL for the clock  
A module family are Registered DIMM modules distribution. This reduces capacitive loading to the  
“RDIMMs” with 30,0 mm height based on DDR2 system bus, but adds one cycle to the SDRAM timing.  
technology. DIMMs are available as ECC modules in Decoupling capacitors are mounted on the PCB board.  
32M x 72 (256 MByte) and 64M x 72 (512 MByte The DIMMs feature serial presence detect based on a  
organization and density, intended for mounting into serial E2PROM device using the 2-pin I2C protocol. The  
240-pin connector sockets.  
first 128 bytes are programmed with configuration data  
and are write-protected; the second 128 bytes are  
available to the customer.  
The memory array is designed with 256 Mb Double-  
Data-Rate-Two (DDR2) Synchronous DRAMs . All  
control and address signals are re-driven on the DIMM  
Table 2  
Ordering Information for RoHS Compliant Products  
Product Type1)  
Compliance Code2)  
Description SDRAM Technology  
PC2-3200  
HYS72T32000HR–5–A  
HYS72T64001HR–5–A  
HYS72T64020HR–5–A  
PC2–4200  
256 MB 1R×8 PC2–3200R–333–11–F1 1 Rank, ECC 256 Mbit (×8)  
512 MB 1R×4 PC2–3200R–333–11–H1 1 Rank, ECC 256 Mbit (×4)  
512 MB 2R×8 PC2–3200R–333–11–G1 2 Rank, ECC 256 Mbit (×8)  
HYS72T32000HR–3.7–A  
HYS72T64001HR–3.7–A  
HYS72T64020HR–3.7–A  
256 MB 1R×8 PC2–4200R–444–11–F1 1 rank, ECC 256 Mbit (×8)  
512 MB 1R×4 PC2–4200R–444–11–H1 1 rank, ECC 256 Mbit (×4)  
512 MB 2R×8 PC2–4200R–444–11–G1 2 rank, ECC 256 Mbit (×8)  
1) All part numbers end with a place code, designating the silicon die revision. Example: HYS72T32000HR–5–A, indicating  
Rev. “A” dies are used for DDR2 SDRAM components. For all INFINEON DDR2 module and component nomenclature see  
Chapter 7 of this data sheet.  
2) The Compliance Code is printed on the module label and describes the speed grade, for example “PC2–4200R–444–11–  
F1”, where 4200R means Registered DIMM modules with 4.26 GB/sec Module Bandwidth and “444-11” means Column  
Address Strobe (CAS) latency = 4, Row Column Delay (RCD) latency = 4 and Row Precharge (RP) latency = 4 using the  
latest JEDEC SPD Revision 1.1 and produced on the Raw Card “F”  
Table 3  
DIMM  
Address Format  
Module  
Memory ECC/  
# of  
# of row/bank/columns bits Raw Card  
Density Organization  
Ranks  
Non-ECC  
SDRAMs  
256 MB  
512 MB  
512 MB  
32M ×72  
64M ×72  
64M ×72  
1
1
2
ECC  
ECC  
ECC  
9
18  
18  
14/2/10  
14/2/11  
14/2/10  
F
H
G
Data Sheet  
7
Rev. 1.0, 2004-10  
02182004-UN2L-F13U  
HYS72T[32/64]0[0/2][0/1]HR–[3.7/5]–A  
Registered Double-Data-Rate-Two SDRAM Modules  
Overview  
Table 4  
Product Type2)  
HYS72T32000HR–3.7–A HYB18T256800AF–3.7  
HYS72T64001HR–3.7–A HYB18T256400AF-3.7  
HYS72T64020HR–3.7–A HYB18T256800AF-3.7  
Components on Modules 1)  
DRAM Components2)  
DRAM Density  
256 Mbit  
256 Mbit  
DRAM Organization  
32M × 8  
64M × 4  
256 Mbit  
32M × 8  
HYS72T32000HR–5–A  
HYS72T64001HR–5–A  
HYS72T64020HR–5–A  
HYB18T256800AF–5  
HYB18T256400AF–5  
HYB18T256800AF–5  
256 Mbit  
256 Mbit  
256 Mbit  
32M × 8  
64M × 4  
32M × 8  
1) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet.  
2) Green Product  
Data Sheet  
8
Rev. 1.0, 2004-10  
02182004-UN2L-F13U  
 
HYS72T[32/64]0[0/2][0/1]HR–[3.7/5]–A  
Registered Double-Data-Rate-Two SDRAM Modules  
Pin Configuration  
2
Pin Configuration  
The pin configuration of the Registered DDR2 SDRAM explained in Table 6 and Table 7 respectively. The pin  
DIMM is listed by function in Table 5 (240 pins). The numbering is depicted in Figure 1.  
abbreviations used in columns Pin and Buffer Type are  
Table 5  
Pin#  
Pin Configuration of RDIMM  
Name  
Pin  
Buffer  
Function  
Type  
Type  
Clock Signals  
185  
186  
CK0  
CK0  
I
I
SSTL  
SSTL  
Clock Signal CK0, Complementary Clock Signal CK0  
Note: The system clock inputs. All address and command lines  
are sampled on the cross point of the rising edge of CK  
and the falling edge of CK. A Delay Locked Loop (DLL)  
circuit is driven from the clock inputs and output timing for  
read operations is synchronized to the input clock.  
52  
171  
CKE0  
CKE1  
I
I
SSTL  
SSTL  
Clock Enables 1:0  
Note: Activates the DDR2 SDRAM CK signal when HIGH and  
deactivates the CK signal when LOW. By deactivating the  
clocks, CKE0 initiates the Power Down Mode or the Self  
Refresh Mode.  
Note: 2-Ranks module  
Note: 1-Rank module  
NC  
NC  
—
Control Signals  
193  
76  
S0  
S1  
I
I
SSTL  
SSTL  
Chip Select Rank 1:0  
Note: Enables the associated DDR2 SDRAM command  
decoder when LOW and disables the command decoder  
when HIGH. When the command decoder is disabled,  
new commands are ignored but previous operations  
continue. Rank 0 is selected by S0; Rank 1 is selected by  
S1. The input signals also disable all outputs (except CKE  
and ODT) of the register(s) on the DIMM when both inputs  
are high. When S is HIGH, all register outputs (except CK,  
ODT and Chip select) remain in the previous state.  
Note: 2-Ranks module  
Note: 1-Rank module  
NC  
NC  
—
192  
74  
73  
RAS  
CAS  
WE  
I
I
I
SSTL  
SSTL  
SSTL  
Row Address Strobe (RAS), Column Address Strobe (CAS),  
Write Enable (WE)  
Note: When sampled at the cross point of the rising edge of  
CK,and falling edge of CK, RAS, CAS and WE define the  
operation to be executed by the SDRAM.  
18  
RESET  
I
CMOS  
Register Reset  
Note: The RESET pin is connected to the RST pin on the  
register and to the OE pin on the PLL. When LOW, all  
register outputs will be driven LOW and the PLL clocks to  
the DRAMs and the register(s) will be set to low level. The  
PLL will remain synchronized with the input clock.  
Address Signals  
71  
190  
BA0  
BA1  
I
I
SSTL  
SSTL  
Bank Address Bus 1:0  
Note: Selects internal SDRAM memory bank  
Data Sheet  
9
Rev. 1.0, 2004-10  
02182004-UN2L-F13U  
HYS72T[32/64]0[0/2][0/1]HR–[3.7/5]–A  
Registered Double-Data-Rate-Two SDRAM Modules  
Pin Configuration  
Table 5  
Pin#  
Pin Configuration of RDIMM (cont’d)  
Name  
Pin  
Buffer  
Function  
Type  
Type  
54  
BA2  
I
SSTL  
Bank Address Bus 2  
Note: greater than 512Mb DDR2 SDRAMS  
Note: less than 1Gb DDR2 SDRAMS  
Address Bus 12:0, Address Signal 10/AutoPrecharge  
NC  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
188  
183  
63  
182  
61  
60  
180  
58  
Note: During a Bank Activate command cycle, defines the row  
address when sampled at the crosspoint of the rising  
edge of CK and falling edge of CK. During a Read or Write  
command cycle, defines the column address when  
sampled at the cross point of the rising edge of CK and  
falling edge of CK. In addition to the column address, AP  
is used to invoke autoprecharge operation at the end of  
the burst read or write cycle. If AP is HIGH, autoprecharge  
is selected and BA[1:0] defines the bank to be  
precharged. If AP is LOW, autoprecharge is disabled.  
During a Precharge command cycle, AP is used in  
conjunction with BA[1:0] to control which bank(s) to  
precharge. If AP is HIGH, all banks will be precharged  
regardless of the state of BA[1:0] inputs. If AP is LOW,  
then BA[1:0] are used to define which bank to precharge.  
179  
177  
70  
A8  
A9  
A10  
AP  
A11  
A12  
A13  
57  
176  
196  
Address Signal 13  
Note: modules based on ×4, ×8  
Note: modules based on ×16  
Address Signal 14  
NC  
A14  
NC  
I
–
174  
SSTL  
Note: 2 Gbit based module  
NC  
NC  
–
Note: 1 Gbit based module or smaller  
Data Sheet  
10  
Rev. 1.0, 2004-10  
02182004-UN2L-F13U  
HYS72T[32/64]0[0/2][0/1]HR–[3.7/5]–A  
Registered Double-Data-Rate-Two SDRAM Modules  
Pin Configuration  
Table 5  
Pin#  
Pin Configuration of RDIMM (cont’d)  
Name  
Pin  
Buffer  
Function  
Type  
Type  
Data Signals  
3
4
9
10  
122  
123  
128  
129  
12  
13  
21  
22  
131  
132  
140  
141  
24  
25  
30  
31  
143  
144  
149  
150  
33  
DQ0  
DQ1  
DQ2  
DQ3  
DQ4  
DQ5  
DQ6  
DQ7  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
Data Bus 63:0  
Note: Data Input/Output pins  
DQ8  
DQ9  
DQ10  
DQ11  
DQ12  
DQ13  
DQ14  
DQ15  
DQ16  
DQ17  
DQ18  
DQ19  
DQ20  
DQ21  
DQ22  
DQ23  
DQ24  
DQ25  
DQ26  
DQ27  
34  
39  
40  
Data Sheet  
11  
Rev. 1.0, 2004-10  
02182004-UN2L-F13U  
HYS72T[32/64]0[0/2][0/1]HR–[3.7/5]–A  
Registered Double-Data-Rate-Two SDRAM Modules  
Pin Configuration  
Table 5  
Pin#  
Pin Configuration of RDIMM (cont’d)  
Name  
Pin  
Buffer  
Function  
Type  
Type  
152  
153  
158  
159  
80  
81  
86  
87  
199  
200  
205  
206  
89  
90  
95  
96  
DQ28  
DQ29  
DQ30  
DQ31  
DQ32  
DQ33  
DQ34  
DQ35  
DQ36  
DQ37  
DQ38  
DQ39  
DQ40  
DQ41  
DQ42  
DQ43  
DQ44  
DQ45  
DQ46  
DQ47  
DQ48  
DQ49  
DQ50  
DQ51  
DQ52  
DQ53  
DQ54  
DQ55  
DQ56  
DQ57  
DQ58  
DQ59  
DQ60  
DQ61  
DQ62  
DQ63  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
Data Bus 63:0  
208  
209  
214  
215  
98  
99  
107  
108  
217  
218  
226  
227  
110  
111  
116  
117  
229  
230  
235  
236  
Data Sheet  
12  
Rev. 1.0, 2004-10  
02182004-UN2L-F13U  
HYS72T[32/64]0[0/2][0/1]HR–[3.7/5]–A  
Registered Double-Data-Rate-Two SDRAM Modules  
Pin Configuration  
Table 5  
Pin#  
Pin Configuration of RDIMM (cont’d)  
Name  
Pin  
Buffer  
Function  
Type  
Type  
42  
43  
48  
49  
161  
162  
167  
168  
CB0  
CB1  
CB2  
CB3  
CB4  
CB5  
CB6  
CB7  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
Check Bits 7:0  
Note: Check Bit Input / Output pins  
Note: NC on Non-ECC module  
Data Strobe Bus  
7
6
DQS0  
DQS0  
DQS1  
DQS1  
DQS2  
DQS2  
DQS3  
DQS3  
DQS4  
DQS4  
DQS5  
DQS5  
DQS6  
DQS6  
DQS7  
DQS7  
DQS8  
DQS8  
DQS9  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
–
Data Strobes 17:0  
Note: The data strobes, associated with one data byte, sourced  
with data transfers. In Write mode, the data strobe is  
sourced by the controller and is centered in the data  
window. In Read mode the data strobe is sourced by the  
DDR2 SDRAM and is sent at the leading edge of the data  
window. DQS signals are complements, and timing is  
relative to the crosspoint of respective DQS and DQS. If  
the module is to be operated in single ended strobe mode,  
all DQS signals must be tied on the system board to VSS  
through a 20 ohm to 10 Kohm resistor and DDR2 SDRAM  
mode registers programmed appropriately.  
16  
15  
28  
27  
37  
36  
84  
83  
93  
92  
105  
104  
114  
113  
46  
45  
126  
Note: See block diagram for corresponding DQ signals  
Note: ×8 based DIMMs only  
Note: ×4 based DIMMs  
135  
147  
156  
203  
212  
DQS10 I/O  
NC NC  
DQS11 I/O  
NC NC  
DQS12 I/O  
NC NC  
DQS13 I/O  
NC NC  
DQS14 I/O  
NC NC  
SSTL  
–
SSTL  
–
SSTL  
–
SSTL  
–
Note: ×8 based DIMMs only  
Note: ×4 based DIMMs  
Note: ×8 based DIMMs only  
Note: ×4 based DIMMs  
Note: ×8 based DIMMs only  
Note: ×4 based DIMMs  
Note: ×8 based DIMMs only  
Note: ×4 based DIMMs  
SSTL  
–
Note: ×8 based DIMMs only  
Note: ×4 based DIMMs  
Data Sheet  
13  
Rev. 1.0, 2004-10  
02182004-UN2L-F13U  
HYS72T[32/64]0[0/2][0/1]HR–[3.7/5]–A  
Registered Double-Data-Rate-Two SDRAM Modules  
Pin Configuration  
Table 5  
Pin#  
Pin Configuration of RDIMM (cont’d)  
Name  
Pin  
Buffer  
Function  
Type  
Type  
224  
233  
165  
DQS15 I/O  
NC NC  
DQS16 I/O  
NC NC  
DQS17 I/O  
SSTL  
–
SSTL  
–
SSTL  
–
Note: ×8 based DIMMs only  
Note: ×4 based DIMMs  
Note: ×8 based DIMMs only  
Note: ×4 based DIMMs  
Note: ×8 based DIMMs only  
Note: ×4 based DIMMs  
Data Strobes 17:9  
NC  
DQS9  
NC  
I/O  
125  
134  
146  
155  
202  
211  
223  
232  
164  
125  
134  
146  
155  
202  
211  
223  
232  
164  
EEPROM  
120  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
Note: ×4 based module  
DQS10 I/O  
DQS11 I/O  
DQS12 I/O  
DQS13 I/O  
DQS14 I/O  
DQS15 I/O  
DQS16 I/O  
DQS17 I/O  
DM0  
DM1  
DM2  
DM3  
DM4  
DM5  
DM6  
DM7  
DM8  
I
I
I
I
I
I
I
I
I
Data Masks 7:0  
Note: The data write masks, associated with one data byte. In  
Write mode, DM operates as a byte mask by allowing  
input data to be written if it is LOW but blocks the write  
operation if it is HIGH. In Read mode, DM lines have no  
effect.  
Note: ×8 based module  
SCL  
SDA  
I
CMOS  
OD  
Serial Bus Clock  
Note: This signal is used to clock data into and out of the SPD  
EEPROM.  
Serial Bus Data  
119  
I/O  
Note: This is a bidirectional pin used to transfer data into or out  
of the SPD EEPROM. A resistor must be connected from  
SDA to VDDSPD on the motherboard to act as a pull-up.  
239  
240  
101  
SA0  
SA1  
SA2  
I
I
I
CMOS  
CMOS  
CMOS  
Serial Address Select Bus 2:0  
Note: These signals are tied at the system planar to either VSS  
or VDDSPD to configure the serial SPD EEPROM address  
range  
Power Supplies  
1
VREF  
AI  
–
I/O Reference Voltage  
Note: Reference voltage for the SSTL-18 inputs.  
Data Sheet  
14  
Rev. 1.0, 2004-10  
02182004-UN2L-F13U  
HYS72T[32/64]0[0/2][0/1]HR–[3.7/5]–A  
Registered Double-Data-Rate-Two SDRAM Modules  
Pin Configuration  
Table 5  
Pin#  
Pin Configuration of RDIMM (cont’d)  
Name  
Pin  
Buffer  
Function  
Type  
Type  
238  
VDDSPD PWR  
–
EEPROM Power Supply  
Note: Serial EEPROM positive power supply, wired to a  
separated power pin at the connector which supports from  
1.7 Volt to 3.6 Volt.  
51, 56, 62, 72,  
75, 78, 170, 175,  
181, 191, 194  
VDDQ  
PWR  
PWR  
–
–
I/O Driver Power Supply  
Note: Power and ground for the DDR SDRAM  
53, 59, 64, 67,  
69, 172, 178,  
184,  
VDD  
Power Supply  
Note: Power and ground for the DDR SDRAM  
187, 189, 197  
2, 5, 8, 11, 14,  
17, 20, 23, 26,  
29, 32, 35, 38,  
41, 44, 47, 50,  
65, 66, 79, 82,  
85, 88, 91, 94,  
97, 100, 103,  
106, 109, 112,  
115, 118, 121,  
124, 127, 130,  
133, 136, 139,  
142, 145, 148,  
151, 154, 157,  
160, 163, 166,  
169, 198, 201,  
204, 207, 210,  
213, 216, 219,  
222, 225, 228,  
231, 234, 237  
VSS  
GND  
–
Ground Plane  
Note: Power and ground for the DDR SDRAM  
Other Pins  
19, 55, 68, 102, NC  
137, 138, 173,  
220, 221  
NC  
–
Not connected  
Pins not connected on Infineon RDIMM’s  
195  
77  
ODT0  
ODT1  
I
I
SSTL  
SSTL  
On-Die Termination Control 1:0  
Note: Asserts on-die termination for DQ, DM, DQS, and DQS  
signals if enabled via the DDR2 SDRAM mode register.  
Note: 2-Ranks module  
Note: 1-Rank modules  
NC  
NC  
–
Table 6  
Abbreviation  
SSTL  
CMOS  
OD  
Abbreviations for Buffer Type  
Description  
Serial Stub Terminated Logic (SSTL_18)  
CMOS Levels  
Open Drain. The corresponding pin has 2 operational states, active low and tristate,  
and allows multiple devices to share as a wire-OR.  
Data Sheet  
15  
Rev. 1.0, 2004-10  
02182004-UN2L-F13U  
HYS72T[32/64]0[0/2][0/1]HR–[3.7/5]–A  
Registered Double-Data-Rate-Two SDRAM Modules  
Pin Configuration  
Table 7  
Abbreviation  
Abbreviations for Pin Type  
Description  
I
O
Standard input-only pin. Digital levels.  
Output. Digital levels.  
I/O is a bidirectional input/output signal.  
Input. Analog levels.  
Power  
Ground  
Not Usable  
Not Connected  
I/O  
AI  
PWR  
GND  
NU  
NC  
Data Sheet  
16  
Rev. 1.0, 2004-10  
02182004-UN2L-F13U  
HYS72T[32/64]0[0/2][0/1]HR–[3.7/5]–A  
Registered Double-Data-Rate-Two SDRAM Modules  
Pin Configuration  
VREF  
DQ0  
VSS  
- Pin 001  
- Pin 003  
- Pin 005  
- Pin 007  
- Pin 009  
- Pin 011  
- Pin 013  
- Pin 015  
- Pin 017  
- Pin 019  
Pin 121 - VSS  
Pin 122 - DQ4  
VSS  
- Pin 002  
- Pin 004  
Pin 123 - DQ5  
DQ1  
Pin 124 - VSS  
Pin 125 - DM0/DQS9  
Pin 126 - NC/DQS9  
Pin 127 - VSS  
DQS0 - Pin 006  
DQS0  
DQ2  
VSS  
VSS  
- Pin 008  
- Pin 010  
- Pin 012  
- Pin 014  
Pin 128 - DQ6  
Pin 129 - DQ7  
DQ3  
DQ8  
VSS  
Pin 130 - VSS  
Pin 131 - DQ12  
Pin 132 - DQ13  
Pin 133 - VSS  
DQ9  
DQS1  
VSS  
Pin 134 - DM1/DQS10  
Pin 135 - NC/DQS10  
Pin 136 - VSS  
DQS1 - Pin 016  
RESET - Pin 018  
Pin 137 - NC  
Pin 138 - NC  
NC  
Pin 139 - VSS  
VSS  
- Pin 020  
Pin 140 - DQ14  
-
DQ10  
VSS  
Pin 021  
Pin 141  
Pin 143  
Pin 145  
Pin 147  
Pin 149  
Pin 151  
Pin 153  
Pin 155  
Pin 157  
Pin 159  
Pin 161  
Pin 163  
Pin 165  
Pin 167  
Pin 169  
Pin 171  
Pin 173  
Pin 175  
Pin 177  
Pin 179  
Pin 181  
Pin 183  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DQ15  
DQ20  
VSS  
-
-
Pin 142 VSS  
DQ11  
DQ16  
VSS  
Pin 022  
-
Pin 023  
-
-
Pin 144 DQ21  
Pin 024  
DQ17  
DQS2  
VSS  
- Pin 025  
- Pin 027  
- Pin 029  
- Pin 031  
- Pin 033  
- Pin 035  
- Pin 037  
- Pin 039  
- Pin 041  
- Pin 043  
- Pin 045  
- Pin 047  
- Pin 049  
- Pin 051  
- Pin 053  
- Pin 055  
- Pin 057  
- Pin 059  
- Pin 061  
- Pin 063  
-
-
-
-
-
Pin 146 DM2/DQS11  
Pin 026  
Pin 028  
Pin 030  
Pin 032  
NC/DQS11  
DQ22  
VSS  
-
Pin 148 VSS  
DQS2  
DQ18  
VSS  
-
Pin 150 DQ23  
DQ19  
DQ24  
VSS  
-
Pin 152 DQ28  
DQ29  
DM3/DQS12  
VSS  
DQ25 - Pin 034  
DQS3 - Pin 036  
Pin 154 - VSS  
Pin 156 - NC/DQS12  
Pin 158 - DQ30  
Pin 160 - VSS  
DQS3  
DQ26  
VSS  
VSS  
- Pin 038  
DQ31  
CB4  
DQ27 - Pin 040  
-
Pin 162 CB5  
CB0  
VSS  
- Pin 042  
CB1  
DQS8  
VSS  
VSS  
-
-
-
-
-
-
Pin 164 DM8/DQS17  
Pin 044  
Pin 046  
Pin 048  
Pin 050  
Pin 052  
NC/DQS17  
CB6  
-
Pin 166 VSS  
DQS8  
CB2  
VSS  
-
Pin 168 CB7  
CB3  
VDDQ  
VDD  
VSS  
-
Pin 170 VDDQ  
NC/CKE1  
NC  
-
Pin 172 VDD  
CKE0  
-
-
Pin 174 NC/A14  
NC/BA2 Pin 054  
NC  
VDDQ  
-
-
-
-
-
Pin 176 A12  
VDDQ  
A7  
Pin 056  
Pin 058  
Pin 060  
Pin 062  
A11  
A9  
-
Pin 178 VDD  
VDD  
A8  
-
Pin 180 A6  
A5  
A4  
VDDQ  
-
VDDQ  
VDD  
Pin 182 A3  
A2  
A1  
- Pin 064  
Pin 184 - VDD  
VSS  
- Pin 065  
- Pin 067  
- Pin 069  
- Pin 071  
- Pin 073  
- Pin 075  
Pin 185  
Pin 187  
Pin 189  
Pin 191  
Pin 193  
Pin 195  
Pin 197  
Pin 199  
Pin 201  
Pin 203  
Pin 205  
Pin 207  
Pin 209  
Pin 211  
Pin 213  
Pin 215  
Pin 217  
Pin 219  
Pin 221  
Pin 223  
Pin 225  
Pin 227  
Pin 229  
Pin 231  
Pin 233  
Pin 235  
Pin 237  
Pin 239  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CK0  
-
Pin 186 CK0  
VSS  
NC  
- Pin 066  
- Pin 068  
VDD  
VDD  
BA0  
WE  
VDD  
-
Pin 188 A0  
VDD  
A10/AP - Pin 070  
Pin 190 - BA1  
VDDQ  
-
-
-
-
-
-
-
-
-
Pin 192 RAS  
VDDQ  
CAS  
Pin 072  
Pin 074  
Pin 076  
Pin 078  
Pin 080  
Pin 082  
Pin 084  
Pin 086  
S0  
-
Pin 194 VDDQ  
VDDQ  
ODT0  
VDD  
-
Pin 196 NC/A13  
NC/S1  
VDDQ  
DQ32  
VSS  
NC/ODT1 - Pin 077  
-
Pin 198 VSS  
VSS  
- Pin 079  
- Pin 081  
- Pin 083  
- Pin 085  
- Pin 087  
- Pin 089  
- Pin 091  
- Pin 093  
- Pin 095  
- Pin 097  
- Pin 099  
- Pin 101  
- Pin 103  
- Pin 105  
- Pin 107  
- Pin 109  
- Pin 111  
- Pin 113  
- Pin 115  
- Pin 117  
- Pin 119  
DQ36  
VSS  
-
Pin 200 DQ37  
DQ33  
DQS4  
VSS  
-
Pin 202 DM4/DQS13  
NC/DQS13  
DQ38  
VSS  
-
Pin 204 VSS  
DQS4  
DQ34  
VSS  
-
Pin 206 DQ39  
DQ35  
DQ40  
VSS  
- Pin 088  
Pin 208 - DQ44  
Pin 210 - VSS  
DQ45  
DM5/DQS14  
VSS  
DQ41 - Pin 090  
DQS5 - Pin 092  
Pin 212 - NC/DQS14  
Pin 214 - DQ46  
DQS5  
DQ42  
VSS  
VSS  
- Pin 094  
DQ47  
DQ52  
VSS  
-
Pin 216 VSS  
DQ43 - Pin 096  
DQ48 - Pin 098  
-
Pin 218 DQ53  
DQ49  
SA2  
-
-
-
-
-
-
-
-
-
-
Pin 220 NC  
VSS  
Pin 100  
Pin 102  
Pin 104  
Pin 106  
Pin 108  
Pin 110  
Pin 112  
Pin 114  
Pin 116  
NC  
-
Pin 222 VSS  
NC  
VSS  
DM6/DQS15  
VSS  
-
Pin 224 NC/DQS15  
DQS6  
VSS  
DQS6  
DQ50  
VSS  
-
Pin 226 DQ54  
DQ55  
DQ60  
VSS  
-
Pin 228 VSS  
DQ51  
DQ56  
VSS  
-
Pin 230 DQ61  
DQ57  
DQS7  
VSS  
-
Pin 232 DM7/DQS16  
NC/DQS16  
DQ62  
VSS  
-
Pin 234 VSS  
DQS7  
DQ58  
VSS  
-
Pin 236 DQ63  
DQ59  
SDA  
- Pin 118  
- Pin 120  
Pin 238 VDDSPD  
Pin 240 SA1  
SA0  
SCL  
MPPT0170  
Figure 1  
Pin Configuration for RDIMM (240 pins)  
Data Sheet  
17  
Rev. 1.0, 2004-10  
02182004-UN2L-F13U  
HYS72T[32/64]0[0/2][0/1]HR–[3.7/5]–A  
Registered Double-Data-Rate-Two SDRAM Modules  
Pin Configuration  
2.1  
Block Diagrams  
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ꢇꢄ  
ꢇꢉ  
ꢇꢌ  
ꢇꢍ  
ꢇꢊ  
ꢇꢋ  
ꢇꢆ  
ꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢑꢏ  
ꢒꢇꢎꢏ  
ꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢑꢏ  
ꢒꢇꢎꢏ  
ꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢑꢏ  
ꢒꢇꢎꢏ  
ꢇꢎꢏꢄ  
ꢇꢎꢏꢄ  
ꢇꢎꢏꢉ  
ꢇꢎꢏꢉ  
ꢇꢎꢏꢊ  
ꢇꢎꢏꢊ  
ꢒꢇꢎꢏ  
ꢒꢇꢎꢏ  
ꢒꢇꢎꢏ  
ꢇꢀꢄꢐꢇꢎꢏꢙ  
ꢇꢎꢏꢙ  
ꢇꢎꢄ  
ꢒꢇꢀꢐꢚꢇꢎꢏ  
ꢒ%&ꢐꢚꢇꢎꢏ  
ꢒ'ꢐꢔꢒꢄ  
ꢇꢀꢉꢐꢇꢎꢏꢅꢈ  
ꢇꢎꢏꢅꢈ  
ꢇꢎꢈꢌ  
ꢒꢇꢀꢐꢚꢇꢎꢏ  
ꢒ%&ꢐꢚꢇꢎꢏ  
ꢒ'ꢐꢔꢒꢄ  
ꢇꢀꢊꢐꢇꢎꢏꢅꢍ  
ꢇꢎꢏꢅꢍ  
ꢇꢎꢌꢆ  
ꢒꢇꢀꢐꢚꢇꢎꢏ  
ꢒ%&ꢐꢚꢇꢎꢏ  
ꢒ'ꢐꢔꢒꢄ  
ꢇꢎꢅ  
ꢒ'ꢐꢔꢒꢅ  
ꢇꢎꢈꢍ  
ꢒ'ꢐꢔꢒꢅ  
ꢇꢎꢌꢙ  
ꢒ'ꢐꢔꢒꢅ  
ꢇꢎꢈ  
ꢒ'ꢐꢔꢒꢈ  
ꢇꢎꢈꢊ  
ꢒ'ꢐꢔꢒꢈ  
ꢇꢎꢍꢄ  
ꢒ'ꢐꢔꢒꢈ  
ꢇꢎꢉ  
ꢒ'ꢐꢔꢒꢉ  
ꢇꢎꢈꢋ  
ꢒ'ꢐꢔꢒꢉ  
ꢇꢎꢍꢅ  
ꢒ'ꢐꢔꢒꢉ  
ꢇꢎꢌ  
ꢒ'ꢐꢔꢒꢌ  
ꢇꢎꢈꢆ  
ꢒ'ꢐꢔꢒꢌ  
ꢇꢎꢍꢈ  
ꢒ'ꢐꢔꢒꢌ  
ꢇꢎꢍ  
ꢒ'ꢐꢔꢒꢍ  
ꢇꢎꢈꢙ  
ꢒ'ꢐꢔꢒꢍ  
ꢇꢎꢍꢉ  
ꢒ'ꢐꢔꢒꢍ  
ꢇꢎꢊ  
ꢒ'ꢐꢔꢒꢊ  
ꢇꢎꢉꢄ  
ꢒ'ꢐꢔꢒꢊ  
ꢇꢎꢍꢌ  
ꢒ'ꢐꢔꢒꢊ  
ꢇꢎꢋ  
ꢒ'ꢐꢔꢒꢋ  
ꢇꢎꢉꢅ  
ꢒ'ꢐꢔꢒꢋ  
ꢇꢎꢍꢍ  
ꢒ'ꢐꢔꢒꢋ  
ꢇꢅ  
ꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢑꢏ  
ꢒꢇꢎꢏ  
ꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢑꢏ  
ꢒꢇꢎꢏ  
ꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢑꢏ  
ꢒꢇꢎꢏ  
ꢇꢎꢏꢅ  
ꢇꢎꢏꢅ  
ꢇꢎꢏꢌ  
ꢇꢎꢏꢌ  
ꢇꢎꢏꢋ  
ꢇꢎꢏꢋ  
ꢒꢇꢎꢏ  
ꢒꢇꢎꢏ  
ꢒꢇꢎꢏ  
ꢇꢀꢅꢐꢇꢎꢏꢅꢄ  
ꢇꢎꢏꢅꢄ  
ꢇꢎꢆ  
ꢒꢇꢀꢐꢚꢇꢎꢏ  
ꢒ%&ꢐꢚꢇꢎꢏ  
ꢒ'ꢐꢔꢒꢄ  
ꢇꢀꢌꢐꢇꢎꢏꢅꢉ  
ꢇꢎꢏꢅꢉ  
ꢇꢎꢉꢈ  
ꢒꢇꢀꢐꢚꢇꢎꢏ  
ꢒ%&ꢐꢚꢇꢎꢏ  
ꢒ'ꢐꢔꢒꢄ  
ꢇꢀꢋꢐꢇꢎꢏꢅꢊ  
ꢇꢎꢏꢅꢊ  
ꢇꢎꢍꢊ  
ꢒꢇꢀꢐꢚꢇꢎꢏ  
ꢒ%&ꢐꢚꢇꢎꢏ  
ꢒ'ꢐꢔꢒꢄ  
ꢇꢎꢙ  
ꢒ'ꢐꢔꢒꢅ  
ꢇꢎꢉꢉ  
ꢒ'ꢐꢔꢒꢅ  
ꢇꢎꢍꢋ  
ꢒ'ꢐꢔꢒꢅ  
ꢇꢎꢅꢄ  
ꢒ'ꢐꢔꢒꢈ  
ꢇꢎꢉꢌ  
ꢒ'ꢐꢔꢒꢈ  
ꢇꢎꢍꢆ  
ꢒ'ꢐꢔꢒꢈ  
ꢇꢎꢅꢅ  
ꢒ'ꢐꢔꢒꢉ  
ꢇꢎꢉꢍ  
ꢒ'ꢐꢔꢒꢉ  
ꢇꢎꢍꢙ  
ꢒ'ꢐꢔꢒꢉ  
ꢇꢎꢅꢈ  
ꢒ'ꢐꢔꢒꢌ  
ꢇꢎꢉꢊ  
ꢒ'ꢐꢔꢒꢌ  
ꢇꢎꢊꢄ  
ꢒ'ꢐꢔꢒꢌ  
ꢇꢎꢅꢉ  
ꢒ'ꢐꢔꢒꢍ  
ꢇꢎꢉꢋ  
ꢒ'ꢐꢔꢒꢍ  
ꢇꢎꢊꢅ  
ꢒ'ꢐꢔꢒꢍ  
ꢇꢎꢅꢌ  
ꢒ'ꢐꢔꢒꢊ  
ꢇꢎꢉꢆ  
ꢒ'ꢐꢔꢒꢊ  
ꢇꢎꢊꢈ  
ꢒ'ꢐꢔꢒꢊ  
ꢇꢎꢅꢍ  
ꢒ'ꢐꢔꢒꢋ  
ꢇꢎꢉꢙ  
ꢒ'ꢐꢔꢒꢋ  
ꢇꢎꢊꢉ  
ꢒ'ꢐꢔꢒꢋ  
ꢇꢈ  
ꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢑꢏ  
ꢒꢇꢎꢏ  
ꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢑꢏ  
ꢒꢇꢎꢏ  
ꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢑꢏ  
ꢒꢇꢎꢏ  
ꢇꢎꢏꢈ  
ꢇꢎꢏꢈ  
ꢇꢎꢏꢍ  
ꢇꢎꢏꢍ  
ꢇꢎꢏꢆ  
ꢇꢎꢏꢆ  
ꢇꢀꢆꢐꢇꢎꢏꢅꢋ  
ꢇꢎꢏꢅꢋ  
ꢑꢂꢄ  
ꢒꢇꢎꢏ  
ꢒꢇꢎꢏ  
ꢒꢇꢎꢏ  
ꢇꢀꢈꢐꢇꢎꢏꢅꢅ  
ꢇꢎꢏꢅꢅ  
ꢇꢎꢅꢊ  
ꢒꢇꢀꢐꢚꢇꢎꢏ  
ꢒ%&ꢐꢚꢇꢎꢏ  
ꢒ'ꢐꢔꢒꢄ  
ꢇꢀꢍꢐꢇꢎꢏꢅꢌ  
ꢇꢎꢏꢅꢌ  
ꢇꢎꢌꢄ  
ꢒꢇꢀꢐꢚꢇꢎꢏ  
ꢒ%&ꢐꢚꢇꢎꢏ  
ꢒ'ꢐꢔꢒꢄ  
ꢒꢇꢀꢐꢚꢇꢎꢏ  
ꢒ%&ꢐꢚꢇꢎꢏ  
ꢒ'ꢐꢔꢒꢄ  
ꢇꢎꢅꢋ  
ꢒ'ꢐꢔꢒꢅ  
ꢇꢎꢌꢅ  
ꢒ'ꢐꢔꢒꢅ  
ꢑꢂꢅ  
ꢒ'ꢐꢔꢒꢅ  
ꢇꢎꢅꢆ  
ꢒ'ꢐꢔꢒꢈ  
ꢇꢎꢌꢈ  
ꢒ'ꢐꢔꢒꢈ  
ꢑꢂꢈ  
ꢒ'ꢐꢔꢒꢈ  
ꢇꢎꢅꢙ  
ꢒ'ꢐꢔꢒꢉ  
ꢇꢎꢌꢉ  
ꢒ'ꢐꢔꢒꢉ  
ꢑꢂꢉ  
ꢒ'ꢐꢔꢒꢉ  
ꢇꢎꢈꢄ  
ꢒ'ꢐꢔꢒꢌ  
ꢇꢎꢌꢌ  
ꢒ'ꢐꢔꢒꢌ  
ꢑꢂꢌ  
ꢒ'ꢐꢔꢒꢌ  
ꢇꢎꢈꢅ  
ꢒ'ꢐꢔꢒꢍ  
ꢇꢎꢌꢍ  
ꢒ'ꢐꢔꢒꢍ  
ꢑꢂꢍ  
ꢒ'ꢐꢔꢒꢍ  
ꢇꢎꢈꢈ  
ꢒ'ꢐꢔꢒꢊ  
ꢇꢎꢌꢊ  
ꢒ'ꢐꢔꢒꢊ  
ꢑꢂꢊ  
ꢒ'ꢐꢔꢒꢊ  
ꢇꢎꢈꢉ  
ꢒ'ꢐꢔꢒꢋ  
ꢇꢎꢌꢋ  
ꢒ'ꢐꢔꢒꢋ  
ꢑꢂꢋ  
ꢒ'ꢐꢔꢒꢋ  
ꢀꢁꢂꢃꢄꢅꢆꢄ  
Figure 2  
Block Diagram Raw Card F RDIMM (x72, 1Rank, x8)  
Notes  
2. S0 connects to DCS and VDD connects to CSR on  
the register.  
1. Unless otherwise noted, resistors are 22 Ω ± 5 %  
Data Sheet  
18  
Rev. 1.0, 2004-10  
02182004-UN2L-F13U  
HYS72T[32/64]0[0/2][0/1]HR–[3.7/5]–A  
Registered Double-Data-Rate-Two SDRAM Modules  
Pin Configuration  
ꢀꢇꢇꢘꢏꢁꢇ  
ꢀꢇꢇꢛꢒꢏꢁꢇꢒꢕꢕꢁꢚꢔꢀꢒꢕꢄ  
ꢑꢖꢄ  
ꢑꢖꢄ  
ꢒꢒꢒꢁꢓꢓ  
ꢁꢑꢖꢄꢗꢁꢑꢖꢊꢘꢒꢁꢑꢖꢆꢘꢒꢁꢑꢖꢙ  
ꢁꢑꢖꢄꢗꢁꢑꢖꢊꢘꢒꢁꢑꢖꢆꢘꢒꢁꢑꢖꢙ  
ꢁꢑꢖꢋ  
ꢑꢖꢛꢒꢏꢇꢚꢜꢀꢝꢒꢇꢄꢗꢇꢅꢋ  
ꢑꢖꢛꢒꢏꢇꢚꢜꢀꢝꢒꢇꢄꢗꢇꢅꢋ  
ꢑꢖꢛꢒꢚ !"ꢝ# $  
ꢀ
ꢐꢀ  
ꢀ
ꢀ
ꢀ
ꢐꢀ  
ꢛꢒꢏꢇꢚꢜꢀꢝꢒꢇꢄꢗꢇꢅꢋ  
ꢇꢇ ꢇꢇꢎ  
ꢇꢇ ꢇꢇꢎ  
ꢀꢚꢕꢞ  
ꢚꢕꢞꢛꢒꢏꢇꢚꢜꢀꢝꢒꢇꢄꢗꢇꢅꢋ  
ꢚꢕꢏꢕꢃ  
ꢒꢔꢕ  
ꢅꢛꢈ  
ꢁꢑꢖꢋ  
ꢑꢖꢛꢒꢚ !"ꢝ# $  
ꢀ
ꢛꢒꢏꢇꢚꢜꢀꢝꢒꢇꢄꢗꢇꢅꢋ  
ꢏꢏ  
ꢏꢏ  
ꢏꢄ  
ꢏꢅ  
ꢚꢏꢄ  
ꢑꢏꢛꢒꢏꢇꢚꢜꢀꢝꢒꢇꢄꢗꢇꢆ  
ꢑꢏꢛꢒꢏꢇꢚꢜꢀꢝꢒꢇꢙꢗꢇꢅꢋ  
ꢚꢏꢅ  
ꢂꢜꢄꢒꢗꢒꢂꢜ*  
ꢜꢄꢒꢗꢒꢜ*  
ꢚꢜꢏ  
ꢚ
ꢕ
)
'
ꢚꢂꢜꢄꢗꢚꢂꢜ*  
ꢚꢜꢄꢗꢚꢜ*  
ꢚꢚꢜꢏ  
ꢂꢜꢄꢗꢂꢜ*ꢛꢒꢏꢇꢚꢜꢀꢝꢒꢇꢄꢗꢇꢅꢋ  
ꢜꢄꢗꢜ*ꢛꢒꢏꢇꢚꢜꢀꢝꢒꢇꢄꢗꢇꢅꢋ  
ꢚꢜꢏꢛꢒꢏꢇꢚꢜꢀꢝꢒꢇꢄꢗꢇꢅꢋ  
ꢑꢜꢏꢛꢒꢏꢇꢚꢜꢀꢝꢒꢇꢄꢗꢇꢅꢋ  
(ꢕꢛꢒꢏꢇꢚꢜꢀꢝꢒꢇꢄꢗꢇꢅꢋ  
ꢑꢖꢕꢄꢛꢒꢏꢇꢚꢜꢀꢝꢒꢇꢄꢗꢇꢆ  
ꢑꢖꢕꢅꢛꢒꢏꢇꢚꢜꢀꢝꢒꢇꢙꢗꢇꢅꢋ  
ꢔꢇꢃꢄꢛꢒꢏꢇꢚꢜꢀꢝꢒꢇꢄꢗꢇꢆ  
ꢔꢇꢃꢅꢛꢒꢏꢇꢚꢜꢀꢝꢒꢇꢙꢗꢇꢅꢋ  
ꢇꢌ  
ꢇꢅꢉ  
ꢇꢅꢌ  
ꢇꢅꢍ  
ꢇꢅꢊ  
ꢇꢅꢋ  
ꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢑꢏ  
ꢒꢇꢎꢏ  
ꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢑꢏ  
ꢒꢇꢎꢏ  
ꢇꢎꢏꢌ  
ꢑꢜꢏ  
ꢚꢑꢜꢏ  
ꢏ
ꢃ
ꢕ
ꢚ
ꢇꢎꢏꢌ  
ꢇꢀꢌꢐꢇꢎꢏꢅꢉ  
ꢇꢎꢏꢅꢉ  
ꢇꢎꢉꢈ  
ꢒꢇꢎꢏ  
ꢒꢇꢎꢏ  
(ꢕ  
ꢚ(ꢕ  
ꢒꢇꢀꢐꢚꢇꢎꢏ  
ꢒ%&ꢐꢚꢇꢎꢏ  
ꢒ'ꢐꢔꢒꢄ  
ꢒꢇꢀꢐꢚꢇꢎꢏ  
ꢒ%&ꢐꢚꢇꢎꢏ  
ꢒ'ꢐꢔꢒꢄ  
ꢑꢖꢕꢄ  
ꢑꢖꢕꢅ  
ꢔꢇꢃꢄ  
ꢔꢇꢃꢅ  
ꢁꢑꢖꢋ  
ꢁꢑꢖꢋ  
ꢚꢕꢏꢕꢃ  
ꢚꢑꢖꢕꢄ  
ꢚꢑꢖꢕꢅ  
ꢚꢔꢇꢃꢄ  
ꢚꢔꢇꢃꢅ  
ꢇꢎꢉꢉ  
ꢒ'ꢐꢔꢒꢅ  
ꢒ'ꢐꢔꢒꢅ  
ꢇꢎꢉꢌ  
ꢒ'ꢐꢔꢒꢈ  
ꢒ'ꢐꢔꢒꢈ  
ꢇꢎꢉꢍ  
ꢒ'ꢐꢔꢒꢉ  
ꢒ'ꢐꢔꢒꢉ  
ꢇꢎꢉꢊ  
ꢒ'ꢐꢔꢒꢌ  
ꢒ'ꢐꢔꢒꢌ  
ꢇꢎꢉꢋ  
ꢒ'ꢐꢔꢒꢍ  
ꢒ'ꢐꢔꢒꢍ  
ꢇꢎꢉꢆ  
ꢒ'ꢐꢔꢒꢊ  
ꢒ'ꢐꢔꢒꢊ  
ꢚꢏꢄ  
ꢚꢏꢄ  
ꢇꢎꢉꢙ  
ꢒ'ꢐꢔꢒꢋ  
ꢒ'ꢐꢔꢒꢋ  
ꢇꢄ  
ꢇꢙ  
ꢇꢍ  
ꢇꢊ  
ꢇꢋ  
ꢇꢆ  
ꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢑꢏ  
ꢒꢇꢎꢏ  
ꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢑꢏ  
ꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢑꢏ  
ꢒꢇꢎꢏ  
ꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢑꢏ  
ꢒꢇꢎꢏ  
ꢇꢎꢏꢄ  
ꢇꢎꢏꢄ  
ꢇꢀꢄꢐꢇꢎꢏꢙ  
ꢇꢎꢏꢙ  
ꢇꢎꢄ  
ꢒꢇꢎꢏ  
ꢇꢎꢏꢍ  
ꢇꢎꢏꢍ  
ꢒꢇꢎꢏ  
ꢒꢇꢎꢏ  
ꢒꢇꢎꢏ  
ꢒꢇꢎꢏ  
ꢒꢇꢀꢐꢚꢇꢎꢏ  
ꢒ%&ꢐꢚꢇꢎꢏ  
ꢒ'ꢐꢔꢒꢄ  
ꢒꢇꢀꢐꢚꢇꢎꢏ  
ꢒ%&ꢐꢚꢇꢎꢏ  
ꢒ'ꢐꢔꢒꢄ  
ꢇꢀꢍꢐꢇꢎꢏꢅꢌ  
ꢇꢎꢏꢅꢌ  
ꢒꢇꢀꢐꢚꢇꢎꢏ  
ꢒ%&ꢐꢚꢇꢎꢏ  
ꢒ'ꢐꢔꢒꢄ  
ꢒꢇꢀꢐꢚꢇꢎꢏ  
ꢒ%&ꢐꢚꢇꢎꢏ  
ꢒ'ꢐꢔꢒꢄ  
ꢇꢎꢌꢄ  
ꢇꢎꢅ  
ꢒ'ꢐꢔꢒꢅ  
ꢒ'ꢐꢔꢒꢅ  
ꢇꢎꢌꢅ  
ꢕꢄ  
ꢒ'ꢐꢔꢒꢅ  
ꢒ'ꢐꢔꢒꢅ  
ꢇꢎꢈ  
ꢒ'ꢐꢔꢒꢈ  
ꢒ'ꢐꢔꢒꢈ  
ꢇꢎꢌꢈ  
ꢇꢎꢌꢉ  
ꢇꢎꢌꢌ  
ꢇꢎꢌꢍ  
ꢇꢎꢌꢊ  
ꢇꢎꢌꢋ  
ꢒ'ꢐꢔꢒꢈ  
ꢒ'ꢐꢔꢒꢈ  
ꢒꢏꢑꢓ  
ꢒꢏꢇꢜ  
ꢒꢜꢄ  
ꢏꢑꢓ  
ꢏꢇꢜ  
ꢏꢜꢄ  
ꢏꢜꢅ  
ꢏꢜꢈ  
ꢇꢎꢉ  
ꢒ'ꢐꢔꢒꢉ  
ꢒ'ꢐꢔꢒꢉ  
ꢒ'ꢐꢔꢒꢉ  
ꢒ'ꢐꢔꢒꢉ  
ꢇꢎꢌ  
ꢒ'ꢐꢔꢒꢌ  
ꢒ'ꢐꢔꢒꢌ  
ꢒ'ꢐꢔꢒꢌ  
ꢒ'ꢐꢔꢒꢌ  
ꢇꢎꢍ  
ꢒ'ꢐꢔꢒꢍ  
ꢒ'ꢐꢔꢒꢍ  
ꢒ'ꢐꢔꢒꢍ  
ꢒ'ꢐꢔꢒꢍ  
ꢒꢜꢅ  
ꢇꢎꢊ  
ꢒ'ꢐꢔꢒꢊ  
ꢒ'ꢐꢔꢒꢊ  
ꢒ'ꢐꢔꢒꢊ  
ꢒ'ꢐꢔꢒꢊ  
ꢒꢜꢈ  
ꢇꢎꢋ  
ꢒ'ꢐꢔꢒꢋ  
ꢒ'ꢐꢔꢒꢋ  
ꢒ'ꢐꢔꢒꢋ  
ꢒ'ꢐꢔꢒꢋ  
ꢒ(ꢁ  
ꢀ
ꢏꢏ  
ꢇꢅ  
ꢇꢈ  
ꢇꢉ  
ꢇꢅꢄ  
ꢇꢅꢅ  
ꢇꢅꢈ  
ꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢑꢏ  
ꢒꢇꢎꢏ  
ꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢑꢏ  
ꢒꢇꢎꢏ  
ꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢑꢏ  
ꢒꢇꢎꢏ  
ꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢑꢏ  
ꢒꢇꢎꢏ  
ꢇꢎꢏꢅ  
ꢇꢎꢏꢅ  
ꢇꢎꢏꢊ  
ꢇꢎꢏꢊ  
ꢒꢇꢎꢏ  
ꢒꢇꢎꢏ  
ꢒꢇꢎꢏ  
ꢒꢇꢎꢏ  
ꢇꢀꢅꢐꢇꢎꢏꢅꢄ  
ꢇꢎꢏꢅꢄ  
ꢇꢎꢆ  
ꢒꢇꢀꢐꢚꢇꢎꢏ  
ꢒ%&ꢐꢚꢇꢎꢏ  
ꢒ'ꢐꢔꢒꢄ  
ꢒꢇꢀꢐꢚꢇꢎꢏ  
ꢒ%&ꢐꢚꢇꢎꢏ  
ꢒ'ꢐꢔꢒꢄ  
ꢇꢀꢊꢐꢇꢎꢏꢅꢍ  
ꢇꢎꢏꢅꢍ  
ꢇꢎꢌꢆ  
ꢒꢇꢀꢐꢚꢇꢎꢏ  
ꢒ%&ꢐꢚꢇꢎꢏ  
ꢒ'ꢐꢔꢒꢄ  
ꢒꢇꢀꢐꢚꢇꢎꢏ  
ꢒ%&ꢐꢚꢇꢎꢏ  
ꢒ'ꢐꢔꢒꢄ  
ꢇꢎꢙ  
ꢒ'ꢐꢔꢒꢅ  
ꢒ'ꢐꢔꢒꢅ  
ꢇꢎꢌꢙ  
ꢒ'ꢐꢔꢒꢅ  
ꢒ'ꢐꢔꢒꢅ  
ꢇꢎꢅꢄ  
ꢒ'ꢐꢔꢒꢈ  
ꢒ'ꢐꢔꢒꢈ  
ꢇꢎꢍꢄ  
ꢒ'ꢐꢔꢒꢈ  
ꢒ'ꢐꢔꢒꢈ  
ꢇꢎꢅꢅ  
ꢒ'ꢐꢔꢒꢉ  
ꢒ'ꢐꢔꢒꢉ  
ꢇꢎꢍꢅ  
ꢒ'ꢐꢔꢒꢉ  
ꢒ'ꢐꢔꢒꢉ  
ꢇꢎꢅꢈ  
ꢒ'ꢐꢔꢒꢌ  
ꢒ'ꢐꢔꢒꢌ  
ꢇꢎꢍꢈ  
ꢒ'ꢐꢔꢒꢌ  
ꢒ'ꢐꢔꢒꢌ  
ꢇꢎꢅꢉ  
ꢒ'ꢐꢔꢒꢍ  
ꢒ'ꢐꢔꢒꢍ  
ꢇꢎꢍꢉ  
ꢒ'ꢐꢔꢒꢍ  
ꢒ'ꢐꢔꢒꢍ  
ꢇꢎꢅꢌ  
ꢒ'ꢐꢔꢒꢊ  
ꢒ'ꢐꢔꢒꢊ  
ꢇꢎꢍꢌ  
ꢒ'ꢐꢔꢒꢊ  
ꢒ'ꢐꢔꢒꢊ  
ꢇꢎꢅꢍ  
ꢒ'ꢐꢔꢒꢋ  
ꢒ'ꢐꢔꢒꢋ  
ꢇꢎꢍꢍ  
ꢒ'ꢐꢔꢒꢋ  
ꢒ'ꢐꢔꢒꢋ  
ꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢑꢏ  
ꢒꢇꢎꢏ  
ꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢑꢏ  
ꢒꢇꢎꢏ  
ꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢑꢏ  
ꢒꢇꢎꢏ  
ꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢑꢏ  
ꢒꢇꢎꢏ  
ꢇꢎꢏꢈ  
ꢇꢎꢏꢈ  
ꢇꢎꢏꢋ  
ꢇꢎꢏꢋ  
ꢒꢇꢎꢏ  
ꢒꢇꢎꢏ  
ꢒꢇꢎꢏ  
ꢒꢇꢎꢏ  
ꢇꢀꢈꢐꢇꢎꢏꢅꢅ  
ꢇꢎꢏꢅꢅ  
ꢇꢎꢅꢊ  
ꢒꢇꢀꢐꢚꢇꢎꢏ  
ꢒ%&ꢐꢚꢇꢎꢏ  
ꢒ'ꢐꢔꢒꢄ  
ꢒꢇꢀꢐꢚꢇꢎꢏ  
ꢒ%&ꢐꢚꢇꢎꢏ  
ꢒ'ꢐꢔꢒꢄ  
ꢇꢀꢋꢐꢇꢎꢏꢅꢊ  
ꢇꢎꢏꢅꢊ  
ꢇꢎꢍꢊ  
ꢒꢇꢀꢐꢚꢇꢎꢏ  
ꢒ%&ꢐꢚꢇꢎꢏ  
ꢒ'ꢐꢔꢒꢄ  
ꢒꢇꢀꢐꢚꢇꢎꢏ  
ꢒ%&ꢐꢚꢇꢎꢏ  
ꢒ'ꢐꢔꢒꢄ  
ꢇꢎꢅꢋ  
ꢒ'ꢐꢔꢒꢅ  
ꢒ'ꢐꢔꢒꢅ  
ꢇꢎꢍꢋ  
ꢒ'ꢐꢔꢒꢅ  
ꢒ'ꢐꢔꢒꢅ  
ꢇꢎꢅꢆ  
ꢒ'ꢐꢔꢒꢈ  
ꢒ'ꢐꢔꢒꢈ  
ꢇꢎꢍꢆ  
ꢒ'ꢐꢔꢒꢈ  
ꢒ'ꢐꢔꢒꢈ  
ꢇꢎꢅꢙ  
ꢒ'ꢐꢔꢒꢉ  
ꢒ'ꢐꢔꢒꢉ  
ꢇꢎꢍꢙ  
ꢒ'ꢐꢔꢒꢉ  
ꢒ'ꢐꢔꢒꢉ  
ꢇꢎꢈꢄ  
ꢒ'ꢐꢔꢒꢌ  
ꢒ'ꢐꢔꢒꢌ  
ꢇꢎꢊꢄ  
ꢒ'ꢐꢔꢒꢌ  
ꢒ'ꢐꢔꢒꢌ  
ꢇꢎꢈꢅ  
ꢒ'ꢐꢔꢒꢍ  
ꢒ'ꢐꢔꢒꢍ  
ꢇꢎꢊꢅ  
ꢒ'ꢐꢔꢒꢍ  
ꢒ'ꢐꢔꢒꢍ  
ꢇꢎꢈꢈ  
ꢒ'ꢐꢔꢒꢊ  
ꢒ'ꢐꢔꢒꢊ  
ꢇꢎꢊꢈ  
ꢒ'ꢐꢔꢒꢊ  
ꢒ'ꢐꢔꢒꢊ  
ꢇꢎꢈꢉ  
ꢒ'ꢐꢔꢒꢋ  
ꢒ'ꢐꢔꢒꢋ  
ꢇꢎꢊꢉ  
ꢒ'ꢐꢔꢒꢋ  
ꢒ'ꢐꢔꢒꢋ  
ꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢑꢏ  
ꢒꢇꢎꢏ  
ꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢑꢏ  
ꢒꢇꢎꢏ  
ꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢑꢏ  
ꢒꢇꢎꢏ  
ꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢑꢏ  
ꢒꢇꢎꢏ  
ꢇꢎꢏꢉ  
ꢇꢎꢏꢉ  
ꢇꢎꢏꢆ  
ꢇꢎꢏꢆ  
ꢇꢀꢆꢐꢇꢎꢏꢅꢋ  
ꢇꢎꢏꢅꢋ  
ꢑꢂꢄ  
ꢒꢇꢎꢏ  
ꢒꢇꢎꢏ  
ꢒꢇꢎꢏ  
ꢒꢇꢎꢏ  
ꢇꢀꢉꢐꢇꢎꢏꢅꢈ  
ꢇꢎꢏꢅꢈ  
ꢇꢎꢈꢌ  
ꢒꢇꢀꢐꢚꢇꢎꢏ  
ꢒ%&ꢐꢚꢇꢎꢏ  
ꢒ'ꢐꢔꢒꢄ  
ꢒꢇꢀꢐꢚꢇꢎꢏ  
ꢒ%&ꢐꢚꢇꢎꢏ  
ꢒ'ꢐꢔꢒꢄ  
ꢒꢇꢀꢐꢚꢇꢎꢏ  
ꢒ%&ꢐꢚꢇꢎꢏ  
ꢒ'ꢐꢔꢒꢄ  
ꢒꢇꢀꢐꢚꢇꢎꢏ  
ꢒ%&ꢐꢚꢇꢎꢏ  
ꢒ'ꢐꢔꢒꢄ  
ꢇꢎꢈꢍ  
ꢒ'ꢐꢔꢒꢅ  
ꢒ'ꢐꢔꢒꢅ  
ꢑꢂꢅ  
ꢒ'ꢐꢔꢒꢅ  
ꢒ'ꢐꢔꢒꢅ  
ꢇꢎꢈꢊ  
ꢒ'ꢐꢔꢒꢈ  
ꢒ'ꢐꢔꢒꢈ  
ꢑꢂꢈ  
ꢒ'ꢐꢔꢒꢈ  
ꢒ'ꢐꢔꢒꢈ  
ꢇꢎꢈꢋ  
ꢒ'ꢐꢔꢒꢉ  
ꢒ'ꢐꢔꢒꢉ  
ꢑꢂꢉ  
ꢒ'ꢐꢔꢒꢉ  
ꢒ'ꢐꢔꢒꢉ  
ꢇꢎꢈꢆ  
ꢒ'ꢐꢔꢒꢌ  
ꢒ'ꢐꢔꢒꢌ  
ꢑꢂꢌ  
ꢒ'ꢐꢔꢒꢌ  
ꢒ'ꢐꢔꢒꢌ  
ꢇꢎꢈꢙ  
ꢒ'ꢐꢔꢒꢍ  
ꢒ'ꢐꢔꢒꢍ  
ꢑꢂꢍ  
ꢒ'ꢐꢔꢒꢍ  
ꢒ'ꢐꢔꢒꢍ  
ꢇꢎꢉꢄ  
ꢒ'ꢐꢔꢒꢊ  
ꢒ'ꢐꢔꢒꢊ  
ꢑꢂꢊ  
ꢒ'ꢐꢔꢒꢊ  
ꢒ'ꢐꢔꢒꢊ  
ꢇꢎꢉꢅ  
ꢒ'ꢐꢔꢒꢋ  
ꢒ'ꢐꢔꢒꢋ  
ꢑꢂꢋ  
ꢒ'ꢐꢔꢒꢋ  
ꢒ'ꢐꢔꢒꢋ  
ꢀꢁꢂꢃꢄꢅꢙꢄ  
Figure 3  
Block Diagram Raw Card G RDIMM (x72, 2Ranks, x8)  
Notes  
2. RS0 and RS1 alternate between the back and front  
sides of the DIMM.  
1. Unless otherwise noted, resistors are 22 Ω ± 5 %  
Data Sheet  
19  
Rev. 1.0, 2004-10  
02182004-UN2L-F13U  
HYS72T[32/64]0[0/2][0/1]HR–[3.7/5]–A  
Registered Double-Data-Rate-Two SDRAM Modules  
Pin Configuration  
)
ꢀꢇꢇꢘꢏꢁꢇ  
ꢀꢇꢇꢛꢒꢏꢁꢇꢒꢕꢕꢁꢚꢔꢀꢒꢕꢄ  
ꢑꢖꢄ  
ꢑꢖꢄ  
ꢒꢒꢒꢁꢓꢓ  
ꢁꢑꢖꢄꢗꢁꢑꢖꢊꢘꢒꢁꢑꢖꢆꢘꢒꢁꢑꢖꢙ  
ꢁꢑꢖꢄꢗꢁꢑꢖꢊꢘꢒꢁꢑꢖꢆꢘꢒꢁꢑꢖꢙ  
ꢁꢑꢖꢋ  
ꢑꢖꢛꢒꢏꢇꢚꢜꢀꢝꢒꢇꢄꢗꢇꢅꢋ  
ꢑꢖꢛꢒꢏꢇꢚꢜꢀꢝꢒꢇꢄꢗꢇꢅꢋ  
ꢑꢖꢛꢒꢚ !"ꢝ# $  
ꢀꢇꢇꢐꢀꢇꢇꢎ  
ꢀ
ꢀ
ꢀ
ꢇꢇꢐꢀꢇꢇꢎꢛꢒꢏꢇꢚꢜꢀꢝꢒꢇꢄꢗꢇꢅꢋ  
ꢚꢕꢏꢕꢃ  
ꢒꢔꢕ  
ꢅꢛꢈ  
ꢁꢑꢖꢋ  
ꢑꢖꢛꢒꢚ !"ꢝ# $  
ꢀ
ꢛꢒꢏꢇꢚꢜꢀꢝꢒꢇꢄꢗꢇꢅꢋ  
ꢚꢕꢞ  
ꢚꢕꢞ  
ꢀꢏꢏ  
ꢏꢏꢛꢒꢏꢇꢚꢜꢀꢝꢒꢇꢄꢗꢇꢅꢋ  
ꢏꢄ  
ꢂꢜꢄꢒꢗꢒꢂꢜ*  
ꢜꢄꢒꢗꢒꢜ*  
ꢚꢜꢏ  
ꢚꢏꢄ  
ꢑꢏꢛꢒꢏꢇꢚꢜꢀꢝꢒꢇꢄꢗꢇꢅꢋ  
ꢂꢜꢄꢗꢂꢜ*ꢛꢒꢏꢇꢚꢜꢀꢝꢒꢇꢄꢗꢇꢅꢋ  
ꢚꢂꢜꢄꢗꢚꢂꢜ*  
ꢚꢜꢄꢗꢚꢜ*  
ꢚꢚꢜꢏ  
ꢚ
ꢕ
)
'
ꢜꢄꢗꢜ*ꢛꢒꢏꢇꢚꢜꢀꢝꢒꢇꢄꢗꢇꢅꢋ  
ꢚꢜꢏꢛꢒꢏꢇꢚꢜꢀꢝꢒꢇꢄꢗꢇꢅꢋ  
ꢑꢜꢏꢛꢒꢏꢇꢚꢜꢀꢝꢒꢇꢄꢗꢇꢅꢋ  
(ꢕꢛꢒꢏꢇꢚꢜꢀꢝꢒꢇꢄꢗꢇꢅꢋ  
ꢑꢖꢕꢛꢒꢏꢇꢚꢜꢀꢝꢒꢇꢄꢗꢇꢅꢋ  
ꢔꢇꢃꢛꢒꢏꢇꢚꢜꢀꢝꢒꢇꢄꢗꢇꢅꢋ  
ꢑꢜꢏ  
ꢚꢑꢜꢏ  
ꢕꢄ  
(ꢕ  
ꢚ(ꢕ  
ꢒꢏꢑꢓ  
ꢒꢏꢇꢜ  
ꢒꢜꢄ  
ꢏꢑꢓ  
ꢏꢇꢜ  
ꢏꢜꢄ  
ꢏꢜꢅ  
ꢏꢜꢈ  
ꢀꢏꢏ  
ꢏ
ꢃ
ꢕ
ꢚ
ꢑꢖꢕꢄ  
ꢚꢑꢖꢕꢄ  
ꢚꢔꢇꢃꢄ  
ꢔꢇꢃꢄ  
ꢒꢜꢅ  
ꢁꢑꢖꢋ  
ꢁꢑꢖꢋ  
ꢒꢜꢈ  
ꢒ(ꢁ  
ꢚꢕꢏꢕꢃ  
ꢚꢏꢄ  
ꢇꢄ  
ꢇꢊ  
ꢇꢅꢈ  
ꢇꢅꢉ  
ꢇꢅꢌ  
ꢇꢅꢍ  
ꢇꢅꢊ  
ꢇꢅꢋ  
ꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢑꢏ  
ꢒꢇꢎꢏ  
ꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢑꢏ  
ꢒꢇꢎꢏ  
ꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢑꢏ  
ꢒꢇꢎꢏ  
ꢇꢎꢏꢄ  
ꢇꢎꢏꢄ  
ꢇꢎꢄ  
ꢇꢎꢏꢊ  
ꢇꢎꢏꢊ  
ꢇꢎꢌꢆ  
ꢇꢎꢌꢙ  
ꢇꢎꢍꢄ  
ꢇꢎꢍꢅ  
ꢇꢎꢏꢅꢈ  
ꢇꢎꢏꢅꢈ  
ꢇꢎꢈꢆ  
ꢇꢎꢈꢙ  
ꢇꢎꢉꢄ  
ꢇꢎꢉꢅ  
ꢒꢇꢎꢏ  
ꢒꢇꢎꢏ  
ꢒꢇꢎꢏ  
ꢒ'ꢐꢔꢒꢄ  
ꢒ'ꢐꢔꢒꢄ  
ꢒ'ꢐꢔꢒꢄ  
ꢇꢎꢅ  
ꢒ'ꢐꢔꢒꢅ  
ꢒ'ꢐꢔꢒꢅ  
ꢒ'ꢐꢔꢒꢅ  
ꢇꢎꢈ  
ꢒ'ꢐꢔꢒꢈ  
ꢒ'ꢐꢔꢒꢈ  
ꢒ'ꢐꢔꢒꢈ  
ꢇꢎꢉ  
ꢒ'ꢐꢔꢒꢉ  
ꢒ'ꢐꢔꢒꢉ  
ꢒ'ꢐꢔꢒꢉ  
ꢀ
ꢒꢇꢀ  
ꢀ
ꢒꢇꢀ  
ꢀ
ꢒꢇꢀ  
ꢏꢏ  
ꢏꢏ  
ꢏꢏ  
ꢇꢅ  
ꢇꢈ  
ꢇꢉ  
ꢇꢌ  
ꢇꢍ  
ꢇꢋ  
ꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢑꢏ  
ꢒꢇꢎꢏ  
ꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢑꢏ  
ꢒꢇꢎꢏ  
ꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢑꢏ  
ꢒꢇꢎꢏ  
ꢇꢎꢏꢅ  
ꢇꢎꢏꢅ  
ꢇꢎꢆ  
ꢇꢎꢏꢋ  
ꢇꢎꢏꢋ  
ꢇꢎꢍꢊ  
ꢇꢎꢍꢋ  
ꢇꢎꢍꢆ  
ꢇꢎꢍꢙ  
ꢇꢎꢏꢅꢉ  
ꢇꢎꢏꢅꢉ  
ꢇꢎꢉꢊ  
ꢇꢎꢉꢋ  
ꢇꢎꢉꢆ  
ꢇꢎꢉꢙ  
ꢒꢇꢎꢏ  
ꢒꢇꢎꢏ  
ꢒꢇꢎꢏ  
ꢒ'ꢐꢔꢒꢄ  
ꢒ'ꢐꢔꢒꢄ  
ꢒ'ꢐꢔꢒꢄ  
ꢇꢎꢙ  
ꢒ'ꢐꢔꢒꢅ  
ꢒ'ꢐꢔꢒꢅ  
ꢒ'ꢐꢔꢒꢅ  
ꢇꢎꢅꢄ  
ꢇꢎꢅꢅ  
ꢒ'ꢐꢔꢒꢈ  
ꢒ'ꢐꢔꢒꢈ  
ꢒ'ꢐꢔꢒꢈ  
ꢒ'ꢐꢔꢒꢉ  
ꢒ'ꢐꢔꢒꢉ  
ꢒ'ꢐꢔꢒꢉ  
ꢀ
ꢒꢇꢀ  
ꢀ
ꢒꢇꢀ  
ꢀ
ꢒꢇꢀ  
ꢏꢏ  
ꢏꢏ  
ꢏꢏ  
ꢇꢆ  
ꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢑꢏ  
ꢒꢇꢎꢏ  
ꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢑꢏ  
ꢒꢇꢎꢏ  
ꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢑꢏ  
ꢒꢇꢎꢏ  
ꢇꢎꢏꢈ  
ꢇꢎꢏꢈ  
ꢇꢎꢅꢊ  
ꢇꢎꢅꢋ  
ꢇꢎꢅꢆ  
ꢇꢎꢅꢙ  
ꢇꢎꢏꢆ  
ꢇꢎꢏꢆ  
ꢑꢂꢄ  
ꢇꢎꢏꢅꢌ  
ꢇꢎꢏꢅꢌ  
ꢇꢎꢌꢌ  
ꢇꢎꢌꢍ  
ꢇꢎꢌꢊ  
ꢇꢎꢌꢋ  
ꢒꢇꢎꢏ  
ꢒꢇꢎꢏ  
ꢒꢇꢎꢏ  
ꢒ'ꢐꢔꢒꢄ  
ꢒ'ꢐꢔꢒꢄ  
ꢒ'ꢐꢔꢒꢄ  
ꢒ'ꢐꢔꢒꢅ  
ꢑꢂꢅ  
ꢒ'ꢐꢔꢒꢅ  
ꢒ'ꢐꢔꢒꢅ  
ꢒ'ꢐꢔꢒꢈ  
ꢑꢂꢈ  
ꢒ'ꢐꢔꢒꢈ  
ꢒ'ꢐꢔꢒꢈ  
ꢒ'ꢐꢔꢒꢉ  
ꢑꢂꢉ  
ꢒ'ꢐꢔꢒꢉ  
ꢒ'ꢐꢔꢒꢉ  
ꢀ
ꢒꢇꢀ  
ꢀ
ꢒꢇꢀ  
ꢀ
ꢒꢇꢀ  
ꢏꢏ  
ꢏꢏ  
ꢏꢏ  
ꢇꢙ  
ꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢑꢏ  
ꢒꢇꢎꢏ  
ꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢑꢏ  
ꢒꢇꢎꢏ  
ꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢑꢏ  
ꢒꢇꢎꢏ  
ꢇꢎꢏꢉ  
ꢇꢎꢏꢉ  
ꢇꢎꢈꢌ  
ꢇꢎꢈꢍ  
ꢇꢎꢈꢊ  
ꢇꢎꢈꢋ  
ꢇꢎꢏꢙ  
ꢇꢎꢏꢙ  
ꢇꢎꢌ  
ꢇꢎꢏꢅꢍ  
ꢇꢎꢏꢅꢍ  
ꢇꢎꢍꢈ  
ꢇꢎꢍꢉ  
ꢇꢎꢍꢌ  
ꢇꢎꢍꢍ  
ꢒꢇꢎꢏ  
ꢒꢇꢎꢏ  
ꢒꢇꢎꢏ  
ꢒ'ꢐꢔꢒꢄ  
ꢒ'ꢐꢔꢒꢄ  
ꢒ'ꢐꢔꢒꢄ  
ꢒ'ꢐꢔꢒꢅ  
ꢇꢎꢍ  
ꢒ'ꢐꢔꢒꢅ  
ꢒ'ꢐꢔꢒꢅ  
ꢒ'ꢐꢔꢒꢈ  
ꢇꢎꢊ  
ꢒ'ꢐꢔꢒꢈ  
ꢒ'ꢐꢔꢒꢈ  
ꢒ'ꢐꢔꢒꢉ  
ꢇꢎꢋ  
ꢒ'ꢐꢔꢒꢉ  
ꢒ'ꢐꢔꢒꢉ  
ꢀ
ꢒꢇꢀ  
ꢀ
ꢒꢇꢀ  
ꢀ
ꢒꢇꢀ  
ꢏꢏ  
ꢏꢏ  
ꢏꢏ  
ꢇꢅꢄ  
ꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢑꢏ  
ꢒꢇꢎꢏ  
ꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢑꢏ  
ꢒꢇꢎꢏ  
ꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢑꢏ  
ꢒꢇꢎꢏ  
ꢇꢎꢏꢌ  
ꢇꢎꢏꢌ  
ꢇꢎꢉꢈ  
ꢇꢎꢉꢉ  
ꢇꢎꢉꢌ  
ꢇꢎꢉꢍ  
ꢇꢎꢏꢅꢄ  
ꢇꢎꢏꢅꢄ  
ꢇꢎꢅꢈ  
ꢇꢎꢅꢉ  
ꢇꢎꢅꢌ  
ꢇꢎꢅꢍ  
ꢇꢎꢏꢅꢊ  
ꢇꢎꢏꢅꢊ  
ꢇꢎꢊꢄ  
ꢇꢎꢊꢅ  
ꢇꢎꢊꢈ  
ꢇꢎꢊꢉ  
ꢒꢇꢎꢏ  
ꢒꢇꢎꢏ  
ꢒꢇꢎꢏ  
ꢒ'ꢐꢔꢒꢄ  
ꢒ'ꢐꢔꢒꢄ  
ꢒ'ꢐꢔꢒꢄ  
ꢒ'ꢐꢔꢒꢅ  
ꢒ'ꢐꢔꢒꢅ  
ꢒ'ꢐꢔꢒꢅ  
ꢒ'ꢐꢔꢒꢈ  
ꢒ'ꢐꢔꢒꢈ  
ꢒ'ꢐꢔꢒꢈ  
ꢒ'ꢐꢔꢒꢉ  
ꢒ'ꢐꢔꢒꢉ  
ꢒ'ꢐꢔꢒꢉ  
ꢀ
ꢒꢇꢀ  
ꢀ
ꢒꢇꢀ  
ꢀ
ꢒꢇꢀ  
ꢏꢏ  
ꢏꢏ  
ꢏꢏ  
ꢇꢅꢅ  
ꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢑꢏ  
ꢒꢇꢎꢏ  
ꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢑꢏ  
ꢒꢇꢎꢏ  
ꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢒꢑꢏ  
ꢒꢇꢎꢏ  
ꢇꢎꢏꢍ  
ꢇꢎꢏꢍ  
ꢇꢎꢌꢄ  
ꢇꢎꢌꢅ  
ꢇꢎꢌꢈ  
ꢇꢎꢌꢉ  
ꢇꢎꢏꢅꢅ  
ꢇꢎꢏꢅꢅ  
ꢇꢎꢈꢄ  
ꢇꢎꢈꢅ  
ꢇꢎꢈꢈ  
ꢇꢎꢈꢉ  
ꢀꢏꢏ  
ꢇꢎꢏꢅꢋ  
ꢇꢎꢏꢅꢋ  
ꢑꢂꢌ  
ꢒꢇꢎꢏ  
ꢒꢇꢎꢏ  
ꢒꢇꢎꢏ  
ꢒ'ꢐꢔꢒꢄ  
ꢒ'ꢐꢔꢒꢄ  
ꢒ'ꢐꢔꢒꢄ  
ꢒ'ꢐꢔꢒꢅ  
ꢒ'ꢐꢔꢒꢅ  
ꢑꢂꢍ  
ꢒ'ꢐꢔꢒꢅ  
ꢒ'ꢐꢔꢒꢈ  
ꢒ'ꢐꢔꢒꢈ  
ꢑꢂꢊ  
ꢒ'ꢐꢔꢒꢈ  
ꢒ'ꢐꢔꢒꢉ  
ꢒ'ꢐꢔꢒꢉ  
ꢑꢂꢋ  
ꢒ'ꢐꢔꢒꢉ  
ꢀ
ꢒꢇꢀ  
ꢒꢇꢀ  
ꢀ
ꢒꢇꢀ  
ꢏꢏ  
ꢏꢏ  
ꢀꢁꢂꢃꢄꢈꢄꢄ  
Figure 4  
Notes  
Block Diagram Raw Card H RDIMM (x72, 1Rank, x4)  
3. CSR of register1 and DCS of register2 connects to  
VDD  
.
1. Unless otherwise noted, resistors are 22 Ω ± 5 %  
2. S0 connects to DCS of register1 and CSR of  
register2.  
4. RESET, PCK7 and PCK7 connect to both registers.  
Data Sheet  
20  
Rev. 1.0, 2004-10  
02182004-UN2L-F13U  
HYS72T[32/64]0[0/2][0/1]HR–[3.7/5]–A  
Registered Double-Data-Rate-Two SDRAM Modules  
IDD Specifications and Conditions  
3
IDD Specifications and Conditions  
Table 8  
I
DD Measurement Conditions1)2)3)4)5)6)7)8)  
Parameter  
Symbol  
Operating Current 0  
IDD0  
One bank Active - Precharge; tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN, CKE is HIGH, CS is HIGH  
between valid commands. Address and control inputs are SWITCHING, Databus inputs are  
SWITCHING.  
Operating Current 1  
IDD1  
One bank Active - Read - Precharge; IOUT = 0 mA, BL = 4, tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN  
,
t
RCD = tRCD.MIN, AL = 0, CL = CL.MIN; CKE is HIGH, CS is HIGH between valid commands. Address and  
control inputs are SWITCHING, Databus inputs are SWITCHING.  
Precharge Standby Current  
IDD2N  
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are  
SWITCHING, Data bus inputs are SWITCHING.  
Precharge Power-Down Current  
IDD2P  
IDD2Q  
Other control and address inputs are STABLE, Data bus inputs are FLOATING.  
Precharge Quiet Standby Current  
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are STABLE,  
Data bus inputs are FLOATING.  
Active Power-Down Current  
IDD3P(0)  
IDD3P(1)  
IDD3N  
All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus  
inputs are FLOATING. MRS A12 bit is set to LOW (Fast Power-down Exit);  
Active Power-Down Current  
All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus  
inputs are FLOATING. MRS A12 bit is set to HIGH (Slow Power-down Exit);  
Active Standby Current  
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN  
;
t
RAS = tRAS.MAX, tRP = tRP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address inputs are  
SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA.  
Operating Current  
IDD4R  
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN  
;
t
RAS = tRAS.MAX., tRP = tRP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address inputs are  
SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA.  
Operating Current  
IDD4W  
Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN  
;
t
RAS = tRAS.MAX., tRP = tRP.MAX; CKE is HIGH, CS is HIGH between valid commands. Address inputs are  
SWITCHING; Data Bus inputs are SWITCHING;  
Burst Refresh Current  
IDD5B  
t
CK = tCK.MIN., Refresh command every tRFC = tRFC.MIN interval, CKE is HIGH, CS is HIGH between valid  
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.  
Distributed Refresh Current  
IDD5D  
t
CK = tCK.MIN, Refresh command every tRFC = tREFI interval, CKE is LOW and CS is HIGH between valid  
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.  
Data Sheet  
21  
Rev. 1.0, 2004-10  
02182004-UN2L-F13U  
HYS72T[32/64]0[0/2][0/1]HR–[3.7/5]–A  
Registered Double-Data-Rate-Two SDRAM Modules  
IDD Specifications and Conditions  
Table 8  
I
DD Measurement Conditions1)2)3)4)5)6)7)8)  
Parameter  
Symbol  
Self-Refresh Current  
IDD6  
CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING,  
Data bus inputs are FLOATING. RESET is LOW. IDD6 current values are guaranteed up to TCASE of  
85 °C max.  
All Bank Interleave Read Current  
IDD7  
All banks are being interleaved at minimum tRC without violating tRRD using a burst length of 4. Control  
and address bus inputs are STABLE during DESELECTS. IOUT = 0 mA.  
1) VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V  
2) IDD specifications are tested after the device is properly initialized and IDD parameter are specified with ODT disabled.  
3) Definitions for IDD  
:
LOW is defined as VIN ≤ VIL(ac).MAX, HIGH is defined as VIN ≥ VIH(ac).MIN  
STABLE is defined as: inputs are stable at a HIGH or LOW level  
FLOATING is defined as: inputs are VREF = VDDQ /2  
SWITCHING is defined as: inputs are changing between HIGH and LOW every other clock (once per 2 cycles)  
for address and control signals, and inputs changing between HIGH and LOW every other data transfer  
(once per cycle) for DQ signals not including mask or strobes.  
4) IDD1, IDD4R and IDD7 current measurements are defined with the outputs disabled (IOUT = 0 mA). To achieve this on module  
level the output buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to  
HIGH.  
5) For two rank modules: for all active current measurements the other rank is in Precharge Power-Down Mode IDD2P  
6) RESET signal is HIGH for all currents, except for IDD6 (Self Refresh)  
7) All current measurements includes Register and PLL current consumption  
8) For details and notes see the relevant INFINEON component data sheet  
Data Sheet  
22  
Rev. 1.0, 2004-10  
02182004-UN2L-F13U  
HYS72T[32/64]0[0/2][0/1]HR–[3.7/5]–A  
Registered Double-Data-Rate-Two SDRAM Modules  
IDD Specifications and Conditions  
Table 9  
IDD Specification for HYS72T[32000/64001/64020]HR-3.7-A  
Unit  
Notes1)  
Organization  
256MB  
×72  
512MB  
×72  
512MB  
×72  
1 Rank  
–3.7  
Max.  
830  
870  
650  
370  
560  
650  
470  
366  
960  
1100  
1100  
50  
1 Rank  
–3.7  
Max.  
1490  
1580  
1130  
570  
950  
1130  
790  
2 Ranks  
–3.7  
Max.  
860  
910  
960  
400  
780  
680  
620  
Symbol  
IDD0  
IDD1  
IDD2N  
IDD2P  
IDD2Q  
IDD3N  
IDD3P(MRS= 0)  
IDD3P(MRS= 1)  
IDD4R  
IDD4W  
IDD5B  
2)  
2)  
3)  
3)  
3)  
3)  
3)  
3)  
2)  
2)  
2)  
3)  
3)  
2)  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
572  
402  
1760  
2030  
2030  
110  
70  
2930  
1000  
1130  
1130  
90  
70  
1580  
IDD5D  
IDD6  
IDD7  
40  
1550  
1) Module IDD is calculated on the basis of component IDD andcurrents includes Registers and PLL. ODT disabled. IDD1, IDD4R  
and IDD7 are defined with the outputs disabled.  
2) The other rank is in IDD2P Precharge Power-Down Standby Current mode  
3) Both ranks are in the same IDD mode  
Data Sheet  
23  
Rev. 1.0, 2004-10  
02182004-UN2L-F13U  
 
 
HYS72T[32/64]0[0/2][0/1]HR–[3.7/5]–A  
Registered Double-Data-Rate-Two SDRAM Modules  
IDD Specifications and Conditions  
Table 10  
IDD Specification for HYS72T[32000/64001/64020]HR-5-A  
Unit  
Notes1)  
Organization  
256MB  
×72  
512MB  
×72  
512MB  
×72  
1 Rank  
–5  
1 Rank  
–5  
2 Ranks  
–5  
Symbol  
IDD0  
IDD1  
IDD2N  
IDD2P  
IDD2Q  
IDD3N  
IDD3P(MRS= 0)  
IDD3P(MRS= 1)  
IDD4R  
IDD4W  
IDD5B  
Max.  
730  
770  
530  
310  
460  
550  
390  
311  
820  
910  
1000  
50  
40  
Max.  
1310  
1400  
910  
480  
770  
950  
640  
477  
1490  
1670  
1850  
110  
70  
2660  
Max.  
760  
810  
780  
350  
640  
580  
510  
347  
850  
940  
1030  
90  
70  
2)  
2)  
3)  
3)  
3)  
3)  
3)  
3)  
2)  
2)  
2)  
3)  
3)  
2)  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
IDD5D  
IDD6  
IDD7  
1400  
1440  
1) Module IDD is calculated on the basis of component IDD andcurrents includes Registers and PLL. ODT disabled. IDD1, IDD4R  
and IDD7 are defined with the outputs disabled.  
2) The other rank is in IDD2P Precharge Power-Down Standby Current mode  
3) Both ranks are in the same IDD mode  
Data Sheet  
24  
Rev. 1.0, 2004-10  
02182004-UN2L-F13U  
 
 
HYS72T[32/64]0[0/2][0/1]HR–[3.7/5]–A  
Registered Double-Data-Rate-Two SDRAM Modules  
IDD Specifications and Conditions  
3.1  
IDD Test Conditions  
For testing the IDD parameters, the following timing parameters are used:  
Table 11  
IDD Measurement Test Conditions  
Parameter  
Symbol  
–3.7  
–5  
Unit  
PC2-4200-4-4-4 PC2-3200-3-3-3  
CAS Latency  
Clock Cycle Time  
CL(IDD)  
tCK(IDD)  
tRCD(IDD)  
tRC(IDD)  
4
3
5
tCK  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
µs  
3.75  
15  
60  
7.5  
10  
Active to Read or Write delay  
Active to Active / Auto-Refresh command period  
15  
55  
7.5  
10  
40  
70000  
15  
75  
7.8  
Active bank A to Active bank B command delay ×81) tRRD(IDD)  
×162) tRRD(IDD)  
Active to Precharge Command  
Precharge Command Period  
Auto-Refresh to Active / Auto-Refresh command period tRFC(IDD)  
Average periodic Refresh interval  
tRAS.MIN(IDD) 45  
tRAS.MAX(IDD) 70000  
tRP(IDD)  
15  
75  
7.8  
tREFI  
1) For modules based on ×8 components  
2) For modules based on ×16 components  
3.2  
On Die Termination (ODT) Current  
The ODT function adds additional current consumption current consumption for any terminated input pin,  
to the DDR2 SDRAM when enabled by the EMRS(1). depends on the input pin is in tri-state or driving 0 or 1,  
Depending on address bits A[6,2] in the EMRS(1) a as long a ODT is enabled during a given period of time.  
“weak” or “strong” termination can be selected. The  
Table 12  
ODT current per terminated pin  
Parameter  
Symbol Min. Typ.  
Max. Unit  
EMRS(1) State  
Enabled ODT current per DQ  
IODTO  
5
6
3
12  
6
7.5  
3.75  
15  
mA/DQ A6 = 0, A2 = 1  
mA/DQ A6 = 1, A2 = 0  
mA/DQ A6 = 0, A2 = 1  
mA/DQ A6 = 1, A2 = 0  
ODT is HIGH; Data Bus inputs are FLOATING  
2.5  
10  
5
Active ODT current per DQ  
IODTT  
ODT is HIGH; worst case of Data Bus inputs  
are STABLE or SWITCHING.  
7.5  
Data Sheet  
25  
Rev. 1.0, 2004-10  
02182004-UN2L-F13U  
HYS72T[32/64]0[0/2][0/1]HR–[3.7/5]–A  
Registered Double-Data-Rate-Two SDRAM Modules  
Electrical Characteristics  
4
Electrical Characteristics  
4.1  
Operating Conditions  
Table 13  
Absolute Maximum Ratings  
Parameter  
Symbol  
Values  
Min.  
– 0.5  
– 1.0  
– 0.5  
5
Unit  
Note/Test  
Condition  
1)  
1)  
1)  
1)  
Max.  
2.3  
2.3  
2.3  
95  
Voltage on any pins relative to VSS  
Voltage on VDD relative to VSS  
Voltage on VDD Q relative to VSS  
Storage Humidity (without condensation)  
VIN, VOUT  
VDD  
VDDQ  
V
V
V
%
HSTG  
1) Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and device  
functional operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions  
for extended periods may affect reliability  
Table 14  
Operating Conditions  
Parameter  
Symbol Values  
Min.  
Unit Notes  
Max.  
+55  
+95  
+100  
+105  
90  
DIMM Module Operating Temperature Range (ambient)  
DRAM Component Case Temperature Range  
Storage Temperature  
Barometric Pressure (operating & storage)  
Operating Humidity (relative)  
TOPR  
TCASE  
TSTG  
PBar  
HOPR  
0
0
– 50  
+69  
10  
°C  
°C  
1)2)3)4)  
°C  
kPa  
5)  
%
1) DRAM Component Case Temperature is the surface temperature in the center on the top side of any of the DRAMs.  
2) Within the DRAM Component Case Temperature range all DRAM specification will be supported.  
3) Above 85 °C DRAM case temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 µs.  
4) Self-Refresh period is hard-coded in the DRAMs and therefore it is imperative that the system ensures the DRAM is below  
85 °C case temperature before initiating self-refresh operation.  
5) Up to 3000 m  
Table 15  
Supply Voltage Levels and DC Operating Conditions  
Parameter  
Symbol  
Values  
Min.  
1.7  
1.7  
0.49 x VDDQ  
1.7  
Unit  
Notes  
Nom.  
1.8  
1.8  
0.5 x VDDQ  
—
—
—
Max.  
1.9  
1.9  
0.51 x VDDQ  
3.6  
Device Supply Voltage  
Output Supply Voltage  
Input Reference Voltage  
SPD Supply Voltage  
DC Input Logic High  
DC Input Logic Low  
VDD  
V
V
V
V
V
V
µA  
1)  
2)  
VDDQ  
VREF  
VDDSPD  
VIH (DC)  
VIL (DC)  
IL  
V
REF + 0.125  
V
V
5
DDQ + 0.3  
REF – 0.125  
– 0.30  
– 5  
3)  
In / Output Leakage Current  
1) Under all conditions, VDDQ must be less than or equal to VDD  
2) Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC).VREF is also expected to track noise variations in VDDQ  
3) Input voltage for any connector pin under test of 0 V ≤ VIN ≤ VDDQ + 0.3 V; all other pins at 0 V. Current is per pin  
.
Data Sheet  
26  
Rev. 1.0, 2004-10  
02182004-UN2L-F13U  
 
HYS72T[32/64]0[0/2][0/1]HR–[3.7/5]–A  
Registered Double-Data-Rate-Two SDRAM Modules  
Electrical Characteristics  
Table 16  
Speed Grade Definition Speed Bins  
Speed Grade  
DDR2–533C  
–3.7  
4–4–4  
DDR2–400B  
–5  
3–3–3  
Unit  
Notes  
IFX Sort Name  
CAS-RCD-RP latencies  
Parameter  
tCK  
—
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Symbol  
tCK  
tCK  
Min.  
5
Max.  
8
Min.  
5
Max.  
8
1)2)3)4)  
1)2)3)4)  
1)2)3)4)  
1)2)3)4)5)  
1)2)3)4)  
1)2)3)4)  
1)2)3)4)  
Clock Frequency  
@ CL = 3  
@ CL = 4  
@ CL = 5  
3.75  
3.75  
45  
8
8
5
8
tCK  
5
8
RAS-CAS-Delay  
Row Precharge Time  
Row Active Time  
Row Cycle Time  
tRAS  
tRC  
tRCD  
tRP  
70000  
—
40  
55  
15  
15  
70000  
—
—
60  
15  
—
15  
—
—
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a  
differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. . Timings are  
further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) only.  
2) The CK CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS,  
RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode  
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is  
recognized as low.  
4) The output timing reference voltage level is VTT.  
5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is  
equal to 9 x tREFI  
.
Table 17  
Parameter  
Timing Parameter by Speed Grade - DDR2-400B & DDR2-533C  
Symbol  
–3.7  
–5  
Unit Notes1)  
DDR2–533 4–4–4  
DDR2–400 3–3–3  
Min.  
–500  
2
0.45  
3
Max.  
+500  
—
0.55  
—
Min.  
–600  
2
0.45  
3
Max.  
+600  
—
0.55  
—
DQ output access time from CK / CK tAC  
ps  
CAS A to CAS B command period  
tCCD  
tCK  
tCK  
tCK  
CK, CK high-level width  
tCH  
CKE minimum high and low pulse  
width  
tCKE  
CK, CK low-level width  
tCL  
tDAL  
0.45  
WR + tRP  
0.55  
—
0.45  
WR + tRP  
0.55  
—
tCK  
tCK  
Auto-Precharge write recovery +  
precharge time  
Minimum time clocks remain ON after tDELAY  
tIS + tCK  
+
––  
––  
—
—
tIS + tCK  
+
—
––  
—
—
ns  
ps  
ps  
tCK  
CKE asynchronously drops LOW  
tIH  
tIH  
DQ and DM input hold time  
tDH(base) 225  
tDH1(base) –25  
275  
(differential data strobe)  
DQ and DM input hold time (single  
ended data strobe)  
25  
DQ and DM input pulse width (each tDIPW  
0.35  
0.35  
input)  
DQS output access time from CK / CK tDQSCK  
–450  
0.35  
+450  
—
–500  
0.35  
+500  
—
ps  
tCK  
DQS input low (high) pulse width  
tDQSL,H  
(write cycle)  
Data Sheet  
27  
Rev. 1.0, 2004-10  
02182004-UN2L-F13U  
HYS72T[32/64]0[0/2][0/1]HR–[3.7/5]–A  
Registered Double-Data-Rate-Two SDRAM Modules  
Electrical Characteristics  
Table 17  
Parameter  
Timing Parameter by Speed Grade - DDR2-400B & DDR2-533C  
Symbol  
–3.7  
–5  
Unit Notes1)  
DDR2–533 4–4–4  
DDR2–400 3–3–3  
Min.  
Max.  
Min.  
Max.  
DQS-DQ skew (for DQS & associated tDQSQ  
—
300  
—
350  
ps  
DQ signals)  
Write command to 1st DQS latching tDQSS  
WL – 0.25 WL + 0.25 WL – 0.25 WL + 0.25 tCK  
transition  
DQ and DM input setup time  
tDS(base) 100  
tDS1(base) –25  
—
—
—
—
150  
25  
—
—
—
—
ps  
ps  
tCK  
tCK  
(differential data strobe)  
DQ and DM input setup time (single  
ended data strobe)  
DQS falling edge hold time from CK tDSH  
0.2  
0.2  
0.2  
0.2  
(write cycle)  
DQS falling edge to CK setup time  
tDSS  
tHP  
(write cycle)  
Clock half period  
MIN. (tCL, tCH)  
tAC.MAX  
MIN. (tCL, tCH)  
—
Data-out high-impedance time from tHZ  
—
tAC.MAX  
ps  
CK / CK  
Address and control input hold time tIH(base) 375  
—
—
475  
0.6  
—
—
ps  
tCK  
Address and control input pulse width tIPW  
0.6  
(each input)  
Address and control input setup time tIS(base) 250  
DQ low-impedance time from CK / CK tLZ(DQ)  
—
350  
—
ps  
ps  
ps  
tCK  
2 × tAC.MIN tAC.MAX  
2 × tAC.MIN tAC.MAX  
tAC.MIN  
2
DQS low-impedance from CK / CK  
tLZ(DQS)  
tMRD  
tAC.MIN  
tAC.MAX  
—
tAC.MAX  
—
Mode register set command cycle  
2
time  
OCD drive mode output delay  
Data output hold time from DQS  
tOIT  
tQH  
0
12  
—
0
12  
—
ns  
t
HP – tQHS  
tHPQ  
–
tQHS  
Data hold skew factor  
Average periodic refresh Interval  
tQHS  
tREFI  
—
—
—
75  
400  
7.8  
3.9  
—
—
—
—
75  
450  
7.8  
3.9  
—
ps  
µs  
µs  
ns  
2)  
3)  
Auto-Refresh to Active/Auto-Refresh tRFC  
command period  
Precharge-All (4 banks) command  
tRP  
t
RP + 1tCK  
—
t
RP + 1tCK  
—
ns  
period  
Read preamble  
Read postamble  
tRPRE  
tRPST  
tRRD  
0.9  
0.40  
7.5  
10  
1.1  
0.60  
—
—
—
0.9  
0.40  
7.5  
10  
1.1  
0.60  
—
—
—
tCK  
tCK  
ns  
ns  
ns  
Active bank A to Active bank B  
command period  
Internal Read to Precharge command tRTP  
7.5  
7.5  
delay  
Write preamble  
Write postamble  
tWPRE  
tWPST  
0.35xtCK  
0.40  
—
0.60  
0.35xtCK  
0.40  
—
0.60  
tCK  
tCK  
Data Sheet  
28  
Rev. 1.0, 2004-10  
02182004-UN2L-F13U  
HYS72T[32/64]0[0/2][0/1]HR–[3.7/5]–A  
Registered Double-Data-Rate-Two SDRAM Modules  
Electrical Characteristics  
Table 17  
Parameter  
Timing Parameter by Speed Grade - DDR2-400B & DDR2-533C  
Symbol  
–3.7  
–5  
Unit Notes1)  
DDR2–533 4–4–4  
DDR2–400 3–3–3  
Min.  
Max.  
Min.  
Max.  
Write recovery time for write without tWR  
15  
—
15  
—
ns  
tCK  
ns  
tCK  
Auto-Precharge  
Write recovery time for write with  
WR  
t
WR/tCK  
tWR/tCK  
Auto-Precharge  
Internal Write to Read command  
delay  
tWTR  
tXARD  
7.5  
2
—
—
10  
2
—
—
Exit power down to any valid  
command  
(other than NOP or Deselect)  
Exit active power-down mode to Read tXARDS  
6 – AL  
2
—
—
6 – AL  
2
—
—
tCK  
tCK  
command (slow exit, lower power)  
Exit precharge power-down to any  
valid command (other than NOP or  
Deselect)  
tXP  
Exit Self-Refresh to non-Read  
tXSNR  
t
RFC +10  
—
—
t
RFC +10  
—
—
ns  
command  
Exit Self-Refresh to Read command tXSRD  
200  
200  
tCK  
1) For details and notes see the relevant INFINEON component data sheet  
2) 0 ≤ TCASE ≤ 85 °C  
3) 85 °C < TCASE ≤ 95 °C  
Table 18  
ODT AC Electrical Characteristics and Operating Conditions  
Symbol Parameter / Condition  
Values  
Min.  
2
Unit  
Notes  
Max.  
2
tAOND  
tAON  
ODT turn-on delay  
ODT turn-on  
tCK  
ns  
1)  
tAC.MIN  
tAC.MAX + 1 ns  
tAONPD  
tAOFD  
tAOF  
tAOFPD  
tANPD  
tAXPD  
ODT turn-on (Power-Down Modes)  
ODT turn-off delay  
ODT turn-off  
ODT turn-off (Power-Down Modes)  
ODT to Power Down Mode Entry Latency 3  
ODT Power Down Exit Latency  
tAC.MIN + 2 ns 2 tCK + tAC.MAX + 1 ns ns  
2.5  
2.5  
tCK  
2)  
tAC.MIN  
tAC.MAX + 0.6 ns  
ns  
tAC.MIN + 2 ns 2.5 tCK +tAC.MAX + 1 ns ns  
—
—
tCK  
tCK  
8
1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time  
max is when the ODT resistance is fully on. Both are measure from tAOND  
2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high  
impedance. Both are measured from tAOFD  
.
.
Data Sheet  
29  
Rev. 1.0, 2004-10  
02182004-UN2L-F13U  
HYS72T[32/64]0[0/2][0/1]HR–[3.7/5]–A  
Registered Double-Data-Rate-Two SDRAM Modules  
SPD Codes  
5
SPD Codes  
Table 19  
SPD Codes for HYS72T[32000/64001/64020]HR–3.7–A  
Product Type  
Organization  
Label Code  
256 MB  
×72  
1 Rank (×8)  
512 MB  
×72  
1 Rank (×4)  
512 MB  
×72  
2 Ranks (×8)  
PC2–4200R– PC2–4200R– PC2–4200R–  
444  
Rev. 1.1  
HEX  
80  
444  
Rev. 1.1  
HEX  
80  
444  
Rev. 1.1  
HEX  
80  
JEDEC SPD Revision  
Byte# Description  
0
Programmed SPD Bytes in EEPROM  
1
2
3
4
5
6
Total number of Bytes in EEPROM  
Memory Type (DDR2)  
Number of Row Addresses  
Number of Column Addresses  
DIMM Rank and Stacking Information  
Data Width  
08  
08  
0D  
0A  
60  
08  
08  
0D  
0B  
60  
08  
08  
0D  
0A  
61  
48  
48  
48  
7
Not used  
00  
00  
00  
8
Interface Voltage Level  
05  
05  
05  
9
t
t
CK @ CLMAX (Byte 18) [ns]  
AC SDRAM @ CLMAX (Byte 18) [ns]  
3D  
50  
02  
82  
08  
08  
00  
0C  
04  
38  
00  
01  
04  
01  
3D  
50  
3D  
50  
02  
82  
04  
04  
00  
0C  
04  
38  
00  
01  
05  
01  
3D  
50  
3D  
50  
02  
82  
08  
08  
00  
0C  
04  
38  
00  
01  
05  
01  
3D  
50  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
Error Correction Support (non-ECC, ECC)  
Refresh Rate and Type  
Primary SDRAM Width  
Error Checking SDRAM Width  
Not used  
Burst Length Supported  
Number of Banks on SDRAM Device  
Supported CAS Latencies  
DIMM Mechanical Characteristics  
DIMM Type Information  
DIMM Attributes  
Component Attributes  
t
t
CK @ CLMAX -1 (Byte 18) [ns]  
AC SDRAM @ CLMAX -1 [ns]  
Data Sheet  
30  
Rev. 1.0, 2004-10  
02182004-UN2L-F13U  
HYS72T[32/64]0[0/2][0/1]HR–[3.7/5]–A  
Registered Double-Data-Rate-Two SDRAM Modules  
SPD Codes  
Table 19  
SPD Codes for HYS72T[32000/64001/64020]HR–3.7–A (cont’d)  
Product Type  
Organization  
Label Code  
256 MB  
×72  
1 Rank (×8)  
512 MB  
×72  
1 Rank (×4)  
512 MB  
×72  
2 Ranks (×8)  
PC2–4200R– PC2–4200R– PC2–4200R–  
444  
Rev. 1.1  
HEX  
50  
444  
Rev. 1.1  
HEX  
50  
444  
Rev. 1.1  
HEX  
50  
JEDEC SPD Revision  
Byte# Description  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
t
t
t
t
t
t
CK @ CLMAX -2 (Byte 18) [ns]  
AC SDRAM @ CLMAX -2 [ns]  
RP.MIN [ns]  
RRD.MIN [ns]  
RCD.MIN [ns]  
60  
60  
60  
3C  
1E  
3C  
2D  
40  
25  
37  
10  
22  
3C  
1E  
1E  
00  
3C  
1E  
3C  
2D  
80  
25  
37  
10  
22  
3C  
1E  
1E  
00  
3C  
1E  
3C  
2D  
40  
25  
37  
10  
22  
3C  
1E  
1E  
00  
RAS.MIN [ns]  
Module Density per Rank  
t
t
t
t
t
t
t
AS.MIN and tCS.MIN [ns]  
AH.MIN and tCH.MIN [ns]  
DS.MIN [ns]  
DH.MIN [ns]  
WR.MIN [ns]  
WTR..MIN [ns]  
RTP..MIN [ns]  
Analysis Characteristics  
t
t
t
t
t
t
RC and tRFC Extension  
RC.MIN [ns]  
RFC.MIN [ns]  
CK.MAX [ns]  
DQSQ.MAX [ns]  
QHS.MAX [ns]  
00  
00  
00  
3C  
4B  
80  
1E  
28  
0F  
55  
82  
36  
3C  
4B  
80  
1E  
28  
0F  
55  
82  
36  
3C  
4B  
80  
1E  
28  
0F  
55  
82  
36  
PLL Relock Time  
T
Psi(T-A) DRAM  
∆T0 (DT0)  
∆T2N (DT2N, UDIMM) or ∆T2Q ( (DT2Q, RDIMM)  
∆T2P (DT2P)  
CASE.MAX Delta / ∆T4R4W Delta  
1F  
21  
1F  
21  
1F  
21  
Data Sheet  
31  
Rev. 1.0, 2004-10  
02182004-UN2L-F13U  
HYS72T[32/64]0[0/2][0/1]HR–[3.7/5]–A  
Registered Double-Data-Rate-Two SDRAM Modules  
SPD Codes  
Table 19  
SPD Codes for HYS72T[32000/64001/64020]HR–3.7–A (cont’d)  
Product Type  
Organization  
Label Code  
256 MB  
×72  
1 Rank (×8)  
512 MB  
×72  
1 Rank (×4)  
512 MB  
×72  
2 Ranks (×8)  
PC2–4200R– PC2–4200R– PC2–4200R–  
444  
Rev. 1.1  
HEX  
1D  
28  
14  
2C  
15  
444  
Rev. 1.1  
HEX  
1D  
28  
14  
2C  
15  
444  
Rev. 1.1  
HEX  
1D  
28  
14  
2C  
15  
JEDEC SPD Revision  
Byte# Description  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
∆T3N (DT3N)  
∆T3P.fast (DT3P fast)  
∆T3P.slow (DT3P slow)  
∆T4R (DT4R) / ∆T4R4W S Sign (DT4R4W)  
∆T5B (DT5B)  
∆T7 (DT7)  
Psi(ca) PLL  
Psi(ca) REG  
∆TPLL (DTPLL)  
21  
21  
21  
C4  
8C  
61  
78  
11  
A7  
C1  
00  
00  
00  
00  
00  
00  
00  
xx  
37  
32  
54  
C4  
8C  
61  
78  
11  
E1  
C1  
00  
00  
00  
00  
00  
00  
00  
xx  
37  
32  
54  
C4  
8C  
61  
78  
11  
A9  
C1  
00  
00  
00  
00  
00  
00  
00  
xx  
37  
32  
54  
∆TREG (DTREG) / Toggle Rate  
SPD Revision  
Checksum of Bytes 0-62  
JEDEC ID Code of Infineon (1)  
JEDEC ID Code of Infineon (2)  
JEDEC ID Code of Infineon (3)  
JEDEC ID Code of Infineon (4)  
JEDEC ID Code of Infineon (5)  
JEDEC ID Code of Infineon (6)  
JEDEC ID Code of Infineon (7)  
JEDEC ID Code of Infineon (8)  
Module Manufacturer Location  
Product Type, Char 1  
Product Type, Char 2  
Product Type, Char 3  
Product Type, Char 4  
Product Type, Char 5  
Product Type, Char 6  
33  
32  
30  
36  
34  
30  
36  
34  
30  
Data Sheet  
32  
Rev. 1.0, 2004-10  
02182004-UN2L-F13U  
HYS72T[32/64]0[0/2][0/1]HR–[3.7/5]–A  
Registered Double-Data-Rate-Two SDRAM Modules  
SPD Codes  
Table 19  
SPD Codes for HYS72T[32000/64001/64020]HR–3.7–A (cont’d)  
Product Type  
Organization  
Label Code  
256 MB  
×72  
1 Rank (×8)  
512 MB  
×72  
1 Rank (×4)  
512 MB  
×72  
2 Ranks (×8)  
PC2–4200R– PC2–4200R– PC2–4200R–  
444  
Rev. 1.1  
HEX  
30  
444  
Rev. 1.1  
HEX  
30  
444  
Rev. 1.1  
HEX  
32  
JEDEC SPD Revision  
Byte# Description  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
95  
96  
97  
98  
Product Type, Char 7  
Product Type, Char 8  
Product Type, Char 9  
30  
48  
52  
33  
2E  
37  
41  
20  
20  
20  
20  
1x  
xx  
xx  
xx  
xx  
xx  
31  
48  
52  
33  
2E  
37  
41  
20  
20  
20  
20  
1x  
xx  
xx  
xx  
xx  
xx  
30  
48  
52  
33  
2E  
37  
41  
20  
20  
20  
20  
1x  
xx  
xx  
xx  
xx  
xx  
Product Type, Char 10  
Product Type, Char 11  
Product Type, Char 12  
Product Type, Char 13  
Product Type, Char 14  
Product Type, Char 15  
Product Type, Char 16  
Product Type, Char 17  
Product Type, Char 18  
Module Revision Code  
Test Program Revision Code  
Module Manufacturing Date Year  
Module Manufacturing Date Week  
Module Serial Number (1)  
Module Serial Number (2)  
Module Serial Number (3)  
Module Serial Number (4)  
Not used  
xx  
xx  
00  
xx  
xx  
00  
xx  
xx  
00  
99 -  
127  
Data Sheet  
33  
Rev. 1.0, 2004-10  
02182004-UN2L-F13U  
HYS72T[32/64]0[0/2][0/1]HR–[3.7/5]–A  
Registered Double-Data-Rate-Two SDRAM Modules  
SPD Codes  
Table 20  
SPD Codes for HYS72T[32000/64001/64020]HR–5–A  
Product Type  
Organization  
Label Code  
256 MB  
×72  
1 Rank (×8)  
512 MB  
×72  
1 Rank (×4)  
512 MB  
×72  
2 Ranks (×8)  
PC2–3200R– PC2–3200R– PC2–3200R–  
333  
Rev. 1.1  
HEX  
80  
333  
Rev. 1.1  
HEX  
80  
333  
Rev. 1.1  
HEX  
80  
JEDEC SPD Revision  
Byte# Description  
0
Programmed SPD Bytes in EEPROM  
1
2
3
4
5
6
Total number of Bytes in EEPROM  
Memory Type (DDR2)  
Number of Row Addresses  
Number of Column Addresses  
DIMM Rank and Stacking Information  
Data Width  
08  
08  
0D  
0A  
60  
08  
08  
0D  
0B  
60  
08  
08  
0D  
0A  
61  
48  
48  
48  
7
Not used  
00  
00  
00  
8
Interface Voltage Level  
05  
05  
05  
9
t
t
CK @ CLMAX (Byte 18) [ns]  
AC SDRAM @ CLMAX (Byte 18) [ns]  
50  
60  
02  
82  
08  
08  
00  
0C  
04  
38  
00  
01  
04  
01  
50  
60  
50  
50  
60  
02  
82  
04  
04  
00  
0C  
04  
38  
00  
01  
05  
01  
50  
60  
50  
50  
60  
02  
82  
08  
08  
00  
0C  
04  
38  
00  
01  
05  
01  
50  
60  
50  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
Error Correction Support (non-ECC, ECC)  
Refresh Rate and Type  
Primary SDRAM Width  
Error Checking SDRAM Width  
Not used  
Burst Length Supported  
Number of Banks on SDRAM Device  
Supported CAS Latencies  
DIMM Mechanical Characteristics  
DIMM Type Information  
DIMM Attributes  
Component Attributes  
t
t
t
t
CK @ CLMAX -1 (Byte 18) [ns]  
AC SDRAM @ CLMAX -1 [ns]  
CK @ CLMAX -2 (Byte 18) [ns]  
AC SDRAM @ CLMAX -2 [ns]  
60  
60  
60  
Data Sheet  
34  
Rev. 1.0, 2004-10  
02182004-UN2L-F13U  
HYS72T[32/64]0[0/2][0/1]HR–[3.7/5]–A  
Registered Double-Data-Rate-Two SDRAM Modules  
SPD Codes  
Table 20  
SPD Codes for HYS72T[32000/64001/64020]HR–5–A (cont’d)  
Product Type  
Organization  
Label Code  
256 MB  
×72  
1 Rank (×8)  
512 MB  
×72  
1 Rank (×4)  
512 MB  
×72  
2 Ranks (×8)  
PC2–3200R– PC2–3200R– PC2–3200R–  
333  
Rev. 1.1  
HEX  
3C  
1E  
3C  
28  
40  
35  
47  
15  
27  
3C  
28  
1E  
00  
00  
37  
4B  
80  
23  
2D  
0F  
333  
Rev. 1.1  
HEX  
3C  
1E  
3C  
28  
80  
35  
47  
15  
27  
3C  
28  
1E  
00  
00  
37  
4B  
80  
23  
2D  
0F  
333  
Rev. 1.1  
HEX  
3C  
1E  
3C  
28  
40  
35  
47  
15  
27  
3C  
28  
1E  
00  
00  
37  
4B  
80  
23  
2D  
0F  
JEDEC SPD Revision  
Byte# Description  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
t
t
t
t
RP.MIN [ns]  
RRD.MIN [ns]  
RCD.MIN [ns]  
RAS.MIN [ns]  
Module Density per Rank  
t
t
t
t
t
t
t
AS.MIN and tCS.MIN [ns]  
AH.MIN and tCH.MIN [ns]  
DS.MIN [ns]  
DH.MIN [ns]  
WR.MIN [ns]  
WTR.MIN [ns]  
RTP.MIN [ns]  
Analysis Characteristics  
t
t
t
t
t
t
RC and tRFC Extension  
RC.MIN [ns]  
RFC.MIN [ns]  
CK.MAX [ns]  
DQSQ.MAX [ns]  
QHS.MAX [ns]  
PLL Relock Time  
T
Psi(T-A) DRAM  
∆T0 (DT0)  
∆T2N (DT2N, UDIMM) or ∆T2Q ( (DT2Q, RDIMM)  
∆T2P (DT2P)  
∆T3N (DT3N)  
∆T3P.fast (DT3P fast)  
∆T3P.slow (DT3P slow)  
CASE.MAX Delta / ∆T4R4W Delta  
53  
82  
2E  
19  
21  
19  
20  
14  
53  
82  
2E  
19  
21  
19  
20  
14  
53  
82  
2E  
19  
21  
19  
20  
14  
Data Sheet  
35  
Rev. 1.0, 2004-10  
02182004-UN2L-F13U  
HYS72T[32/64]0[0/2][0/1]HR–[3.7/5]–A  
Registered Double-Data-Rate-Two SDRAM Modules  
SPD Codes  
Table 20  
SPD Codes for HYS72T[32000/64001/64020]HR–5–A (cont’d)  
Product Type  
Organization  
Label Code  
256 MB  
×72  
1 Rank (×8)  
512 MB  
×72  
1 Rank (×4)  
512 MB  
×72  
2 Ranks (×8)  
PC2–3200R– PC2–3200R– PC2–3200R–  
333  
Rev. 1.1  
HEX  
26  
333  
Rev. 1.1  
HEX  
26  
333  
Rev. 1.1  
HEX  
26  
JEDEC SPD Revision  
Byte# Description  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
∆T4R (DT4R) / ∆T4R4W S Sign (DT4R4W)  
∆T5B (DT5B)  
∆T7 (DT7)  
Psi(ca) PLL  
Psi(ca) REG  
∆TPLL (DTPLL)  
∆TREG (DTREG) / Toggle Rate  
SPD Revision  
14  
14  
14  
1F  
C4  
8C  
59  
5C  
11  
D8  
C1  
00  
00  
00  
00  
00  
00  
00  
xx  
37  
32  
54  
33  
32  
1F  
C4  
8C  
59  
5C  
11  
12  
C1  
00  
00  
00  
00  
00  
00  
00  
xx  
37  
32  
54  
36  
34  
1F  
C4  
8C  
59  
5C  
11  
DA  
C1  
00  
00  
00  
00  
00  
00  
00  
xx  
37  
32  
54  
36  
34  
Checksum of Bytes 0-62  
JEDEC ID Code of Infineon (1)  
JEDEC ID Code of Infineon (2)  
JEDEC ID Code of Infineon (3)  
JEDEC ID Code of Infineon (4)  
JEDEC ID Code of Infineon (5)  
JEDEC ID Code of Infineon (6)  
JEDEC ID Code of Infineon (7)  
JEDEC ID Code of Infineon (8)  
Module Manufacturer Location  
Product Type, Char 1  
Product Type, Char 2  
Product Type, Char 3  
Product Type, Char 4  
Product Type, Char 5  
Product Type, Char 6  
Product Type, Char 7  
Product Type, Char 8  
Product Type, Char 9  
Product Type, Char 10  
30  
30  
30  
48  
30  
30  
31  
48  
30  
32  
30  
48  
52  
52  
52  
Data Sheet  
36  
Rev. 1.0, 2004-10  
02182004-UN2L-F13U  
HYS72T[32/64]0[0/2][0/1]HR–[3.7/5]–A  
Registered Double-Data-Rate-Two SDRAM Modules  
SPD Codes  
Table 20  
SPD Codes for HYS72T[32000/64001/64020]HR–5–A (cont’d)  
Product Type  
Organization  
Label Code  
256 MB  
×72  
1 Rank (×8)  
512 MB  
×72  
1 Rank (×4)  
512 MB  
×72  
2 Ranks (×8)  
PC2–3200R– PC2–3200R– PC2–3200R–  
333  
Rev. 1.1  
HEX  
35  
41  
20  
20  
20  
20  
20  
20  
1x  
xx  
xx  
xx  
xx  
xx  
xx  
333  
Rev. 1.1  
HEX  
35  
41  
20  
20  
20  
20  
20  
20  
1x  
xx  
xx  
xx  
xx  
xx  
xx  
333  
Rev. 1.1  
HEX  
35  
41  
20  
20  
20  
20  
20  
20  
1x  
xx  
xx  
xx  
xx  
xx  
xx  
JEDEC SPD Revision  
Byte# Description  
83  
84  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
95  
96  
97  
98  
Product Type, Char 11  
Product Type, Char 12  
Product Type, Char 13  
Product Type, Char 14  
Product Type, Char 15  
Product Type, Char 16  
Product Type, Char 17  
Product Type, Char 18  
Module Revision Code  
Test Program Revision Code  
Module Manufacturing Date Year  
Module Manufacturing Date Week  
Module Serial Number (1)  
Module Serial Number (2)  
Module Serial Number (3)  
Module Serial Number (4)  
Not used  
xx  
00  
xx  
00  
xx  
00  
99 -  
127  
Data Sheet  
37  
Rev. 1.0, 2004-10  
02182004-UN2L-F13U  
HYS72T[32/64]0[0/2][0/1]HR–[3.7/5]–A  
Registered Double-Data-Rate-Two SDRAM Modules  
SPD Codes  
Table 21  
SPD Codes for HYS72T[64000/128000/128020]HR–5–A  
Product Type  
Organization  
512 MB  
×72  
1 GByte  
×72  
1 GByte  
×72  
1 Rank (×8)  
1 Rank (×4)  
2 Ranks (×8)  
Label Code  
PC2–3200R–333 PC2–3200R–333 PC2–3200R–333  
JEDEC SPD Revision  
Byte# Description  
Rev. 1.1  
HEX  
80  
Rev. 1.1  
HEX  
80  
Rev. 1.1  
HEX  
80  
0
Programmed SPD Bytes in EEPROM  
1
2
3
4
5
6
Total number of Bytes in EEPROM  
Memory Type (DDR2)  
Number of Row Addresses  
Number of Column Addresses  
DIMM Rank and Stacking Information  
Data Width  
08  
08  
0E  
0A  
60  
08  
08  
0E  
0B  
60  
08  
08  
0E  
0A  
61  
48  
48  
48  
7
Not used  
00  
00  
00  
8
Interface Voltage Level  
05  
05  
05  
9
t
t
CK @ CLMAX (Byte 18) [ns]  
AC SDRAM @ CLMAX (Byte 18) [ns]  
50  
60  
02  
82  
08  
08  
00  
0C  
04  
38  
00  
01  
04  
01  
50  
60  
50  
50  
60  
02  
82  
04  
04  
00  
0C  
04  
38  
00  
01  
05  
01  
50  
60  
50  
50  
60  
02  
82  
08  
08  
00  
0C  
04  
38  
00  
01  
05  
01  
50  
60  
50  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
Error Correction Support (non-ECC, ECC)  
Refresh Rate and Type  
Primary SDRAM Width  
Error Checking SDRAM Width  
Not used  
Burst Length Supported  
Number of Banks on SDRAM Device  
Supported CAS Latencies  
DIMM Mechanical Characteristics  
DIMM Type Information  
DIMM Attributes  
Component Attributes  
t
t
t
t
t
CK @ CLMAX -1 (Byte 18) [ns]  
AC SDRAM @ CLMAX -1 [ns]  
CK @ CLMAX -2 (Byte 18) [ns]  
AC SDRAM @ CLMAX -2 [ns]  
RP.MIN [ns]  
60  
3C  
60  
3C  
60  
3C  
Data Sheet  
38  
Rev. 1.0, 2004-10  
02182004-UN2L-F13U  
HYS72T[32/64]0[0/2][0/1]HR–[3.7/5]–A  
Registered Double-Data-Rate-Two SDRAM Modules  
SPD Codes  
Table 21  
SPD Codes for HYS72T[64000/128000/128020]HR–5–A (cont’d)  
Product Type  
Organization  
512 MB  
×72  
1 GByte  
×72  
1 GByte  
×72  
1 Rank (×8)  
1 Rank (×4)  
2 Ranks (×8)  
Label Code  
PC2–3200R–333 PC2–3200R–333 PC2–3200R–333  
JEDEC SPD Revision  
Byte# Description  
Rev. 1.1  
HEX  
1E  
3C  
28  
80  
35  
47  
15  
27  
3C  
28  
1E  
00  
00  
37  
69  
80  
23  
Rev. 1.1  
HEX  
1E  
3C  
28  
01  
35  
47  
15  
27  
3C  
28  
1E  
00  
00  
37  
69  
80  
23  
2D  
0F  
51  
78  
32  
1D  
1E  
1B  
1E  
17  
Rev. 1.1  
HEX  
1E  
3C  
28  
80  
35  
47  
15  
27  
3C  
28  
1E  
00  
00  
37  
69  
80  
23  
2D  
0F  
51  
78  
32  
1D  
1E  
1B  
1E  
17  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
t
t
t
RRD.MIN [ns]  
RCD.MIN [ns]  
RAS.MIN [ns]  
Module Density per Rank  
t
t
t
t
t
t
t
AS.MIN and tCS.MIN [ns]  
AH.MIN and tCH.MIN [ns]  
DS.MIN [ns]  
DH.MIN [ns]  
WR.MIN [ns]  
WTR.MIN [ns]  
RTP.MIN [ns]  
Analysis Characteristics  
t
t
t
t
t
t
RC and tRFC Extension  
RC.MIN [ns]  
RFC.MIN [ns]  
CK.MAX [ns]  
DQSQ.MAX [ns]  
QHS.MAX [ns]  
2D  
0F  
51  
78  
32  
PLL Relock Time  
T
Psi(T-A) DRAM  
∆T0 (DT0)  
∆T2N (DT2N, UDIMM) or ∆T2Q ( (DT2Q, RDIMM) 1D  
∆T2P (DT2P)  
∆T3N (DT3N)  
∆T3P.fast (DT3P fast)  
∆T3P.slow (DT3P slow)  
∆T4R (DT4R) / ∆T4R4W S Sign (DT4R4W)  
CASE.MAX Delta / ∆T4R4W Delta  
1E  
1B  
1E  
17  
28  
28  
28  
Data Sheet  
39  
Rev. 1.0, 2004-10  
02182004-UN2L-F13U  
HYS72T[32/64]0[0/2][0/1]HR–[3.7/5]–A  
Registered Double-Data-Rate-Two SDRAM Modules  
SPD Codes  
Table 21  
SPD Codes for HYS72T[64000/128000/128020]HR–5–A (cont’d)  
Product Type  
Organization  
512 MB  
×72  
1 GByte  
×72  
1 GByte  
×72  
1 Rank (×8)  
1 Rank (×4)  
2 Ranks (×8)  
Label Code  
PC2–3200R–333 PC2–3200R–333 PC2–3200R–333  
JEDEC SPD Revision  
Byte# Description  
Rev. 1.1  
HEX  
1B  
1E  
C4  
8C  
59  
5C  
11  
3B  
C1  
00  
00  
00  
00  
00  
00  
00  
xx  
37  
Rev. 1.1  
HEX  
1B  
1E  
C4  
8C  
59  
5C  
11  
B6  
C1  
00  
00  
00  
00  
00  
00  
00  
xx  
37  
Rev. 1.1  
HEX  
1B  
1E  
C4  
8C  
59  
5C  
11  
3D  
C1  
00  
00  
00  
00  
00  
00  
00  
xx  
37  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
∆T5B (DT5B)  
∆T7 (DT7)  
Psi(ca) PLL  
Psi(ca) REG  
∆TPLL (DTPLL)  
∆TREG (DTREG) / Toggle Rate  
SPD Revision  
Checksum of Bytes 0-62  
JEDEC ID Code of Infineon (1)  
JEDEC ID Code of Infineon (2)  
JEDEC ID Code of Infineon (3)  
JEDEC ID Code of Infineon (4)  
JEDEC ID Code of Infineon (5)  
JEDEC ID Code of Infineon (6)  
JEDEC ID Code of Infineon (7)  
JEDEC ID Code of Infineon (8)  
Module Manufacturer Location  
Product Type, Char 1  
Product Type, Char 2  
Product Type, Char 3  
Product Type, Char 4  
Product Type, Char 5  
Product Type, Char 6  
Product Type, Char 7  
Product Type, Char 8  
Product Type, Char 9  
Product Type, Char 10  
Product Type, Char 11  
32  
54  
36  
34  
30  
30  
30  
48  
32  
54  
31  
32  
38  
30  
30  
30  
32  
54  
31  
32  
38  
30  
32  
30  
52  
35  
48  
52  
48  
52  
Data Sheet  
40  
Rev. 1.0, 2004-10  
02182004-UN2L-F13U  
HYS72T[32/64]0[0/2][0/1]HR–[3.7/5]–A  
Registered Double-Data-Rate-Two SDRAM Modules  
SPD Codes  
Table 21  
SPD Codes for HYS72T[64000/128000/128020]HR–5–A (cont’d)  
Product Type  
Organization  
512 MB  
×72  
1 GByte  
×72  
1 GByte  
×72  
1 Rank (×8)  
1 Rank (×4)  
2 Ranks (×8)  
Label Code  
PC2–3200R–333 PC2–3200R–333 PC2–3200R–333  
JEDEC SPD Revision  
Byte# Description  
Rev. 1.1  
HEX  
41  
20  
20  
20  
20  
20  
20  
2x  
xx  
xx  
xx  
xx  
xx  
xx  
xx  
Rev. 1.1  
HEX  
35  
41  
20  
20  
20  
20  
20  
2x  
xx  
xx  
xx  
xx  
xx  
xx  
xx  
Rev. 1.1  
HEX  
35  
41  
20  
20  
20  
20  
20  
2x  
xx  
xx  
xx  
xx  
xx  
xx  
xx  
84  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
95  
96  
97  
98  
Product Type, Char 12  
Product Type, Char 13  
Product Type, Char 14  
Product Type, Char 15  
Product Type, Char 16  
Product Type, Char 17  
Product Type, Char 18  
Module Revision Code  
Test Program Revision Code  
Module Manufacturing Date Year  
Module Manufacturing Date Week  
Module Serial Number (1)  
Module Serial Number (2)  
Module Serial Number (3)  
Module Serial Number (4)  
Not used  
99 -  
00  
00  
00  
127  
Data Sheet  
41  
Rev. 1.0, 2004-10  
02182004-UN2L-F13U  
HYS72T[32/64]0[0/2][0/1]HR–[3.7/5]–A  
Registered Double-Data-Rate-Two SDRAM Modules  
SPD Codes  
Table 22  
SPD Codes for HYS72T[256020/256220]HR–5–A  
Product Type  
Organization  
2 GByte  
2 GByte  
×72  
×72  
2 Ranks (×4)  
2 Ranks (×4)  
Label Code  
PC2–3200R–333  
PC2–3200R–333  
JEDEC SPD Revision  
Byte# Description  
Rev. 1.1  
HEX  
80  
Rev. 1.1  
HEX  
80  
0
Programmed SPD Bytes in EEPROM  
1
2
3
4
5
6
Total number of Bytes in EEPROM  
Memory Type (DDR2)  
Number of Row Addresses  
Number of Column Addresses  
DIMM Rank and Stacking Information  
Data Width  
08  
08  
0E  
0B  
61  
08  
08  
0E  
0B  
61  
48  
48  
7
Not used  
00  
00  
8
Interface Voltage Level  
05  
05  
9
t
t
CK @ CLMAX (Byte 18) [ns]  
AC SDRAM @ CLMAX (Byte 18) [ns]  
50  
60  
02  
82  
04  
04  
00  
0C  
04  
38  
00  
01  
07  
01  
50  
60  
50  
50  
60  
02  
82  
04  
04  
00  
0C  
04  
38  
00  
01  
07  
01  
50  
60  
50  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
Error Correction Support (non-ECC, ECC)  
Refresh Rate and Type  
Primary SDRAM Width  
Error Checking SDRAM Width  
Not used  
Burst Length Supported  
Number of Banks on SDRAM Device  
Supported CAS Latencies  
DIMM Mechanical Characteristics  
DIMM Type Information  
DIMM Attributes  
Component Attributes  
t
t
t
t
t
CK @ CLMAX -1 (Byte 18) [ns]  
AC SDRAM @ CLMAX -1 [ns]  
CK @ CLMAX -2 (Byte 18) [ns]  
AC SDRAM @ CLMAX -2 [ns]  
RP.MIN [ns]  
60  
3C  
60  
3C  
Data Sheet  
42  
Rev. 1.0, 2004-10  
02182004-UN2L-F13U  
HYS72T[32/64]0[0/2][0/1]HR–[3.7/5]–A  
Registered Double-Data-Rate-Two SDRAM Modules  
SPD Codes  
Table 22  
SPD Codes for HYS72T[256020/256220]HR–5–A (cont’d)  
Product Type  
Organization  
2 GByte  
2 GByte  
×72  
×72  
2 Ranks (×4)  
2 Ranks (×4)  
Label Code  
PC2–3200R–333  
PC2–3200R–333  
JEDEC SPD Revision  
Byte# Description  
Rev. 1.1  
HEX  
1E  
3C  
28  
01  
35  
47  
15  
27  
3C  
28  
1E  
00  
00  
37  
69  
80  
23  
Rev. 1.1  
HEX  
1E  
3C  
28  
01  
35  
47  
15  
27  
3C  
28  
1E  
00  
00  
37  
69  
80  
23  
2D  
0F  
51  
78  
32  
1D  
1E  
1B  
1E  
17  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
t
t
t
RRD.MIN [ns]  
RCD.MIN [ns]  
RAS.MIN [ns]  
Module Density per Rank  
t
t
t
t
t
t
t
AS.MIN and tCS.MIN [ns]  
AH.MIN and tCH.MIN [ns]  
DS.MIN [ns]  
DH.MIN [ns]  
WR.MIN [ns]  
WTR.MIN [ns]  
RTP.MIN [ns]  
Analysis Characteristics  
t
t
t
t
t
t
RC and tRFC Extension  
RC.MIN [ns]  
RFC.MIN [ns]  
CK.MAX [ns]  
DQSQ.MAX [ns]  
QHS.MAX [ns]  
2D  
0F  
51  
78  
32  
PLL Relock Time  
T
Psi(T-A) DRAM  
∆T0 (DT0)  
∆T2N (DT2N, UDIMM) or ∆T2Q ( (DT2Q, RDIMM) 1D  
∆T2P (DT2P)  
∆T3N (DT3N)  
∆T3P.fast (DT3P fast)  
∆T3P.slow (DT3P slow)  
∆T4R (DT4R) / ∆T4R4W S Sign (DT4R4W)  
CASE.MAX Delta / ∆T4R4W Delta  
1E  
1B  
1E  
17  
28  
28  
Data Sheet  
43  
Rev. 1.0, 2004-10  
02182004-UN2L-F13U  
HYS72T[32/64]0[0/2][0/1]HR–[3.7/5]–A  
Registered Double-Data-Rate-Two SDRAM Modules  
SPD Codes  
Table 22  
SPD Codes for HYS72T[256020/256220]HR–5–A (cont’d)  
Product Type  
Organization  
2 GByte  
2 GByte  
×72  
×72  
2 Ranks (×4)  
2 Ranks (×4)  
Label Code  
PC2–3200R–333  
PC2–3200R–333  
JEDEC SPD Revision  
Byte# Description  
Rev. 1.1  
HEX  
1B  
1E  
C4  
8C  
59  
5C  
11  
B9  
C1  
00  
00  
00  
00  
00  
00  
00  
xx  
37  
Rev. 1.1  
HEX  
1B  
1E  
C4  
8C  
59  
5C  
11  
B9  
C1  
00  
00  
00  
00  
00  
00  
00  
xx  
37  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
∆T5B (DT5B)  
∆T7 (DT7)  
Psi(ca) PLL  
Psi(ca) REG  
∆TPLL (DTPLL)  
∆TREG (DTREG) / Toggle Rate  
SPD Revision  
Checksum of Bytes 0-62  
JEDEC ID Code of Infineon (1)  
JEDEC ID Code of Infineon (2)  
JEDEC ID Code of Infineon (3)  
JEDEC ID Code of Infineon (4)  
JEDEC ID Code of Infineon (5)  
JEDEC ID Code of Infineon (6)  
JEDEC ID Code of Infineon (7)  
JEDEC ID Code of Infineon (8)  
Module Manufacturer Location  
Product Type, Char 1  
Product Type, Char 2  
Product Type, Char 3  
Product Type, Char 4  
Product Type, Char 5  
Product Type, Char 6  
Product Type, Char 7  
Product Type, Char 8  
Product Type, Char 9  
Product Type, Char 10  
Product Type, Char 11  
32  
54  
32  
35  
36  
30  
32  
30  
32  
54  
32  
35  
36  
32  
32  
30  
48  
52  
48  
52  
Data Sheet  
44  
Rev. 1.0, 2004-10  
02182004-UN2L-F13U  
HYS72T[32/64]0[0/2][0/1]HR–[3.7/5]–A  
Registered Double-Data-Rate-Two SDRAM Modules  
SPD Codes  
Table 22  
SPD Codes for HYS72T[256020/256220]HR–5–A (cont’d)  
Product Type  
Organization  
2 GByte  
2 GByte  
×72  
×72  
2 Ranks (×4)  
2 Ranks (×4)  
Label Code  
PC2–3200R–333  
PC2–3200R–333  
JEDEC SPD Revision  
Byte# Description  
Rev. 1.1  
HEX  
35  
41  
20  
20  
20  
20  
20  
2x  
xx  
xx  
xx  
xx  
xx  
xx  
xx  
Rev. 1.1  
HEX  
35  
41  
20  
20  
20  
20  
20  
2x  
xx  
xx  
xx  
xx  
xx  
xx  
xx  
84  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
95  
96  
97  
98  
Product Type, Char 12  
Product Type, Char 13  
Product Type, Char 14  
Product Type, Char 15  
Product Type, Char 16  
Product Type, Char 17  
Product Type, Char 18  
Module Revision Code  
Test Program Revision Code  
Module Manufacturing Date Year  
Module Manufacturing Date Week  
Module Serial Number (1)  
Module Serial Number (2)  
Module Serial Number (3)  
Module Serial Number (4)  
Not used  
99 -  
00  
00  
127  
Data Sheet  
45  
Rev. 1.0, 2004-10  
02182004-UN2L-F13U  
HYS72T[32/64]0[0/2][0/1]HR–[3.7/5]–A  
Registered Double-Data-Rate-Two SDRAM Modules  
Package Outlines  
6
Package Outlines  
133.35  
2.7 MAX.  
128.95  
1
120  
4
C
2.5  
0.4  
5
±0.1  
1.27  
63  
55  
A
±0.1  
1.5  
121  
240  
B
(3)  
Detail of contacts  
1
±0.05  
0.8  
0.1 A B C  
Burr max. 0.4 allowed  
GLD09655  
Figure 5  
Package Outline Raw Card F L-DIM-240-11  
Data Sheet  
46  
Rev. 1.0, 2004-10  
02182004-UN2L-F13U  
HYS72T[32/64]0[0/2][0/1]HR–[3.7/5]–A  
Registered Double-Data-Rate-Two SDRAM Modules  
Package Outlines  
133.35  
4 MAX.  
128.95  
1
120  
4
C
2.5  
0.4  
5
±0.1  
1.27  
63  
55  
A
±0.1  
1.5  
121  
240  
B
(3)  
Detail of contacts  
1
±0.05  
0.8  
0.1 A B C  
Burr max. 0.4 allowed  
GLD09656  
Figure 6  
Package Outline Raw Card G L-DIM-240-12  
Data Sheet  
47  
Rev. 1.0, 2004-10  
02182004-UN2L-F13U  
HYS72T[32/64]0[0/2][0/1]HR–[3.7/5]–A  
Registered Double-Data-Rate-Two SDRAM Modules  
Package Outlines  
133.35  
4 MAX.  
128.95  
1
120  
4
C
2.5  
0.4  
5
±0.1  
1.27  
63  
55  
A
±0.1  
1.5  
121  
240  
B
(3)  
Detail of contacts  
1
±0.05  
0.8  
0.1 A B C  
Burr max. 0.4 allowed  
GLD09657  
Figure 7  
Package Outline Raw Card H L-DIM-240-13  
Data Sheet  
48  
Rev. 1.0, 2004-10  
02182004-UN2L-F13U  
HYS72T[32/64]0[0/2][0/1]HR–[3.7/5]–A  
Registered Double-Data-Rate-Two SDRAM Modules  
Product Type Nomenclature (DDR2 DRAMs and DIMMs)  
7
Product Type Nomenclature (DDR2 DRAMs and DIMMs)  
Infineon’s nomenclature uses simple coding combined with some propriatory coding. Table 23 provides examples  
for module and component product type number as well as the field number. The detailed field description together  
with possible values and coding explanation is listed for modules in Table 24 and for components in Table 25.  
Table 23  
Example for  
Nomenclature Fields and Examples  
Field Number  
1
HYS  
HYB  
2
64  
18  
3
T
T
4
64  
512  
5
0
16  
6
2
7
0
0
8
K
A
9
M
C
10  
–5  
–5  
11  
–A  
Micro-DIMM  
DDR2 DRAM  
1) Multiplying “Memory Density per I/O” with “Module Data  
Width” and dividing by 8 for Non-ECC and 9 for ECC  
modules gives the overall module memory density in  
MBytes as listed in column “Coding”.  
Table 24  
Field Description  
DDR2 DIMM Nomenclature  
Values Coding  
1
INFINEON  
HYS  
Constant  
Modul Prefix  
2
Module Data  
64  
72  
T
Non-ECC  
ECC  
DDR2  
Table 25  
Field Description  
DDR2 DRAM Nomenclature  
Values Coding  
Width [bit]  
3
4
DRAM  
1
INFINEON  
HYB  
Constant  
Technology  
Component Prefix  
Memory Density  
32  
64  
128  
256  
0 .. 9  
256 MByte  
512 MByte  
1 GByte  
2 GByte  
look up table  
2
3
4
Interface Voltage [V] 18  
DRAM Technology  
Component Density 256  
SSTL1.8  
DDR2  
256 Mbit  
512 Mbit  
1 Gbit  
2 Gbit  
×4  
per I/O [Mbit];  
T
Module Density1)  
[Mbit]  
512  
1G  
2G  
40  
5
6
Raw Card  
Generation  
Number of Module 0, 2, 4 1, 2, 4  
5+6 Number of I/Os  
Ranks  
80  
×8  
7
8
Product Variations 0 .. 9  
look up table  
look up table  
16  
×16  
Package,  
A .. Z  
7
8
Product Variations 0 .. 9  
Die Revision  
look up table  
First  
Second  
Lead-Free Status  
A
B
C
9
Module Type  
D
M
R
U
–3.7  
–5  
–A  
–B  
SO-DIMM  
Micro-DIMM  
Registered  
Unbuffered  
PC2–4200 4–4–4  
PC2–3200 3–3–3  
First  
9
Package,  
FBGA,  
Lead-Free Status  
lead-containing  
F
–3.7  
–5  
FBGA, lead-free  
DDR2-533C  
DDR2-400B  
10  
11  
Speed Grade  
Die Revision  
10  
11  
Speed Grade  
N/A for Components  
Second  
Data Sheet  
49  
Rev. 1.0, 2004-10  
02182004-UN2L-F13U  
 
 
 
w w w . i n f i n e o n . c o m  
Published by Infineon Technologies AG  
厂商 型号 描述 页数 下载

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