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TZA3024U

型号：

TZA3024U

品牌：

PHILIPS[ PHILIPS SEMICONDUCTORS ]

页数：

20 页

PDF大小：

364 K

下载PDF手册
INTEGRATED CIRCUITS  
DATA SHEET  
TZA3024T; TZA3024U  
SDH/SONET STM4/OC12  
postamplifiers  
1998 Aug 18  
Objective specification  
File under Integrated Circuits, IC19  
Philips Semiconductors  
Objective specification  
SDH/SONET STM4/OC12 postamplifiers  
TZA3024T; TZA3024U  
FEATURES  
APPLICATIONS  
• Pin compatible with the NE/SA5224 and NE/SA5225 but  
with extended power supply range and less external  
component count  
• Digital fibre optic receiver in short, medium and long  
haul optical telecommunications transmission systems  
or in high speed data networks  
• Wideband operation from 1.0 kHz to 620 MHz typical  
• Applicable in 622 Mbits/s SDH/SONET receivers  
• Single supply voltage from 3.0 to 5.5 V  
• Wideband RF gain block.  
GENERAL DESCRIPTION  
• PECL (Positive Emitter Coupled Logic) compatible data  
outputs  
The TZA3024 is a high gain limiting amplifier that is  
designed to process signals from fibre optic preamplifiers  
such as the TZA3023. It is pin compatible with the  
NE/SA5224 and NE/SA5225 but with an extended power  
supply range, and needs less external components.  
Capable of operating at 622 Mbits/s, the chip has input  
signal level detection with a user-programmable threshold.  
The data and level-detection status outputs are differential  
outputs for optimum noise margin and ease of use.  
• Programmable input signal level-detection which can be  
adjusted using a single external resistor  
• On-chip DC offset compensation without external  
capacitor  
• Fully differential for excellent PSRR.  
ORDERING INFORMATION  
TYPE  
PACKAGE  
NUMBER  
NAME  
DESCRIPTION  
VERSION  
SOT109-1  
−
TZA3024T  
TZA3024U  
SO16  
plastic small outline package; 16 leads; body width 3.9 mm  
−
naked die in waffle pack carriers; die dimensions 1.58 × 1.58 mm  
1998 Aug 18  
2
Philips Semiconductors  
Objective specification  
SDH/SONET STM4/OC12 postamplifiers  
TZA3024T; TZA3024U  
BLOCK DIAGRAM  
TEST  
2
(2, 10, 15, 21, 26)  
DC-OFFSET  
TZA3024  
COMPENSATION  
(24) 13  
(23) 12  
4 (7)  
5 (8)  
DIN  
DOUT  
A1  
A2  
A3  
DOUTQ  
DINQ  
(16) 8  
25 kΩ  
JAM  
RECTIFIER  
(18) 10  
(17) 9  
ST  
16 (30)  
15 (29)  
A4  
RSET  
STQ  
1 kΩ  
BAND GAP  
REFERENCE  
V
ref  
(3, 4, 6, 9) (1, 14)  
(11, 12)  
6
(13) (19, 20, 22, 25) (27, 28)  
3
1
7
11  
14  
AGND  
SUB  
V
CF DGND  
V
CCD  
MBK851  
CCA  
The numbers in brackets refer to the pad numbers of the naked die version.  
Fig.1 Block diagram.  
1998 Aug 18  
3
Philips Semiconductors  
Objective specification  
SDH/SONET STM4/OC12 postamplifiers  
TZA3024T; TZA3024U  
PINNING  
SYMBOL  
PIN  
TYPE  
DESCRIPTION  
SUB  
1
2
3
4
substrate  
test pin  
ground  
substrate pin; must be at the same potential as AGND (pin 3)  
for test purpose only; to be left open-circuit in the application  
analog ground; must be at the same potential as DGND (pin 11)  
TEST  
AGND  
DIN  
analog input differential input; DC bias level is set internally at approximately 2.55 V;  
complimentary to DINQ (pin 5)  
DINQ  
5
analog input differential input; DC bias level is set internally at approximately 2.55 V;  
complimentary to DIN (pin 4)  
VCCA  
CF  
6
7
supply  
analog supply voltage; must be at the same potential as VCCD (pin 14)  
analog input filter capacitor for input signal level detector; capacitor should be connected  
between this pin and VCCA (pin 6)  
JAM  
8
PECL input  
PECL-compatible input; controls the output buffers DOUT and DOUTQ  
(pins 13 and 12). When a LOW signal is applied, the outputs will follow the input  
signal. When a HIGH signal is applied, the DOUT and DOUTQ pins will latch into  
LOW and HIGH states, respectively. When left unconnected, this pin is actively  
pulled LOW (JAM off).  
STQ  
ST  
9
PECL output PECL-compatible status output of the input signal level detector; when the input  
signal is below the user-programmed threshold level, this output is HIGH;  
complimentary to ST (pin 10)  
10  
PECL output PECL-compatible status output of the input signal level detector; when the input  
signal is below the user-programmed threshold level, this output is LOW;  
complimentary to STQ (pin 9)  
DGND  
11  
12  
ground  
digital ground; must be at the same potential as AGND (pin 3)  
DOUTQ  
PECL output PECL-compatible differential output; when JAM is HIGH, this pin will be forced  
into a HIGH condition; complimentary to DOUT (pin 13)  
DOUT  
13  
PECL output PECL-compatible differential output; when JAM is HIGH, this pin will be forced  
into a LOW condition; complimentary to DOUTQ (pin 12)  
VCCD  
Vref  
14  
15  
16  
supply  
digital supply voltage; must be at the same potential as VCCA (pin 6)  
analog output band gap reference voltage; typical value is 1.2 V; internal series resistor of 1 kΩ  
RSET  
analog input input signal level detector programming; nominal DC voltage is VCCA − 1.5 V;  
threshold level is set by connecting an external resistor between RSET and VCCA  
or by forcing a current into RSET; default value for this resistor is 180 kΩ which  
corresponds with approximately 4 mV(p-p) differential input signal  
1998 Aug 18  
4
Philips Semiconductors  
Objective specification  
SDH/SONET STM4/OC12 postamplifiers  
TZA3024T; TZA3024U  
PAD CONFIGURATION  
Pad centre locations  
COORDINATES(1)  
SYMBOL  
SUB  
PAD  
x
y
handbook, halfpage  
1
−235.7  
−392.8  
−532.8  
−647.8  
−647.8  
−647.8  
−647.8  
−647.8  
−647.8  
−647.8  
−647.8  
−532.8  
−392.8  
−235.7  
−78.6  
+647.8  
+647.8  
+647.8  
+507.1  
+350.0  
+210.0  
+70.0  
SUB  
TEST  
AGND  
DIN  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
RSET  
TEST  
AGND  
AGND  
n.c.  
2
V
ref  
3
V
CCD  
4
DOUT  
DOUTQ  
DGND  
ST  
5
TZA3024T  
DINQ  
AGND  
DIN  
6
V
7
CCA  
DINQ  
AGND  
TEST  
VCCA  
VCCA  
CF  
8
−70.0  
CF  
9
−210.0  
−350.0  
−507.1  
−647.8  
−647.8  
−647.8  
−647.8  
−647.8  
−647.8  
−647.8  
−647.8  
−507.1  
−350.0  
−210.0  
−70.0  
STQ  
JAM  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
MBK852  
SUB  
TEST  
JAM  
Fig.2 Pin configuration.  
+61.4  
STQ  
+218.5  
+375.6  
+532.7  
+647.8  
+647.8  
+647.8  
+647.8  
647.8  
ST  
DGND  
DGND  
TEST  
DGND  
DOUTQ  
DOUT  
DGND  
TEST  
VCCD  
VCCD  
Vref  
70.0  
647.8  
210.0  
647.8  
350.0  
647.8  
507.1  
532.7  
647.8  
392.7  
647.8  
RSET  
n.c.  
235.6  
647.8  
78.5  
647.8  
n.c.  
−78.6  
+647.8  
Note  
1. Coordinates represent the position of the centre of the  
pad, in µm, with respect to the centre of the die.  
1998 Aug 18  
5
Philips Semiconductors  
Objective specification  
SDH/SONET STM4/OC12 postamplifiers  
TZA3024T; TZA3024U  
Bonding pad locations  
3
2
1
32  
31  
30  
29 28  
V
27  
AGND  
4
CCD  
n.c.  
AGND  
DIN  
26  
25  
24  
23  
22  
21  
5
6
TEST  
DGND  
DOUT  
DOUTQ  
DGND  
TEST  
7
(1)  
x
1.58  
mm  
0
8
DINQ  
AGND  
TEST  
0
y
9
TZA3024U  
10  
V
20  
11  
DGND  
CCA  
12 13  
14  
15 16  
17  
18  
19  
(1)  
1.58 mm  
MBK853  
(1) Typical value.  
Pad size: 90 × 90 µm.  
Fig.3 Bonding pad locations of TZA3024U.  
outputs ST and STQ. This flag can also be used to prevent  
FUNCTIONAL DESCRIPTION  
the PECL outputs DOUT and DOUTQ from reacting to  
noise in the absence of a valid input signal, by connecting  
the output STQ to the input JAM. This insures that data will  
only be transmitted when the input signal-to-noise ratio is  
sufficient for low bit error rate system operation.  
The TZA3024 accepts up to 622 Mbits/s SDH/SONET  
data streams, with amplitudes from 2 mV(p-p) up to 1 V(p-p)  
single-ended. The input signal will be amplified and limited  
to differential PECL output levels (see Fig.1).  
The input buffer A1 presents an impedance of  
approximately 4.5 kΩ to the data stream on the inputs  
DIN and DINQ. The input can be used both single-ended  
and differential, but differential operation is preferred for  
better performance.  
PECL logic  
The logic level symbol definitions for PECL are shown in  
Fig.4.  
Because of the high gain of the postamplifier, a very small  
offset voltage would shift the decision level in such a way  
that the input sensitivity decreases drastically. Therefore a  
DC offset compensation circuit is implemented in the  
TZA3024, which keeps the input of buffer A3 at its toggle  
point in the absence of any input signal.  
Input biasing  
The input pins DIN and DINQ are DC biased at  
approximately 2.55 V by an internal reference generator  
(see Fig.5). The TZA3024 can be DC-coupled, but  
AC-coupling is preferred. In case of DC-coupling, the  
driving source must operate within the allowable input  
signal range (2.0 V to VCCA + 0.5 V).  
An input signal level detection is implemented to check if  
the input signal is above the user-programmed level.  
The outcome of this test is available at the PECL  
Also a DC offset voltage of more than a few millivolts  
1998 Aug 18  
6
Philips Semiconductors  
Objective specification  
SDH/SONET STM4/OC12 postamplifiers  
TZA3024T; TZA3024U  
should be avoided, since the internal DC offset  
compensation circuit has a limited correction range.  
Since the voltage on pin RSET is held constant at 1.5 V  
below VCCA, the current flowing into this pin will be:  
1.5  
RDETECT  
If AC coupling is used to remove any DC compatibility  
requirement, the coupling capacitors must be large  
enough to pass the lowest input frequency of interest.  
For example, 1 nF coupling capacitors react with the  
internal 4.5 kΩ input bias resistors to yield a lower −3 dB  
frequency of 35 kHz. This then sets a limit on the  
maximum number of consecutive pulses that can be  
sensed accurately at the system data rate. Capacitor  
tolerance and resistor variation must be included for an  
accurate calculation.  
IRSET  
=
[A ]  
(2)  
-----------------------  
Combining these two formulas results in a general formula  
to calculate RDETECT for a given input signal  
level-detection:  
750  
RDETECT  
=
[Ω ]  
(3)  
-----------------------------------------  
(VDIN – VDINQ  
)
In this formula, VDIN and VDINQ are in Volts.  
Example: Detection should occur if the differential voltage  
of the input signals drops below 4 mV(p-p). In this case,  
a reference current of 0.002 × 0.004 = 8 µA should flow  
into pin RSET. This can be set using a current source or  
simply by connecting a resistor of the appropriate value.  
The resistor must be connected between VCCA and  
pin RSET. In this example the resistor would be:  
DC-offset compensation  
A control loop connected between the inputs of buffer A3  
and amplifier A1 (see Fig.1) will keep the input of buffer A3  
at its toggle point in the absence of any input signal.  
Because of the active offset compensation which is  
integrated in the TZA3024, no external capacitor is  
required. The loop time constant determines the lower  
cut-off frequency of the amplifier chain, which is set at  
approximately 850 Hz.  
750  
0.004  
RDETECT  
=
= 187.5 kΩ  
----------------  
The hysteresis is fixed internally at 3 dB electrical. In the  
example above, a differential level below 4 mV(p-p) of the  
input signal will drive pin ST LOW, and an input signal level  
above 5.7 mV(p-p) will drive pin ST HIGH.  
Input signal level-detection  
The TZA3024 allows for user-programmable input signal  
level-detection and can automatically disable the switching  
of the PECL outputs if the input signal is below a set  
threshold level. This prevents the outputs from reacting to  
noise in the absence of a valid input signal, and insures  
that data will only be transmitted when the signal-to-noise  
ratio of the input signal is sufficient for low bit error rate  
system operation. Complementary PECL flags (ST and  
STQ) indicate whether the input signal is above or below  
the programmed threshold level.  
Since a JAM function is provided which forces the data  
outputs to a predetermined state (DOUT = LOW and  
DOUTQ = HIGH), the pins STQ and JAM can be  
connected to automatically disable the signal transmission  
when the chip senses that the input signal is below the  
programmed threshold level.  
The response time of the input signal level-detection circuit  
is determined by the time constant of the input capacitors,  
together with the filter time constant (1 µs internal plus the  
additional capacitor at pin CF).  
The input signal is amplified and rectified before being  
compared to a programmable threshold reference. A filter  
is included to prevent noise spikes from triggering the  
level-detector. This filter has a nominal 1 µs time constant  
and additional filtering can be achieved by using an  
external capacitor between pin CF and VCCA (the internal  
driving impedance nominally is 25 kΩ). The resultant  
signal is then compared to a threshold current through  
pin RSET (see Fig.6). This current can be set by  
PECL output circuits  
The output circuit of ST and STQ is given in Fig.7.  
The output circuit of DOUT and DOUTQ is given in Fig.8.  
Some PECL termination schemes are given in Fig.9.  
connecting an external resistor RDETECT between  
pin RSET and VCCA, or by forcing a current into pin RSET.  
The relationship between the threshold current and the  
detected input voltage is approximately:  
IRSET = 0.002 × (VDIN – VDINQ) [A]  
(1)  
1998 Aug 18  
7
Philips Semiconductors  
Objective specification  
SDH/SONET STM4/OC12 postamplifiers  
TZA3024T; TZA3024U  
V
V
CC  
V
O(max)  
V
OQH  
V
OH  
o(p-p)  
V
OQL  
V
OO  
V
OL  
V
O(min)  
MGR243  
Fig.4 Logic level symbol definitions for PECL.  
V
CC  
DIN  
DINQ  
4.5 kΩ  
4.5 kΩ  
330 µA  
330 µA  
2.55 V  
MGR244  
Fig.5 Data input circuit DIN and DINQ.  
8
1998 Aug 18  
Philips Semiconductors  
Objective specification  
SDH/SONET STM4/OC12 postamplifiers  
TZA3024T; TZA3024U  
V
handbook, halfpage  
CC  
RSET  
1.5 V  
MGR245  
Fig.6 Level-detect input circuit RSET.  
V
handbook, halfpage  
CC  
V
V
LOW  
HIGH  
ST, STQ  
10 kΩ  
MGR246  
Fig.7 PECL output circuit ST and STQ.  
V
handbook, halfpage  
CC  
105 Ω  
105 Ω  
DOUT  
DOUTQ  
0.5 mA  
9 mA  
0.5 mA  
MGR247  
Fig.8 PECL output circuit DOUT and DOUTQ.  
9
1998 Aug 18  
Philips Semiconductors  
Objective specification  
SDH/SONET STM4/OC12 postamplifiers  
TZA3024T; TZA3024U  
V
− 2 V  
CC  
R1 = 50 Ω  
R1 = 50 Ω  
V
V
O
V
I
Z
= 50 Ω  
o
V
IQ  
MGR248  
OQ  
V
= 3.3 V  
CC  
R1 = 127 Ω  
R1 = 127 Ω  
V
O
V
I
Z
= 50 Ω  
o
V
IQ  
V
OQ  
R2 = 82.5 Ω  
R2 = 82.5 Ω  
GND  
MGR249  
V
= 5.0 V  
CC  
R1 = 83.3 Ω  
R1 = 83.3 Ω  
V
V
O
V
I
Z
= 50 Ω  
o
V
IQ  
OQ  
R2 = 125 Ω  
R2 = 125 Ω  
GND  
MGR250  
Fig.9 PECL output termination schemes.  
10  
1998 Aug 18  
Philips Semiconductors  
Objective specification  
SDH/SONET STM4/OC12 postamplifiers  
TZA3024T; TZA3024U  
LIMITING VALUES  
In accordance with the Absolute Maximum Rating System (IEC 134).  
SYMBOL  
VCC  
Vn  
PARAMETER  
CONDITIONS  
MIN.  
−0.5  
MAX.  
+6  
UNIT  
supply voltage  
DC voltage  
V
note 1  
pins 4 and 5 (7 and 8): DIN and DINQ  
pin 7 (13): CF  
−0.5  
−0.5  
−0.5  
V
CC + 0.5  
CC + 0.5  
V
V
V
V
V
pin 8 (16): JAM  
VCC + 0.5  
VCC + 0.5  
pins 9, 10, 12 and 13 (17, 18, 23 and 24):  
STQ, ST, DOUTQ and DOUT  
VCC − 2  
pin 15 (29): Vref  
pin 16 (30): RSET  
DC current  
−0.5  
−0.5  
+3.2  
V
V
VCC + 0.5  
In  
note 1  
pin 4 and 5 (7 and 8): DIN and DINQ  
pin 7 (13): CF  
−1  
+1  
mA  
mA  
mA  
mA  
−1  
+1  
pin 8 (16): JAM  
−1  
+1  
pins 9, 10, 12 and 13 (17, 18, 23 and 24):  
STQ, ST, DOUTQ and DOUT  
−25  
+10  
pin 15 (29): Vref  
−2  
−2  
−
+2.5  
+2  
mA  
mA  
mW  
°C  
pin 16 (30): RSET  
Ptot  
Tstg  
Tj  
total power dissipation  
storage temperature  
junction temperature  
operating ambient temperature  
tbf  
−65  
−
+150  
150  
+85  
°C  
Tamb  
−40  
°C  
Note  
1. The numbers in brackets refer to the pad numbers of the naked die version.  
THERMAL CHARACTERISTICS  
SYMBOL  
PARAMETER  
VALUE  
UNIT  
Rth(j-s)  
Rth(j-a)  
thermal resistance from junction to solder point  
thermal resistance from junction to ambient  
tbf  
tbf  
K/W  
K/W  
1998 Aug 18  
11  
Philips Semiconductors  
Objective specification  
SDH/SONET STM4/OC12 postamplifiers  
TZA3024T; TZA3024U  
CHARACTERISTICS  
For typical values Tamb = 25 °C and VCC = 3.3 V; minimum and maximum values are valid over the entire ambient  
temperature range and supply voltage range; all voltages measured with respect to ground; unless otherwise specified.  
SYMBOL  
Supplies  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNIT  
VCC  
ICCD  
ICCA  
Ptot  
Tj  
digital supply voltage  
digital supply current  
3
−
−
−
3.3  
5.5  
27  
22  
V
note 1  
18  
15  
110  
−
mA  
mA  
mW  
°C  
analog supply current  
total power dissipation  
junction temperature  
note 1  
270  
−40  
−40  
+120  
+85  
Tamb  
operating ambient temperature  
+25  
°C  
Inputs: DIN and DINQ  
Vi(se)(p-p) input signal voltage  
0.002  
0.004  
−
−
1.0  
2.0  
V
V
single-ended (peak-to-peak  
value)  
Vi(dif)(p-p)  
input signal voltage differential  
(peak-to-peak value)  
VI  
absolute input signal voltage  
2.1  
2.55  
VCCA + 0.5  
50  
V
VIO(eq)  
equivalent input signal offset  
voltage  
−
−
µV  
VIO(cor)  
input offset voltage correction  
range  
note 2  
−5  
−
+5  
mV  
Ri  
input resistance  
single-ended  
single-ended  
note 3  
2.9  
−
4.5  
−
7.6  
2.5  
115  
kΩ  
pF  
µV  
Ci  
input capacitance  
Vn(i)(rms)  
equivalent input RMS noise  
voltage  
−
90  
Input signal level-detect: RSET  
Iref  
input reference current  
input reference voltage  
note 4  
5
−
60  
µA  
V
Vref  
referenced to VCCA  
−1.55  
−1.5  
−
−1.45  
12  
Vth(p-p)  
programmability (single-ended,  
peak-to-peak value)  
Vi = 200 kHz square  
wave  
2
mV  
hys  
RF  
tF  
hysteresis  
electrically measured  
2
3
4
dB  
kΩ  
µs  
filter resistance  
filter time constant  
14  
0.5  
25  
1.0  
41  
2.0  
CF = 0  
1998 Aug 18  
12  
Philips Semiconductors  
Objective specification  
SDH/SONET STM4/OC12 postamplifiers  
TZA3024T; TZA3024U  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNIT  
PECL outputs: DOUT and DOUTQ  
VOL  
VOH  
tr  
LOW-level output voltage  
HIGH-level output voltage  
output rise time  
RL = 50 Ω to VCC − 2 V  
RL = 50 Ω to VCC − 2 V  
20% to 80%  
V
CC − 1840 −  
CC − 1100 −  
V
V
CC − 1620 mV  
CC − 900 mV  
V
−
200  
300  
250  
30  
ps  
tf  
output fall time  
80% to 20%  
−
140  
−
ps  
tw(p-p)  
f-3dB(l)  
f-3dB(h)  
pulse width distortion  
low frequency −3 dB point  
high frequency −3 dB point  
−
ps  
−
0.85  
620  
1.5  
770  
kHz  
MHz  
460  
PECL outputs: ST and STQ  
VOL  
VOH  
tr  
LOW-level output voltage  
RL = 50 Ω to VCC − 2 V  
RL = 50 Ω to VCC − 2 V  
20% to 80%  
V
V
−
−
CC − 1840 −  
CC − 1100 −  
V
CC − 1620 mV  
CC − 900 mV  
HIGH-level output voltage  
output rise time  
V
−
−
600  
200  
ns  
ns  
tf  
output fall time  
80% to 20%  
PECL input: JAM  
VIL  
LOW-level input voltage  
−
−
V
CC − 1490 mV  
VIH  
HIGH-level input voltage  
JAM input current  
V
CC − 1165 −  
−
mV  
Ii(JAM)  
note 5  
note 6  
−10  
−
+10  
µA  
Reference voltage output: Vref  
Vref  
reference voltage  
1.165  
1.20  
1.235  
V
Notes  
1. DOUT, DOUTQ, ST and STQ outputs are left unconnected.  
2. If the input is DC coupled, the preceding amplifier’s output offset voltage should not exceed these limits, in order to  
avoid malfunctioning of the DC offset compensation circuit.  
total output RMS noise  
low frequency gain  
3. Input RMS noise =  
------------------------------------------------------------  
4. The reference currents can be set by a resistor between VCCA and pin RSET. The corresponding input signal  
level-detect range is from 2 to 12 mV(p-p) single-ended. See Section “Input signal level-detection” for detailed  
information.  
5. Internal pull-down resistor of 500 kΩ to DGND.  
6. Internal series resistor of 1 kΩ.  
1998 Aug 18  
13  
Philips Semiconductors  
Objective specification  
SDH/SONET STM4/OC12 postamplifiers  
TZA3024T; TZA3024U  
APPLICATION INFORMATION  
V
CC  
100 nF  
100 nF  
180 kΩ  
RSET  
16  
CF  
V
V
CCD  
V
ref  
CCA  
7
15  
(29)  
14  
(27, 28)  
6
(30)  
(13)  
(11, 12)  
10 nF  
10 nF  
DIN  
DOUT  
4 (7)  
(24) 13  
data in  
data out  
TZA3024  
DINQ  
DOUTQ  
5 (8)  
(23) 12  
(3, 4, 6, 9) (1, 14) (16)  
(17)  
9
(18) (19, 20, 22, 25)  
10 11  
3
1
8
AGND SUB JAM  
STQ ST  
DGND  
level-detect  
status  
1 kΩ  
50 Ω  
50 Ω  
V
− 2 V  
CC  
MBK854  
The numbers in brackets refer to the pad numbers of the naked die version.  
Fig.10 Application diagram.  
1998 Aug 18  
14  
Philips Semiconductors  
Objective specification  
SDH/SONET STM4/OC12 postamplifiers  
TZA3024T; TZA3024U  
BM8K5  
e
1998 Aug 18  
15  
Philips Semiconductors  
Objective specification  
SDH/SONET STM4/OC12 postamplifiers  
TZA3024T; TZA3024U  
PACKAGE OUTLINE  
SO16: plastic small outline package; 16 leads; body width 3.9 mm  
SOT109-1  
D
E
A
X
v
c
y
H
M
A
E
Z
16  
9
Q
A
2
A
(A )  
3
A
1
pin 1 index  
θ
L
p
L
1
8
e
w
M
detail X  
b
p
0
2.5  
scale  
5 mm  
DIMENSIONS (inch dimensions are derived from the original mm dimensions)  
A
(1)  
(1)  
(1)  
UNIT  
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.  
0.25  
0.10  
1.45  
1.25  
0.49  
0.36  
0.25  
0.19  
10.0  
9.8  
4.0  
3.8  
6.2  
5.8  
1.0  
0.4  
0.7  
0.6  
0.7  
0.3  
mm  
1.27  
0.050  
1.05  
0.041  
1.75  
0.25  
0.01  
0.25  
0.01  
0.25  
0.1  
8o  
0o  
0.010 0.057  
0.004 0.049  
0.019 0.0100 0.39  
0.014 0.0075 0.38  
0.16  
0.15  
0.244  
0.228  
0.039 0.028  
0.016 0.020  
0.028  
0.012  
inches  
0.069  
0.01 0.004  
Note  
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
EIAJ  
95-01-23  
97-05-22  
SOT109-1  
076E07S  
MS-012AC  
1998 Aug 18  
16  
Philips Semiconductors  
Objective specification  
SDH/SONET STM4/OC12 postamplifiers  
TZA3024T; TZA3024U  
SOLDERING  
Introduction  
Wave soldering  
Wave soldering techniques can be used for all SO  
packages if the following conditions are observed:  
There is no soldering method that is ideal for all IC  
packages. Wave soldering is often preferred when  
through-hole and surface mounted components are mixed  
on one printed-circuit board. However, wave soldering is  
not always suitable for surface mounted ICs, or for  
printed-circuits with high population densities. In these  
situations reflow soldering is often used.  
• A double-wave (a turbulent wave with high upward  
pressure followed by a smooth laminar wave) soldering  
technique should be used.  
• The longitudinal axis of the package footprint must be  
parallel to the solder flow.  
• The package footprint must incorporate solder thieves at  
the downstream end.  
This text gives a very brief insight to a complex technology.  
A more in-depth account of soldering ICs can be found in  
our “Data Handbook IC26; Integrated Circuit Packages”  
(order code 9398 652 90011).  
During placement and before soldering, the package must  
be fixed with a droplet of adhesive. The adhesive can be  
applied by screen printing, pin transfer or syringe  
dispensing. The package can be soldered after the  
adhesive is cured.  
Reflow soldering  
Reflow soldering techniques are suitable for all SO  
packages.  
Maximum permissible solder temperature is 260 °C, and  
maximum duration of package immersion in solder is  
10 seconds, if cooled to less than 150 °C within  
Reflow soldering requires solder paste (a suspension of  
fine solder particles, flux and binding agent) to be applied  
to the printed-circuit board by screen printing, stencilling or  
pressure-syringe dispensing before package placement.  
6 seconds. Typical dwell time is 4 seconds at 250 °C.  
A mildly-activated flux will eliminate the need for removal  
of corrosive residues in most applications.  
Several techniques exist for reflowing; for example,  
thermal conduction by heated belt. Dwell times vary  
between 50 and 300 seconds depending on heating  
method. Typical reflow temperatures range from  
215 to 250 °C.  
Repairing soldered joints  
Fix the component by first soldering two diagonally-  
opposite end leads. Use only a low voltage soldering iron  
(less than 24 V) applied to the flat part of the lead. Contact  
time must be limited to 10 seconds at up to 300 °C. When  
using a dedicated tool, all other leads can be soldered in  
one operation within 2 to 5 seconds between  
270 and 320 °C.  
Preheating is necessary to dry the paste and evaporate  
the binding agent. Preheating duration: 45 minutes at  
45 °C.  
1998 Aug 18  
17  
Philips Semiconductors  
Objective specification  
SDH/SONET STM4/OC12 postamplifiers  
TZA3024T; TZA3024U  
DEFINITIONS  
Data sheet status  
Objective specification  
Preliminary specification  
Product specification  
This data sheet contains target or goal specifications for product development.  
This data sheet contains preliminary data; supplementary data may be published later.  
This data sheet contains final product specifications.  
Limiting values  
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or  
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation  
of the device at these or at any other conditions above those given in the Characteristics sections of the specification  
is not implied. Exposure to limiting values for extended periods may affect device reliability.  
Application information  
Where application information is given, it is advisory and does not form part of the specification.  
LIFE SUPPORT APPLICATIONS  
These products are not designed for use in life support appliances, devices, or systems where malfunction of these  
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for  
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such  
improper use or sale.  
1998 Aug 18  
18  
Philips Semiconductors  
Objective specification  
SDH/SONET STM4/OC12 postamplifiers  
TZA3024T; TZA3024U  
NOTES  
1998 Aug 18  
19  
Philips Semiconductors – a worldwide company  
Argentina: see South America  
Middle East: see Italy  
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,  
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,  
Tel. +61 2 9805 4455, Fax. +61 2 9805 4466  
Tel. +31 40 27 82785, Fax. +31 40 27 88399  
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 160 1010,  
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,  
Fax. +43 160 101 1210  
Tel. +64 9 849 4160, Fax. +64 9 849 7811  
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,  
Norway: Box 1, Manglerud 0612, OSLO,  
220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773  
Tel. +47 22 74 8000, Fax. +47 22 74 8341  
Belgium: see The Netherlands  
Brazil: see South America  
Pakistan: see Singapore  
Philippines: Philips Semiconductors Philippines Inc.,  
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,  
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474  
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,  
51 James Bourchier Blvd., 1407 SOFIA,  
Tel. +359 2 689 211, Fax. +359 2 689 102  
Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,  
Tel. +48 22 612 2831, Fax. +48 22 612 2327  
Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,  
Tel. +1 800 234 7381  
Portugal: see Spain  
Romania: see Italy  
China/Hong Kong: 501 Hong Kong Industrial Technology Centre,  
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,  
Tel. +852 2319 7888, Fax. +852 2319 7700  
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,  
Tel. +7 095 755 6918, Fax. +7 095 755 6919  
Colombia: see South America  
Czech Republic: see Austria  
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,  
Tel. +65 350 2538, Fax. +65 251 6500  
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,  
Tel. +45 32 88 2636, Fax. +45 31 57 0044  
Slovakia: see Austria  
Slovenia: see Italy  
Finland: Sinikalliontie 3, FIN-02630 ESPOO,  
Tel. +358 9 615800, Fax. +358 9 61580920  
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,  
2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,  
Tel. +27 11 470 5911, Fax. +27 11 470 5494  
France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,  
Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427  
South America: Al. Vicente Pinzon, 173, 6th floor,  
04547-130 SÃO PAULO, SP, Brazil,  
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,  
Tel. +49 40 23 53 60, Fax. +49 40 23 536 300  
Tel. +55 11 821 2333, Fax. +55 11 821 2382  
Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS,  
Spain: Balmes 22, 08007 BARCELONA,  
Tel. +30 1 4894 339/239, Fax. +30 1 4814 240  
Tel. +34 93 301 6312, Fax. +34 93 301 4107  
Hungary: see Austria  
Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,  
Tel. +46 8 5985 2000, Fax. +46 8 5985 2745  
India: Philips INDIA Ltd, Band Box Building, 2nd floor,  
254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,  
Tel. +91 22 493 8541, Fax. +91 22 493 0966  
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,  
Tel. +41 1 488 2741 Fax. +41 1 488 3263  
Indonesia: PT Philips Development Corporation, Semiconductors Division,  
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,  
Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080  
Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,  
TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874  
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,  
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,  
Tel. +66 2 745 4090, Fax. +66 2 398 0793  
Ireland: Newstead, Clonskeagh, DUBLIN 14,  
Tel. +353 1 7640 000, Fax. +353 1 7640 200  
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,  
Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,  
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007  
Tel. +90 212 279 2770, Fax. +90 212 282 6707  
Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,  
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,  
20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557  
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461  
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,  
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,  
TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077  
MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421  
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,  
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,  
Tel. +82 2 709 1412, Fax. +82 2 709 1415  
Tel. +1 800 234 7381  
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,  
Tel. +60 3 750 5214, Fax. +60 3 757 4880  
Uruguay: see South America  
Vietnam: see Singapore  
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,  
Tel. +9-5 800 234 7381  
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,  
Tel. +381 11 625 344, Fax.+381 11 635 777  
For all other countries apply to: Philips Semiconductors,  
Internet: http://www.semiconductors.philips.com  
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,  
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825  
© Philips Electronics N.V. 1998  
SCA60  
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.  
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed  
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license  
under patent- or other industrial or intellectual property rights.  
Printed in The Netherlands  
425102/200/01/pp20  
Date of release: 1998 Aug 18  
Document order number: 9397 750 04086  
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