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CYM9261A-50C

型号：

CYM9261A-50C

品牌：

CYPRESS[ CYPRESS ]

页数：

11 页

PDF大小：

249 K

下载PDF手册
1CYM9262A/B  
fax id: 2042  
CYM9260  
CYM9261A/B  
CYM9262A/B  
CYM9263  
PRELIMINARY  
64K x 72 SRAM Module  
128K x 72 SRAM Module  
256K x 72 SRAM Module  
512K x 72 SRAM Module  
(9262B, 9263) SRAM’s in plastic surface mount packages on  
an epoxy laminate board with pins. The modules are designed  
to be incorporated into large memory arrays.  
Features  
• Operates at 50 MHz.  
• Uses 64K x 18/ 128K x 18 or 256K x 18 highperformance  
synchronous SRAMs.  
• 168-position Angled DIMM from Amp p/n 179508-2  
• 3.3V inputs/data outputs  
The module is configured as either one or two banks, where  
each bank has seperate chip select and output enable con-  
trols. Seperate clocks are provided for every pair of SRAMs’s.  
Multiple ground pins and on-board de-coupling capacitors en-  
sure high performance with maximum noise immunity.  
Functional Description  
All components on the cache modules are surface mounted  
on a multi-layer epoxy laminate (FR-4) substrate. The contact  
pins are plated with 150 micro-inches of nickel covered by 30  
micro-inches of gold flash.  
The CYM9260, CYM9261, CYM9262 and the CYM9263 are  
high-performance synchronous memory modules organized  
as 64K(9260), 128K(9261), 256K(9262) or 512K(9263) by 72  
bits. These modules are constructed from either 64K x 18  
(9260, 9261A), 128K x 18(9261B, 9262A) or 256K x 18  
LogicBlockDiagram- CYM9260/CYM9261A  
Vcc3  
R2  
Vcc3  
R4  
A[15:0]  
WE[7:0]  
DQ[0:15]  
DQP[0:1]  
R3  
ADSP  
A15:0  
OE[0:1]  
ADSP  
OE  
OE0  
D[0:63]  
DP[0:7]  
CE[0:1]  
CS0  
CS  
WEH  
WEL  
R1  
CLK  
ADSC  
BANK 0  
CLK[0:3]  
D[0:15]  
DQ[0:1]  
A15:0  
ADSP  
OE  
R1, R2, R3, R4 are Optional resistors.  
R1, R2,R4 are mounted for access using ADSC  
OE1  
R3, R2,R4 are mounted for access using ADSP  
CS1  
CS  
WEH  
WEL  
PD  
PD  
1
0
ADSC  
CLK  
GND NC  
BANK 0  
64Kx72  
NC GND  
BANK 0 & 1  
BANK 1  
128KX72  
9260-1  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
August 19, 1997  
CYM9260  
CYM9261A/B  
CYM9262A/B  
CYM9263  
PRELIMINARY  
LogicBlockDiagram- CYM9261B/CYM9262A  
Vcc3  
R2  
Vcc3  
R4  
A[16:0]  
WE[0:7]  
ADSP  
DQ[0:15]  
DQP[0:1]  
R3  
A16:0  
OE[0:1]  
ADSP  
OE  
OE0  
D[0:63]  
DP[0:7]  
CE[0:1]  
CE0  
CS  
WEH  
WEL  
R1  
CLK  
ADSC  
BANK 0  
CLK[0:3]  
D[0:15]  
DQ[0:1]  
A16:0  
ADSP  
OE  
R1, R2, R3, R4 are Optional resistors.  
R1, R2, R4 are mounted for access using ADSC  
R3, R2, R4 are mounted for access using ADSP  
OE1  
CE1  
CS  
WEH  
WEL  
PD  
PD  
1
0
ADSC  
CLK  
NC  
GND BANK 0  
128Kx72  
256KX72  
GND GND  
BANK 0 & 1  
BANK 1  
9260-2  
2
CYM9260  
CYM9261A/B  
CYM9262A/B  
CYM9263  
PRELIMINARY  
LogicBlockDiagram- CYM9262B/CYM9263  
Vcc3  
R2  
Vcc3  
R4  
A[17:0]  
WE[0:7]  
ADSP  
DQ[0:15]  
DQP[0:1]  
R3  
A17:0  
OE[0:1]  
ADSP  
OE  
OE0  
D[0:63]  
DP[0:7]  
CE[0:1]  
CE0  
CS  
WEH  
WEL  
CLK  
ADSC  
R1  
BANK 0  
CLK[0:3]  
D[0:15]  
DQ[0:1]  
A17:0  
ADSP  
OE  
R1, R2, R3, R4 are Optional resistors.  
R1, R2, R4 are mounted for access using ADSC  
R3, R2, R4 are mounted for access using ADSP  
OE1  
CE1  
CS  
WEH  
WEL  
PD  
PD  
1
0
ADSC  
CLK  
GND GND BANK 0  
256Kx72  
512KX72  
NC NC  
BANK 0 & 1  
BANK 1  
9260-3  
Selection Guide  
Synchronous Cache Module  
CYM9260-50 CYM9261A-50 CYM9261B-50 CYM9262A-50 CYM9262B-50 CYM9263-50  
Part Number  
Cache Size  
64 K x 72  
128 K x 72  
8 of 64K x 18  
50  
128 K x 72  
256 K x 72  
256 K x 72  
512 K x 72  
SRAM’s Used  
4 of 64K x 18  
4 of 128K x 18 8 of 128K x 18 4 of 256K x 18 8 of 256K x 18  
System Clock (MHz) 50  
Data t 10.3 ns  
50  
50  
50  
50  
10.3 ns  
10.3 ns  
10.3 ns  
10.3 ns  
10.3 ns  
CDV  
3
CYM9260  
CYM9261A/B  
CYM9262A/B  
CYM9263  
PRELIMINARY  
Pin Configuration  
Dual Read-Out SIMM (DIMM)  
Top View  
GND  
1
2
3
4
5
6
7
85  
86  
GND  
DP7  
D61  
GND  
D59  
D57  
D63  
D62  
VCC3  
D60  
D58  
GND  
D56  
D55  
87  
88  
89  
90  
91  
92  
93  
94  
GND  
8
DP6  
9
D54  
10  
GND  
VCC3  
D53  
D51  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
95  
96  
97  
98  
99  
D52  
D50  
GND  
D48  
D47  
GND  
D45  
D43  
GND  
D41  
GND  
D49  
DP5  
VCC3  
100  
101  
102  
103  
104  
105  
106  
107  
108  
109  
110  
111  
112  
113  
114  
115  
116  
117  
118  
119  
120  
121  
122  
123  
124  
D46  
D44  
GND  
D42  
D40  
GND  
D39  
D37  
GND  
D35  
D33  
GND  
CLK3  
GND  
DP3  
D30  
VCC3  
D28  
DP  
4
VCC3  
D38  
D36  
GND  
D34  
D32  
GND  
CLK2  
GND  
D31  
D29  
GND  
D27  
D26  
GND  
D24  
D25  
GND  
DP2  
37  
38  
39  
40  
D23  
D22  
VCC3  
GND  
D21  
D20  
D19  
GND  
D17  
D18  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
75  
77  
78  
79  
80  
81  
82  
83  
84  
125  
126  
127  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
139  
140  
141  
142  
143  
144  
145  
146  
147  
148  
149  
150  
151  
152  
153  
154  
155  
156  
157  
158  
159  
GND  
D16  
D15  
GND  
D13  
D11  
GND  
D9  
DP0  
VCC3  
D6  
D4  
GND  
D2  
DP1  
VCC3  
D14  
D12  
GND  
D10  
D8  
GND  
D7  
D5  
GND  
D3  
D1  
D0  
VCC3  
GND  
PD1  
PD0  
NC  
GND  
A16  
A14  
GND  
A12  
A10  
GND  
A8  
A6  
VCC3  
A4  
A2  
A0  
GND  
CLK1  
GND  
WE7  
WE5  
GND  
A17  
GND  
A15  
A13  
VCC3  
A11  
A9  
GND  
A7  
A5  
GND  
A3  
A1  
ADSP  
GND  
CLK0  
GND  
WE6  
WE4  
GND  
WE2  
160  
161  
162  
163  
164  
165  
166  
167  
168  
WE3  
WE0  
WE1  
VCC3  
GND  
OE0  
CE0  
GND  
OE1  
CE1  
GND  
9260-4  
4
CYM9260  
CYM9261A/B  
CYM9262A/B  
CYM9263  
PRELIMINARY  
Pin Definitions  
Signal  
Description  
V
3V Supply  
CC3  
GND  
Ground  
A[17:0]  
OE[1:0]  
WE[7:0]  
CS[1:0]  
Addresses from processor  
Output Enables for the two banks  
Byte Write Enables  
Chip Select for the two banks  
Presence Detect output pins  
Data lines from processor  
Data Parity lines from processor  
Clock lines to the module  
Address Strobe from the processor  
Signal not connected on module  
Reserved  
PD –PD  
0
1
D[63:0]  
DP[7:0]  
CLK[0:3]  
ADSP  
NC  
RSVD  
Presence Detect Pins  
PD  
PD  
0
1
CYM9260 - 64K x 72  
CYM9261 - 128K x 72  
CYM9262 - 256K x 72  
CYM9263 - 512K x 72  
GND  
NC  
NC  
GND  
GND  
NC  
GND  
NC  
5
CYM9260  
CYM9261A/B  
CYM9262A/B  
CYM9263  
PRELIMINARY  
DC Input Voltage ........................................... –0.5V to +4.6V  
Output Current into Outputs (LOW)............................. 20 mA  
Maximum Ratings  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
Operating Range  
Storage Temperature ................................. –55°C to +125°C  
Ambient  
Ambient Temperature  
with Power Applied ........................................ –0°C to +70°C  
Range  
Temperature  
V
CC  
Commercial  
0°C to +70°C  
3.3V ± 5%  
3.3V Supply Voltage to Ground Potential...... –0.5V to +4.5V  
DC Voltage Applied to Outputs  
in High Z State .............................................. –0.5V to +4.6V  
Electrical Characteristics Over the Operating Range  
Parameter  
Description  
Input HIGH Voltage  
Input LOW Voltage  
Output HIGH Voltage  
Output LOW Voltage  
Test Condition  
Min.  
2.2  
Max.  
V + 0.3  
CC  
Unit  
V
V
IH  
V
V
V
–0.3  
2.4  
0.8  
V
IL  
V
V
V
V
=Min. I = −4 mA  
V
OH  
CC  
CC  
CC  
CC  
OH  
=Min. I = 8 mA  
0.4  
V
OL  
OL  
I
I
V
V
Operating Supply Current  
Operating Supply Current  
=Max., I  
=Max., I  
=0 mA, f=f  
=0 mA, f=f  
=1/t  
=1/t  
500  
mA  
mA  
CC (9260)  
CC (9261)  
CC  
CC  
OUT  
OUT  
MAX  
RC  
RC  
500(64K)  
MAX  
1000(128K)  
I
I
V
V
Operating Supply Current  
Operating Supply Current  
V
V
=Max., I  
=Max., I  
=0 mA, f=f  
=0 mA, f=f  
=1/t  
=1/t  
2000(128K)  
1200(256K)  
mA  
mA  
CC (9262)  
CC (9263)  
CC  
CC  
CC  
CC  
OUT  
OUT  
MAX  
MAX  
RC  
RC  
6000(256K)  
Capacitance[1]  
Parameter  
Description  
Test Conditions  
Max.  
9260  
9261  
Max.  
Unit  
C
Address Input Capacitance  
Control Input Capacitance  
Input/Output Capacitance  
Clock Capacitance  
T = 25°C, f = 1 MHz,  
24  
pF  
pF  
A
A
V
= 5.0V  
CC  
48 (64Kx18)  
14 (128Kx18)  
9262  
28(128K x 18)  
20(256K x 18)  
pF  
9263  
9260  
9261  
40(256K x 18)  
24  
pF  
pF  
pF  
C
T = 25°C, f = 1 MHz,  
A
I
V
= 5.0V  
CC  
48(64Kx18)  
16(128Kx18)  
9262  
32(128K x 18)  
20(256K x 18)  
pF  
9263  
9260  
9261  
40(256K x 18)  
9
pF  
pF  
pF  
C
T = 25°C, f = 1 MHz,  
A
O
V
= 5.0V  
CC  
18(64Kx18)  
5(128Kx18)  
9262  
10(128K x 18)  
8(256K x 18)  
pF  
9263  
9260  
9261  
16(256K x 18)  
6
pF  
pF  
pF  
C
T = 25°C, f = 1 MHz,  
A
CLK  
V
= 5.0V  
CC  
12(64Kx18)  
3(128Kx18)  
9262  
9262  
6(128K x 18)  
5(256K x 18)  
pF  
pF  
10(256K x 18)  
Note:  
1. Tested initially and after any design or process changes that may affect these parameters.  
6
CYM9260  
CYM9261A/B  
CYM9262A/B  
CYM9263  
PRELIMINARY  
AC Test Loads and Waveforms[3]  
R1  
V
CCQ  
OUTPUT  
ALL INPUT PULSES  
OUTPUT  
3.3V  
GND  
90%  
R = 50 Ω  
L
90%  
10%  
R2  
10%  
5 pF  
V =1.5V  
L
INCLUDING  
JIGAND  
≤ 3 ns  
≤ 3 ns  
[2]  
9260-5  
SCOPE  
(a)  
(b)  
9660-6  
Switching Characteristics Over the Operating Range  
CYM9260  
CYM9261  
CYM9262  
CYM963  
Parameter  
Description  
Min Max Min Max Min. Max. Min. Max. Unit  
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Clock Cycle Time  
Clock HIGH  
12  
4
12  
4
12  
4
12  
4
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
CYC  
CH  
Clock LOW  
4
4
4
4
CL  
Address Set-Up Before CLK Rise  
Address Hold After CLK Rise  
Data Output Valid After CLK Rise  
Data Output Hold After CLK Rise  
ADSP, ADSC Set-Up Before CLK Rise  
ADSP, ADSC Hold After CLK Rise  
WH, WL Set-Up Before CLK Rise  
WH, WL Hold After CLK Rise  
Data Input Set-Up Before CLK Rise  
Data Input Hold After CLK Rise  
Chip Select Set-Up  
3.1  
0.5  
3.1  
0.5  
3.1  
0.5  
3.1  
0.5  
AS  
AH  
10.3  
10.3  
10.3  
10.3  
CDV  
DOH  
ADS  
ADSH  
WES  
WEH  
DS  
3
3
3
3
3.1  
0. 5  
3.1  
0.5  
3.3  
0.5  
3.1  
0.5  
3.1  
0.5  
3.1  
0.5  
3.3  
0.5  
3.1  
0.5  
3.1  
0.5  
3.1  
0.5  
3.3  
0.5  
3.1  
0.5  
3.1  
0.5  
3.1  
0.5  
3.3  
0.5  
3.1  
0.5  
DH  
CSS  
CSH  
EOZ  
EOV  
Chip Select Hold After CLK Rise  
[4]  
OE HIGH to Output High Z  
7
7
7
7
OE LOW to Output Valid  
7
7
7
7
Notes:  
2. Resistor values for VCCQ=3.3V are R1= 317Ω and R2= 351 Ω.  
3. Unless otherwise noted, test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output  
loading of the specified IOL/IOH and load capacitance. Shown in (a) and (b) of AC test loads. All measurements are made at room temperature.  
4. tEOZ is specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 500 mV from steady-state voltage.  
7
CYM9260  
CYM9261A/B  
CYM9262A/B  
CYM9263  
PRELIMINARY  
Switching Waveforms  
[5]  
Single Read  
t
t
CL  
t
CYC  
CH  
CLK  
CS  
t
t
CSH  
CSS  
t
AS  
t
AH  
ADDRESS  
[6]  
t
t
ADSH  
ADS  
ADSP  
or  
ADSC  
t
t
WEH  
WES  
[7]  
WH, WL  
t
t
DOH  
CDV  
DATA OUT  
9260-7  
Single Write Timing (Using ADSC)  
t
t
CL  
CH  
CLK  
CS  
t
t
CSH  
CSS  
t
AS  
t
AH  
ADDRESS  
t
t
ADSH  
ADS  
ADSC  
t
t
WEH  
WES  
WH, WL  
t
t
DH  
DS  
DATA IN  
DATA OUT  
t
EOZ  
OE  
9260-8  
Notes:  
5. OE is LOW throughout this operation.  
6. If ADSP is asserted while CS is HIGH, ADSP will be ignored.  
7. ADSP has no effect on ADV, WL, and WH if CS is HIGH.  
8
CYM9260  
CYM9261A/B  
CYM9262A/B  
CYM9263  
PRELIMINARY  
Switching Waveforms (continued)  
Single Write Cycle using ADSP  
t
t
CL  
CH  
CLK  
t
t
CSS  
CSH  
CS  
t
AS  
t
AH  
ADDRESS  
ADSP  
t
t
ADSH  
ADS  
t
t
WEH  
WES  
[7]  
WH, WL  
t
t
DH  
DS  
DATA IN  
DATA OUT  
t
EOZ  
OE  
9260-9  
Output (Controlled by OE)  
DATA OUT  
t
t
EOV  
EOZ  
OE  
9260-10  
Output Timing (Controlled by CS)  
CLK  
t
t
ADSH  
ADS  
t
t
ADS  
ADSH  
ADSC  
t
t
CSH  
CSS  
t
t
CSH  
CSS  
CS  
t
t
CSOZ  
CDV  
DATA OUT  
9260-11  
9
CYM9260  
CYM9261A/B  
CYM9262A/B  
CYM9263  
PRELIMINARY  
Switching Waveforms (continued)  
Output Timing (Controlled by WH/ WL)  
CLK  
t
ADSH  
t
t
t
ADSH  
ADS  
ADS  
ADSC and  
ADSP  
t
t
WES  
WEH  
WH, WL  
t
t
WEOZ  
WEOV  
DATA OUT  
9260-12  
Ordering Information  
Speed(  
MHz)  
Package  
Name  
Operating  
Range  
Ordering Code  
Package Type  
Description  
50  
CYM9260-50C  
CYM9261A-50C  
CYM9261B-50C  
CYM9262A-50C  
CYM9262B-50C  
CYM9263-50C  
PM43  
PM44  
PM43  
PM44  
PM43  
PM44  
168-Pin Dual-Readout SIMM (DIMM) Sync 64K x 72  
168-Pin Dual-Readout SIMM (DIMM) Sync 128K x 72  
168-Pin Dual-Readout SIMM (SIMM) Sync 128K x 72  
168-Pin Dual-Readout SIMM (DIMM) Sync 256K x 72  
168-Pin Dual-Readout SIMM (DIMM) Sync 256K x 72  
168-Pin Dual-Readout SIMM (DIMM) Sync 512K x 72  
Commercial  
Document #: 38-M-00082  
Package Diagrams  
168-Pin Single-Sided DIMM PM43  
10  
CYM9260  
CYM9261A/B  
CYM9262A/B  
CYM9263  
PRELIMINARY  
Package Diagrams (continued)  
168-Pin Dual Sided DIMM PM44  
© Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of anycircuitry other than circuitry embodied in a CypressSemiconductor product. Nor does it conveyor imply any license under patent or other rights. CypressSemiconductor does not authorize  
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.  
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