请登录

免费注册
全部商品
电子元器件
方案中心
工业品
PDF资料
购物车 0
上传BOM

产品分类

找货询价

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

QQ咨询

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

会员中心
购物车
技术支持

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

售后咨询

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

CYS25G0102DX-ATC

型号：

CYS25G0102DX-ATC

品牌：

CYPRESS[ CYPRESS ]

页数：

16 页

PDF大小：

203 K

下载PDF手册
G0102DX  
CYS25G0102DX  
PRELIMINARY  
SONET OC-48 Transceiver  
Features  
Functional Description  
• SONET OC-48 operation  
• Full Bellcore and ITU jitter compliance  
• 2.488-GBaud serial signaling rate  
• Multiple selectable loopback/loop-through modes  
• Single 155.52-MHz reference clock  
• Transmit FIFO for flexible data interface clocking  
• 16-bit parallel-to-serial conversion in transmit path  
• Serial to 16-bit parallel conversion in receive path  
• Synchronous parallel interface  
The CYS25G0102DX SONET OC-48 Transceiver is a commu-  
nications building block for high-speed SONET data commu-  
nications.It provides complete parallel-to-serial and serial-to-  
parallel conversion, clock generation, and clock and data  
recovery operations in a single chip, optimized for full SONET  
compliance.  
Transmit Path  
New data is accepted at the 16-bit parallel transmit interface  
at rate of 155.52 Mbits/second. This data is passed to a small  
integrated FIFO to allow flexible transfer of data between the  
SONET processor and the transmit serializer. As each 16-bit  
word is read from the transmit FIFO, it is serialized and sent  
out the high-speed differential line driver at a rate of 2.488  
Gbits/second.  
— LVPECL-compliant  
— HSTL-compliant  
• Internal transmit and receive PLLs  
• Differential CML serial input  
— 50 mV input sensitivity  
Receive Path  
As serial data is received at the differential line receiver, it is  
passed to a clock and data recovery (CDR) phase-locked loop  
(PLL), which extracts a precision low-jitter clock from the  
transitions in the data stream. This bit-rate clock is then used  
to sample the data stream and receive the data. Every 16 bit-  
times, a new word is presented at the receive parallel interface  
along with a 155.52-MHz synchronous clock.  
— Internal termination and DC-restoration  
• Differential CML serial output  
— Source matched for 50Ω transmission lines  
• Direct interface to standard fiber-optic modules  
• 0.550 watt typical power  
• 120-pin 14-mm × 14-mm TQFP  
• Standby power-saving mode for inactive loops  
• 0.25µ SiGe BiCMOS technology  
Parallel Interface  
The parallel I/O interface supports high-speed bus communi-  
cations using HSTL signaling levels to minimize both power  
consumption and board landscape. The HSTL outputs are  
capable of driving unterminated transmission lines of less than  
70 mm, and terminated 50Ω transmission lines of more than  
twice that length.  
• Control inputs are 3.3V tolerant  
The CYS25G0102DX transceiver’s parallel HSTL I/O can also  
be configured to operate at LVPECL signaling levels. This can  
be done externally by changing VDDQ, VREF, and creating a  
simple circuit at the termination of the transceiver’s parallel  
output interface and proper biasing of the parallel input  
interface.  
SONET Data  
Processor  
16  
CYS25G0102DX  
TXD[15:0]  
TXCLKI  
Transmit Data  
Interface  
FIFO_RST  
FIFO_ERR  
TXCLKO  
155.52 MHz  
BITS Time  
Reference  
2
REFCLK±  
16  
Host Bus  
Interface  
RXD[15:0]  
RXCLK  
Receive Data  
Interface  
IN+  
IN–  
SD  
OUT–  
OUT+  
RD+  
RD–  
SD  
TD–  
TD+  
Serial Data  
Serial Data  
LOOPTIME  
DIAGLOOP  
LOOPA  
Data & Clock  
Direction  
Control  
Optical  
XCVR  
Optical  
Fiber Links  
LINELOOP  
RESET  
PWRDN  
LOCKREF  
LFI  
Status and  
System  
Control  
Figure 1. CYS25G0102DX System Connections  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
Document #: 38-02026 Rev. *A  
Revised January 30, 2002  
PRELIMINARY  
CYS25G0102DX  
Clocking  
Multiple loopback and loop-through modes are available for  
both diagnostic and normal operation. For systems containing  
redundant SONET rings that are maintained in standby, the  
CYS25G0102DX may also be dynamically powered down to  
conserve system power.  
The source clock for the transmit data path is selectable from  
either the recovered clock or an external BITS (Building  
Integrated Timing Source) reference clock. The low jitter of the  
CDR PLL allows loop-timed operation of the transmit data path  
while still meeting all Bellcore and ITU jitter requirements.  
Logic Block Diagram  
(155.52 MHz)  
(155.52 MHz)  
(155.52 MHz)  
RXCLK  
TXCLKI  
REFCLK±  
TXD[15:0]  
16  
RXD[15:0]  
16  
FIFO_ERR TXCLKO  
FIFO_RST  
Input  
Register  
Output  
Register  
TX PLL  
X16  
÷16  
Shifter  
FIFO  
÷16  
Recovered  
Bit-Clock  
TX Bit-Clock  
Shifter  
RX CDR  
PLL  
Retimed  
Data  
Lock-to-Ref  
LOOPTIME  
DIAGLOOP  
Lock-to-Data/  
Clock Control  
Logic  
LINELOOP  
LOOPA  
OUT±  
IN±  
PWRDN LOCKREF SD LFI RESET  
Document #: 38-02026 Rev. *A  
Page 2 of 16  
PRELIMINARY  
CYS25G0102DX  
CYS25G0102DX Pinout[1]  
Top View  
NC  
90  
LFI  
RESET  
1
VCCQ  
2
89  
VSSQ  
88  
DIAGLOOP  
LINELOOP  
LOOPA  
3
REFCLK+  
4
87  
REFCLK–  
5
86  
NC  
VSSN  
6
85  
LOOPTIME  
84  
VCCN  
7
PWRDN  
VSSN  
8
83  
VSSN  
SD  
VSSN  
9
82  
81  
80  
79  
78  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
VCCN  
VSSN  
LOCKREF  
RXD[0]  
RXD[1]  
RXD[2]  
RXD[3]  
VSSN  
VDDQ  
RXD[4]  
RXD[5]  
RXD[6]  
RXD[7]  
VSSN  
VDDQ  
RXCLK  
VSSN  
VDDQ  
NC  
TXCLKO  
VSSN  
CYS25G0102DX  
VDDQ  
TXD[0]  
TXD[1]  
TXD[2]  
TXD[3]  
VCCQ  
VSSQ  
VCCN  
VSSN  
TXD[4]  
TXD[5]  
TXD[6]  
TXD[7]  
TXD[8]  
NC  
TXD[9]  
NC  
TXD[10]  
TXD[11]  
NC  
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60  
Notes:  
1. No connect (NC) pins must be left unconnected, or floating. Connecting any of these pins to the positive or negative power supply may cause improper operation  
or failure of the device.  
Document #: 38-02026 Rev. *A  
Page 3 of 16  
 
PRELIMINARY  
CYS25G0102DX  
Pin Descriptions  
Name  
I/OCharacteristics  
Signal Description  
Transmit Path Signals  
TXD[15:0]  
HSTL inputs  
sampled by  
TXCLKI↑  
Parallel Transmit Data Inputs. A 16-bit word, sampled by TXCLKI↑. TXD[15] is the most  
significant bit (MSB), the first bit transmitted.  
TXCLKI  
HSTL clock input  
Parallel Transmit Data Input Clock. The TXCLKI is used to transfer the data into the input  
register of the serializer. The TXCLKI samples the data, TXD [15:0], on the rising edge of  
the clock cycle.  
TXCLKO  
VREF  
HSTL clock output Transmit Clock Output. Divide by 16 of the selected transmit bit-rate clock. It can be used  
to coordinate byte-wide transfers between upstream logic and the CYS25G0102DX.  
HSTL analog  
reference  
Reference Voltage for HSTL Parallel Input Bus. VDDQ/2.[2]  
Receive Path Signals  
RXD[15:0]  
HSTL output,  
synchronous  
Parallel Receive Data Output. These outputs change following RXCLK↓. RXD[15] is the  
most significant bit of the output word, and is received first on the serial interface.  
RXCLK  
HSTL clock output Receive Clock Output. Divide by 16 of the bit-rate clock extracted from the received serial  
stream. RXD [15:0] is clocked out on the falling edge of the RXCLK.  
CM_SER  
RXCN1  
RXCN2  
RXCP1  
RXCP2  
Analog  
Analog  
Analog  
Analog  
Analog  
Common Mode Termination. Capacitor shunt to VSS for common mode noise.  
Receive Loop Filter Capacitor (Negative)  
Receive Loop Filter Capacitor (Negative)  
Receive Loop Filter Capacitor (Positive)  
Receive Loop Filter Capacitor (Positive)  
Device Control and Status Signals  
REFCLK±  
Differential LVPECL Reference Clock. This clock input is used as the timing reference for the transmit and  
input  
receive PLLs. A derivative of this input clock may also be used to clock the transmit parallel  
interface. The reference clock input signal must be AC-coupled before it is received by the  
input buffer (see Figure 6).  
LFI  
LVCMOS2.5 output Line Fault Indicator. When LOW, this signal indicates that the selected receive data stream  
has been detected as invalid by either a LOW input on SD, or by the receive VCO being  
operated outside its specified limits.  
RESET  
LVCMOS2.5 input  
LVCMOS2.5 input  
Reset for all logic functions except the transmit FIFO.  
LOCKREF  
Receive PLL Lock to Reference. When LOW, the receive PLL locks to REFCLK instead  
of the received serial data stream.  
SD  
LVCMOS2.5 input  
Signal Detect. When LOW, the receive PLL locks to REFCLK instead of the received serial  
data stream. The SD is to be connected to an external optical module to indicate a loss of  
received optical power.  
FIFO_ERR LVCMOS2.5 output OutputTransmitFIFOError. WhenHIGHthetransmitFIFOhasunderoroverflowed. When  
this occurs, the FIFO’s internal clearing mechanism will clear the FIFO within nine clock  
cycles. In addition, FIFO_RST must be activated at device power-up to ensure that the in  
and out pointers of the FIFO are set to maximum separation.  
FIFO_RST LVCMOS2.5 input  
Input Transmit FIFO Reset. When LOW, the in and out pointers of the transmit FIFO are  
set to maximum separation. FIFO_RST must be activated at device power-up to ensure that  
the in and out pointers of the FIFO are set to maximum separation. When the FIFO is being  
reset, the output data is a 1010... pattern.  
PWRDN  
LVCMOS2.5 input  
Device Power Down. When LOW, the logic and drivers are all disabled and placed into a  
standby condition where only minimal power is dissipated.  
Loop Control Signals  
DIAGLOOP LVCMOS2.5 input  
Diagnostic Loopback Control. When HIGH, transmit data is routed through the receive  
clockanddatarecoveryandpresentedattheRXD[15:0]outputs. WhenLOW, receivedserial  
data is routed through the receive clock and data recovery and presented at the RXD[15:0]  
outputs.  
Note:  
2. See Figure 10 for implementing VREF as an LVPECL interface.  
Document #: 38-02026 Rev. *A  
Page 4 of 16  
 
PRELIMINARY  
CYS25G0102DX  
Pin Descriptions (continued)  
Name  
I/OCharacteristics  
Signal Description  
LINELOOP LVCMOS2.5 input  
Line Loopback Control. When HIGH, received serial data is looped back from receive to  
transmit after being reclocked by a recovered clock. When LINELOOP is LOW, the data  
passed to the OUT± line driver is controlled by LOOPA. When both LINELOOP and LOOPA  
are LOW, the data passed to the OUT± line driver is generated in the transmit shifter.  
LOOPA  
LVCMOS2.5 input  
Analog Line Loopback. When LINELOOP is LOW and LOOPA is HIGH, received serial  
data is looped back from receive input buffer to transmit output buffer, but is not routed  
through the clock and data recovery PLL. When LOOPA is LOW, the data passed to the  
OUT± line driver is controlled by LINELOOP.  
LOOPTIME LVCMOS2.5 input  
Loop Time Mode. When HIGH, the extracted receive bit-clock replaces transmit bit clock.  
When LOW, the REFCLK input is multiplied by 16 to generate the transmit bit clock.  
Serial I/O  
OUT±  
Differential CML  
output  
Differential Serial Data Output. This differential CML output is capable of driving termi-  
nated 50Ω transmission lines or commercial fiber-optic transmitter modules.  
IN±  
Differential CML  
input  
Differential Serial Data Input. This differential input accepts the serial data stream for  
deserialization and clock extraction.  
Power  
VCCN  
VSSN  
Power  
+2.5V supply (for digital and low-speed I/O functions)  
Signal and power ground (for digital and low-speed I/O functions)  
+2.5V quiet power (for analog functions)  
Ground  
VCCQ  
VSSQ  
VDDQ  
Quiet ground (for analog functions)  
+1.5V supply for HSTL outputs[3]  
can be externally reset to clear the error indication or if no  
action is taken, the internal clearing mechanism will clear the  
FIFO in nine clock cycles. When the FIFO is being reset, the  
output data is a 1010 pattern.  
CYS25G0102DX Operation  
The CYS25G0102DX is a highly configurable device designed  
to support reliable transfer of large quantities of data using  
high-speed serial links. It performs necessary clock and data  
recovery, clock generation, serial-to-parallel conversion, and  
parallel-to-serial conversion. CYS25G0102DX also provides  
various loopback functions.  
Transmit PLL Clock Multiplier  
The Transmit PLL Clock Multiplier accepts a 155.52-MHz  
external clock at the AC-coupled REFCLK input, and multiplies  
that clock by 16 to generate a bit-rate clock for use by the  
transmit shifter. The operating serial signaling rate and  
allowable range of REFCLK frequencies is listed in Table 6.  
The REFCLK input is a standard LVPECL input. The reference  
clock input signal must be AC-coupled before it is received by  
the input buffer (see Figure 6).  
CYS25G0102DX Transmit Data Path  
Operating Modes  
The transmit path of the CYS25G0102DX supports 16-bit-  
wide data paths.  
Serializer  
Phase-Align Buffer  
The parallel data from the phase-align buffer is passed to the  
Serializer, which converts the parallel data to serial data using  
the bit-rate clock generated by the Transmit PLL clock multi-  
plier. TXD[15] is the MSB of the output word, and is transmitted  
first on the serial interface.  
Data from the input register is passed to a phase-align buffer  
(FIFO). This buffer is used to absorb clock phase differences  
between the transmit input clock and the internal character  
clock.  
Initialization of the phase-align buffer takes place when the  
FIFO_RST input is asserted LOW. When FIFO_RST is  
returned HIGH, the present input clock phase relative to  
TXCLKO is set. Once set, the input clock is allowed to skew in  
time up to half a character period in either direction relative to  
REFCLK; i.e. ±180°. This time shift allows the delay path of the  
character clock (relative to REFLCK) to change due to  
operating voltage and temperature while not effecting the  
desired operation. FIFO_RST is an asynchronous input.  
FIFO_ERR is the transmit FIFO Error indicator. When HIGH,  
the transmit FIFO has either under or overflowed. The FIFO  
Serial Output Driver  
The serial interface Output Driver makes use of high-perfor-  
mance differential CML (Current Mode Logic) to provide a  
source-matched driver for the transmission lines. This driver  
receives its data from the Transmit Shifters or the receive  
loopback data. The outputs have signal swings equivalent to  
that of standard LVPECL drivers, and are capable of driving  
AC-coupled optical modules or transmission lines.  
Note:  
3. VDDQ equals 2.5V if interfacing to a parallel LVPECL interface.  
Document #: 38-02026 Rev. *A  
Page 5 of 16  
 
PRELIMINARY  
CYS25G0102DX  
Deserializer  
CYS25G0102DX Receive Data Path  
The CDR circuit extracts bits from the serial data stream and  
clocks these bits into the Deserializer at the bit-clock rate. The  
Deserializer converts serial data into parallel data. RXD[15] is  
the MSB of the output word and is received first on the serial  
interface.  
Serial Line Receivers  
A differential line receiver, IN±, is available to accept the input  
serial data stream. The serial line receiver inputs can accom-  
modate high wire interconnect and filtering losses or trans-  
mission line attenuation (VDIF > 25 mV, or 50 mV peak-to-peak  
differential), and can be AC-coupled to +3.3V- or +5V-powered  
fiber-optic interface modules. The common-mode tolerance of  
these line receivers accommodates a wide range of signal  
termination voltages.  
Loopback/Timing Modes  
CYS25G0102DX supports various loopback modes as  
described below.  
Facility Loopback (line loopback with retiming)  
Lock to Data Control  
When the LINELOOP signal is set HIGH, the Facility Loopback  
mode is activated and the high-speed serial receive data (IN±)  
is presented to the high-speed transmit output (OUT±) after  
retiming. In Facility Loopback mode, the high-speed receive  
data (IN±) is also converted to parallel data and presented to  
the low-speed receive data output pins (RXD[15:0]). The  
receive recovered clock is also divided down and presented to  
the low-speed clock output (RXCLK).  
The line Receiver routed to the clock and data recovery PLL is  
monitored for  
• status of the signal detect (SD) pin  
• status of the LOCKREF pin.  
This status is presented on the LFI (Line Fault Indicator)  
output, which changes asynchronously in the cases when SD  
or LOCKREF goes from HIGH to LOW. Otherwise, it changes  
synchronously to the REFCLK.  
Equipment Loopback (diagnostic loopback with retiming)  
When the DIAGLOOP signal is set HIGH, transmit data is  
looped back to the RX PLL, replacing IN±. Data is looped back  
from the parallel TX inputs to the parallel RX outputs. The data  
is looped back at the internal serial interface and goes through  
transmit shifter and the receive CDR. SD is ignored in this  
mode.  
Clock/Data Recovery  
The extraction of a bit-rate clock and recovery of data bits from  
the received serial stream is performed by a Clock/Data  
Recovery (CDR) block. The clock extraction function is  
performed by a high-performance embedded phase-locked  
loop (PLL) that tracks the frequency of the incoming bit stream  
and aligns the phase of the internal bit-rate clock to the transi-  
tions in the selected serial data stream.  
Line Loopback Mode (non-retimed data)  
When the LOOPA signal is set HIGH, the RX serial data is  
directly buffered out to the transmit serial data. The data at the  
serial output is not retimed.  
CDR accepts a character-rate (bit-rate divided by 16)  
reference clock on the REFCLK input. This REFCLK input is  
used to ensure that the VCO (within the CDR) is operating at  
the correct frequency (rather than some harmonic of the bit-  
rate), to improve PLL acquisition time, and to limit unlocked  
frequency excursions of the CDR VCO when no data is  
present at the serial inputs.  
Loop Timing Mode  
When the LOOPTIME signal is set HIGH, the TX PLL is  
bypassed and receive bit-rate clock is used for transmit side  
shifter.  
Regardless of the type of signal present, the CDR will attempt  
to recover a data stream from it. If the frequency of the  
recovered data stream is outside the limits set by the range  
controls, the CDR PLL will track REFCLK instead of the data  
stream. When the frequency of the selected data stream  
returns to a valid frequency, the CDR PLL is allowed to track  
the received data stream. The frequency of REFCLK is  
required to be within ±100 ppm of the frequency of the clock  
that drives the REFCLK signal of the remote transmitter to  
ensure a lock to the incoming data stream.  
Reset Modes  
ALL logic circuits in the device can be reset using RESET and  
FIFO_RST signals. When RESET is set LOW, all logic circuits  
except FIFO are internally reset. When FIFO_RST is set LOW,  
the FIFO logic is reset.  
Power-down Mode  
CYS25G0102DX provides a global power-down signal  
PWRDN. When LOW, this signal powers down the entire  
device to a minimal power dissipation state. RESET and  
FIFO_RST signals should be asserted LOW along with  
PWRDN signal to ensure low power dissipation.  
For systems using multiple or redundant connections, the LFI  
output can be used to select an alternate data stream. When  
an LFI indication is detected, external logic can toggle  
selection of the input device. When such a port switch takes  
place, it is necessary for the PLL to reacquire lock to the new  
serial stream.  
LVPECL Compliance  
The CYS25G0102DX HSTL parallel I/O can be configured to  
LVPECL compliance with slight termination modifications. On  
the transmit side of the transceiver, the TXD[15:0] and TXCLKI  
can be made LVPECL compliant by following the guidelines  
illustrated in Figure 10. To emulate a LVPECL signal on the  
receiver side, VDDQ needs to be set to 2.5V and the trans-  
mission lines need to be terminated with the equivalent 50Ω  
impedance. A simple resistive translation is illustrated in  
Figure 9. This circuit needs to be used on all 16 RXD[15:0]  
pins, TXCLKO, and RXCLK. The circuit has been calculated  
assuming the system is built with 50Ω transmission lines.  
External Filter  
The CDR circuit uses external capacitors for the PLL filter.  
A 0.1-µF capacitor needs be connected between RXCN1 and  
RXCP1. Similarly a 0.1-µF capacitor needs to be connected  
between RXCN2 and RXCP2. The recommended packages  
and dielectric material for these capacitors are 0805 X7R or  
0603 X7R.  
Document #: 38-02026 Rev. *A  
Page 6 of 16  
PRELIMINARY  
CYS25G0102DX  
DC Voltage Applied to HSTL Outputs  
Maximum Ratings  
in High-Z State[4] ................................. –0.5V to VDDQ + 0.5V  
(Stresses beyond those listed under “Maximum Ratings” may  
cause permanent damage to the device. These are stress  
ratings only, and functional operation of the device at these or  
any other conditions beyond those indicated under the recom-  
mended operating conditions is not implied. Exposure to  
absolute-maximum-rated conditions for extended periods may  
affect device reliability.)  
DC Voltage Applied to any output in the High-Z state or  
power-off state[4] ................................... –0.5V to VCC + 0.5V  
DC Input Voltage[4] ................................ –0.5V to VCC + 0.5V  
Static Discharge Voltage .......................................... > 2001V  
(per MIL-STD-883, Method 3015)  
Latch-Up Current.................................................... > 200 mA  
Storage Temperature .................................–65°C to +150°C  
Operating Range  
Ambient Temperature with  
Power Applied.............................................–55°C to +125°C  
Ambient  
Range  
Commercial  
Industrial  
Temperature  
VDDQ  
VCC  
VCC Supply Voltage to Ground Potential ....... –0.5V to +3.6V  
0°C to +70°C 1.4V to 1.6V[5] 2.5V ±5%  
-40°C to +85°C 1.4V to 1.6V[5] 2.5V ±5%  
VDDQ Supply Voltage to Ground Potential..... –0.5V to +3.6V  
DC Specifications  
Table 1. DC Specifications – LVCMOS2.5  
Parameter  
Description  
Test Conditions  
Min.  
Max.  
Unit  
LVCMOS2.5 Outputs  
VOHT  
Output HIGH Voltage  
VCC = 2.375V,  
IOH = –1 mA, VIH = 1.7V  
2
V
V
V
VCC = 2.375V,  
IOH = –8 mA, VIH = 1.7V  
1.8  
VOLT  
Output LOW Voltage  
VCC = 2.375V,  
IOL = 1 mA,  
VIL=0.7V  
0.4  
0.6  
VCC = 2.375V,  
IOL = 8 mA,  
VIL=0.7V  
V
IOS  
Output Short Circuit Current  
VOUT = 0V  
–20  
–90  
mA  
LVCMOS2.5 Inputs  
VIHT  
Input HIGH Voltage  
VCC = 2.375V to 2.625V  
VCC = 2.375V to 2.625V  
VIN = VCC  
1.7  
3.6  
0.7  
10  
V
V
VILT  
Input LOW Voltage  
Input HIGH Current  
Input LOW Current  
–0.3  
IIHT  
µA  
µA  
IILT  
VIN = GND  
–10  
Capacitance  
CIN  
Input Capacitance  
VCC = Max.  
@ f = 1 MHz  
5
pF  
Table 2. DC Specifications – Power  
Parameter  
Power  
Description  
Test Conditions  
Typ.  
Max.  
Unit  
ICC  
Active Power Supply Current  
Standby Current  
240  
285  
5
mA  
mA  
ISB  
Notes:  
4. This value is limited to 3.6V maximum.  
5. For LVPECL interface, VDDQ = VCC  
.
Document #: 38-02026 Rev. *A  
Page 7 of 16  
 
 
PRELIMINARY  
CYS25G0102DX  
Table 3. DC Specifications – Differential LVPECL Input (REFCLK)  
Parameter  
Description  
Test Conditions  
Min.  
Max.  
Unit  
Receiver LVPECL Compatible Inputs  
VINSGLE  
VDIFFE  
Input Single-ended Swing  
Input Differential Voltage  
200  
400  
600  
mV  
mV  
1200  
Capacitance  
CINE  
Input Capacitance  
4
pF  
Table 4. DC Specifications – Differential CML  
Parameter Description  
Transmitter CML Compatible Outputs  
Test Conditions  
Min.  
Max.  
Unit  
VOHC  
Output HIGH Voltage  
(VCC Referenced)  
100Ω differential load VCC – 0.5 VCC – 0.15  
100Ω differential load VCC – 1.2 VCC – 0.7  
V
V
VOLC  
Output LOW Voltage  
(VCC Referenced)  
VDIFFOC  
VSGLCO  
Output Differential Swing  
100Ω differential load  
100Ω differential load  
560  
280  
1600  
800  
mV  
mV  
Output Single-ended Voltage  
Receiver CML Compatible Inputs  
VINSGLC  
VDIFFC  
VICHH  
VICLL  
Input Single-ended Swing  
Input Differential Voltage  
Highest Input HIGH Voltage  
Lowest Input LOW Voltage  
Input HIGH Current  
25  
50  
600  
1200  
VCC  
mV  
mV  
V
1.1  
V
IICH  
VIN = VICHH Max.  
VIN = VICLL Min.  
47  
20  
µA  
µA  
IICL  
Input LOW Current  
Capacitance  
CINC  
Input Capacitance  
4
pF  
Table 5. DC Specifications – HSTL  
Parameter  
HSTL Outputs  
VOHH  
Description  
Test Conditions  
Min.  
Max.  
Unit  
Output HIGH Voltage  
Output LOW Voltage  
VCC = Min.,  
IOH= –4.0 mA  
V
DDQ – 0.4  
V
V
VOLH  
VCC = Min.,  
0.4  
IOL= 4.0 mA  
IOSH  
Output Short Circuit Current  
VOUT = 0V  
100  
mA  
HSTL Inputs  
VIHH  
Input HIGH Voltage  
Input LOW Voltage  
Input HIGH Current  
VREF + 0.13 VDDQ + 0.3  
V
V
VILH  
–0.3  
VREF – 0.1  
IIHH  
VDDQ = Max.  
VIN = VDDQ  
50  
µA  
IILH  
Input LOW Current  
VDDQ = Max.  
VIN = 0V  
–40  
µA  
Capacitance  
CINH  
Input Capacitance  
VDDQ = Max.  
@ f = 1 MHz  
5
pF  
Document #: 38-02026 Rev. *A  
Page 8 of 16  
PRELIMINARY  
CYS25G0102DX  
AC Specifications  
Table 6. AC Specifications – REFCLK  
Parameter  
Description  
Min.  
154.5  
6.38  
35  
Max.  
156.5  
6.47  
65  
Unit  
MHz  
ns  
tREF  
REFCLK Input Frequency  
REFCLK Period  
tREFP  
tREFD  
tREFT  
tREFR  
tREFF  
REFCLK Duty Cycle  
%
REFCLK Frequency Tolerance (relative to received serial data)[6]  
–100  
0.3  
+100  
1.5  
ppm  
ns  
REFCLK Rise Time  
REFCLK Fall Time  
0.3  
1.5  
ns  
Table 7. AC Specifications – Parallel Interface  
Parameter  
Description  
Min.  
154.5  
6.38  
40  
Max.  
156.5  
6.47  
60  
Unit  
MHz  
ns  
tTS  
TXCLKI Frequency (must be frequency coherent to REFCLK)  
TXCLKI Period  
tTXCLKI  
tTXCLKID  
tTXCLKIR  
tTXCLKIF  
tTXDS  
TXCLKI Duty Cycle  
%
TXCLKi Rise Time  
0.3  
1.5  
ns  
TXCLKi Fall Time  
0.3  
1.5  
ns  
Write Data Set-up to ↑ of TXCLKI  
Write Data Hold from ↑ of TXCLKI  
TXCLKO Frequency  
1.5  
ns  
tTXDH  
0.5  
ns  
tTOS  
154.5  
6.38  
43  
156.5  
6.47  
57  
MHz  
ns  
tTXCLKO  
tTXCLKOD  
tTXCLKOR  
tTXCLKOF  
tRS  
TXCLKO Period  
TXCLKO Duty Cycle  
%
TXCLKO Rise Time  
0.3  
1.5  
ns  
TXCLKO Fall Time  
0.3  
1.5  
ns  
RXCLK Frequency  
154.5  
6.38  
43  
156.5  
6.47  
57  
MHz  
ns  
tRXCLK  
tRXCLKD  
tRXCLKR  
tRXCLKF  
tRXDS  
RXCLK Period  
RXCLK Duty Cycle  
RXCLK Rise Time[7]  
RXCLK Fall Time[7]  
%
0.3  
1.5  
ns  
0.3  
1.5  
ns  
Recovered Data Set-up with reference to ↑ of RXCLK.  
Recovered Data Hold with reference to ↑ of RXCLK.  
Valid Propagation delay  
2.2  
ns  
tRXDH  
2.2  
ns  
tRXPD  
-1.0  
1.0  
ns  
Table 8. AC Specifications – CML Serial Outputs  
Parameter Description  
tRISE  
tFALL  
tTJ  
Min.  
60  
Typ.  
Max.  
170  
Unit  
ps  
CML Output Rise Time (20–80%, 100Ω balanced load)  
CML Output Fall Time (80–20%, 100Ω balanced load)  
Total Output Jitter (p-p)[8]  
60  
170  
ps  
0.035  
0.005  
0.05  
0.007  
UI  
Total Output Jitter (rms)[8]  
UI  
Note:  
6. +20 ppm is required to meet the SONET output frequency specification.  
7. RXCLK rise and fall times are measured at the 20 to 80 percentile region of the rising and falling edge of the clock signal.  
8. The RMS and P-to-P Jitter values are measured using a 12-KHz to 20-MHz SONET Filter.  
Document #: 38-02026 Rev. *A  
Page 9 of 16  
PRELIMINARY  
CYS25G0102DX  
Jitter Waveforms  
Figure 2. Jitter Transfer Waveform of CYS25G0102DX  
Figure 3. Jitter Tolerance Waveform of CYS25G0102DX  
Document #: 38-02026 Rev. *A  
Page 10 of 16  
PRELIMINARY  
CYS25G0102DX  
Switching Waveforms  
Transmit Interface Timing  
tTXCLKI  
tTXCLKIDH  
tTXCLKIDL  
TXCLKI  
tTXDS tTXDH  
TXD[15:0]  
tTXCLKO  
tTXCLKODL  
tTXCLKODH  
TXCLKO  
Receive Interface Timing  
tRXCLK  
tRXCLKDL  
tRXCLKDH  
RXCLK  
tRXPD  
tRXDS  
tRXDH  
RXD[15:0]  
Document #: 38-02026 Rev. *A  
Page 11 of 16  
PRELIMINARY  
CYS25G0102DX  
AC Test Loads and Waveforms  
Input Test Waveform Specifications  
V
V
ICHH  
CC  
V
CC  
90%  
10%  
90%  
10%  
80%  
80%  
V =V /2  
V =V /2  
th  
CC  
th  
CC  
20%  
≤ 150 ps  
20%  
≤ 150 ps  
GND  
V
ICLL  
< 2 ns  
< 2 ns  
(a) LVCMOS2.5 Input Test Waveform  
(b) CML Input Test Waveform  
V
V
IHH  
IEHH  
80%  
80%  
80%  
20%  
80%  
20%  
V =0.75V  
V =0.75V  
th  
th  
20%  
≤ 1.0 ns  
20%  
V
V
IHL  
IELL  
≤ 1.0 ns  
< 1 ns  
< 1 ns  
(d) LVPECL Input Test Waveform  
(c) HSTL  
Input Test Waveform  
AC Test Loads  
OUTPUT  
OUT+  
C
R1= 500Ω  
L
(Includes fixture and  
probe capacitance)  
L
R =100Ω  
L
C
= 30 pF  
R
L
R1  
OUT–  
(a) LVCMOS2.5 AC Test Load  
(b) CML AC Test Load  
1.5V  
R1  
OUTPUT  
R1=100Ω  
R2=100Ω  
L
C
L
C
≤ 7 pF  
R2  
(Includes fixture and  
probe capacitance)  
(c) HSTL  
AC Test Load  
Document #: 38-02026 Rev. *A  
Page 12 of 16  
PRELIMINARY  
CYS25G0102DX  
CYS25G0102DX  
Limiting Amp  
F
µ
0.1  
0.1  
Ω
Zo=50  
IN+  
IN–  
OUT+  
OUT–  
Ω
100  
Ω
Zo=50  
F
µ
Figure 4. Serial Input Termination  
Optical Module  
CYS25G0102DX  
0.1  
0.1  
F
µ
Ω
Zo=50  
IN+  
OUT+  
OUT–  
Ω
100  
IN–  
Ω
Zo=50  
F
µ
Figure 5. Serial Output Termination  
Clock Oscillator  
CYS25G0102DX  
VCC  
Ω
Zo=50  
0.1uF  
Ω
130  
VCC  
130  
LVPECL  
OUTPUT  
Ω
82  
Ω
Refclock Internally  
Biased  
0.1uF  
Ω
Ω
Zo=50  
82  
Figure 6. Clock Oscillator Termination  
CYS25G0102DX  
FRAMER  
VDDQ=1.5V  
HSTL  
INPUT  
HSTL  
OUTPUT  
Ω
Ω
Zo=50  
100  
Ω
100  
Figure 7. TXCLKO/ RXCLK Termination  
CYS25G0102DX  
FRAMER  
HSTL  
INPUT  
HSTL  
OUTPUT  
Ω
Zo=50  
Figure 8. RXD[15:0] Termination  
Document #: 38-02026 Rev. *A  
Page 13 of 16  
PRELIMINARY  
CYS25G0102DX  
VDDQ=2.5V  
RXD[15;0],  
FRAMER  
VDDQ=3.3V  
59Ω  
RXCLK,  
Ω
Zo=50  
70Ω  
LVPECL INPUT  
TXCLKO  
OUTPUT  
Ω
150  
CYS25G0102DX  
Figure 9. LVPECL Level Termination  
3.3V  
2.5V  
3.3V  
Ω
656  
CYS25G0102DX  
VREF  
VCCN  
VCCQ  
Ω
LVPECL Device  
344  
VDDQ  
3.3V  
Ω
130  
Ω
O = 50  
Z
3.3V  
130  
Ω
35.5  
TXD0  
Ω
Ω
46.5  
Ω
82  
TXD15  
Figure 10. LVPECL Parallel Input  
Ordering Information  
Speed  
Ordering Code  
Package Name  
Package Type  
Operating Range  
Standard  
AT120  
120-Pin TQFP  
Commercial  
Document #: 38-02026 Rev. *A  
Page 14 of 16  
PRELIMINARY  
CYS25G0102DX  
Package Diagram  
120-Pin Thin Quad Flatpack (14 × 14 × 1.4 mm) with Heat Slug AT120  
51-85116  
All product and company names mentioned in this document may be the trademarks of their respective holders.  
Document #: 38-02026 Rev. *A  
Page 15 of 16  
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize  
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.  
PRELIMINARY  
CYS25G0102DX  
Document Title: CYS25G0102DX SONET OC-48 Transceiver  
Document Number: 38-02026  
Issue  
Orig. of  
Change  
REV.  
**  
ECN NO.  
109132  
110444  
Date  
Description of Change  
8/27/01  
02/20/02  
CGX  
CGX  
New Data Sheet  
*A  
Fixed typos: 155 Gbits to 155 Mbits  
Changed pins 113, 116, and 119 to quiet power supplies  
Added Industrial temperature  
Document #: 38-02026 Rev. *A  
Page 16 of 16  
厂商 型号 描述 页数 下载

CRYSTEKMICROWAVE

 		CYS1A11A-20.000 石英晶体薄型HC49S含铅水晶[ Quartz Crystal Low Profile HC49S Leaded Crystal ] 1 页

CRYSTEKMICROWAVE

 		CYS1A11A-FREQ 石英晶体薄型HC49S含铅水晶[ Quartz Crystal Low Profile HC49S Leaded Crystal ] 1 页

CRYSTEKMICROWAVE

 		CYS1A11AS-20.000 石英晶体薄型HC49S含铅水晶[ Quartz Crystal Low Profile HC49S Leaded Crystal ] 1 页

CRYSTEKMICROWAVE

 		CYS1A11AS-FREQ 石英晶体薄型HC49S含铅水晶[ Quartz Crystal Low Profile HC49S Leaded Crystal ] 1 页

CRYSTEKMICROWAVE

 		CYS1A11B-20.000 石英晶体薄型HC49S含铅水晶[ Quartz Crystal Low Profile HC49S Leaded Crystal ] 1 页

CRYSTEKMICROWAVE

 		CYS1A11B-FREQ 石英晶体薄型HC49S含铅水晶[ Quartz Crystal Low Profile HC49S Leaded Crystal ] 1 页

CRYSTEKMICROWAVE

 		CYS1A11BS-20.000 石英晶体薄型HC49S含铅水晶[ Quartz Crystal Low Profile HC49S Leaded Crystal ] 1 页

CRYSTEKMICROWAVE

 		CYS1A11BS-FREQ 石英晶体薄型HC49S含铅水晶[ Quartz Crystal Low Profile HC49S Leaded Crystal ] 1 页

CRYSTEKMICROWAVE

 		CYS1A11C-20.000 石英晶体薄型HC49S含铅水晶[ Quartz Crystal Low Profile HC49S Leaded Crystal ] 1 页

CRYSTEKMICROWAVE

 		CYS1A11C-FREQ 石英晶体薄型HC49S含铅水晶[ Quartz Crystal Low Profile HC49S Leaded Crystal ] 1 页

购物指南

支付方式

配送服务

售后服务

发票须知

优惠券使用规则

特色服务

PCBA制造

国产品牌推荐

国产料号替代

质量保证

技术资料

行业资讯

关于我们

关于达普

联系我们

联系我们

服务热线：400-618-9990

企业邮箱：smail@ic72.com

服务时间：周一至周六 8:30-17:30

达普官方微信号

PDF索引：

A

B

C

D

E

F

G

H

I

J

K

L

M

N

O

P

Q

R

S

T

U

V

W

X

Y

Z

0

1

2

3

4

5

6

7

8

9

IC型号索引：

A

B

C

D

E

F

G

H

I

J

K

L

M

N

O

P

Q

R

S

T

U

V

W

X

Y

Z

0

1

2

3

4

5

6

7

8

9

Copyright 2024 gkzhan.com Al Rights Reserved 京ICP备06008810号-21 京

深圳网络警察报警平台
公共信息安全网络监察
经营性网站备案信息
不良信息举报中心
工商网监电子标识
全国公安机关备案
0.254315s