CYP25G01K100V1-MGC,PDF,CYP25G01K100V1-MGC PDF资料,Datasheet,下载CYP25G01K100V1-MGC技术资料

2.5-Gbps Programmable Serial Interface™

— Circuit board traces

— Backplane links

Features

• High-speed (HS) Programmable Serial Interface™

(PSI™)

— Box-to-box links

• 2.48- to 2.5-Gbps serial signaling rate

• Full Bellcore and ITU jitter compliance

• Flexible parallel-to-serial conversion in transmit path

• Flexible serial-to-parallel conversion in receive path

• Multiple selectable loopback/loop-through modes

• 100K of usable gates of CPLD logic

— Chip-to-chip communication

• Extremely flexible clocking options

— Four global clocks

— Up to 192 additional product term clocks

— Clock polarity at every register

• Carry chain logic for fast and efficient arithmetic

operations

• JTAG programming interface with boundary scan

support

• 240K of integrated memory

— 192K of synchronous or asynchronous SRAM

— 48K of true Dual-Port or FIFO RAM

• Power-saving mode

• Supported standards:

• Internal transmit and receive phase-locked loops

(PLLs)

• Logic dedicated Spread Aware PLL

— SONET OC-48 and SDH STM-16

• Transmit FIFO for flexible variable phase clocking

• Differential CML serial input with internal termination

and DC-restoration

— InfiniBand™

— Custom 2.5-Gbps interface

• Differential CML serial output with source-matched

impedance of 50Ω

Development Software

• Warp^®

• 240 user-programmable I/Os

• Any Volt™ I/O interface

— IEEE 1076/1164 VHDL or IEEE 1364 Verilog context

— Programmable as 1.5V, 1.8V, 2.5V, 3.3V

• Multiple I/O standards

sensitive editing

— Active-HDL FSM graphical finite state machine

editor

— LVCMOS, LVTTL, 3.3V PCI, SSTL2(I-II), SSTL3(I-II),

HSTL(I-IV), and GTL+

— Active-HDL SIM post-synthesis timing simulator

— Architecture Explorer for detailed design analysis

— Static Timing Analyzer for critical path analysis

— Available on Windows^®9x, 2000, NT 4.0, XP, and ME

— Supports all Cypress programmable logic products

— Fully PCI-compliant (Rev. 2.2)

• Direct interface to standard fiber-optic modules

• Designed to drive:

— Fiberoptic modules

— Copper cables

2.5-Gbps PSI Family—Standards Supported

PSI Device

CYS25G01K100

CYP25G01K100

SONET/SDH (OC48/STM16)

InfiniBand

Custom

SONET/SDH

High Speed

X

2.5-Gbps PSI Family—General Features

Cluster

Channel

Typical

Gates

Memory Memory

Maximum User-

Programmable I/O

Device

Macrocells (Kbits)

(Kbits)

Package Offering

25G01K100 46K–144K

1536 192

48

240

456-BGA (35 × 35 mm, 1.27-mm pitch)

2.5-Gbps PSI Family—Performance

Logic Speed—

Device

Channels and Link Speed

Total Bandwidth

f_MAX2(Logic)^[1](MHz)

t_PDPin-to-Pin^[1](ns)

25G01K100

1 × 2.5 Gbps

2.5 Gbps

222

7.5

Note:

1. See the section titled Switching Characteristics for definition.

Cypress Semiconductor Corporation

Document #: 38-02021 Rev. *C

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised December 4, 2002

2.5-Gbps Programmable Serial Interface

PLL & Clock MUX

GCLK[1:0]

RXCLK

GCTL[3:0]

4

TXCLK

I/O Bank

GCLK[1:0], RXCLK, TXCLK

4

LB 0

LB 1

LB 2

LB 3

LB 7

LB 0

LB 1

LB 2

LB 3

LB 7

LB 6

LB 5

LB 4

LB 0

LB 1

LB 2

LB 3

LB 7

LB 6

LB 5

LB 4

LB 0

LB 7

LB 6

LB 5

LB 4

LB 1

LB 2

LB 3

Channel

RAM

Channel

RAM

Channel

RAM

Channel

RAM

PIM

LB 5

LB 4

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

GCLK[1:0], RXCLK, TXCLK

4

LB 0

LB 1

LB 2

LB 3

LB 7

LB 6

LB 5

LB 4

LB 0

LB 1

LB 2

LB 3

LB 7

LB 6

LB 5

LB 4

LB 0

LB 1

LB 2

LB 3

LB 7

LB 6

LB 5

LB 4

LB 0

LB 1

LB 2

LB 3

LB 7

LB 6

LB 5

LB 4

Channel

RAM

Channel

RAM

Channel

RAM

Channel

RAM

PIM

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

GCLK[1:0], RXCLK, TXCLK

4

LB 0

LB 1

LB 2

LB 3

LB 7

LB 6

LB 5

LB 4

LB 0

LB 1

LB 2

LB 3

LB 7

LB 6

LB 5

LB 4

LB 0

LB 1

LB 2

LB 3

LB 7

LB 6

LB 5

LB 4

LB 0

LB 1

LB 2

LB 3

LB 7

LB 6

LB 5

LB 4

Channel

RAM

Channel

RAM

Channel

RAM

Channel

RAM

PIM

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

Phase Align

Buffer

Deserializer

Serializer

RX

TX

Serial Signal Bank

Figure 1. High-speed PSI™ Block Diagram (25G01K100) with I/O Bank Structure

Document #: 38-02021 Rev. *C

Page 2 of 44

2.5-Gbps Programmable Serial Interface

Functional Description

CY PSI

The 2.5-Gbps PSI is a point-to-point or point-to-multipoint

programmable communications building block allowing the

manipulation and transfer of data over high-speed serial links

at 2.5 Gbps per serial link. The 2.5-Gbps PSI is designed to

combine the high speed, predictable timing, high density, low

power, and ease of use of complex programmable logic

devices (CPLD) with the serializing/deserializing (SERDES)

capability of high-speed serial transceivers.

+

REFCLK±

–

Optical

Transceiver

Programmable

Host Bus

Interface

Serial

Data

IN+

IN–

SD

RD+

RD–

SD

TD–

TD+

Optical

Fiber Links

OUT–

OUT+

The architecture of the device is based on logic block clusters

(LBC) and serial transceiver blocks that are connected by

horizontal and vertical routing channels. Each LBC features

eight individual logic blocks (LB) of 16 macrocells and two

cluster memory blocks. Adjacent to each LBC is a channel

memory block which is externally accessible through the I/O

interface. Each transmit channel of the transceiver accepts 16

bit parallel characters, and converts it to serial data. Each

receive channel accepts serial data and converts it to 16-bit

parallel data, and presents these characters to the routing

channels of the Programmable Logic.

Serial

Data

Figure 2. High-speed PSI System Connections

with an Optical Interface

Standard Datapath Cell

Figure 3 is a block diagram of the PSI datapath cell. The

datapath cell contains a three-state transmit buffer, a receive

buffer, and a register that can be configured as a transmit or

receive register.

High-speed Transceiver

The transceiver operation of the high-speed programmable

serial interface devices is self-contained in a single block. It

has a separate Transmit PLL (TXPLL) and a Receive Clock

and Data Recovery PLL (RX CDR PLL) and a phase align

buffer for flexible clocking. The transmit channel accepts a

16-bit input character from the routing channels and passes

the character to the phase align buffer. This character is then

serialized and output to differential CML output drivers at 2.5

Gbps. The receive channel accepts a serial bit-stream from

the differential CML receiver. This bit-stream is deserialized

and a 16-bit character is presented to the routing channels in

the PSI device. The block also features loop-back and

loop-through modes for simplified design debugging.

The Transceiver Enable (TE) can be selected from one of the

four global control signals(GCTL[0:3]) or from one of two

Output Control Channel (OCC) signals. The transmit enable

can be configured as always enabled or always disabled or it

can be controlled by one of the remaining inputs to the mux.

The selection is done via a mux that includes V_CCand GND

as inputs.

One of the global clocks(GCLK[1:0], TXCLK or RXCLK) can

be selected as the clock for the datapath cell register. The

clock mux output is an input to a clock polarity mux that allows

the transmit/receive register to be clocked on either edge of

the clock.

The transceiver block interfaces to the routing channels of the

PSI device through highly configurable datapath cells. For

specific architecture and operation of the transceiver blocks

please refer to the Serial Transceiver Operation section

(page 14).

Global Routing Description

The routing architecture in the PLD block of a PSI device is

made up of horizontal and vertical (H&V) routing channels.

These routing channels allow signals to move among I/Os,

logic blocks and memories. In addition to the horizontal and

vertical routing channels that interconnect the I/O banks,

channel memory blocks, transceiver blocks and logic block

clusters, each LBC contains a Programmable Interconnect

Matrix™ (PIM™), which is used to route signals among the

logic blocks and the cluster memory blocks in the LBC.

The internal interfacing to the transceiver blocks of the

high-speed device occur through the port definition of the

high-speed transceiver block. The internal signals and their

definition are described in the “Pin and Signal Description”

section (page 38). These internal signals can be routed to the

programmable logic by instantiation and port mapping them

through hardware description using Warp Software.

Figure 4 is a block diagram of the routing channels that

interface within the PSI architecture.

Document #: 38-02021 Rev. *C

Page 3 of 44

2.5-Gbps Programmable Serial Interface

Registered TE

Mux

TE Mux

D

Q

From

Output PIM

C

3

C

Receive

Mux

RES

To Routing

Channel

Register Receive

Mux

C

Transmit

Mux

Signal

Register Enable

Mux

D

E

Q

Clock

Polarity

Mux

C

RES

3

C

Clock Mux

C

2

3

Register Reset

Mux

C

Figure 3. Block Diagram of a Standard Datapath Cell

Logic Block Cluster (LBC)

memory blocks within the same LBC as well as other LBCs to

implement larger memory functions. If a cluster memory block

is not specifically utilized by the designer, Cypress’s Warp

software can automatically use it to implement large blocks of

logic.

The PSI architecture consists of several logic block clusters,

each of which have eight Logic Blocks (LBs) and two cluster

memory blocks connected via a PIM, as shown in Figure 5.

Each cluster memory block consists of 8-Kbit single-port RAM,

which is configurable as synchronous or asynchronous. The

cluster memory blocks can be cascaded with other cluster

All LBCs interface with each other via horizontal and vertical

routing channels.

I/O Block

LB

72

64

Cluster

PIM

Channel memory

outputs drive

dedicated tracks in the

horizontal and vertical

routing channels

Channel

Memory

Block

Cluster

Memory

Block

Cluster

Memory

Block

72

64

H-to-V

PIM

V-to-H

PIM

Pin inputs from the I/O cells

drive dedicated tracks in the

horizontal and vertical routing

channels

Figure 4. PSI Routing Interface

Document #: 38-02021 Rev. *C

Page 4 of 44

2.5-Gbps Programmable Serial Interface

Clock Inputs

GCLK[1:0], RXCLK and TXCLK

4

Logic

Block

0

Logic

Block

7

36

16

36

16

Logic

Block

1

Logic

Block

6

36

16

36

16

Logic

Block

2

Logic

Block

5

36

16

36

16

PIM

Logic

Block

3

Logic

Block

4

36

16

36

16

Cluster

Memory

0

Cluster

Memory

1

25

8

25

8

CC = Carry Chain

64 Inputs From

Vertical Routing

Channel

64 Inputs From

Horizontal Routing

Channel

144 Outputs to

Horizontal and Vertical

cluster-to-channel PIMs

Figure 5. PSI Logic Block Cluster Diagram

Logic Block

important capabilities without affecting performance: product

term steering and product term sharing.

The LB is the basic building block of the programmable logic

block of the PSI architecture. It consists of a product term

array, an intelligent product-term allocator, and 16 macrocells.

Product Term Steering

Product term steering is the process of assigning product

terms to macrocells as needed. For example, if one macrocell

requires ten product terms while another needs just three, the

product term allocator will “steer” ten product terms to one

macrocell and three to the other. On PSI devices, product

terms are steered on an individual basis. Any number between

1and 16 product terms can be steered to any macrocell.

Product Term Array

Each LB features a 72 × 83 programmable product term array.

This array accepts 36 inputs from the PIM. These inputs

originate from device pins and macrocell feedbacks as well as

cluster memory and channel memory feedbacks. Active LOW

and active HIGH versions of each of these inputs are

generated to create the full 72-input field. The 83 product

terms in the array can be created from any of the 72 inputs.

Product Term Sharing

Product term sharing is the process of using the same product

term among multiple macrocells. For example, if more than

one function has one or more product terms in its equation that

are common to other functions, those product terms are only

created once. The PSI product term allocator allows sharing

across groups of four macrocells in a variable fashion. The

software automatically takes advantage of this capability so

that the user does not have to intervene.

Of the 83 product terms, 80 are for general-purpose use for

the 16 macrocells in the LB. Two of the remaining three

product terms in the LB are used as asynchronous set and

asynchronous reset product terms. The final product term is

the Product Term clock (PTCLK) and is shared by all 16

macrocells within an LB.

Product Term Allocator

Note that neither product term sharing nor product term

steering have any effect on the speed of the product. All

steering and sharing configurations have been incorporated in

Through the product term allocator, Warp software automati-

cally distributes the 80 product terms as needed among the 16

macrocells in the LB. The product term allocator provides two

the timing specifications for the PSI devices.

.

Document #: 38-02021 Rev. *C

Page 5 of 44

2.5-Gbps Programmable Serial Interface

Macrocell

through the use of carry-in arithmetic, which drives through the

circuit quickly. Figure 6 shows that the carry chain logic within

the macrocell consists of two product terms (CPT0 and CPT1)

from the PTA and an input carry-in for carry logic. The inputs

to the carry chain mux are connected directly to the product

terms in the PTA. The output of the carry chain mux generates

the carry-out for the next macrocell in the LB as well as the

local carry input that is connected to an input of the XOR input

mux. Carry-in and a configuration bit are inputs to an AND

gate. This AND gate provides a method of segmenting the

carry chain in any macrocell in the LB.

Within each LB there are 16 macrocells. Each macrocell

accepts a sum of up to 16 product terms from the product term

array. The sum of these 16 product terms can be output in

either registered or combinatorial mode. Figure 6 displays the

block diagram of the macrocell. The register can be asynchro-

nously preset or asynchronously reset at the macrocell level

with the separate preset and reset product terms. Each of

these product terms features programmable polarity. This

allows the registers to be preset or reset based on an AND

expression or an OR expression.

An XOR gate in the PSI macrocell allows for many different

types of equations to be realized. It can be used as a polarity

mux to implement the true or complement form of an equation

in the product term array or as a toggle to turn the D flip-flop

into a T flip-flop. The carry-chain input mux allows additional

flexibility for the implementation of different types of logic. The

macrocell can utilize the carry chain logic to implement adders,

subtractors, magnitude comparators, parity tree, or even

generic XOR logic. The output of the macrocell is either regis-

tered or combinatorial.

Macrocell Clocks

Clocking of the register is highly flexible. Four global

synchronous clocks (GCLK[1:0], RXCLK and TXCLK) and a

Product Term clock (PTCLK) are available at each macrocell

register. Furthermore, a clock polarity mux within each

macrocell allows the register to be clocked on the rising or the

falling edge (see macrocell diagram in Figure 6).

PRESET/RESET Configurations

The macrocell register can be asynchronously preset and

reset using the PRESET and RESET mux. Both signals are

active high and can be controlled by either of two Preset/Reset

product terms (PRC[1:0] in Figure 6) or GND. In situations

where the PRESET and RESET are active at the same time,

RESET takes priority over PRESET.

Carry Chain Logic

The PSI macrocell features carry chain logic which is used for

fast and efficient implementation of arithmetic operations. The

carry logic connects macrocells in up to four LBs for a total of

64 macrocells. Effective data path operations are implemented

Carry In

(from m acrocell n-1)

PRE SET

Mux

0

1

C

XO R Input

3

Carry Chain

M ux

C

CPT0

CPT1

O utput M ux

C

2

To P IM

C

D ^PSET

C

Q

FRO M P TM

Up To 16 P Ts

Clock

Clock Mux

Polarity

Mux

Q

R ES

G CLK [1:0], RXCLK ,

TXCLK

P TCLK

3

C

0

1

Carry O ut

(to m acrocell n+1)

3

C

R ESE T

M ux

Figure 6. PSI Macrocell

Document #: 38-02021 Rev. *C

Page 6 of 44

2.5-Gbps Programmable Serial Interface

Embedded Memory

Cluster Memory Initialization

The 2.5-Gbps PSI family contains two types of embedded

memory blocks. The channel memory block is placed at the

intersection of horizontal and vertical routing channels. Each

channel memory block is 4096 bits in size and can be

configured as asynchronous or synchronous Dual-Port RAM,

Single-Port RAM, Read-Only memory (ROM), or synchronous

FIFO memory. The memory organization is configurable as

4K × 1, 2K × 2, 1K × 4 and 512 × 8. The second type of memory

block is located within each LBC and is referred to as a cluster

memory block. Each LBC contains two cluster memory blocks

that are 8192 bits in size. Similar to the channel memory

blocks, the cluster memory blocks can be configured as

8K × 1, 4K × 2, 2K × 4 and 1K × 8 and can be configured as

either asynchronous or synchronous Single-Port RAM or

ROM.

The cluster memory powers up in an undefined state, but is set

to a user-defined known state during configuration. To facilitate

the use of look-up-table (LUT) logic and ROM applications, the

cluster memory blocks can be initialized with a given set of

data when the device is configured at power up. For LUT and

ROM applications, the user cannot write to memory blocks.

Channel Memory

The PSI architecture includes an embedded memory block at

each crossing point of horizontal and vertical routing channels.

The channel memory is a 4096-bit embedded memory block

that can be configured as asynchronous or synchronous

Single-Port RAM, Dual-Port RAM, ROM, or synchronous FIFO

memory.

Data, address, and control inputs to the channel memory are

driven from horizontal and vertical routing channels. All data

and FIFO logic outputs drive dedicated tracks in the horizontal

and vertical routing channels. The clocks for the channel

memory block are selected from four global clocks and pin

inputs from the horizontal and vertical channels. The clock

muxes also include a polarity mux for each clock so that the

user can choose an inverted clock.

Cluster Memory

Each LB cluster of the PSI device contains two 8192-bit cluster

memory blocks. Figure 7 is a block diagram of the cluster

memory block and the interface of the cluster memory block to

the cluster PIM.

The output of the cluster memory block can be optionally regis-

tered to perform synchronous pipelining or to register

asynchronous read and write operations. The output registers

contain an asynchronous RESET which can be used in any

type of sequential logic circuits (e.g., state machines).

Dual-Port (Channel Memory) Configuration

Each port has distinct address inputs, as well as separate data

and control inputs that can be accessed simultaneously. The

inputs to the Dual-Port memory are driven from the horizontal

and vertical routing channels. The data outputs drive

dedicated tracks in the routing channels. The interface to the

routing is such that Port A of the Dual-Port interfaces primarily

with the horizontal routing channel and Port B interfaces

There are four global clocks and one local clock available for

the input and the output registers. The local clock for the input

registers is independent of the one used for the output

registers. The local clock is generated in the user-design in a

macrocell or comes from an I/O pin.

primarily with the vertical routing channel.

.

W rite

Control

Logic

DIN[7:0]

A DDR[12:0]

W E

3

D

Q

C

2

8

C

1024x8

Asynchronous

SRAM

10

C

Cluster PIM

RXCLK, TXCLK ,

GCLK [1:0]

5:1

Local CLK

3

C

8

C

DOUT[7:0]

Read

Control

Logic

Q

D

C

R

RE SET

2

RXCLK, TXCLK,

C

G CLK[1:0]

5:1

Local CLK

3

C

Figure 7. Block Diagram of Cluster Memory Block

Document #: 38-02021 Rev. *C

Page 7 of 44

2.5-Gbps Programmable Serial Interface

The clocks for each port of the Dual-Port configuration are

selected from four global clocks and two local clocks. One

local clock is sourced from the horizontal channel and the

other from the vertical channel. The data outputs of the dual-

port memory can also be registered. Clocks for the output

registers are also selected from four global clocks and two

local clocks. One clock polarity mux per port allows the use of

true or complement polarity for input and output clocking

purposes.

port of the FIFO can also be registered. One clock polarity mux

per port allows using true or complement polarity for read and

write operations. The write operation is controlled by the clock

and the write enable pin. The read operation is controlled by

the clock and the read enable pin. The enable pins can be

sourced from horizontal or vertical channels.

Channel Memory Initialization

The channel memory powers up in an undefined state, but is

set to a user-defined known state during configuration. To facil-

itate the use LUT logic and ROM applications, the channel

memory blocks can be initialized with a given set of data when

the device is configured at power up. For LUT and ROM appli-

cations, the user cannot write to memory blocks.

Arbitration

The Dual-Port configuration of the Channel Memory Block

provides arbitration when both ports access the same address

at the same time. Depending on the memory operation being

attempted, one port always gets priority. See Table 1 for

details on which port gets priority for read and write operations.

An active-LOW ‘Address Match’ signal is generated when an

address collision occurs.

Channel Memory Routing Interface

Similar to LBC outputs, the channel memory blocks feature

dedicated tracks in the horizontal and vertical routing channels

for the data outputs and the flag outputs, as shown in Figure 8.

This allows the channel memory blocks to be expanded easily.

These dedicated lines can be routed to I/O pins as chip outputs

or to other LB clusters to be used in logic equations.

Table 1. Arbitration Result:

Address Match Signal Becomes Active

Port Port Result of

A

B

Arbitration

Comment

All channel memory

inputs are driven from

the routing channels

Read Read No arbitration Both ports read at the same

required

time

Write Read Port A gets

priority

IfPortBrequestsfirstthenitwill

read the current data. The

output will then change to the

newly written data by Port A

4096-bit Dual Port

Array

Global Clock

Signals

Configurable as

Async/Sync Dual Port or

Sync FIFO

GCLK[3:0]

Configurable as

4Kx1, 2Kx2, 1Kx4 and

512x8 block sizes

Read Write Port B gets

priority

IfPortArequestsfirstthenitwill

read the current data. The

output will then change to the

newly written data by Port B

All channel memory outputs

drive dedicated tracks in the

routing channels

Write Write Port A gets

priority

Port B is blocked until Port A is

finished writing

Horizontal Channel

FIFO (Channel Memory) Configuration

The channel memory blocks are also configurable as

synchronous FIFO RAM. In the FIFO mode of operation, the

channel memory block supports all normal FIFO operations

without the use of any general-purpose logic resources in the

device.

Figure 8. Block Diagram of Channel Memory Block

I/O Banks

The PSI interfaces the horizontal and vertical routing channels

to the pins through I/O banks. There are several I/O banks per

device as shown in Figure 9 and all I/Os from an I/O bank are

located in the same section of a package for PCB layout

convenience. There exist two kinds of I/O banks; fixed-signal

I/O banks and user programmable I/O banks.

The FIFO block contains all of the necessary FIFO flag logic,

including the read and write address pointers. The FIFO flags

include an empty/full flag (EF), half-full flag (HF), and program-

mable almost-empty/full (PAEF) flag output. The FIFO config-

uration has the ability to perform simultaneous read and write

operations using two separate clocks. These clocks may be

tied together for a single operation or may run independently

for asynchronous read/write (with reference to . each other)

applications. The data and control inputs to the FIFO block are

driven from the horizontal or vertical routing channels. The

data and flag outputs are driven onto dedicated routing tracks

in both the horizontal and vertical routing channels. This allows

the FIFO blocks to be expanded by using multiple FIFO blocks

on the same horizontal or vertical routing channel without any

speed penalty.

The first fixed signal bank is the Serial Signal Bank. This bank

includes all differential serial data transmission and receive

signals. The second bank is the Transceiver Control Bank.

This bank includes all static signal pins required for the config-

uration and operation of the transceiver blocks in each of the

PSI devices.

Each PSI device has several types of user programmable I/O

banks. The table in the next column (PSI programmable I/O

Banks) indicates the availability of each type of programmable

bank. Supported I/O standards for each bank are addressed

by the appropriate V_REFand V_CCIOvoltages. All the V_REFand

V_CCIOpins in an I/O bank must be connected to the same V_REF

and V_CCIOvoltage respectively. This requirement restricts the

number of I/O standards supported by an I/O bank at any given

In FIFO mode, the write and read ports are controlled by

separate clock and enable signals. The clocks for each port

are selected from four global clocks and two local clocks.

One local clock is sourced from the horizontal channel and the

other from the vertical channel. The data outputs from the read

Document #: 38-02021 Rev. *C

Page 8 of 44

2.5-Gbps Programmable Serial Interface

time. It also dictates the I/O standard used for the GCTL[3:0]

pins.

Table 2.

IO Standards

The architecture defining each programmable I/O bank

consists of several I/O cells, where each I/O cell contains an

input/output register, an output enable register, programmable

slew rate control and programmable bus hold control logic.

Each I/O cell drives a pin output of the device; the cell also

supplies an input to the device that connects to a dedicated

track in the associated routing channel.

I/O

Termination

V_CCIOVoltage (V_TT)

Standard

V_REF(V)

Min Max

LVTTL

N/A

3.3 V

3.0 V

2.5 V

1.8 V

3.3 V

N/A

1.5

LVCMOS

LVCMOS3

LVCMOS2

LVCMOS18

3.3V PCI

GTL+

There are four dedicated inputs (GCTL[3:0]) that are used as

Global Control Signals available to every I/O cell. These global

control signals may be used as output enables, register resets

and register clock enables as shown in Figure 10. Each global

control originates from a particular bank though they can be

used to control any I/O cell in the device. The input signalling

standard for a particular global control signal is same as the

I/O standard for bank from which it originates.

0.9

1.3

1.1

1.7

SSTL3 I

SSTL3 II

SSTL2 I

SSTL2 II

HSTL I

3.3 V

2.5 V

1.5 V

1.5

1.3

1.7

1.5

1.15

0.68

1.35

0.9

1.25

0.75

1.5

I/O Bank I/O Bank I/O Bank

HSTL II

0.9

HSTL III

HSTL IV

0.9

PSI

0.9

1.5

I/O Banks for Global Controls

GCTL[0] GCTL[1]

GCTL[2]

GCTL[3]

7

Bank

0

5

6

I/O Bank I/O Bank I/O Bank

I/O Banks for Global CLKs

GCLK[0]

Figure 9. PSI I/O Bank Block Diagram

PSI Programmable I/O Banks

GCLK[1]

Bank

0

5

Specific

Semi-

Device

25G01K100 Bank[0:3, 5] Bank[4]

_CCIO=3.3V

Flexible

Flexible V_CCIO

V_REF

Bank[6:7]

1.5V 0.68-0.90V

V

Document #: 38-02021 Rev. *C

Page 9 of 44

2.5-Gbps Programmable Serial Interface

Registered OE

Mux

OE Mux

D

Q

From

C

Output PIM

3

C

Input

Mux

RES

To Routing

Channel

Register Input

Mux

C

Output Mux

Bus

Hold

I/O

Register Enable

Mux

D

E

Q

Clock

C

Polarity

Mux

Slew

Rate

RES

3

C

Control

Clock Mux

C

2

3

Register Reset

Mux

C

Figure 10. Block Diagram of I/O Cell

I/O Cell

pull-up resistor, is a weak latch connected to the pin that does

not degrade the device’s performance. As a latch, bus-hold

maintains the last state of a pin when the pin is placed in a

high-impedance state, thus reducing system noise in bus-

interface applications. Bus-hold additionally allows unused

device pins to remain unconnected on the board, which is

particularly useful during prototyping as designers can route

new signals to the device without cutting trace connections to

V_CCor GND. For more information, see the application note

“Understanding Bus-Hold − A Feature of Cypress CPLDs.”

Figure 10 is a block diagram of the PSI I/O cell. The I/O cell

contains a three-state input buffer, an output buffer, and a

register that can be configured as an input or output register.

The output buffer has a slew rate control option that can be

used to configure the output for a slower slew rate. The input

of the device and the pin output can each be configured as

registered or combinatorial, however only one path can be

configured as registered in a given design.

The output enable can be selected from one of the four global

control signals or from one of two OCC signals. The output

enable can be configured as always enabled or always

disabled or it can be controlled by one of the remaining inputs

to the mux. The selection is done via a mux that includes V_CC

and GND as inputs.

Clocks

PSI has four primary internal global clock trees in the CPLD

portion of the device (INTCLK[3:0]). Each of these clock trees

distributes a clock signal to every cluster, channel memory,

and I/O cell in the CPLD. The global clock trees are designed

such that the clock skew is minimized while maintaining an

acceptable clock delay. Each of the internal global clocks can

choose from two input sources for the clock signal: a PLL

derived output or another one as shown in the table below.

One of the global clocks can be selected as the clock for the

I/O cell register. The clock mux output is an input to a clock

polarity mux that allows the input/output register to be clocked

on either edge of the clock.

Slew Rate Control

IN-

Device

TCLK[0] TCLK[1] TCLK[2] TCLK[3]

The output buffer has a slew rate control option. This allows

the ouput buffer to slew at a fast rate (3 V/ns) or a slow rate

(1 V/ns). All I/Os default to fast slew rate. For designs

concerned with meeting FCC emissions standards the slow

edge provides for lower system noise. For designs requiring

very high performance the fast edge rate provides maximum

system performance.

25G01K100 GCLK[0] GCLK[1] TXCLK RXCLK

GCLK[0] and GCLK[1] are accessible through pins on the

device package. TXCLK and RXCLK are provided internally to

the device. TXCLK (transmit clock) is intended for data

transfer from the CPLD block to the transmit channel of the

transceiver block. RXCLK (receive clock) is intended for data

transfer from the receive channel of the transceiver block to

the CPLD block. The TXCLK and RXCLK can also be used for

logic inside the CPLD block, e.g., for data processing.

Programmable Bus Hold

On each I/O pin, user-programmable bus-hold is included.

Bus-hold, which is an improved version of the popular internal

Document #: 38-02021 Rev. *C

Page 10 of 44

2.5-Gbps Programmable Serial Interface

Clock Tree Distribution

amount of spread on the input clock should be limited to 0.6%

of the fundamental frequency. Spread Aware feature is

supported only with X1, X2 and X4 multiply options.

The global clock tree performs two primary functions. First, the

clock tree generates the four internal global clocks by multi-

plexing four reference clocks derived from the Transceiver

Blocks and from the package pins and four PLL driven clocks.

Second, the clock tree distributes the four global clocks to

every cluster, channel memory, I/O block, and datapath cell on

the die. The global clock tree is designed such that the clock

skew is minimized while maintaining an acceptable clock

delay.

The Voltage Controlled Oscillator (VCO), the core of the PSI

PLL is designed to operate within the frequency range of 100

MHz to 266 MHz. Hence, the multiply option combined with

input (GCLK[0]) frequency should be selected such that this

VCO operating frequency requirement is met. This is demon-

strated in Table 3 (columns 1, 2, and 3).

Another feature of this PLL is the ability to drive the output

clock (INTCLK) off the PSI chip to clock other devices on the

board, as shown in Figure 11 below. This off-chip clock is half

the frequency of the output clock as it has to go through a

register (I/O register or a macrocell register).

Spread Aware™ PLL

The 2.5-Gbps PSI device features an on-chip PLL designed

using Spread Aware™ technology for low EMI applications. In

general, PLLs are used to implement time-division-multiplex

circuits to achieve higher performance with fewer device

resources.

This PLL can also be used for board deskewing purpose by

driving a PLL output clock off-chip, routing it to the other

devices on the board and feeding it back to the PLL’s external

feedback input (GCLK[1]). When this feature is used, only

limited multiply, divide and phase shift options can be used.

Table 3 describes the valid multiply and divide options that can

be used without an external feedback. Table 4 describes the

valid multiply and divide options that can be used with an ex-

ternal feedback.

For example, a system that operates on a 32-bit data path that

runs at 40 MHz can be implemented with 16-bit circuitry that

runs internally at 80 MHz. PLLs can also be used to take

advantage of the positioning of the internally generated clock

edges to shift performance towards improved setup, hold or

clock-to-out times.

Table 5 describes the valid phase shift options that can be

used with or without an external feedback.

There are several frequency multiply (X1, X2, X3, X4, X5, X6,

X8, X16) and divide (/1, /2, /3, /4, /5, /6, /8, /16) options

available to create a wide range of clock frequencies from a

single clock input (GCLK[0]). For increased flexibility, there are

seven phase shifting options which allow clock skew/de-skew

by 45°, 90°, 135°, 180°, 225°, 270°, or 315°.

Table 6 is an example of the effect of all the available divide

and phase shift options on a VCO output of 250 MHz. It also

shows the effect of division on the duty cycle of the resultant

clock. Note that the duty cycle is 50-50 when a VCO output is

divided by an even number. Also note that the phase shift

applies to VCO output and not to the divided output.

The Spread Aware feature refers to the ability of the PLL to

track a spread-spectrum input clock such that its spread is

seen on the output clock with the PLL staying locked. The total

o ff- c h ip s ig n a l (e x te rn a l fe e d b a c k )

IN T C L K 0 , IN T C L K 1 , IN T C L K 2 , IN T C L K 3

A n y R e g is te r

S e n d

a g lo b a l

c lo c k o ff c h ip

G C L K 1

N o r m a l I/O s ig n a l p a th

L o c k D e te c t/IO p in

C

C lo c k T re e

D e la y

P h a s e s e le c tio n

D iv id e

2

÷

1 - 6 ,8 ,1 6

C

IN T C L K 0

G C L K 0

fb

2

P h a s e s e le c tio n

L o c k

C

D iv id e

÷

1 -6 ,8 ,1 6

C lk 0 ⁰

IN T C L K 1

C lk 4 5 ⁰

G C L K 1

C

lk 9 0 ⁰

P h a s e s e le c tio n

2

G C L K 0

S o u r c e

C lo c k

C

C lk 1 3 5 ⁰

C lk 1 8 0 ⁰

C lk 2 2 5 ⁰

C lk 2 7 0 ⁰

C lk 3 1 5 ⁰

D iv id e

1 - 6 ,8 ,1 6

IN T C L K 2

T X C L K

2

P L L

C

X 1 , X 2 , X 3 , X 4 , X 5 ,

X 6 , X 8 , X 1 6

P h a s e s e le c tio n

D iv id e

÷

1 -6 ,8 ,1 6

IN T C L K 3

R X C L K

2

C

Figure 11. Block Diagram of Spread Aware PLL for CYP25G01K100

Document #: 38-02021 Rev. *C

Page 11 of 44

2.5-Gbps Programmable Serial Interface

Table 3. PLL Multiply and Divide Options—without INTCLK1 Feedback

Valid Multiply Options

Valid Divide Options

Input Frequency

(GCLK[0])

VCO Output

Value Frequency (MHz)

Output Frequency (INTCLK[3:0]) Off-chip Clock

f

DC–12.5

100–133

50–133

_PLLI(MHz)

Value

f_PLLO(MHz)

DC–12.5

6.25–133

6.25–266

Frequency

N/A

1

N/A

DC–6.25

100–133

100–266

200–266

1–6, 8, 16

3.125–66

3.125–133

3.1–266

2

33.3–88.7

25–66

3

4

3.125–133

3.1–133

20–53.2

5

16.6–44.3

12.5–33

6

3.1–133

8

3.125–133

12.5–16.625

16

Table 4. PLL Multiply and Divide Options—with External Feedback

Valid Multiply Options

Valid Divide Options

Input (GCLK) Frequency

f_PLLI(MHz)

VCO Output

Frequency (MHz)

Output (INTCLK) Frequency

f_PLLO(MHz)

Off-chip Clock

Frequency

Value

50–133

1

100–266

125–266

150–266

200–266

1

2

3

4

5

6

8

100–266

50–133

25–66.5

50–133

25–66.5

16.67–44.33

12.5–33.25

12.5–26.6

12.5–22.17

12.5–16.63

33.33–88.66

25–66.5

16.67–44.33

12.5–33.25

12.5–26.6

12.5–22.17

12.5–16.63

25–53.2

25–44.34

25–33.25

Table 5. PLL Phase Shift Options with and without INTCLK1 Feedback

Without External Feedback

With External Feedback

0°,45°, 90°, 135°, 180°, 225°, 270°, 315°

0°

Table 6. Timing of Clock Phases for all Divide Options for a VCO Output Frequency of 250 MHz

Divide

Factor

Period

(ns)

Duty

Cycle%

0°

(ns)

45°

(ns)

90°

(ns)

135°

(ns)

180°

(ns)

225°

(ns)

270°

(ns)

315°

(ns)

1

2

4

40–60

50

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

8

3

12

16

20

24

32

64

33–67

50

4

5

40–60

50

6

8

50

16

50

Timing Model

LBs within the same cluster, as well as separate LBs within

different clusters. This is shown as t_SCSand t_SCS2in Figure 12.

For combinatorial paths, any input to any output (from corner

to corner on the device), incurs a worst-case delay in the 100K

gate PSI regardless of the amount of logic or which horizontal

and vertical channels are used. This is the t_PDshown in

Figure 12. For synchronous systems, the input set-up time to

the output macrocell register and the clock to output time are

shown as the parameters t_MCSand t_MCCOshown in the

One important feature of the 2.5-Gbps PSI is the simplicity of

its timing. All combinatorial and registered/synchronous

delays are worst case and system performance is static (as

shown in the AC specs section) as long as data is routed

through the same horizontal and vertical channels. Figure 12

illustrates the true timing model for the programmable LB of

the device. For synchronous clocking of macrocells, a delay is

incurred from macrocell clock to macrocell clock of separate

Document #: 38-02021 Rev. *C

Page 12 of 44

2.5-Gbps Programmable Serial Interface

Figure 12. These measurements are for any output and

synchronous clock, regardless of the logic placement.

• no added delay for steering product terms

• no added delay for sharing product terms

• no output bypass delays.

PSI features:

• no dedicated vs. I/O pin delays

• no penalty for using 0–16 product terms

The simple timing model of the 2.5-Gbps PSI eliminates

unexpected performance penalties.

t_SCS

GCLK[1:0], RXCLK, TXCLK

4

LB 0

LB 1

LB 2

LB 3

LB 7

LB 6

LB 5

LB 4

LB 0

LB 1

LB 2

LB 3

LB 7

LB 6

LB 5

LB 4

LB 0

LB 1

LB 2

LB 3

LB 7

LB 6

LB 5

LB 4

LB 0

LB 1

LB 2

LB 3

LB 7

LB 6

LB 5

LB 4

Channel

RAM

Channel

RAM

Channel

RAM

Channel

RAM

PIM

t_MCS

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

8 Kb

SRAM

8 Kb

SRAM

GCLK[1:0], RXCLK, TXCLK

4

t_SCS2

LB 0

LB 1

LB 2

LB 3

LB 7

LB 6

LB 5

LB 4

LB 0

LB 1

LB 2

LB 3

LB 7

LB 6

LB 5

LB 4

LB 0

LB 1

LB 2

LB 3

LB 7

LB 6

LB 5

LB 4

LB 0

LB 1

LB 2

LB 3

LB 7

LB 6

LB 5

LB 4

Channel

RAM

Channel

RAM

Channel

RAM

Channel

RAM

PIM

t_PD

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

GCLK[1:0], TXCLK, RXCLK

4

LB 0

LB 1

LB 2

LB 3

LB 7

LB 6

LB 5

LB 4

LB 0

LB 1

LB 2

LB 3

LB 7

LB 6

LB 5

LB 4

LB 0

LB 1

LB 2

LB 3

LB 7

LB 6

LB 5

LB 4

LB 0

LB 1

LB 2

LB 3

LB 7

LB 6

LB 5

LB 4

Channel

RAM

Channel

RAM

Channel

RAM

Channel

RAM

PIM

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

t_MCCO

Figure 12. Timing Model for 100K gate PSI Devices

Document #: 38-02021 Rev. *C

Page 13 of 44

2.5-Gbps Programmable Serial Interface

the bit-rate clock generated by the Transmit PLL clock multi-

plier. TXD[15] is the most significant bit of the output word, and

is transmitted first on the serial interface.

Serial Transceiver Operation

The PSI transceiver block is a highly configurable transceiver

designed to support reliable transfer of large quantities of data,

using high-speed serial links, from one or multiple sources to

one or multiple destinations. This block supports serialization

of a 16-bit dataword in the transmit side, and clock recovery

and deserialization on the receive side. The interconnection

between the serial transceiver block and the embedded

programmable logic has to be specified using hardware

description in Warp Software.

Serial Output Driver

The serial interface Output Driver makes use of high-perfor-

mance differential CML (Current Mode Logic) to provide a

source-matched driver for the transmission lines. This driver

receives its data from the Transmit Shifters or the receive

loopback data. The outputs have signal swings equivalent to

that of standard LVPECL drivers, and are capable of driving

AC-coupled optical modules or transmission lines.

High-speed PSI Transceiver Operation

Receive Data Path

Registering TXD[15:0] Data Before it enters Serial

Transceiver Block

Serial Line Receivers

Before the 16-bit parallel input data TXD[15:0] enters the serial

transceiver block, it is required to register this data in a

standard data path cell without any output enables. It is also

required that these datapath cells are clocked on the rising

edge of the global TXCLK.

A differential line receiver, IN±, is available for accepting the

input serial data stream. The serial line receiver inputs can

accommodate high wire interconnect and filtering losses or

transmission line attenuation (V_SE> 25 mV, or 50 mV peak-to-

peak differential), and can be AC-coupled to +3.3V or +5V

powered fiber-optic interface modules. The common-mode

tolerance of these line receivers accommodates a wide range

of signal termination voltages.

Transmit Data Path

The registered 16-bit parallel TXD input data from the

programmable LB of the device is input into the input register

of the serial transceiver block. This input register is clocked

using TXCLK, which is one of the four global clocks of the

programmable logic.

Lock to Data Control

Line Receiver routed to the clock and data recovery PLL is

monitored for

• status of signal detect (SD) pin

• status of LOCKREF pin

• received data stream outside normal frequency range

(±100 ppm).

Phase-Align Buffer

Data from the input register is passed to a phase-align buffer

(FIFO). This buffer is used to absorb clock phase differences

between the transmit input clock entering the serial transceiver

and the internal character clock.

This status is presented on the LFI (Line Fault Indicator) output

signal, which changes asynchronously in the cases when SD

or LOCKREF goes from HIGH to LOW. Otherwise, it changes

synchronously to the REFCLK.

Initialization of the phase-align buffer takes place when the

FIFO_RST signal is asserted LOW. When FIFO_RST is

returned HIGH, the present input clock phase relative to

TXCLK is set. Once set, the input clock is allowed to skew in

time up to half a character period in either direction relative to

REFCLK (i.e., ±180). This time shift allows the delay path of

the character clock (relative to REFCLK) to change due to

operating voltage and temperature while not effecting the

desired operation. FIFO_RST is an asynchronous signal.

FIFO_ERR is the transmit FIFO Error indicator. When HIGH,

the transmit FIFO has either under or overflowed. The FIFO

can be externally reset or logically reset by PSI logic to clear

the error indication or if no action is taken, the internal clearing

mechanism will clear the FIFO in nine clock cycles. When the

FIFO is being reset, the output data is 1010.

Clock/Data Recovery

The extraction of a bit-rate clock and recovery of data bits from

received serial stream is performed by a Clock/Data Recovery

(CDR) block. The clock extraction function is performed by

high-performance embedded PLL that tracks the frequency of

the incoming bit stream and aligns the phase of the internal bit-

rate clock to the transitions in the selected serial data stream.

CDR accepts a character-rate (bit-rate ÷ 16) reference clock

on the REFCLK input. This REFCLK input is used to ensure

that the VCO (within the CDR) is operating at the correct

frequency (rather than some harmonic of the bit-rate), to

improve PLL acquisition time, and to limit unlocked frequency

excursions of the CDR VCO when no data is present at the

serial inputs.

Transmit PLL Clock Multiplier

The Transmit PLL Clock Multiplier accepts an external clock at

the REFCLK input, and multiplies that clock by 16 to generate

a bit-rate clock (2.5 Gbps) for use by the transmit shifter. The

operating serial signaling rate and allowable range of REFCLK

frequencies are listed in the High-speed PSI Transceiver

Timing Parameter Values table under “REFCLK Timing

Parameters” (see page 24). The REFCLK± input is a standard

LVPECL input.

Regardless of the type of signal present, the CDR will attempt

to recover a data stream from it. If the frequency of the

recovered data stream is outside the limits set by the range

controls, the CDR PLL will track REFCLK instead of the data

stream. When the frequency of the selected data stream

returns to a valid frequency, the CDR PLL is allowed to track

the received data stream. The frequency of REFCLK is

required to be within ±100 ppm of the frequency of the clock

that drives the REFCLK signal of the remote transmitter to

ensure a lock to the incoming data stream.

Serializer

The parallel data from the phase-align buffer is passed to the

Serializer which converts the parallel data to serial data using

Document #: 38-02021 Rev. *C

Page 14 of 44

2.5-Gbps Programmable Serial Interface

External Filter

receive recovered clock is also divided down and presented to

the low speed clock output (RXCLK).

The CDR circuit uses external capacitors for the PLL filter. A

0.1-µF capacitor needs be connected between RXCN1 and

RXCP1. Similarly a 0.1-µF capacitor needs to be connected

between RXCN2 and RXCP2. The recommended packages

and dielectric material for these capacitors are 0805 X7R or

0603 X7R. These capacitors should be surface mount

packages and be placed as close as possible to the device.

Equipment Loopback (Diagnostic Loopback With Retiming)

When the DIAGLOOP signal is set HIGH, transmit data is

looped back to the RX PLL, replacing IN±. Data is looped back

from the parallel TX inputs to the parallel RX outputs. The data

is looped back at the internal serial interface and goes through

transmit shifter and the receive CDR. SD is ignored in this

mode.

Deserializer

The CDR circuit extracts bits from the serial data stream and

clocks these bits into the Deserializer at the bit-clock rate. The

Deserializer converts serial data into parallel data. RXD[15] is

the most significant bit of the output word and is received first

on the serial interface. This RXD[15:0] data is output regis-

tered and fed to the programmable LB of the device.

Line Loopback Mode (Non-retimed Data)

When the LOOPA signal is set HIGH, the RX serial data is

directly buffered out to the transmit serial data. The data at the

serial output is not retimed.

Loop Timing Mode

Registering RXD[15:0] Data Before It Enters

Programmable LB

When the LOOPTIME signal is set HIGH, the TX PLL is

bypassed and receive bit-rate clock is used for transmit side

shifter.

Before the RXD[15:0] enters the programmable LB it is

required to register these signals in standard datapath cells

without any output enables. It is also required to clock these

standard datapath cells using the rising edge of the global

RXCLK.

Reset Modes for the serial transceiver

All logic circuits in the serial transceiver block can be reset

using RESET and FIFO_RST signals. When RESET is set

LOW, all logic circuits in the serial transceiver except FIFO are

internally reset. When FIFO_RST is set LOW, the FIFO logic

is reset.

Loopback/Timing Modes

High-speed PSI supports various loopback modes as

described below.

Power-down Mode for serial transceiver

Facility Loopback (Line Loopback With Retiming)

High-speed PSI transceiver block provide a power-down

signal PWRDN. When LOW, this signal powers down the

entire serial transceiver block to a minimal power dissipation

state. RESET and FIFO_RST signals should be asserted

LOW along with PWRDN signal to ensure low-power

dissipation.

When the LINELOOP signal is set HIGH, the Facility Loopback

mode is activated and the high-speed serial receive data (IN±)

is presented to the high-speed transmit output (OUT±) after

retiming. In Facility Loopback mode, the high-speed receive

data (IN±) is also converted to parallel data and presented to

the low-speed receive data output pins (RXD[15:0]). The

Document #: 38-02021 Rev. *C

Page 15 of 44

2.5-Gbps Programmable Serial Interface

REFCLK+

TXD[0:15] FIFO_ERR TXCLK

16

RXCLK

RXD[0:15]

16

TXCLK

FIFO_RST

Output

Register

Input

Register

/16

TX PLL

X16

Shifter

FIFO

/16

Recovered

Bit-Clock

Shifter

RX CDR PLL

Lock-to-Ref

LOOPTIME

DIAGLOOP

LINELOOP

LOOPA

Lock-to-Data/

Clock Control

Logic

PWRDN LOCKREF

LFI

RESET

OUT+

SD

IN+

Figure 13. High-speed PSI Transceiver Logic Block Diagram^[2]

Note:

2. All signal names outside the dotted box have dedicated pins in the package. Other signals are internal and must be port-mapped to programmable logic using

hardware description in Warp software.

Document #: 38-02021 Rev. *C

Page 16 of 44

2.5-Gbps Programmable Serial Interface

IEEE 1149.1-compliant JTAG Operation

There are multiple configuration options available for issuing

the IEEE std 1149.1 JTAG instructions to the PSI. The first

method is to use a PC with the C3 ISR programming cable and

software. With this method, the ISR pins of the PSI devices in

the system are routed to a connector at the edge of the printed

circuit board. The C3 ISR programming cable is then

connected between the PC and this connector. A simple

configuration file instructs the ISR software of the

programming operations to be performed on the PSI devices

in the system. The ISR software then automatically completes

all of the necessary data manipulations required to accomplish

configuration, reading, verifying, and other ISR functions.

The 2.5-Gbps PSI has an IEEE standard 1149.1 JTAG

interface for both Boundary Scan and ISR operations.

Four dedicated pins are reserved on each device for use by

the Test Access Port (TAP).

The serial transceiver block of this device does not support

JTAG since most of the blocks in the serial transceiver block

are analog. Hence the serial transceiver portion is not a part

of the JTAG test chain.

Boundary Scan

The 2.5-Gbps PSI supports Bypass, Sample/Preload, Extest,

Intest, Idcode and Usercode boundary scan instructions. The

JTAG interface is shown in Figure 14.

For systems with embedded controllers/processors, a

controller/processor may be used to configure the PSI. The

PSI ISR software assists in this method by converting the

device HEX file into the ISR serial stream that contains the ISR

instruction information and the addresses and data of

locations to be configured. The controller/processor then

simply directs this ISR stream to the chain of PSI devices to

complete the desired reconfiguration or diagnostic operations.

Contact your local sales office for information on availability of

this option.

Instruction Register

TDI

TDO

Bypass Reg.

JTAG

TMS

TAP

CONTROLLER

Boundary Scan

idcode

TCLK

Programming

The on-chip EEPROM device of the CPLD block is

programmed by issuing the appropriate IEEE std 1149.1 JTAG

instruction. This can be done automatically using ISR/STAPL

software. The configuration bits are sent from a PC through

the JTAG port into the PSI via the C3 ISR programming cable.

The data is then passed to the internal EEPROM through the

Non-Volatile (NV) port of the CPLD block. For more infor-

mation on how to program the PSI through ISR/STAPL, please

refer to the ISR/STAPL User Guide.

Usercode

ISR Prog.

Data Registers

Figure 14. JTAG Interface

In-System Reprogramming™ (ISR™)

Third-Party Programmers

In-System Reprogramming is the combination of the capability

to program or reprogram a device on-board, and the ability to

support design changes without changing the system timing

or device pinout. This combination means design changes

during debug or field upgrades do not cause board respins.

The 2.5-Gbps PSI implements ISR by providing a JTAG

compliant interface for on-board programming, robust routing

resources for pinout flexibility, and a simple timing model for

consistent system performance.

Cypress support is available on a wide variety of third-party

programmers. All major programmers (including BP Micro,

System General, Hi-Lo) support the PSI family.

Development Software Support

Warp

Warp is a state-of-the-art design environment for designing

with Cypress programmable logic. Warp utilizes a subset of

IEEE 1076/1164 VHDL and IEEE 1364 as the Hardware

Description Language (HDL) for design entry. Warp accepts

VHDL or Verilog input, synthesizes and optimizes the entered

design, and outputs a configuration bitstream for the desired

PSI device. For simulation, Warp provides a graphical

waveform simulator as well as VHDL and Verilog Timing

Models.

Configuration

The CPLD block in the 2.5-Gbps PSI is designed with Self-

Boot capability. An embedded on-chip EEPROM is used to

store configuration data. For PSI devices, programming is

defined as the loading of a user’s design into the internal

EEPROM. Configuration, on the other hand, is defined as the

loading of a user’s design into the volatile CPLD block.

VHDL and Verilog are open, powerful, non-proprietary

Hardware Description Languages (HDLs) that are standards

for behavioral design entry and simulation. HDL allows

designers to learn a single language that is useful for all facets

of the design process.

Configuration can begin in two ways. It can be initiated by

toggling the Reconfig pin from LOW to HIGH, or by issuing the

appropriate IEEE std 1149.1 JTAG instruction to the PSI

device via the JTAG interface. There are two IEEE std 1149.1

JTAG instructions that initiate configuration of the PSI. The

Self Config instruction causes the PSI to (re)configure with

data store in the internal EEPROM. The Load Config

instruction causes the PSI to (re)configure with data provided

by other sources such as a PC, Automatic Test Equipment

(ATE), or an embedded micro-controller/processor via the

JTAG port.

Third-party Software

Cypress products are supported in a number of third-party

design entry and simulation tools. Refer to the third-party

software data sheet or contact your local sales office for a list

of currently supported third party vendors.

Document #: 38-02021 Rev. *C

Page 17 of 44

2.5-Gbps Programmable Serial Interface

Output Current into LVCMOS Outputs (LOW)............. 30 mA

DC Input voltage...............................................–0.5V to 4.5V

DC Current into Outputs...................... ...................± 20 mA^[3]

Maximum Ratings

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Static Discharge Voltage........................................... > 1100V

(per MIL-STD-883, Method 3015)

Storage Temperature .................................–65°C to +150°C

Soldering Temperature.................................................220°C

Latch-up Current.....................................................> 200 mA

Ambient Temperature with

Power Applied...............................................–40°C to +85°C

Operating Range

Junction Temperature ..................................................135°C

V_CCrelative to Ground Potential...................... –0.5V to 4.2V

Ambient

Temperature

Range

V_CC

V_DDQ

V_CCIOrelative to Ground Potential................... –0.5V to 4.6V

Commercial

0°C to +70°C

3.3V ± 10% 1.4V to 1.6V

DC Voltage Applied to Outputs in High-Z State –0.5V to 4.5V

Operating Range

Ambient

Temperature

Junction

Temperature

Output

Condition

V_CCJTAG/

V_CCCNFGV_CCPLL

Range

V_CCIO

V_CC

V_CEP

Commercial

0°C to +70°C

0°C to +85°C

3.3V

2.5V

1.8V

1.5V

3.3V ± 0.3V

2.5V ± 0.2V

1.8V ± 0.15V

1.5V ± 0.1V

3.3V

±

0.3V

Same as Same as

3.3V ±

0.3V

V_CCIO

V_CC

Test Waveforms to High-speed PSI Transceiver Block

V

3.0V

ICHH

3.0V

V =1.4V

2.0V

0.8V

2.0V

0.8V

80%

V =1.4V

th

20%

≤ 150 ps

20%

≤ 150 ps

GND

< 1 ns

V

ICLL

< 1 ns

(a) LVTTL Input Test Waveform

(b) CML Input Test Waveform

V

IEHH

80%

20%

V

IELL

≤ 1 ns

(c) LVPECL Input Test Waveform

AC Test Loads to High-speed Transceiver Block

3.3V

R1

R2

OUTPUT

R1 = 330Ω

R2 = 510Ω

L

OUT+

C

L

R = 100Ω

L

C ≤ 10 pF

R

L

OUT–

(Includes fixture and

probe capacitance)

(a) TTL AC Test Load

(b) CML AC Test Load

Note:

3. DC current into outputs is 36 mA with HSTL III and 48 mA with HSTL IV.

Document #: 38-02021 Rev. *C

Page 18 of 44

2.5-Gbps Programmable Serial Interface

Electrical Characteristics Over the Operating

Range

DC Characteristics

V_CCIO= 3.3V V_CCIO= 2.5V V_CCIO= 1.8V

Parameter Description

Data Retention V_CCVoltage (config

Test Conditions

Min. Max. Min. Max. Min. Max. Unit

1.5

V

V_DRINT

data may be lost below this)

DataRetentionV_CCIOVoltage(config

data may be lost below this)

1.2

V

V_DRIO

I_IX

Input Leakage Current

GND ≤ V_I≤ 3.6V

–10

10

–10

10

–10

10

µA

I_OZ

Output Leakage Current

Output Short Circuit Current

GND ≤ V_O≤ V_CCIO

[4]

I_OS

V_CCIO= Max., V_OUT= 0.5V

–160

–160 mA

µA

I_BHL

Input Bus Hold LOW Sustaining Current V_CC= Min., V_PIN= V_IL

Input Bus Hold HIGH Sustaining Current V_CC= Min., V_PIN= V_IH

Input Bus Hold LOW Overdrive Current V_CC= Max.

+40

+30

+25

I_BHH

–40

–30

–25

µA

I_BHLO

I_BHHO

+250

+200

+150 µA

–150 µA

Input Bus Hold HIGH Overdrive Current V_CC= Max.

–250

–200

Capacitance

Parameter

C_I/O

Description

Input/Output Capacitance

PCI compliant I/O Capacitance

Clock Signal Capacitance

PECL Input Capacitance

SD Pin Input Capacitance

CML Input Capacitance

Test Conditions

Min.

Max.

10

8

Unit

pF

V_in= V_CCIO@ f = 1 MHz 25°C

V_CC= 3.3V @ f = 1 MHz 25°C

C_PCI

C_CLK

5

12

4

C_INPECL

C_SD1

5

C_INC1

4

DC Characteristics (I/O)

V_REF(V)

V_OH(V)

V_OH(Min.) @ I_OL

V_OL(V)

V_IH(V)

Max.

V_IL(V)

Input/Output

Standard

V_CCIO

(V)

@ I_OH

=

V_OL(Max.) Min.

Min.

Max.

LVTTL –2 mA

LVTTL –4 mA

LVTTL –6 mA

LVTTL –8 mA

LVTTL –12 mA

LVTTL –16 mA

LVTTL –24 mA

LVCMOS

N/A

3.3

3.0

2.5

–2 mA

–4 mA

–6 mA

–8 mA

2.4

2 mA

4 mA

6 mA

8 mA

0.4

0.2

0.4

0.7

0.45

2.0 V V_CCIO+ 0.3 –0.3V 0.8V

2.0V V_CCIO+ 0.3 –0.3V 0.8V

1.7V V_CCIO+ 0.3 –0.3V 0.7V

–12 mA

–16 mA

–24 mA

12 mA

16 mA

24 mA

–0.1 mA V_CCIO– 0.2V 0.1 mA

LVCMOS3

–0.1 mA

–1.0 mA

–2.0 mA

2.1

2.0

1.7

0.1 mA

1.0 mA

2.0 mA

LVCMOS2

1.8

3.3

– 2 mA V_CCIO–0.45V 2.0 mA

0.65V_CV_CCIO+0.3 –0.3V 0.35V

LVCMOS18

3.3V PCI

CIO

CCIO

–0.5 mA 0.9V_CCIO1.5 mA

0.1V_CCIO0.5V_CCV_CCIO+0.5 –0.5V 0.3V_C

IO

CIO

Note:

4. Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. V_OUT=0.5V has been chosen to avoid test

problems caused by tester ground degradation. Tested initially and after any design or process changes that may affect these parameters.

Document #: 38-02021 Rev. *C

Page 19 of 44

2.5-Gbps Programmable Serial Interface

DC Characteristics (I/O)

V_REF(V)

V

_OH(V) V_OL(V)

V_IH(V)

Max.

V_IL(V)

Min. Max.

Input/Output

Standard

V_CCIO

(V)

@ I_OH

=

V_OH(Min.) @ I_OL= V_OL(Max.) Min.

GTL+

0.9 1.1 Note 5

36 mA^[6]

8 mA

0.6

0.7

V_REF

0.2

+

V_REF

0.2

–

SSTL3 I

SSTL3 II

SSTL2 I

SSTL2 II

HSTL I

1.3 1.7

1.15 1.35

0.68 0.9

3.3

2.5

1.5

–8 mA

V_CCIO–1.1V

V_REF

0.2

V_CCIO+0.3 –0.3V V_REF

0.2

–16 mA V_CCIO–0.9V 16 mA

–7.6 mA V_CCIO–0.62V 7.6 mA

–15.2 mA V_CCIO–0.43V 15.2 mA

0.5

V_REF

0.2

V_CCIO+0.3 –0.3V V_REF

0.2

0.54

0.35

0.4

V_REF

0.18

V_CCIO+0.3 –0.3V V_REF

0.18

V_REF+

V_CCIO+0.3 –0.3V V_REF–

0.18

–8 mA

V_CCIO–0.4V

8 mA

V_REF+

V_CCIO+0.3 –0.3V V_REF–

0.1

HSTL II

HSTL III

HSTL IV

–16 mA V_CCIO–0.4V 16 mA

0.4

V_REF

0.1

+

V_CCIO+0.3 –0.3V V_REF

–

0.1

–8 mA

V_CCIO–0.4V 24 mA

V_CCIO–0.4V 48 mA

0.4

V_REF

0.1

V_CCIO+0.3 –0.3V V_REF

0.1

0.4

V_REF

0.1

V_CCIO+0.3 –0.3V V_REF

0.1

Parameter

SD Pin LVTTL Inputs

Description

Test Conditions

Min.

Max.

Unit

V_IHT

V_ILT

I_IHT

I_ILT

Input HIGH Voltage

Input LOW Voltage

Low = 2.0V, High = V_CC+ 0.5V

Low = –3.0V, High = 0.8V

V_CC= Max., V_IN= V_CC

V_CC= Max., V_IN= 0V

2.0

V_CC– 0.3

0.8

V

–0.3

Input HIGH Current

Input LOW Current

50

µA

–50

REFCLK LVPECL-compatible Inputs

V_INSGLE

V_DIFFE

V_IEHH

V_IELL

I_IEH

Input Single-ended Swing

Input Differential Voltage

Highest Input HIGH Voltage

Lowest Input LOW Voltage

Input HIGH Current

200

400

600

mV

V

1200

V_CC– 1.2 V_CC– 0.3

V_CC– 2.0 V_CC– 1.45

V

V_IN= V_IEHHMax.

V_IN= V_IELLMin.

750

µA

I_IEL

Input LOW Current

–200

Transmitter Differential CML-compatible Outputs

V_OHC

V_OLC

I_ACCM

V_ACCM

Z_D

Output HIGH Voltage (V_CCReferenced)

Output LOW Voltage (V_CCReferenced)

AC Common Mode Current

100Ω differential load

V_CC– 0.5 V_CC– 0.15

V

V_CC– 1.2 V_CC– 0.7

5

µA

mV

Ω

AC Common Mode Voltage

25

Differential Output Impedance

Single Ended Output Impedance

75

30

125

75

Z_SE

Ω

Single Ended Output Impedance Matching

Within a Single Lane

Z_MSE

10

%

I_DSHORT

V_DIFFOC

Short Circuit Current

–100

1000

500

100

1600

800

mA

mV

Output Differential Swing

Output Single Ended Swing

100Ω differential load

V_SGLOC

Notes:

5. See “Power-up Sequence Requirements” for V_CCIOrequirement.

6. 25Ω resistor terminated to termination voltage of 1.5V.

Document #: 38-02021 Rev. *C

Page 20 of 44

2.5-Gbps Programmable Serial Interface

Parameter

Description

Test Conditions

Min.

Max.

V_CC

30

Unit

Receiver Differential CML Compatible Inputs

V_ICHH

V_ICLL

Z_VTT

Highest Input HIGH Voltage

Lowest Input LOW Voltage

V_TTImpedance

V

1.2

Ω

L_DR

Differential Return Loss

Common Mode Return Loss

Voltage Threshold

10

6

dB

mV

V

L_CMR

V_RSD

V_RMAX

V_DIFFC

V_INSGLC

20

Maximum Input Voltage (p-p)

Input Differential Voltage

Input Single-ended Swing

1.6

50

25

2000

1000

mV

Configuration Parameters

Parameter

Description

Min.

Unit

ns

t_RECONFIG

Reconfig pin LOW time before it goes HIGH

200

IN +

IN -

V

I N S G L C

V

D

V

_{D IF F C}= ( IN + ) - ( IN - )

O U T +

O U T -

V

S G L O C

V

D

V

_{D I F F O C}= ( O U T + ) - ( O U T - )

Figure 15. Differential Parameters Waveforms

Power-up Sequence Requirements

• V_CCpins can be powered up in any order. This includes

V_CC, V_DDQ, V_CCIO, V_CCJTAG, V_CCCNFG, V_CCPLLand VCEP.

• Upon power-up, all the outputs remain three-stated until all

the V_CCpins have powered up to the nominal voltage and

the part has completed configuration.

• All V_CCIOs on a bank should be tied to the same potential

and powered up together.

• All V_CCIOs (even the unused banks) need to be powered up

• The part will not start configuration until V_CC, V_DDQ, V_CCIO

V_CCJTAG, V_CCCNFG, V_CCPLLand VCEP have reached

nominal voltage.

,

to at least 1.5V before configuration has completed.

• Maximum ramp time for all V_CCs should be 0V to nominal

voltage in 100 ms.

Document #: 38-02021 Rev. *C

Page 21 of 44

2.5-Gbps Programmable Serial Interface

Switching Characteristics

Timing Parameter Values ^[7]

Parameter

Description

Min. Max. Unit

Combinatorial Mode Parameters

t_PD

Delay from any pin input, through any cluster on the channel associated with that pin input,

to any pin output on the horizontal or vertical channel associated with that cluster

7.5

ns

t_EA

Global control to output enable

5.0

ns

t_ER

Global control to output disable

t_PRR

Asynchronous macrocell RESET or PRESET recovery time from any pin input on the

horizontal or vertical channel associated with the cluster the macrocell is in

6.0

t_PRO

Asynchronous macrocell RESET or PRESET from any pin input on the horizontal or vertical 10

channel associated with the cluster that the macrocell is in to any pin output on those same

channels

ns

t_PRW

Asynchronous macrocell RESET or PRESET minimum pulse width, from any pin input to a 3.6

macrocell in the farthest cluster on the horizontal or vertical channel the pin is associated with

Synchronous Clocking Parameters

t_MCS

t_MCH

t_MCCO

t_IOS

Set-up time of any input pin to a macrocell in any cluster on the channel associated with that 3.0

input pin, relative to a global clock

ns

Hold time of any input pin to a macrocell in any cluster on the channel associated with that

input pin, relative to a global clock

0.0

Global clock to output of any macrocell to any output pin on the horizontal or vertical channel

associated with the cluster that macrocell is in

6.0

4.0

Set-up time of any input pin to the I/O cell register associated with that pin, relative to a global 1.0

clock

t_IOH

Hold time of any input pin to the I/O cell register associated with that pin, relative to a global 1.0

clock

t_IOCO

t_SCS

Clock to output of an I/O cell register to the output pin associated with that register

ns

Macrocell clock to macrocell clock through array logic within the same cluster

3.5

4.5

t_SCS2

Macrocell clock to macrocell clock through array logic in different clusters on the same

channel

t_ICS

I/O register clock to any macrocell clock in a cluster on the channel the I/O register is

associated with

5.0

ns

t_OCS

Macrocell clock to any I/O register clock on the horizontal or vertical channel associated with 5.0

the cluster that the macrocell is in

t_CHZ

t_CLZ

f_MAX

f_MAX2

Clock to output disable (high-impedance)

3.5

ns

Clock to output enable (low-impedance)

1.5

Maximum frequency with internal feedback—within the same cluster

286 MHz

222 MHz

Maximum frequency with internal feedback—within different clusters at the opposite ends of

a horizontal or vertical channel

Product Term Clocking Parameters

t_MCSPT

t_MCHPT

t_MCCOPT

t_SCS2PT

Set-up time for macrocell used as input register, from input to product term clock

3.0

1.0

ns

Hold time of macrocell used as an input register

Product term clock to output delay from input pin

8.0

ns

Register to register delay through array logic in different clusters on the same channel using 6.5

a product term clock

Channel Interconnect Parameters

t_CHSW

Adder for a signal to switch from a horizontal to vertical channel and vice-versa

Cluster to Cluster delay adder (through channels and channel PIM)

1.0

2.0

ns

t_CL2CL

Note:

7. Add t_CHSWto signals making a horizontal to vertical channel switch or vice versa.

Document #: 38-02021 Rev. *C

Page 22 of 44

2.5-Gbps Programmable Serial Interface

Switching Characteristics

Timing Parameter Values ^[7](continued)

Parameter

Description

Min. Max. Unit

Miscellaneous Parameters

t_CPLD

Delay from the input of a cluster PIM, through a macrocell in the cluster, back to a cluster PIM

3.0

ns

input. This parameter can be added to the t_PDand t_SCSparameters for each extra pass

through the AND/OR array required by a given signal path

t_MCCD

Adder for carry chain logic per macrocell

0.25

PLL Parameters

t_MCCJ

t_DWSA

t_DWOSA

t_LOCK

f_PLLO

f_PLLI

Maximum cycle to cycle jitter time

–150 150

–1.35 –0.85

–150 150

250

ps

ns

ps

µs

PLL delay with skew adjustment

PLL delay without any skew adjustment

Lock time for the PLL

Output frequency of the PLL

Input frequency of the PLL

6.2

266 MHz

12.5 133 MHz

Cluster Memory Timing Parameter Values

200

Parameter

Description

Min. Max. Unit

Asynchronous Mode Parameters

t_CLMAA

t_CLMPWE

t_CLMSA

t_CLMHA

t_CLMSD

t_CLMHD

Cluster memory access time. Delay from address change to read data out

Write enable pulse width

11

ns

6.0

2.0

1.0

6.0

0.5

Address set-up to the beginning of write enable

Address hold after the end of write enable with both signals from the same I/O block

Data set-up to the end of write enable

Data hold after the end of write enable

Synchronous Mode Parameters

Clock cycle time for flow-through read and write operations (from macrocell register

through cluster memory back to a macrocell register in the same cluster)

10

ns

t_CLMCYC1

t_CLMCYC2

Clock cycle time for pipelined read and write operations (from cluster memory input

register through the memory to cluster memory output register)

5.0

t_CLMS

Address, data, and WE set-up time of pin inputs, relative to a global clock

Address, data, and WE hold time of pin inputs, relative to a global clock

Global clock to data valid on output pins for flow through data

Global clock to data valid on output pins for pipelined data

3.0

0.0

ns

t_CLMH

t_CLMDV1

t_CLMDV2

t_CLMMACS1

t_CLMMACS2

t_MACCLMS1

t_MACCLMS2

11

7.5

Cluster memory input clock to macrocell clock in the same cluster

Cluster memory output clock to macrocell clock in the same cluster

Macrocell clock to cluster memory input clock in the same cluster

Macrocell clock to cluster memory output clock in the same cluster

8.0

5.0

4.0

6.5

Internal Parameters

t_CLMCLAA

Asynchronous cluster memory access time from input of cluster to output of cluster

6.0

ns

Channel Memory Timing Parameter Values

Parameter

Description

Min. Max. Unit

Dual-Port Asynchronous Mode Parameters

t_CHMAA

t_CHMPWE

t_CHMSA

Channel memory access time. Delay from address change to read data out

Write enable pulse width

11

ns

6.0

2.0

Address set-up to the beginning of write enable

Document #: 38-02021 Rev. *C

Page 23 of 44

2.5-Gbps Programmable Serial Interface

Channel Memory Timing Parameter Values (continued)

t_CHMHA

t_CHMSD

t_CHMHD

t_CHMBA

Address hold after the end of write enable with both signals from the same I/O block

1.0

6.0

0.5

ns

Data set-up to the end of write enable

Data hold after the end of write enable

ns

Channel memory asynchronous dual port address match (busy access time)

9.0 ns

Dual-Port Synchronous Mode Parameters

Clock cycle time for flow through read and write operations (from macrocell register through 10

channel memory back to a macrocell register in the same cluster)

ns

t_CHMCYC1

t_CHMCYC2

Clock cycle time for pipelined read and write operations (from channel memory input register 5.3

through the memory to channel memory output register)

t_CHMS

Address, data, and WE set-up time of pin inputs, relative to a global clock

Address, data, and WE hold time of pin inputs, relative to a global clock

Global clock to data valid on output pins for flow through data

3.3

0.0

ns

t_CHMH

t_CHMDV1

t_CHMDV2

t_CHMBDV

t_CHMMACS1

t_CHMMACS2

t_MACCHMS1

t_MACCHMS2

11

ns

Global clock to data valid on output pins for pipelined data

7.5 ns

Channel memory synchronous dual-port address match (busy, clock to data valid)

Channel memory input clock to macrocell clock in the same cluster

Channel memory output clock to macrocell clock in the same cluster

Macrocell clock to channel memory input clock in the same cluster

Macrocell clock to channel memory output clock in the same cluster

9.0 ns

9.0

5.0

7.3

ns

Synchronous FIFO Data Parameters

t_CHMCLKRead and write minimum clock cycle time

t_CHMFS

5.0

4.0

0.0

ns

Data, read enable, and write enable set-up time relative to pin inputs

Data, read enable, and write enable hold time relative to pin inputs

Data access time to output pins from rising edge of read clock (read clock to data valid)

Channel memory FIFO read clock to macrocell clock for read data

Macrocell clock to channel memory FIFO write clock for write data

t_CHMFH

ns

t_CHMFRDV

t_CHMMACS

t_MACCHMS

7.0

5.0

ns

Synchronous FIFO Flag Parameters

t_CHMFO

Read or write clock to respective flag output at output pins

11

ns

t_CHMMACF

t_CHMFRS

Read or write clock to macrocell clock with FIFO flag

Master Reset Pulse Width

9

5.0

t_CHMFRSR

t_CHMFRSF

t_CHMSKEW1

t_CHMSKEW2

t_CHMSKEW3

Master Reset Recovery Time

4.0 ns

10.0 ns

2.0 ns

5.0 ns

Master Reset to Flag and Data Output Time

Read/Write Clock Skew Time for Full Flag

Read/Write Clock Skew Time for Empty Flag

Read/Write Clock Skew Time for Boundary Flags

Internal Parameters

t_CHMCHAAAsynchronous channel memory access time from input of channel memory to output of

channel memory

7.0

ns

High-speed PSI Transceiver Timing Parameter Values

Parameter

Description

Min.

Max.

Unit

Transceiver Interfacing Timing Parameters

t_TS

t_TXCLK

TXCLK Frequency (must be frequency coherent to REFCLK)

TXCLK Period

154.5

6.38

156.5

6.47

MHz

ns

t_RS

RXCLK Frequency

RXCLK Period

154.5

6.38

156.5

6.47

MHz

ns

t_RXCLK

Document #: 38-02021 Rev. *C

Page 24 of 44

2.5-Gbps Programmable Serial Interface

High-speed PSI Transceiver Timing Parameter Values

Parameter

Description

Min.

Max.

Unit

REFCLK Timing Parameters

t_REF

REFCLK Input Frequency

154.5

6.38

35

156.5

6.47

65

MHz

ns

t_REFP

t_REFD

t_REFT

t_REFR

t_REFF

t_REFJ

REFCLK Period

REFCLK Duty Cycle

REFCLK Frequency Tolerance (relative to received serial data)^[8]

%

–100

0.3

+100

1.5

ppm

ns

REFCLK Rise Time

REFCLK Fall Time

REFCLK Jitter

0.3

1.5

ns

See Figure 16 for phasenoise

requirements

CML Serial Outputs

t_DRF

Driver Rise/Fall Time (20–80% rise, 80–20% fall, 100Ω balanced load) 100

ps

[9]

t_UID

Unit Interval

400

CML Serial Outputs

t_RISE

t_FALL

CML Output Rise Time (20–80%, 100Ω balanced load)

CML Output Fall Time (80–20%, 100Ω balanced load)

60

170

ps

Jitter Specifications for CYP25G01K100 (Non-SONET)

t_EYE

t_JDR

t_JTR

t_JD

Eye opening at CML serial inputs

140

ps

UI

Deterministic Jitter allowed at CML serial inputs

Total Jitter allowed at CML serial inputs

Deterministic Jitter at CML serial outputs

Total Jitter at CML serial outputs

0.41

0.65

0.17

0.35

t_JT

Jitter Specifications for CYS25G01K100 (SONET)

Parameter

t_TJ-TXPLL

Description

Total Output Jitter for TX PLL (p-p)^[10]

Total Output Jitter for TX PLL (rms)^[10]

Total Output Jitter for RX CDR PLL (p-p)^[10]

Total Output Jitter for RX CDR PLL (rms)^[10]

Min.

Typical^[11]

Max.^[11]

0.04

Unit

UI

0.03

0.007

0.035

0.008

0.05

UI

t_TJ-RXPLL

UI

0.01

UI

Note:

8. ± 20 ppm is required to meet SONET output frequency specification.

9. Measured with serial bit rate of 2.5 Gbps.

10. The RMS and P-to-P jitter values are measured using a 12 KHz to 20 MHz SONET filter.

11. Typical at room temperature, Max. at 0^odeg C.

Document #: 38-02021 Rev. *C

Page 25 of 44

2.5-Gbps Programmable Serial Interface

Phase Noise Limits for CYS25G01K100(SONET) REFCLK

Source

CYS25G0101DX Reference Clock Phase Noise Limits

-75

-85

-95

-105

-115

-125

-135

-145

-155

1,000

10,000

100,000

1,000,000

Frequency (Hz)

10,000,000

100,000,000

Figure 16. Phase Noise Limits for REFCLK Inputs of CYS25G01K100

Jitter Transfer for CYS25G01K100 (SONET) RXPLL

Figure 17. Jitter Transfer for CYS25G01K100

Jitter Tolerance for CYS25G01K100 (SONET)

Figure 18. Jitter Tolerance for CYS25G01K100

Document #: 38-02021 Rev. *C

Page 26 of 44

2.5-Gbps Programmable Serial Interface

rates^[12]). Apply following adjustments if the inputs and outputs

are configured to operate at other standards.

Input and Output Standard Timing Delay

Adjustments

All the timing specifications in this data sheet are specified

based on 3.3V PCI compliant inputs and outputs (fast slew

Output Delay Adjustments (ns)

Input/Output Stan-

Input Delay Adjustments(ns)

dard

LVTTL – 2 mA

LVTTL – 4 mA

LVTTL – 6 mA

LVTTL – 8 mA

LVTTL – 12 mA

LVTTL – 16 mA

LVTTL – 24 mA

LVCMOS

t_IOD

2.75

1.8

t_EA

t_ER

t_IOIN

0

t_CKIN

0

t_IOREGPIN

0

1.8

0

1.2

0

0.6

0

0.16

0

LVCMOS3

LVCMOS2

LVCMOS18

3.3V PCI

0.14

0.41

1.6

0.05

0.1

0.7

0

0.6^[13]

0.3

0.2

0.4

0.2

0.9

0.8

0.5

0.6

0

0.1

0.2

0.5

0

0.1

0.2

0.4

0

0.2

0.4

0.3

0

0.1

–0.14

0.02^[13]

–0.15

–0.4

–0.02

–0.22

0.94

0.79

0.77

0.44

0

GTL+

0.9^[13]

0.1

0

0.5

0.9

0.5

0.4

0.3

0.5

0.2

0.3

0.6

0.3

SSTL3 I

SSTL3 II

SSTL2 I

0

SSTL2 II

0

HSTL I

0.5

0.1

0

HSTL II

HSTL III

HSTL IV

Notes:

12. For “slow slew rate” output delay adjustments, refer to Warp software’s static timing analyzer results.

13. These delays are based on falling edge output. The rising edge delay depends on the size of pull up resistor and termination voltage.

Switching Waveforms

General Switching Waveforms

Combinatorial Output

INPUT

t

PD

COMBINATORIAL

OUTPUT

Document #: 38-02021 Rev. *C

Page 27 of 44

2.5-Gbps Programmable Serial Interface

Switching Waveforms (continued)

Registered Output with Synchronous Clocking (Macrocell)

INPUT

t

MCH

MCS

SYNCHRONOUS

CLOCK

REGISTERED

OUTPUT

t

MCCO

Registered Input in I/O Cell

DATA

INPUT

t

IOH

t

IOS

INPUT REGISTER

CLOCK

t

IOCO

REGISTERED

OUTPUT

Clock to Clock

INPUT REGISTER

CLOCK

t

ICS

SCS

MACROCELL

REGISTER CLOCK

PT Clock to PT Clock

DATA

INPUT

t

SCS2PT

MCSPT

PT CLOCK

t

PRW

Asynchronous Reset/Preset

RESET/PRESET

INPUT

t

PRO

REGISTERED

OUTPUT

t

PRR

CLOCK

Document #: 38-02021 Rev. *C

Page 28 of 44

2.5-Gbps Programmable Serial Interface

Switching Waveforms (continued)

Output Enable/Disable

GLOBAL CONTROL

INPUT

t

EA

ER

OUTPUTS

Cluster Memory Asynchronous Timing

WRITE

READ

ADDRESS (AT

THE CLUSTER

INPUT)

WRITE ENABLE

t_CLMPWE

INPUT

t_CLMCLAA

OUTPUT

Cluster Memory Asynchronous Timing 2

WRITE

READ

ADDRESS (AT THE

I/O PIN)

t_CLMHA

t_CLMSA

WRITE ENABLE

t_CLMPWE

INPUT

t_CLMHD

t_CLMSD

t_CLMAA

OUTPUT

Document #: 38-02021 Rev. *C

Page 29 of 44

2.5-Gbps Programmable Serial Interface

Switching Waveforms (continued)

Cluster Memory Synchronous Timing

READ

WRITE

READ

GLOBAL

CLOCK

t_CLMCYC1

t_CLMS

t_CLMH

ADDRESS

t_CLMS

t_CLMH

t_CLMS

t_CLMH

WRITE

ENABLE

REGISTERED

INPUT

t_CLMDV1

REGISTERED

OUTPUT

Cluster Memory Internal Clocking

MACROCELL

INPUT CLOCK

t_MACCLMS1

t_CLMMACS1

CLUSTER MEMORY

INPUT CLOCK

t_CLMMACS2

t_MACCLMS2

CLUSTER MEMORY

OUTPUT CLOCK

Document #: 38-02021 Rev. *C

Page 30 of 44

2.5-Gbps Programmable Serial Interface

Switching Waveforms (continued)

Cluster Memory Output Register Timing (Asynchronous Inputs)

ADDRESS

WRITE

ENABLE

INPUT

t_CLMCYC2

GLOBAL CLOCK

(OUTPUT REGISTER)

t_CLMDV2

EGISTERED

OUTPUT

Cluster Memory Output Register Timing (Synchronous Inputs)

ADDRESS

WRITE

ENABLE

INPUT

t_CLMCYC2

GLOBAL CLOCK

(INPUT REGISTER)

t_CLMS

t_CLMH

GLOBAL CLOCK

(OUTPUT REGISTER)

t_CLMDV2

REGISTERED

OUTPUT

Document #: 38-02021 Rev. *C

Page 31 of 44

2.5-Gbps Programmable Serial Interface

Switching Waveforms (continued)

Channel Memory DP Asynchronous Timing

A_n+1

A_n+2

ADDRESS

A_n-1

A_n

t_CHMHA

t_CHMSA

t_CHMPWE

WRITE

ENABLE

t_CHMSD

t_CHMHD

DATA

INPUT

D_n

t_CHMAA

D_n-1

OUTPUT

D_n+1

D_n

Channel Memory Internal Clocking

MACROCELL INPUT

CLOCK

t_MACCHMS1

t_CHMMACS1

CHANNEL MEMORY

INPUT CLOCK

t_CHMMACS2

t_MACCHMS2

CHANNEL MEMORY

OUTPUT CLOCK

Document #: 38-02021 Rev. *C

Page 32 of 44

2.5-Gbps Programmable Serial Interface

Switching Waveforms (continued)

Channel Memory Internal Clocking 2

MACROCELL INPUT

CLOCK

t_CHMMACS

FIFO READ

CLOCK

t_MACCHMS

FIFO WRITE

CLOCK

t_CHMMACF

FIFO READ OR

WRITE CLOCK

Channel Memory DP SRAM Flow Through R/W Timing

CLOCK

t_CHMCYC1

t_CHMS

t_CHMH

A_n+3

A_n+2

A_n+1

A_n-1

A_n

ADDRESS

WRITE

ENABLE

t_CHMS

t_CHMH

DATA

INPUT

D_n-1

D_n+1

D_n+3

t_CHMDV1

D_n-1

D_n

D_n+1

D_n+2

D_n+3

OUTPUT

Document #: 38-02021 Rev. *C

Page 33 of 44

2.5-Gbps Programmable Serial Interface

Switching Waveforms (continued)

Channel Memory DP SRAM Pipeline R/W Timing

CLOCK

t_CHMCYC2

t_CHMS

t_CHMH

A_n-1

A_n

A_n+2

A_n+1

A_n+3

ADDRESS

t_CHMH

t_CHMS

WRITE

ENABLE

t_CHMH

t_CHMS

DATA

INPUT

D_n+3

D_n-1

D_n+1

t_CHMDV2

D_n-1

D_n

D_n+1

OUTPUT

D_n+2

Dual-Port Asynchronous Address Match Busy Signal

B_n

A_n

ADDRESS A

A_n-1

A_n

A_n+1

ADDRESS B

t_CHMBA

ADDRESS

MATCH

Document #: 38-02021 Rev. *C

Page 34 of 44

2.5-Gbps Programmable Serial Interface

Switching Waveforms (continued)

Dual-Port Synchronous Address Match Busy Signal

CLOCK

A_n-1

A_n

ADDRESS A

ADDRESS B

A_n

B_n-1

B_n+1

t_CHMS

ADDRESS

MATCH

t_CHMBDV

Channel Memory Synchronous FIFO Empty/Write Timing

PORT B CLOCK

t_CHMCLK

t_CHMFS

t_CHMFH

WRITE ENABLE

REGISTERED

INPUT

D_n+1

EMPTY FLAG

(active low)

t_CHMSKEW2

t_CHMFO

PORT A CLOCK

READ ENABLE

t_CHMFRDV

REGISTERED

OUTPUT

Document #: 38-02021 Rev. *C

Page 35 of 44

2.5-Gbps Programmable Serial Interface

Switching Waveforms (continued)

Channel Memory Synchronous FIFO Full/Read Timing

PORT A CLOCK

t_CHMCLK

t_CHMFS

t_CHMFH

READ ENABLE

t_CHMFRDV

REGISTERED

OUTPUT

FULL FLAG

(active low)

t_CHMFO

t_CHMSKEW1t_CHMFO

PORT B CLOCK

WRITE ENABLE

t_CHMS

t_CHMH

REGISTERED

INPUT

Channel Memory Synchronous FIFO Programmable Flag Timing

PORT B CLOCK

t_CHMCLK

t_CHMFH

t_CHMFS

WRITE ENABLE

PROGRAMMABLE

ALMOST-EMPTY FLAG

(active LOW)

t_CHMSKEW3

t_CHMFO

PORT A CLOCK

t_CHMFH

t_CHMFS

READ ENABLE

Document #: 38-02021 Rev. *C

Page 36 of 44

2.5-Gbps Programmable Serial Interface

Switching Waveforms (continued)

PORT B CLOCK

t_CHMCLK

WRITE ENABLE

t_CHMFO

PROGRAMMABLE

ALMOST-FULL FLAG

(active LOW)

t_CHMSKEW3

PORT A CLOCK

READ ENABLE

Channel Memory Synchronous FIFO Master Reset Timing

t_CHMFRS

MASTER

RESET INPUT

t_CHMFRSR

READ ENABLE /

WRITE ENABLE

t_CHMFRSF

EMPTY/FULL

PROGRAMMABLE

ALMOST EMPTY

FLAGS

HALF-FULL/

PROGRAMMABLE

ALMOST FULL

FLAGS

REGISTERED

OUTPUT

Optical Module or

Limiting Amplifier

CYS25G01K100

0.1 µF

OUT+

IN+

IN-

50 ohms

100 ohms

0.1 µF

50 ohms

OUT-

Figure 19. Serial Input Termination

Document #: 38-02021 Rev. *C

Page 37 of 44

2.5-Gbps Programmable Serial Interface

0.1 µF

CYS25G01K100

OUT+

50 ohms

100 Ω

Internally source

matched to drive

100 Ω differential

Transmission Lines

OUT-

Figure 20. Serial Output Termination

VCC=3.3V

LVPECL

Clock Source

130Ω

CYS25G01K100

CLKOUT+

50 ohms

REFCLK+

VCC=3.3V

82.5Ω

130Ω

-

CLKOUT-

50 ohms

REFCLK-

82.5Ω

-

Figure 21. REFCLK Oscillator Termination

VCC=3.3V

LVPECL

Clock Source

130Ω

CYS25G01K100

0.01 µF

VCC=3.3V

CLKOUT+

50 ohms

REFCLK+

82.5Ω

130Ω

0.01 µF

-

CLKOUT-

REFCLK-

82.5Ω

-

Figure 22. AC-Coupled REFCLK Oscillator Termination

Pin and Signal Description

Name

Function

Signal Description

Standard Device Signals

CCLK

Output

Configuration Clock for serial interface with the external boot PROM

Flag indicating that configuration is complete

CDONE

CDATA

Output

Input

Pin to receive configuration data from the external boot PROM

Global Input Clock signals 0 through 1. Other global clocks are TXCLK and RXCLK.

Chip select for the external boot PROM

GCLK0-1

CCE

Input

Output

GCTL0-3

IO/V_REF0

IO/V_REF1

IO/V_REF2

IO/V_REF3

IO/V_REF4

IO/V_REF5

Input

Global Control signals 0 through 3

Input/Output

Dual function pin: I/O or Reference Voltage for Bank 0

Dual function pin: I/O or Reference Voltage for Bank 1

Dual function pin: I/O or Reference Voltage for Bank 2

Dual function pin: I/O or Reference Voltage for Bank 3

Dual function pin: I/O or Reference Voltage for Bank 4

Dual function pin: I/O or Reference Voltage for Bank 5

Document #: 38-02021 Rev. *C

Page 38 of 44

2.5-Gbps Programmable Serial Interface

Pin and Signal Description (continued)

Name

IO

Function

Input/Output

Signal Description

Input or Output pin

IO6/Lock

HSTLREF

MSEL

Reconfig

CRST

TCK

Input/Output

Input

Dual function pin: I/O in Bank 6 or PLL lock output signal

Reference Voltage for HSTL Specific IO Banks

Mode Select Pin

Input

Pin to start configuration of PSI

Reset signal to interface with the external boot PROM

JTAG Test Clock

Output

Input

TDI

Input

JTAG Test Data In

TDO

Output

Input

JTAG Test Data Out

TMS

JTAG Test Mode Select

Transmit Path Signals

TXD[15:0]

Internal

Parallel Transmit Data Inputs to the serial transceiver block. A 16-bit word, sampled by

TXCLK↑. TXD[15] is the most significant bit (the first bit transmitted)

TXCLK

Internal

Parallel Transmit Data Input Clock to the serial transceiver block. Divide by 16 of the

selected transmit bit-rate clock. One of the four global clocks in the programmable logic.

Receive Path Signals

RXD[15:0]

Internal

Parallel Receive Data Output from the serial transceiver block. These outputs change

following RXCLK↓. RXD[15] is the most significant bit of the output word, and is received

first on the serial interface

RXCLK

Internal

Receive Clock Output from the serial transceiver block. Divide by 16 of the bit-rate clock

extracted from the received serial stream. One of the four global clocks in the program-

mable.

CMSER

RXCN1

RXCN2

RXCP1

RXCP2

Analog

Common Mode Termination. Capacitor (0.1 µF) shunt to V_SSfor common mode noise

Receive Loop Filter Capacitor (Negative)

Receive Loop Filter Capacitor (Positive)

Transceiver Control and Status Signals

REFCLK±

Differential LVPECL Reference Clock. This clock input is used as the timing reference for the transmit and

input

receive PLLs. A derivative of this input clock may also be used to clock the transmit

parallel interface

LFI

Internal

Line Fault Indicator Output Signal. When LOW, this signal indicates that the selected

receive data stream has been detected as invalid by either a LOW input on SD, or by

the receive VCO being operated outside its specified limits

RESET

Internal

Reset for all logic functions in the serial transceiver block except the transmit FIFO

LOCKREF

Receive PLL Lock to Reference Input Signal. When LOW, the receive PLL locks to

REFCLK instead of the received serial data stream

SD

LVTTL input

Internal

Signal Detect. When LOW, the receive PLL locks to REFCLK instead of the received

serial data stream

FIFO_ERR

FIFO_RST

PWRDN

Transmit FIFO Error Output Signal. When HIGH the transmit FIFO has either under or

overflowed. The FIFO must be reset to clear the error indication

Internal

Transmit FIFO Reset Input Signal. When LOW, the in and out pointers of the transmit

FIFO are set to maximum separation

Internal

Device Power Down Input Signal. When LOW, the logic and drivers are all disabled and

placed into a standby condition where only minimal power is dissipated

Document #: 38-02021 Rev. *C

Page 39 of 44

2.5-Gbps Programmable Serial Interface

Pin and Signal Description (continued)

Name

Function

Signal Description

Transceiver Loop Control Signals

DIAGLOOP

LINELOOP

Internal

Diagnostic Loopback Control Input Signal. When HIGH, transmit data is routed through

the receive clock and data recovery and presented at the RXD[15:0] outputs. When

LOW, received serial data is routed through the receive clock and data recovery and

presented at the RXD[15:0] outputs

Line Loopback Control Input Signal. When HIGH, received serial data is looped back

from receive to transmit after being reclocked by a recovered clock. When LINELOOP

is LOW, the data passed to the OUT± line driver is controlled by LOOPA.

When both LINELOOP and LOOPA are LOW, the data passed to the OUT± line driver

is generated in the transmit shifter

LOOPA

Internal

Analog Line Loopback Input Signal. When LINELOOP is LOW and LOOPA is HIGH,

received serial data is looped back from receive input buffer to transmit output buffer,

but is not routed through the clock and data recovery PLL. When LOOPA is LOW, the

data passed to the OUT± line driver is controlled by LINELOOP

LOOPTIME

Loop Time Mode Input Signal. When HIGH, the extracted receive bit-clock replaces

transmit bit-clock. When LOW, the REFCLK input is multiplied by 16 to generate the

transmit bit clock

Serial I/O

OUT±

Differential CML

output

Differential Serial Data Output. This differential CML output (+3.3V referenced) is

capable of driving terminated 50Ω transmission lines or commercial fiberoptic trans-

mitter modules

IN±

Differential CML

input

Differential Serial Data Input. This differential input accept the serial data stream for

deserialization and clock extraction

Power

V_CC

Power

+3.3V Supply (operating voltage)

Signal and Power Ground

+3.3V Quiet Power

GND

Ground

V_CCQ

V_SSQ

Quiet Ground

V_DDQ

+1.5V Supply for HSTL Outputs

V_CCfor I/O bank 0

V_CCIO0

V_CCIO1

V_CCIO2

V_CCIO3

V_CCIO4

V_CCIO5

V_CCJTAG

V_CCCFG

V_CCPLL

GNPLL

V_CEP

Power

Ground

Power

V_CCfor I/O bank 1

V_CCfor I/O bank 2

V_CCfor I/O bank 3

V_CCfor I/O bank 4

V_CCfor I/O bank 5

V_CCfor JTAG pins

V_CCfor Configuration port

V_CCfor logic PLL

Ground for logic PLL

V_CCfor the Self-Boot™ solution embedded boot PROM

Document #: 38-02021 Rev. *C

Page 40 of 44

2.5-Gbps Programmable Serial Interface

Pin Configurations

456-ball BGA (25G01K100): Top View

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

GND HSTL-

REF

IO7

HSTL-

REF

IO7

HSTL- HSTL-

IO6

IO6 HSTL- IO5

REF

IO5

IO5 IO/VRE IO5

F5

IO5

IO5 IO/VRE IO5

F5

GND

A

B

C

D

E

F

A

B

C

D

E

F

REF

HSTL- HSTL-

REF REF

IO7

IO0

HSTL-

REF

IO7

VDDQ IO7 HSTL-

REF

IO6

IO5

IO5 IO/VRE IO5

F5

IO5

IO0

IO7

IO0

IO7

VDDQ VCC

VCC

IO7 GCTL IO7

3

VDDQ VDDQ VDDQ HSTL- IO6

REF

IO6

IO5

IO5 GCTL2 GCTL1 IO5

IO5

TDO TCK

IO7

VDDQ VDDQ VDDQ GND HSTL- IO7

REF

NC

VDDQ VCC

IO6

IO6 VCCPL VDDQ VDDQ VDDQ VCC

L

NC

GCLK1 IO5

TMS

TDI

IO0 GCTL0 GND

GND

IO7

GND GND HSTL-

REF

IO6

IO6/

Lock

IO6

IO6 IO/VRE IO5

F5

IO5

IO5 VCCIO5 VCCIO5 VCCIO VCCJT

5

AG

IO/VR IO0

EF0

IO0

VCC

GND

NC

IO0 IO/VRE VCC VCCIO0 GCLK0

F0

NC

G

IO0

VCC VCCIO0 GND

NC

VSSQ VSSQ

H

J

H

J

VSSQ VSSQ VSSQ NC

IO0

VCC

IO0

VSSQ VSSQ VSSQ

NC NC NC

NC

K

L

K

L

GND

GND GND GNPLL

GND GND GND

IO0 IO/VRE IO0

F0

IO0

SD RXCN1 RXCP1 RXCN2RXCP2

M

VCC

IO0

GND IO/VRE

F0

GND

GND GND GND

NC

VCCQ VCCQ VCCQ VCCQ

N

IO1

IO0

GND

GND GND GND

NC

VSSQ VSSQ

IN+

IN-

P

R

P

R

IO1 VCCIO1 GND

VSSQ VSSQ VSSQ CMSE

R

IO/VR IO/VRE IO1

IO1

GND

GND GND GND

VSSQ VSSQ VSSQ OUT+ OUT-

T

EF1

F1

IO1

GND

NC

VCCQ VCCQ VCCQ VCCQ

U

V

U

V

IO1

IO1 IO/VRE IO1

F1

REF- VCCIO4 IO4

CLK+

IO4 VCCIO

4

IO1

GND

IO1

REF- VCCIO4 IO4

CLK-

IO4

W

Y

W

Y

IO1

VCEP

IO1

IO4

IO3

VCEP

IO4

IO4 IO/VRE

F4

IO1 VCCIO1 IO/VRE GND

F1

NC

IO4

IO3

AA

AB

AC

AD

AE

AF

AA

AB

AC

AD

AE

AF

GND CDONE VCCIO1 IO1

IO2

GND

IO2 IO/VRE IO2

F2

IO2

IO3

IO2

IO3

GND

IO3

GND

IO3

IO4

CDAT RECON IO2

FIG

IO2 VCCCF VCCIO2VCCIO2VCCIO2VCCIO NC

IO2

VDDQ VCCIO VCCIO IO3

IO3 IO/VRE NC

F3

NC VCCIO4 IO/VRE IO/VRE IO4

F4 F4

A

G

2

3

CRST CCLK

IO2

NC VDDQ VDDQ

IO2

IO2 IO/VRE IO2

F2

IO3

19

VCC VCCIO3VCCIO3 IO/VRE IO3

F3

IO3

CCE MSEL IO/VRE IO2 IO/VRE IO2

IO2

9

IO2 IO/VRE IO2

F2

IO2

IO3

IO3 IO/VRE IO3

F3

IO3

23

IO3 IO/VRE IO3

F3

F2

GND

1

IO2

2

IO2

4

IO2

IO2 IO/VRE IO2

F2

IO2

VCC IO/VRE IO3

F3

IO3 IO/VRE IO3

F3

IO3

GND

3

5

6

7

8

10

11

12

13

14

15

16

17

18

20

21

22

24

25

26

Document #: 38-02021 Rev. *C

Page 41 of 44

2.5-Gbps Programmable Serial Interface

CY P 25G 01 K100 V 1– MG C

Standard Cypress

Designator

C = Commercial

I = Industrial

P = PHY

S = SONET PHY

MG = Package Type

15 = 1.5Gbps

25 = 2.5Gbps

V = Standard Power

3.3V-Vcc

01 = 1 channel

K100 = 100K gates

Ordering Information

Channels and

Package

Name

Operating

Device

Link Speed

1 x 2.5 Gbps

Ordering Code

Package Type

Range

25G01K100

CYP25G01K100V1-MGC

CYS25G01K100V1-MGC

456MGC 456-ball Ball Grid Array

Commercial

Document #: 38-02021 Rev. *C

Page 42 of 44

2.5-Gbps Programmable Serial Interface

Package Diagram

456-ball Ball Grid Array (35 x 35 x 2.33 mm) BG456

51-85133-*A

ZBT is a trademark of IDT. InfiniBand is a trademark of the InfiniBand Trade Association. QDR is a trademark of Micron, IDT, and

Cypress Semiconductor Corporation. Windows is a registered trademark of Microsoft Corporation. SpeedWave and ViewDraw

are trademarks of ViewLogic. Warp is a registered trademark, and NoBL, Programmable Interconnect Matrix, PIM, Spread Aware,

AnyVolt, Self-Boot, In-System Reprogrammable, ISR, Programmable Serial Interface, and PSI are trademarks, of Cypress

Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their respective

holders.

Document #: 38-02021 Rev. *C

Page 43 of 44

of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

2.5-Gbps Programmable Serial Interface

Document History Page

Document Title: 2.5-Gbps Programmable Serial Interface

Document Number: 38-02021

Orig. of

REV.

**

ECN NO. Issue Date Change

Description of Change

106745

107726

109064

120882

05/25/01

06/04/01

09/07/01

12/13/02

SZV

MHW

PDS

Change from Spec #38-01093 to 38-02021

Updated Marketing Part Numbers

*A

*B

*C

Added x8 feature in PLL and CHAR data

Revised data sheet to reflect only 2.5-Gbps single channel 100K program-

mable logic PSI data.

Added SONET jitter specs and jitter performance data for CYS25G01K100.

Added REFCLK phase noise limits plot for CYS25G01K100. Changed title.

Updated logic PLL data with additional multiplication factors available.

Added sections titled “Registering TXD[15:0] Data Before it enters Serial

Transceiver Block” and “Registering RXD[15:0] Data before it enters

Programmable LB” under the major section called “Serial Transceiver

Operation.”

Updated some Timing Parameter Values.

Updated Output Differential Swing and Input Differential Voltage.

Document #: 38-02021 Rev. *C

Page 44 of 44

厂商	型号	描述	页数
NIDEC	CYP	[ PIANO SWITCHES (FULL PITCH) ]	5 页
NIDEC	CYP-0200MB	[ PIANO SWITCHES (FULL PITCH) ]	5 页
NIDEC	CYP-0200MC	[ PIANO SWITCHES (FULL PITCH) ]	5 页
NIDEC	CYP-0200TB	[ PIANO SWITCHES (FULL PITCH) ]	5 页
NIDEC	CYP-0200TC	[ PIANO SWITCHES (FULL PITCH) ]	5 页
NIDEC	CYP-0201MB	[ PIANO SWITCHES (FULL PITCH) ]	5 页
NIDEC	CYP-0201MC	[ PIANO SWITCHES (FULL PITCH) ]	5 页
NIDEC	CYP-0201TB	[ PIANO SWITCHES (FULL PITCH) ]	5 页
NIDEC	CYP-0201TC	[ PIANO SWITCHES (FULL PITCH) ]	5 页
NIDEC	CYP-0202MB	[ PIANO SWITCHES (FULL PITCH) ]	5 页