CYS25G0101DX
CYS25G0101DX Operation
CYS25G0101DX Receive Data Path
The CYS25G0101DX is a highly configurable device designed
to support reliable transfer of large quantities of data using high
speed serial links. It performs necessary clock and data
recovery, clock generation, serial-to-parallel conversion, and
parallel-to-serial conversion. CYS25G0101DX also provides
various loopback functions.
Serial Line Receivers
A differential line receiver, IN±, is available for accepting the input
serial data stream. The serial line receiver inputs accommodate
high wire interconnect and filtering losses or transmission line
attenuation (VSE > 25 mV, or 50 mV peak-to-peak differential). It
can be AC coupled to +3.3V or +5V powered fiber optic interface
modules. The common mode tolerance of these line receivers
accommodates a wide range of signal termination voltages.
CYS25G0101DX Transmit Data Path
Operating Modes
The transmit path of the CYS25G0101DX supports 16-bit wide
data paths.
Lock to Data Control
Line Receiver routed to the clock and data recovery PLL is
monitored for:
Phase Align Buffer
Data from the input register is passed to a phase align buffer
(FIFO). This buffer is used to absorb clock phase differences
between the transmit input clock and the internal character clock.
■ status of signal detect (SD) pin
■ status of LOCKREF pin.
This status is presented on the Line Fault Indicator (LFI) output,
that changes asynchronously in the cases in which SD or
LOCKREF go from HIGH to LOW. Otherwise, it changes
synchronously to the REFCLK.
Initialization of the phase align buffer takes place when the
FIFO_RST input is asserted LOW. When FIFO_RST is returned
HIGH, the present input clock phase, relative to TXCLKO, is set.
Once set, the input clock is enabled to skew in time up to half a
character period in either direction relative to REFCLK (that is,
±180. This time shift enables the delay path of the character
clock (relative to REFLCK) to change due to operating voltage
and temperature not affecting the desired operation. FIFO_RST
is an asynchronous input. FIFO_ERR is the transmit FIFO Error
indicator. When HIGH, the transmit FIFO has either underflowed
or overflowed. The FIFO is externally reset to clear the error
indication; or if no action is taken, the internal clearing
mechanism clears the FIFO in nine clock cycles. When the FIFO
is being reset, the output data is 1010.
Clock Data Recovery
The extraction of a bit rate clock and recovery of data bits from
received serial stream is performed by a Clock Data Recovery
(CDR) block. The clock extraction function is performed by high
performance embedded phase-locked loop (PLL) that tracks the
frequency of the incoming bit stream and aligns the phase of the
internal bit rate clock to the transitions in the selected serial data
stream.
CDR accepts a character rate (bit rate * 16) reference clock on
the REFCLK input. This REFCLK input is used to ensure that the
VCO (within the CDR) is operating at the correct frequency
(rather than some harmonic of the bit rate), to improve PLL
acquisition time and to limit unlocked frequency excursions of the
CDR VCO when no data is present at the serial inputs.
Regardless of the type of signal present, the CDR attempts to
recover a data stream from it. If the frequency of the recovered
data stream is outside the limits set by the range controls, the
CDR PLL tracks REFCLK instead of the data stream. When the
frequency of the selected data stream returns to a valid
frequency, the CDR PLL is allowed to track the received data
stream. The frequency of REFCLK must be within ±100 ppm of
the frequency of the clock that drives the REFCLK signal of the
remote transmitter to ensure a lock to the incoming data stream.
For systems using multiple or redundant connections, the LFI
output can be used to select an alternate data stream. When an
LFI indication is detected, external logic toggles selection of the
input device. When such a port switch takes place, it is
necessary for the PLL to reacquire lock to the new serial stream.
Transmit PLL Clock Multiplier
The Transmit PLL Clock Multiplier accepts a 155.52 MHz
external clock at the REFCLK input. It multiplies that clock by 16
to generate a bit rate clock for use by the transmit shifter. The
operating serial signaling rate and allowable range of REFCLK
frequencies is listed in Table on page 13. The REFCLK phase
noise limits to meet SONET compliancy are shown in Figure 8
on page 15. The REFCLK± input is a standard LVPECL input.
Serializer
The parallel data from the phase align buffer is passed to the
Serializer that converts the parallel data to serial data. It uses the
bit rate clock generated by the Transmit PLL clock multiplier.
TXD[15] is the most significant bit of the output word and is
transmitted first on the serial interface.
Serial Output Driver
The Serial Interface Output Driver makes use of high
performance differential Current Mode Logic (CML) to provide a
source matched driver for the transmission lines. This driver
receives its data from the Transmit Shifters or the receive
loopback data. The outputs have signal swings equivalent to that
of standard LVPECL drivers and are capable of driving AC
coupled optical modules or transmission lines.
External Filter
The CDR circuit uses external capacitors for the PLL filter. A
0.1 F capacitor needs to be connected between RXCN1 and
RXCP1. Similarly a 0.1 F capacitor needs to be connected
between RXCN2 and RXCP2. The recommended packages and
dielectric material for these capacitors are 0805 X7R or 0603
X7R.
Document Number: 38-02009 Rev. *O
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