Management Interface for the CYP32G0401DX
Table 11.Register 31 Bit Assignments
Bit(s)
31.15
Name
Description
1 = Override trim values
R/W
R/W
Frequency Synthesizer Trim Override
0 = Do not override
31.14-9
31.8
Reserved
Read as 00
Frequency Synthesizer Trim Complete 1 = Complete
0 = Incomplete
R/W
R/W
31.7-6
31.5-0
Reserved
Read as 00
Frequency Synthesizer Trim settings 0 Binary value 0-63
through 63.
Table 12.Management Frame Format
Management frame fields
PHYAD REGAD TA
AAAAA RRRRR Z0
AAAAA RRRRR
PRE
1...1
1...1
ST
OP
10
01
DATA
IDLE
Read
Write
01
01
DDDDDDDDDDDDDDDD
DDDDDDDDDDDDDDDD
Z
Z
10
Table 13.
Frequency Synthesizer Test Control Register
This register (Register 31) is unique to the CYP32G0401DX
and is used to control the Frequency Synthesizer. Bit assign-
ment is shown in Table 11. Default value is 0000.
ENCODE
FRAME
SER8_10
First 3 Bits of
Chip PHYAD
On Rising Edge of RESETN
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
000
001
010
011
100
101
110
111
Management Frame Structure
The management frame structure is as shown in Table 12.
The order of bit transmission is left to right.
The IDLE condition (indicated by Z in Table 12) is a high-im-
pedance state on MDIO. All three state drivers are disabled.
Each of the other Management frame fields are described
below:
PRE (preamble). A sequence of 32 contiguous logic one bits
on MDIO. Note that bits do not exist on MDIO without clocks
on MDC. If the STA determines that every PHY that is con-
nected to the MDIO signal is able to accept management
frames that are not preceded by the preamble pattern (bit
1.6), then the STA may suppress generation of the preamble
pattern and initiate management frames with the ST pattern.
Table 14.
Last 2 Bits of Chip
PHYAD
ST (Start of frame). Start of frame is indicated by a <01>
pattern.
Channel ID
a
b
c
d
00
01
10
11
OP (Operation code). The operation code for a read transac-
tion is <10>, while the operation code for a write transaction
is <01>.
PHYAD (PHY Address). The PHY address is five bits, allow-
ing 32 unique PHY addresses. The physical address for the
CYP32G0401DX is set at the end of reset. When RESETN
goes high the three signals ENCODE, FRAME and SER8_10
are locked in as the first three bits of PHYAD. The last two bits
identify the channel. Refer to Table 13 and Table 14.
ister. The first register address bit transmitted is the MSB of
the address.
TA (Turnaround). Turnaround time is a two bit time spacing
between the Register Address field and the Data field of a
Management frame. This time period is utilized to ensure that
contention does not occur on the MDIO line. For a write trans-
action the CYP32G0401DX maintains a high impedance on
MDIO at all times. During a read transaction both the
CYP32G0401DX and STA will maintain a high impedance for
REGAD (Register Address). The Register address is five bits,
allowing 32 individual registers to be addressed within each
PHY. The register accessed at Register Address zero
<00000> shall be the control register, and the register access-
ed at Register Address one <00001> shall be the status reg-
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