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CYM9268PM-100C

型号：

CYM9268PM-100C

品牌：

CYPRESS[ CYPRESS ]

页数：

14 页

PDF大小：

264 K

下载PDF手册
67  
CYM9265/CYM9266  
CYM9267/CYM9268  
PRELIMINARY  
64K/128K/256K/512K x 72 SRAM Modules  
face mount packages on an epoxy laminate board with pins.  
The modules are designed to be incorporated into large mem-  
ory arrays.  
Features  
• Operates at 133 MHz  
• Uses 128K x 18, or 256K x 18 high performance syn-  
chronous SRAMs  
• 168-position Angled DIMM from Amp p/n 179508-2  
• 3.3V inputs/data outputs  
The module is configured as either one or two banks, where  
each bank has separate chip select and output enable con-  
trols. Separate clocks are provided for every pair of SRAMs.  
Multiple ground pins and on-board decoupling capacitors en-  
sure high performance with maximum noise immunity.  
Functional Description  
All components on the cache modules are surface mounted on  
a multi-layer epoxy laminate (FR-4) substrate. The contact  
pins are plated with 150 micro-inches of nickel covered by 30  
micro-inches of gold flash.  
The CYM9265, CYM9266, CYM9267, and the CYM9268 are  
high-performance synchronous memory modules organized  
as 64K(9265), 128K(9266), 256K(9267), or 512K(9268) by 72  
bits. These modules are constructed from either 128K x  
18(9265,9266,9267) or 256K x 18(9268) SRAMs in plastic sur-  
LogicBlockDiagram- CYM9265  
V
cc3  
V
cc3  
R2  
R4  
A[15:0]  
WE[7:0]  
ADSP  
DQ[0:15]  
DQP[0:1]  
R3  
A
15:0  
OE[0:1]  
ADSP  
OE  
OE0  
CS0  
D[0:63]  
DP[0:7]  
CS[0:1]  
CS  
WEH  
WEL  
R1  
ADSC  
CLK  
BANK 0  
CLK[0:3]  
R1, R2, R3, R4 are optional resistors  
R1, R2, R4 are mounted for access using ADSC  
R3, R2, R4 are mounted for access using ADSP  
PD  
PD  
1
0
GND NC  
BANK 0  
64Kx72  
9265-1  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
Document #: 38-05166 Rev. **  
Revised September 21, 2001  
CYM9265/CYM9266  
CYM9267/CYM9268  
PRELIMINARY  
LogicBlockDiagram- CYM9266/CYM9267  
V
cc3  
V
cc3  
R2  
R4  
A[17:0]  
WE[0:7]  
ADSP  
DQ[0:15]  
DQP[0:1]  
R3  
A
17:0  
OE[0:1]  
ADSP  
OE  
OE0  
CE0  
D[0:63]  
DP[0:7]  
CS[0:1]  
CS  
WEH  
WEL  
ADSC  
CLK  
R1  
BANK 0  
CLK[0:3]  
D[0:15]  
DQ[0:1]  
A
17:0  
ADSP  
OE  
OE1  
CE1  
R1, R2, R3, R4 are optional resistors  
R1, R2, R4 are mounted for access using ADSC  
R3, R2, R4 are mounted for access using ADSP  
CS  
WEH  
WEL  
PD  
PD  
1
0
ADSC  
CLK  
NC  
GND BANK 0  
128Kx72  
256KX72  
GND GND  
BANK 0 & 1  
BANK 1  
9265-2  
Document #: 38-05166 Rev. **  
Page 2 of 14  
CYM9265/CYM9266  
CYM9267/CYM9268  
PRELIMINARY  
LogicBlockDiagram- CYM9268  
V
cc3  
V
cc3  
R2  
R4  
A[17:0]  
WE[0:7]  
ADSP  
DQ[0:15]  
DQP[0:1]  
R3  
A
17:0  
OE[0:1]  
ADSP  
OE  
OE0  
CE0  
D[0:63]  
DP[0:7]  
CS[0:1]  
CS  
WEH  
WEL  
ADSC  
CLK  
R1  
BANK 0  
CLK[0:3]  
D[0:15]  
DQ[0:1]  
A
17:0  
ADSP  
OE  
R1, R2, R3, R4 are optional resistors  
R1, R2, R4 are mounted for access using ADSC  
R3, R2, R4 are mounted for access using ADSP  
OE1  
CE1  
CS  
WEH  
WEL  
ADSC  
CLK  
PD  
PD  
1
0
NC  
NC  
BANK 0 & 1  
BANK 1  
512KX72  
9265-3  
Selection Guide  
Synchronous Cache Module  
CYM9266-133 / 100 CYM9267-133 /100  
Part Number  
Cache Size  
CYM9265-133 / 100  
CYM9268-133 /100  
512K x 72  
64K x 72  
128K x 72  
8 of 128K x 18  
133,100  
256K x 72  
8 of 128K x 18  
133,100  
SRAMs Used  
4 of 128K x 18  
133,100  
8 of 256K x 18  
133,100  
System Clock (MHz)  
Data tCO  
4.5, 5.5 ns  
4.5, 5.5 ns  
4.5, 5.5 ns  
4.5, 5.5 ns  
Document #: 38-05166 Rev. **  
Page 3 of 14  
CYM9265/CYM9266  
CYM9267/CYM9268  
PRELIMINARY  
Pin Configuration  
Dual Read-Out SIMM (DIMM)  
Top View  
GND  
1
2
3
4
5
6
7
85  
86  
GND  
D
D
DP  
63  
62  
7
61  
D
87  
88  
89  
90  
91  
92  
93  
94  
V
GND  
CC3  
D
D
D
D
60  
58  
59  
57  
GND  
GND  
D
D
56  
55  
8
DP  
6
54  
9
D
10  
GND  
V
CC3  
D
D
GND  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
95  
96  
97  
98  
99  
D
D
GND  
D
D
GND  
D
D
53  
51  
52  
50  
D
DP  
49  
5
48  
47  
V
D
D
100  
101  
102  
103  
104  
105  
106  
107  
108  
109  
110  
111  
112  
113  
114  
115  
116  
117  
118  
119  
120  
121  
122  
123  
124  
CC3  
46  
44  
45  
43  
GND  
D
GND  
D
42  
41  
D
40  
DP  
4
GND  
V
CC3  
D
39  
D
D
38  
36  
D
37  
GND  
GND  
D
D
D
35  
33  
34  
32  
D
GND  
CLK3  
GND  
CLK2  
GND  
GND  
D
DP  
31  
3
30  
D
D
29  
V
D
CC3  
GND  
D
28  
27  
25  
D
GND  
D
D
26  
GND  
37  
38  
39  
40  
DP  
D
24  
2
22  
D
23  
V
GND  
CC3  
D
21  
D
20  
D
GND  
D
19  
D
GND  
D
D
GND  
D
D
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
125  
126  
127  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
139  
140  
141  
142  
143  
144  
145  
146  
147  
148  
149  
150  
151  
152  
153  
154  
155  
156  
157  
158  
159  
18  
17  
16  
15  
DP  
1
V
CC3  
D
D
GND  
D
14  
12  
13  
11  
GND  
10  
D
9
D
8
DP  
0
GND  
V
D
D
CC3  
D
D
7
5
6
4
GND  
GND  
D
D
D
D
CC3  
3
1
2
0
V
GND  
PD  
NC  
GND  
A
A
GND  
A
A
GND  
A
0
PD  
1
A
17  
GND  
A
16  
14  
15  
A
13  
V
CC3  
A
12  
10  
11  
A
9
GND  
A
67  
7
8
6
A
5
68  
69  
70  
71  
72  
73  
74  
75  
75  
77  
78  
79  
80  
81  
82  
A
GND  
V
CC3  
A
A
3
4
2
0
A
A
1
A
ADSP  
GND  
CLK0  
GND  
CLK1  
GND  
WE7  
WE5  
GND  
GND  
WE6  
WE4  
GND  
WE2  
WE0  
160  
161  
162  
163  
164  
165  
166  
167  
168  
WE3  
WE1  
V
CC3  
GND  
OE0  
CS0  
GND  
OE1  
CS1  
GND  
83  
84  
9260-4  
Document #: 38-05166 Rev. **  
Page 4 of 14  
CYM9265/CYM9266  
CYM9267/CYM9268  
PRELIMINARY  
Pin Definitions  
Signal  
Description  
VCC3  
3V Supply  
GND  
Ground  
A[17:0]  
OE[1:0]  
WE[7:0]  
CS[1:0]  
PD0–PD1  
D[63:0]  
DP[7:0]  
CLK[0:3]  
ADSP  
Addresses From Processor  
Output Enables For The Two Banks  
Byte Write Enables  
Chip Select For The Two Banks  
Presence Detect Output Pins  
Data Lines From Processor  
Data Parity Lines From Processor  
Clock Lines To The Module  
Address Strobe From The Processor  
Signal Not Connected On Module  
Reserved  
NC  
RSVD  
Presence Detect Pins  
PD1  
GND  
NC  
PD0  
NC  
CYM9265 - Pipelined 64K x 72  
CYM9266 - Pipelined 128K x 72  
CYM9267 - Pipelined 256K x 72  
CYM9268 - Pipelined 512K x 72  
GND  
GND  
NC  
GND  
NC  
Document #: 38-05166 Rev. **  
Page 5 of 14  
CYM9265/CYM9266  
CYM9267/CYM9268  
PRELIMINARY  
DC Input Voltage ........................................... –0.5V to +4.6V  
Maximum Ratings  
Output Current into Outputs (LOW)............................. 20 mA  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
Operating Range  
Storage Temperature................................. –55°C to +125°C  
Ambient  
Ambient Temperature  
with Power Applied ........................................ –0°C to +70°C  
Range  
Temperature  
VCC  
Commercial  
0°C to +70°C  
3.3V ± 5%  
3.3V Supply Voltage to Ground Potential ..... –0.5V to +4.5V  
DC Voltage Applied to Outputs  
in High Z State.............................................. –0.5V to +4.6V  
Electrical Characteristics Over the Operating Range  
Parameter  
VIH  
Description  
Input HIGH Voltage  
Input LOW Voltage  
Output HIGH Voltage  
Output LOW Voltage  
Test Condition  
Min.  
2.0  
Max.  
Unit  
V
VCC + 0.3  
0.8  
VIL  
–0.3  
2.4  
V
VOH  
VCC = Min., IOH = –4 mA  
VCC = Min., IOL = 8 mA  
V
VOL  
0.4  
V
ICC (9265)  
ICC (9266)  
ICC (9267)  
ICC (9268)  
VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC  
VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC  
VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f =fMAX = 1/tRC  
VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC  
1000  
1000  
1200  
2400  
mA  
mA  
mA  
mA  
Capacitance[1]  
Parameter  
Description  
Test Conditions  
Max.  
9265  
9266  
9267  
9268  
9265  
9266  
9267  
9268  
9265  
9266  
9267  
9268  
9265  
9266  
9267  
9268  
Max.  
24  
14  
20  
40  
24  
16  
20  
40  
9
Unit  
pF  
pF  
pF  
pF  
pF  
pF  
pF  
pF  
pF  
pF  
pF  
pF  
pF  
pF  
pF  
pF  
CA  
Address Input Capacitance  
Control Input Capacitance  
Input/Output Capacitance  
Clock Capacitance  
TA = 25°C, f = 1 MHz,  
VCC = 5.0V  
CI  
TA = 25°C, f = 1 MHz,  
VCC = 5.0V  
CO  
TA = 25°C, f = 1 MHz,  
VCC = 5.0V  
5
8
16  
6
CCLK  
TA = 25°C, f = 1 MHz,  
VCC = 5.0V  
3
5
10  
Note:  
1. Tested initially and after any design or process changes that may affect these parameters.  
Document #: 38-05166 Rev. **  
Page 6 of 14  
CYM9265/CYM9266  
CYM9267/CYM9268  
PRELIMINARY  
AC Test Loads and Waveforms[3]  
R1  
V
CCQ  
OUTPUT  
ALL INPUT PULSES  
OUTPUT  
3.3V  
GND  
90%  
90%  
R = 50 Ω  
L
10%  
R2  
10%  
5 pF  
V =1.5V  
L
INCLUDING  
JIG AND  
SCOPE  
≤ 3 ns  
≤ 3 ns  
(b)[2]  
9260-5  
(a)  
9660-6  
Switching Characteristics Over the Operating Range  
CYM9265/66/67/68  
133 MHz 100 MHz  
Parameter  
tCYC  
Description  
Min.  
Max.  
Min.  
Max.  
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Clock Cycle Time  
Clock HIGH  
7.5  
1.9  
1.9  
2
10  
3.5  
3.5  
2
tCH  
tCL  
Clock LOW  
tAS  
Address Set-Up Before CLK Rise  
Address Hold After CLK Rise  
Data Output Valid After CLK Rise  
Data Output Hold After CLK Rise  
ADSP, ADSC Set-Up Before CLK Rise  
ADSP, ADSC Hold After CLK Rise  
WH, WL Set-Up Before CLK Rise  
WH, WL Hold After CLK Rise  
Data Input Set-Up Before CLK Rise  
Data Input Hold After CLK Rise  
Chip Select Set-Up  
tAH  
0.5  
0.5  
tCO  
4.5  
5.5  
tDOH  
tADS  
tADSH  
tWES  
tWEH  
tDS  
3
2
3
3.1  
0.5  
2
0. 5  
2
0.5  
2
0.5  
2
tDH  
0.5  
2
0.5  
2
tCSS  
tCSH  
tEOZ  
Chip Select Hold After CLK Rise  
OE HIGH to Output High Z[4]  
OE LOW to Output Valid  
0.5  
0.5  
7
7
tEOV  
4.5  
5.5  
Notes:  
2. Resistor values for VCCQ=3.3V are R1 = 317Ω and R2 = 351 Ω.  
3. Unless otherwise noted, test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output  
loading of the specified IOL/IOH and load capacitance. Shown in (a) and (b) of AC Test Loads. All measurements are made at room temperature.  
4.  
tEOZ is specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 500 mV from steady-state voltage.  
Document #: 38-05166 Rev. **  
Page 7 of 14  
CYM9265/CYM9266  
CYM9267/CYM9268  
PRELIMINARY  
Switching Waveforms  
Write  
Single Write  
Burst Write  
Pipelined Write  
t
Unselected  
CH  
t
CYC  
CLK  
t
ADH  
t
ADS  
t
ADSP ignored with CE inactive  
CL  
1
ADSP  
ADSC  
ADV  
t
ADH  
t
ADSC initiated write  
ADS  
t
t
ADVH  
ADVS  
t
ADV Must Be Inactive for ADSP Write  
WD2  
AS  
WD3  
ADD  
GW  
WE  
WD1  
t
AH  
t
WH  
t
WH  
t
WS  
t
WS  
t
t
CES  
CE masks ADSP  
CEH  
1
CE  
1
t
t
CEH  
CES  
Unselected with CE  
2
CE  
2
CE  
3
t
CES  
t
CEH  
OE  
t
DH  
t
DS  
High-Z  
High-Z  
Data  
In  
3a  
2a  
= UNDEFINED  
1a  
2b  
2c  
2d  
= DON’T CARE  
Document #: 38-05166 Rev. **  
Page 8 of 14  
CYM9265/CYM9266  
CYM9267/CYM9268  
PRELIMINARY  
Switching Waveforms (continued)  
Read  
Burst Read  
Single Read  
Unselected  
tCYC  
tCH  
Pipelined Read  
CLK  
tADH  
tADS  
tCL  
ADSP ignored with CE1 inactive  
ADSP  
tADS  
ADSC initiated read  
ADSC  
ADV  
tADVS  
tADH  
Suspend Burst  
tADVH  
tAS  
ADD  
GW  
RD3  
RD1  
RD2  
tAH  
tWS  
tWS  
tWH  
WE  
tCES  
tCEH  
tWH  
CE1 masks ADSP  
CE1  
Unselected with CE2  
CE2  
tCES  
tCEH  
CE3  
OE  
tCES  
tEOV  
tCEH  
tOEHZ  
tDOH  
tCO  
Data Out  
2c  
1a  
3a  
2d  
2a  
2b  
tCLZ  
tCHZ  
= DON’T CARE  
= UNDEFINED  
Document #: 38-05166 Rev. **  
Page 9 of 14  
CYM9265/CYM9266  
CYM9267/CYM9268  
PRELIMINARY  
Switching Waveforms (continued)  
Read / Write  
Single Read  
tCYC  
Single Write  
tCH  
Unselected  
Burst Read  
Pipelined Read  
CLK  
tADH  
tADS  
tCL  
ADSP ignored with CE1 inactive  
ADSP  
ADSC  
ADV  
tADS  
tADVS  
tADH  
tAS  
tADVH  
WD2  
ADD  
RD1  
RD3  
tAH  
GW  
WE  
CE1  
tWS  
tWS  
tWH  
tCES  
tCEH  
tWH  
CE1 masks ADSP  
CE2  
CE3  
tCES  
tCEH  
tEOV  
tCES  
tCEH  
OE  
tEOHZ  
tDS  
tDH  
tDOH  
See Note.  
2a  
tEOLZ  
tCO  
3b  
Out  
3a  
Out  
3c  
Out  
3d  
Out  
Data In/Out  
1a  
2a  
In  
Out  
Out  
tCHZ  
= UNDEFINED  
= DON’T CARE  
Document #: 38-05166 Rev. **  
Page 10 of 14  
CYM9265/CYM9266  
CYM9267/CYM9268  
PRELIMINARY  
Switching Waveforms (continued)  
Pipeline Timing  
tCYC  
tCL  
tCH  
CLK  
tAS  
WD1  
WD2  
WD3  
WD4  
RD1  
RD2  
RD3  
RD4  
ADD  
tADS  
tADH  
ADSC initiated Reads  
ADSC  
ADSP initiated Reads  
ADSP  
ADV  
tCEH  
tCES  
CE1  
CE  
tWES  
tWEH  
WE  
OE  
ADSP ignored  
with CE1 HIGH  
tCLZ  
Data In/Out  
1a  
In  
1a  
2a  
3a  
4a  
2a  
In  
3a  
In  
4a  
Out Out Out Out  
In  
tCO  
tDOH  
Back to Back Reads  
tCHZ  
= UNDEFINED  
= DON’T CARE  
Document #: 38-05166 Rev. **  
Page 11 of 14  
CYM9265/CYM9266  
CYM9267/CYM9268  
PRELIMINARY  
Ordering Information  
Speed  
Package  
Operating  
(MHz)  
Ordering Code  
CYM9265PM-100C  
CYM9266PM-100C  
CYM9267PM-100C  
CYM9268PM-100C  
CYM9265PM-133C  
CYM9266PM-133C  
CYM9267PM-133C  
CYM9268PM-133C  
Name  
PM43  
PM44  
PM44  
PM44  
PM43  
PM44  
PM44  
PM44  
Package Type  
Description  
Range  
100  
168-Pin Dual-Readout SIMM (DIMM) Sync 64K x 72  
168-Pin Dual-Readout SIMM (SIMM) Sync 128K x 72  
168-Pin Dual-Readout SIMM (DIMM) Sync 256K x 72  
168-Pin Dual-Readout SIMM (DIMM) Sync 512K x 72  
168-Pin Dual-Readout SIMM (DIMM) Sync 64K x 72  
168-Pin Dual-Readout SIMM (SIMM) Sync 128K x 72  
168-Pin Dual-Readout SIMM (DIMM) Sync 256K x 72  
168-Pin Dual-Readout SIMM (DIMM) Sync 512K x 72  
Commercial  
133  
Document #: 38-05166 Rev. **  
Page 12 of 14  
CYM9265/CYM9266  
CYM9267/CYM9268  
PRELIMINARY  
Package Diagrams  
168-Pin Single-Sided DIMM PM43  
168-Pin Dual Sided DIMM PM44  
Document #: 38-05166 Rev. **  
Page 13 of 14  
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize  
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.  
CYM9265/CYM9266  
CYM9267/CYM9268  
PRELIMINARY  
Document Title: CYM9265/CYM9266/CYM9267/CYM9268 64K/128K/512K x 72 SRAM Modules  
Document Number: 38-05166  
Issue  
ECN NO. Date  
Orig. of  
Change  
REV.  
Description of Change  
**  
110196  
09/29/01  
SZV  
Change from Spec number: 38-00779 to 38-05166  
Document #: 38-05166 Rev. **  
Page 14 of 14  
厂商 型号 描述 页数 下载

MERRIMAC

 		CYM-13R-9G 定向耦合器[ DIRECTIONAL COUPLER ] 2 页

SUMIDA

 		CYM-2B 滤波线圈\u003c SMD型： CYM系列\u003e[ Filter Coils < SMD Type: CYM Series> ] 2 页

ETC

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ETC

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ETC

 		CYM1220HD-12MB X4 SRAM模块\n[ x4 SRAM Module ] 5 页

ETC

 		CYM1220HD-15C X4 SRAM模块\n[ x4 SRAM Module ] 5 页

ETC

 		CYM1220HD-15MB X4 SRAM模块\n[ x4 SRAM Module ] 5 页

ETC

 		CYM1220HD-20MB X4 SRAM模块\n[ x4 SRAM Module ] 5 页

CYPRESS

 		CYM1240HD-25C [ SRAM Module, 256KX4, 25ns, CMOS, CDIP28, HERMETIC SEALED, MODULE, DIP-28 ] 1 页

CYPRESS

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