请登录

免费注册
全部商品
电子元器件
方案中心
工业品
PDF资料
购物车 0
上传BOM

产品分类

找货询价

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

QQ咨询

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

会员中心
购物车
技术支持

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

售后咨询

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

HYS72V16220GU-7.5

型号：

HYS72V16220GU-7.5

品牌：

INFINEON[ Infineon ]

页数：

13 页

PDF大小：

104 K

下载PDF手册
3.3V 8M x 64/72-Bit 1 BANK SDRAM Module  
3.3V 16M x 64/72-Bit 2 BANK SDRAM Module  
HYS64/72V8200GU-7.5  
HYS64/72V16220GU-7.5  
PC133 168 pin unbuffered DIMM Modules  
• 168 Pin PC133-compatible unbuffered 8 Byte Dual-In-Line SDRAM Modules  
for PC main memory applications  
• 1 bank 8M x 64, 8M x 72 and 2 bank 16M x 64, 16M x 72 organisation  
• Optimized for byte-write non-parity or ECC applications  
• JEDEC standard Synchronous DRAMs (SDRAM)  
• Fully compatible to JEDEC PC133 module specification  
• SDRAM Performance:  
-7.5  
133  
Units  
MHz  
fCK  
tAC  
Clock frequency (max.)  
Clock access time  
5.4  
ns  
• Programmed Latencies :  
Product Speed  
CL  
3
tRCD  
tRP  
3
-7.5  
PC133  
PC100  
3
2
2
2
• Single +3.3V(± 0.3V ) power supply  
• Programmable CAS Latency, Burst Length and Wrap Sequence  
(Sequential & Interleave)  
• Auto Refresh (CBR) and Self Refresh  
• Decoupling capacitors mounted on substrate  
• All inputs, outputs are LVTTL compatible  
2
• Serial Presence Detect with E PROM  
• Utilizes 8M x 8 SDRAMs in TSOPII-54 packages  
• 4096 refresh cycles every 64 ms  
• 133,35 mm x 31.75 mm x 4,00 mm card size with gold contact pads  
INFINEON TEchnologies  
1
4.99  
HYS64(72)V8200/16220GU-7.5  
PC133 SDRAM-Modules  
The HYS64(72)8200-7.5 and HYS64(72)16220-7.5 are industry standard 168-pin 8-byte Dual in-line Memory  
Modules (DIMMs) which are organised as 8M x 64, 8M x 72 in 1 bank and 16M x 64 and 16M x 72 in two banks  
high speed memory arrays designed with 64M Synchronous DRAMs (SDRAMs) for non-parity and ECC  
applications. The DIMMs use -7.5 speed soredt 8M x 8 SDRAM devices in TSOP54 packages to meet the PC133  
requirement. Decoupling capacitors are mounted on the PC board. The PC board design is according to INTEL’s  
PC SDRAM Rev. 1.0 module specification.  
The DIMMs have a serial presence detect, implemented with a serial E2PROM using the two pin I2C protocol. The  
first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes are available to the end user.  
All INFINEON 168-pin DIMMs provide a high performance, flexible 8-byte interface in a 133,35 mm long footprint,  
with 1,25“ ( 31,75 mm) height.  
Ordering Information  
Type  
Ordering Code  
Package  
Descriptions  
Module  
Height  
133 MHz 8M x 64 1 bank SDRAM module  
133 MHz 8M x 72 1 bank SDRAM module  
133 MHz 16M x 64 2 bank SDRAM module  
133 Mhz 16M x 72 2 bank SDRAM module  
HYS 64V8200GU-7.5  
HYS 72V8200GU-7.5  
PC133-333-520  
PC133-333-520  
L-DIM-168-30  
L-DIM-168-30  
L-DIM-168-30  
L-DIM-168-30  
1,25“  
1,25“  
1,25“  
1,25“  
HYS 64V16220GU-7.5 PC133-333-520  
HYS 72V16220GU-7.5 PC133-333-520  
Pin Names  
A0-A11  
Address Inputs  
Bank Selects  
CLK0 - CLK3  
Clock Input  
Data Mask  
BA0, BA1  
DQMB0 -  
DQMB7  
DQ0 - DQ63  
CB0-CB7  
Data Input/Output  
CS0 - CS3  
Vcc  
Chip Select  
Check Bits (x72  
Power (+3.3 Volt)  
organisation only)  
RAS  
Row Address Strobe  
Vss  
Ground  
CAS  
Column Address Strobe  
Read / Write Input  
Clock Enable  
SCL  
SDA  
N.C.  
Clock for Presence Detect  
WE  
Serial Data Out for Presence Detect  
No Connection  
CKE0, CKE1  
Address Format:  
Part Number  
HYS 64V8200GU  
HYS 72V8200GU  
Rows  
12  
Columns Bank Select  
Refresh  
4k  
Period  
64 ms  
64 ms  
64 ms  
64 ms  
Interval  
15,6 µs  
15,6 µs  
15,6 µs  
15,6 µs  
8M x 64  
8M x 72  
9
9
9
9
2
2
2
2
12  
4k  
16M x 64 HYS 64V16220GU  
16M x 72 HYS 72V16220GU  
12  
4k  
12  
4k  
INFINEON Technologies  
2
HYS64(72)V8200/16220GU-7.5  
PC133 SDRAM-Modules  
Pin Configuration  
PIN #  
Symbol  
PIN #  
Symbol  
PIN #  
Symbol  
PIN #  
Symbol  
1
VSS  
DQ0  
DQ1  
DQ2  
DQ3  
VCC  
DQ4  
DQ5  
DQ6  
DQ7  
DQ8  
VSS  
DQ9  
DQ10  
DQ11  
DQ12  
DQ13  
VCC  
DQ14  
DQ15  
NC (CB0)  
NC (CB1)  
VSS  
NC  
43  
VSS  
85  
VSS  
127  
VSS  
2
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
DU  
86  
DQ32  
DQ33  
DQ34  
DQ35  
VCC  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
139  
140  
141  
142  
143  
144  
145  
146  
147  
148  
149  
150  
151  
152  
153  
154  
155  
156  
157  
158  
159  
160  
161  
162  
163  
164  
165  
166  
167  
168  
CKE0  
CS3  
3
CS2  
87  
4
DQMB2  
DQMB3  
DU  
88  
DQMB6  
DQMB7  
NC  
5
89  
6
90  
7
VCC  
91  
DQ36  
DQ37  
DQ38  
DQ39  
DQ40  
VSS  
VCC  
NC  
8
NC  
92  
9
NC  
93  
NC  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
NC (CB2)  
NC (CB3)  
VSS  
94  
CB6  
95  
CB7  
96  
VSS  
DQ16  
DQ17  
DQ18  
DQ19  
VCC  
97  
DQ41  
DQ42  
DQ43  
DQ44  
DQ45  
VCC  
DQ48  
DQ49  
DQ50  
DQ51  
VCC  
DQ52  
NC  
98  
99  
100  
101  
102  
103  
104  
105  
106  
107  
108  
109  
110  
111  
112  
113  
114  
115  
116  
117  
118  
119  
120  
121  
122  
123  
124  
125  
126  
DQ20  
NC  
DQ46  
DQ47  
NC (CB4)  
NC (CB5)  
VSS  
DU  
DU  
CKE1  
VSS  
NC  
VSS  
DQ21  
DQ22  
DQ23  
VSS  
DQ53  
DQ54  
DQ55  
VSS  
NC  
NC  
NC  
VCC  
WE  
VCC  
DQ24  
DQ25  
DQ26  
DQ27  
VCC  
CAS  
DQ56  
DQ57  
DQ58  
DQ59  
VCC  
DQ60  
DQ61  
DQ62  
DQ63  
VSS  
DQMB0  
DQMB1  
CS0  
DQMB4  
DQMB5  
CS1  
DU  
RAS  
VSS  
A0  
DQ28  
DQ29  
DQ30  
DQ31  
VSS  
VSS  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
CLK2  
NC  
A9  
CLK3  
NC  
A10  
BA0  
BA1  
WP  
A11  
SA0  
VCC  
VCC  
CLK0  
SDA  
VCC  
SA1  
SCL  
CLK1  
NC  
SA2  
VCC  
VCC  
Note : Pinnames in brackets are for the x72 ECC versions  
INFINEON Technologies  
3
HYS64(72)V8200/16220GU-7.5  
PC133 SDRAM-Modules  
WE  
CS0  
CS WE  
CS WE  
DQMB0  
DQ(7:0)  
DQMB4  
DQM  
DQM  
DQ(39:32)  
DQ0-DQ7  
DQ0-DQ7  
D0  
CS WE  
D4  
CS WE  
DQM  
DQM  
DQ0-DQ7  
DQMB1  
DQMB5  
DQ0-DQ7  
DQ(15:8)  
DQ(47:40)  
D1  
CS WE  
D5  
DQM  
CB(7:0)  
DQ0-DQ7  
D8  
CS2  
CS WE  
CS WE  
DQMB2  
DQM  
DQM  
DQMB6  
DQ0-DQ7  
DQ0-DQ7  
DQ(55:48)  
DQ(23:16)  
D6  
CS WE  
D2  
CS WE  
DQMB7  
DQM  
DQM  
DQMB3  
DQ(63:56)  
DQ0-DQ7  
DQ0-DQ7  
DQ(31:24)  
D3  
D0 - D7,(D8)  
D7  
E2PROM (256wordx8bit)  
A0-A11,BA0,BA1  
VCC  
VSS  
SA0  
SA1  
SA2  
SCL  
SA0  
SA1  
SA2  
SCL  
D0 - D7,(D8)  
C0-C15,(C16,C17)  
D0 - D7,(D8)  
SDA  
WP  
47k  
RAS  
CAS  
CKE0  
D0 - D7,(D8)  
D0 - D7,(D8)  
Clock Wiring  
8M x 64  
CLK0 4 SDRAM+3.3pF 5 SDRAM  
CLK1 Termination Termination  
CLK2 4 SDRAM+3.3pF 4 SDRAM+3.3pF  
CLK3 Termination Termination  
8M x 72  
D0 - D7,(D8)  
Note: D8 is only used in the x72 ECC version  
Block Diagram for 8M x 64/72 SDRAM DIMM modules (HYS64/72V8200GU)  
INFINEON Technologies  
4
HYS64(72)V8200/16220GU-7.5  
PC133 SDRAM-Modules  
CS1  
CS0  
CS  
CS  
CS  
CS  
DQMB0  
DQ(7:0)  
DQM  
DQM  
DQMB4  
DQM  
DQM  
DQ0-DQ7  
D0  
DQ0-DQ7  
D8  
DQ(39:32)  
DQ0-DQ7  
D4  
DQ0-DQ7  
D12  
CS  
CS  
CS  
CS  
DQM  
DQM  
DQM  
DQM  
DQMB1  
DQMB5  
DQ(15:8)  
DQ(47:40)  
DQ0-DQ7  
D1  
DQ0-DQ7  
D9  
DQ0-DQ7  
D5  
DQ0-DQ7  
D13  
CS  
CS  
DQM  
DQM  
DQ0-DQ7  
D16  
DQ0-DQ7  
D17  
CB(7:0)  
CS3  
CS2  
CS  
CS  
CS  
CS  
DQM  
DQM  
DQMB2  
DQM  
DQM  
DQMB6  
DQ(23:16)  
DQ(55:48)  
DQ0-DQ7  
D2  
DQ0-DQ7  
D10  
DQ0-DQ7  
D6  
DQ0-DQ7  
D14  
CS  
CS  
CS  
CS  
DQMB3  
DQM  
DQM  
DQMB7  
DQM  
DQM  
DQ(31:24)  
DQ(63:56)  
DQ0-DQ7  
D3  
DQ0-DQ7  
D11  
DQ0-DQ7  
D7  
DQ0-DQ7  
D15  
E2PROM (256wordx8bit)  
D0 - D15,(D16,D17)  
D0 - D15,(D16,D17)  
A0-A11,BA0,BA1  
VDD  
SA0  
SA1  
SA2  
SCL  
SA0  
SDA  
WP  
SA1  
SA2  
SCL  
C0-C31,(C32..C35)  
VSS  
D0 - D7,(D8)  
47k  
RAS, CAS, WE  
CKE0  
D0 - D15,(D16,D17)  
Clock Wiring  
16M x 64  
D0 - D7,(D16)  
16M x 72  
VDD  
10k  
CLK0 4 SDRAM+3.3pF 5 SDRAM  
CLK1 4 SDRAM+3.3pF 5 SDRAM  
CLK2 4 SDRAM+3.3pF 4 SDRAM+3.3pF  
CLK3 4 SDRAM+3.3pF 4 SDRAM+3.3pF  
CKE1  
D9 - D15,(D17)  
Note: D16 & D17 is only used in the x72 ECC version and all resistor values are 10 Ohms except otherwise noted.  
Block Diagram for 16M x 64/72 SDRAM DIMM modules (HYS64/72V1620GU)  
INFINEON Technologies  
5
HYS64(72)V8200/16220GU-7.5  
PC133 SDRAM-Modules  
DC Characteristics  
TA = 0 to 70 °C; VSS = 0 V; VDD,VDDQ = 3.3 V ± 0.3 V  
Parameter  
Symbol  
Limit Values  
Unit  
min.  
max.  
Vcc+0.3  
0.8  
Input high voltage  
VIH  
VIL  
2.0  
– 0.5  
2.4  
V
Input low voltage  
V
Output high voltage (IOUT = – 4.0 mA)  
Output low voltage (IOUT = 4.0 mA)  
VOH  
VOL  
II(L)  
–
V
–
0.4  
V
Input leakage current, any input  
– 40  
40  
µA  
(0 V < VIN < 3.6 V, all other inputs = 0 V)  
Output leakage current  
IO(L)  
– 40  
40  
µA  
(DQ is disabled, 0 V < VOUT < VCC)  
Capacitance  
TA = 0 to 70 °C; VDD = 3.3 V ± 0.3 V, f = 1 MHz  
Parameter  
Symbol  
Limit Values  
Unit  
max.  
max.  
max.  
max.  
8Mx64  
8Mx72 16Mx64 16Mx72  
Input capacitance  
CI1  
65  
72  
105  
144  
pF  
(A0 to A11, BA0, BA1, RAS, CAS, WE)  
Input capacitance (CS0 -CS3, )  
Input capacitance (CLK0 - CLK3)  
Input capacitance (CKE0, CKE1)  
Input capacitance (DQMB0 - DQMB7)  
CI2  
CICL  
CI3  
CI4  
CIO  
32  
35  
65  
13  
10  
40  
38  
72  
13  
10  
32  
35  
65  
20  
15  
40  
38  
72  
20  
15  
pF  
pF  
pF  
pF  
pF  
Input / Output capacitance  
(DQ0-DQ63, CB0-CB7)  
Input Capacitance (SCL,SA0-2)  
Input/Output Capacitance  
C
C
8
8
8
8
pF  
pF  
sc  
10  
10  
10  
10  
sd  
INFINEON Technologies  
6
HYS64(72)V8200/16220GU-7.5  
PC133 SDRAM-Modules  
o
Operating Currents (T = 0 to 70 C, Vdd = 3.3V ± 0.3V 1)  
A
(Recommended Operating Conditions unless otherwise noted)  
Symb.  
Note  
Parameter & Test Condition  
-7.5  
max.  
OPERATING CURRENT  
trc=trcmin., tck=tckmin.  
Ouputs open, Burst Length = 4, CL=3  
All banks operated in random access,  
all banks operated in ping-pong manner  
to maximize gapless data access  
ICC1  
120  
2
mA  
mA  
1
1
PRECHARGE STANDBY CURRENT in tck = min.  
Power Down Mode  
ICC2P  
tck = Infinity  
ICC2PS  
ICC2N  
1
mA  
mA  
1
1
CS =VIH (min.), CKE<=Vil(max)  
PRECHARGE STANDBY CURRENT in tck = min.  
40  
Non-Power Down Mode  
tck = Infinity  
ICC2NS  
ICC3N  
ICC3P  
5
50  
8
mA  
mA  
mA  
1
1
1
CS = VIH (min.), CKE>=Vih(min)  
NO OPERATING CURRENT  
CKE>=VIH(min.)  
CKE<=VIL(max.)  
tck = min., CS = VIH(min),  
active state ( max. 4 banks)  
BURST OPERATING CURRENT  
tck = min.,  
Read command cycling  
ICC4  
ICC5  
80  
mA 1,2  
AUTO REFRESH CURRENT  
tck = min.,  
1
140  
mA  
Auto Refresh command cycling  
SELF REFRESH CURRENT  
Self Refresh Mode, CKE=0.2V  
standard version  
ICC6  
1
mA  
1
INFINEON Technologies  
7
HYS64(72)V8200/16220GU-7.5  
PC133 SDRAM-Modules  
AC Characteristics 3)4)  
TA = 0 to 70 °C; VSS = 0 V; VCC = 3.3 V ± 0.3 V, tT = 1 ns  
Symbol  
Note  
Parameter  
Limit  
Unit  
Values  
-7.5  
PC133-333  
min. max.  
Clock and Clock Enable  
Clock Cycle Time  
tCK  
fCK  
tAC  
CAS Latency = 3  
CAS Latency = 2  
7.5  
10  
–
–
ns  
ns  
System Frequency  
CAS Latency = 3  
CAS Latency = 2  
–
–
133 MHz  
100 MHz  
Clock Access Time  
4,5)  
CAS Latency = 3  
CAS Latency = 2  
–
–
5.4 ns  
6
–
–
–
–
–
ns  
ns  
ns  
ns  
ns  
ns  
6)  
6)  
7)  
7)  
8)  
Clock High Pulse Width  
tCH  
2.5  
2.5  
1.5  
0.8  
2.5  
Clock Low Pulse Width  
Input Setup time  
tCL  
tCS  
Input Hold Time  
tCH  
CKE Setup Time  
tCKSP  
(Power down mode)  
9)  
CKE Setup Time  
(Self Refresh Exit)  
tCKSR  
tT  
8
1
–
–
ns  
ns  
Transition time (rise and fall)  
Common Parameters  
RAS to CAS delay  
Precharge Time  
tRCD  
tRP  
tRAS  
tRC  
tRRD  
tCCD  
20  
20  
–
–
ns  
ns  
Active Command Period  
Cycle Time  
45 100k ns  
–
–
–
67.5  
15  
1
ns  
Bank to Bank Delay Time  
ns  
CAS to CAS delay time (same  
bank)  
CLK  
INFINEON Technologies  
8
HYS64(72)V8200/16220GU-7.5  
PC133 SDRAM-Modules  
Symbol  
Note  
Parameter  
Limit  
Unit  
Values  
-7.5  
PC133-333  
min. max.  
Refresh Cycle  
8)  
9)  
Refresh Period (4096 cycles)  
Self Refresh Exit Time  
tREF  
–
64 ms  
tSREX  
10  
–
ns  
Read Cycle  
4)  
Data Out Hold Time  
tOH  
tLZ  
tHZ  
2.7  
0
–
–
ns  
ns  
Data Out to Low Impedance  
Data Out to High Impedance  
10)  
2.7  
–
7.5 ns  
DQM Data Out Disable Latency tDQZ  
2
CLK  
Write Cycle  
–
–
Data input to Precharge  
(write recovery)  
tWR  
2
0
CLK  
CLK  
DQM Write Mask Latency  
tDQW  
INFINEON Technologies  
9
HYS64(72)V8200/16220GU-7.5  
PC133 SDRAM-Modules  
Notes:  
1. These parameters depend on the cycle rate. These values are measured at 133 MHz. Input  
signals are changed once during tck, excepts for ICC6 and for standby currents when tck=infinity.  
All values are shown per memory component.  
2. These parameters are measured with continous data stream during read access and all DQ  
toggling. CL=3 and BL=4 assumed and the VDDQ current is excluded.  
3. All AC characteristics are shown on SDRAM component level.  
An initial pause of 100µs is required after power-up, then a Precharge All Banks command must  
be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can  
begin.  
4. AC timing tests have V = 0.4 V and V = 2.4 V with the timing referenced to the 1.4 V crossover  
il  
ih  
point. The transition time is measured between V and V . All AC measurements assume t =1ns  
ih  
il  
T
with the AC output load circuit show. Specified tac and toh parameters are measured with a 50  
pF only, without any resistive termination and with a input signal of 1V / ns edge rate between  
0.8V and 2.0 V.  
tCH  
+ 1.4 V  
2.4 V  
CLOCK  
50 Ohm  
0.4 V  
tCL  
t
T
Z=50 Ohm  
tSETUP tHOLD  
I/O  
50 pF  
1.4V  
INPUT  
tAC  
tAC  
I/O  
tLZ  
tOH  
50 pF  
Measurement conditions for  
tac and toh  
1.4V  
OUTPUT  
tHZ  
fig.1  
5. If clock rising time is longer than 1ns, a time (t /2 -0.5) ns has to be added to this parameter.  
T
6. Rated at 1.5 V  
7. If t is longen than 1 ns, a time (t -1) ns has to be added to this parameter.  
T
T
8. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh  
commands must be given to “wake-up“ the device.  
9. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after  
CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied  
once the Self Refresh Exit command is registered.  
10.Referenced to the time which the output achieves the open circuit condition, not to output voltage  
levels.  
INFINEON Technologies  
10  
HYS64(72)V8200/16220GU-7.5  
PC133 SDRAM-Modules  
A serial presence detect storage device - E2PROM - is assembled onto the module. Information about the module  
configuration, speed, etc. is written into the E2PROM device during module production using a serial presence  
detect protocol ( I2C synchronous 2-wire bus).  
SPD-Table for PC133 Modules:  
Byte#  
Description  
SPD Entry Value  
Hex  
8Mx64 8Mx72 16Mx64 16Mx72  
-7.5  
-7.5  
-7.5  
-7.5  
0
1
2
3
Number of SPD bytes  
Total bytes in Serial PD  
Memory Type  
128  
256  
80  
80  
80  
80  
08  
08  
08  
08  
SDRAM  
12  
04  
04  
04  
04  
Number of Row Addresses  
(without BS bits)  
0C  
0C  
0C  
0C  
4
Number of Column Addres-  
ses(for 8Mx8 SDRAMs)  
9
09  
09  
09  
09  
5
6
7
8
9
Number of DIMM Banks  
Module Data Width  
1 / 2  
64 / 72  
0
01  
40  
00  
01  
75  
54  
01  
48  
00  
01  
75  
54  
02  
40  
00  
01  
75  
54  
02  
48  
00  
01  
75  
54  
Module Data Width (cont’d)  
Module Interface Levels  
SDRAM Cycle Time at CL=3  
LVTTL  
7.5 ns  
5.4 ns  
10 SDRAM Access time from  
Clock at CL=3  
11 Dimm Config  
none / ECC  
00  
80  
02  
80  
00  
80  
02  
80  
12 Refresh Rate/Type  
Self-Refresh,  
15.6µs  
1 3 S D R A M w i d t h , P r i m a r y  
x 8  
0 8  
00  
0 8  
08  
0 8  
00  
0 8  
08  
14 Error Checking SDRAM data  
width  
n/a / x8  
15 Minimum clock delay for  
back-to-back random column  
address  
t
ccd = 1 CLK  
01  
8F  
01  
8F  
01  
8F  
01  
8F  
16 Burst Length supported  
1, 2, 4, 8 & full  
page  
17 Number of SDRAM banks  
18 Supported CAS Latencies  
4
04  
06  
04  
06  
04  
06  
04  
06  
CAS latency = 2  
& 3  
19 CS Latencies  
20 WE Latencies  
CS latency = 0  
01  
01  
00  
01  
01  
00  
01  
01  
00  
01  
01  
00  
Write latency = 0  
21 SDRAM DIMM module  
attributes  
non buffered/non  
reg.  
22 SDRAM Device Attributes  
:General  
Vcc tol +/- 10%  
0E  
A0  
60  
FF  
0E  
A0  
60  
FF  
0E  
A0  
60  
FF  
0E  
A0  
60  
FF  
23 Min. Clock Cycle Time at  
CAS Latency = 2  
10.0 ns  
24 Max. data access time from  
Clock for CL=2  
6.0 ns  
25 Minimum Clock Cycle Time  
at CL = 1  
not supported  
INFINEON Technologies  
11  
HYS64(72)V8200/16220GU-7.5  
PC133 SDRAM-Modules  
Byte#  
Description  
SPD Entry Value  
Hex  
8Mx64 8Mx72 16Mx64 16Mx72  
-7.5  
-7.5  
-7.5  
-7.5  
26 Maximum Data Access Time  
from Clock at CL=1  
not supported  
20 ns  
FF  
FF  
FF  
FF  
27 Minimum Row Precharge  
Time  
14  
0F  
14  
2D  
10  
14  
0F  
14  
2D  
10  
14  
0F  
14  
2D  
10  
14  
0F  
14  
2D  
10  
28 Minimum Row Active to Row  
Active delay tRRD  
15  
29 Minimum RAS to CAS delay  
tRCD  
20 ns  
30 Minimum RAS pulse width  
tRAS  
45 ns  
31 Module Bank Density (per  
bank)  
64 MByte  
32 SDRAM input setup time  
33 SDRAM input hold time  
34 SDRAM data input hold time  
1.5 ns  
0.8 ns  
1.5 ns  
0.8 ns  
15  
08  
15  
08  
15  
08  
15  
08  
15  
08  
15  
08  
15  
08  
15  
08  
35 SDRAM data input setup  
time  
62-61 Superset information (may  
be used in future)  
FF  
FF  
FF  
FF  
62 SPD Revision  
Revision 1.2  
133 MHz  
12  
82  
XX  
12  
94  
XX  
12  
83  
12  
95  
XX  
63 Checksum for bytes 0 - 62  
64- Manufacturers information  
125 (optional)  
XX  
(FFh if not used)  
126 Frequency Specification  
127 133 MHz support details  
128+ Unused storage locations  
85  
AD  
FF  
85  
FD  
FF  
85  
AD  
FF  
85  
FD  
FF  
INFINEON Technologies  
12  
HYS64(72)V8200/16220GU-7.5  
PC133 SDRAM-Modules  
L-DIM-168-30  
SDRAM DIMM Module package  
133,35  
127,35  
4,0  
x)  
84  
1
10 11  
40 41  
+ 0.1  
42,18  
1,27  
-
66,68  
A
C
B
85  
94 95  
124 125  
168  
x)  
D
6,35  
6,35  
1,27  
1,0 + 0.5  
-
+
0,2 0,15  
-
2,0  
2,0  
Detail C  
Detail A  
Detail B  
DM168-30.WMF  
2.26  
RADIUS  
x) on ECC modules only  
1.27 + 0.10  
Detail D  
INFINEON Technologies  
13  
厂商 型号 描述 页数 下载

INFINEON

 		HYS64-72V2200GU-8 3.3V 2M ×64 /72- 1位BANK SDRAM模块3.3V 4M ×64 /72- 2位BANK SDRAM模块[ 3.3V 2M x 64/72-Bit 1 BANK SDRAM Module 3.3V 4M x 64/72-Bit 2 BANK SDRAM Module ] 17 页

INFINEON

 		HYS64-74V8200GU 3.3 V 8M ×64 /72- 1位银行SDRAM模块3.3 V 16M ×64 /72- 2位银行SDRAM模块[ 3.3 V 8M x 64/72-Bit 1 Bank SDRAM Module 3.3 V 16M x 64/72-Bit 2 Bank SDRAM Module ] 17 页

INFINEON

 		HYS6472V16200GU 3.3 V 16M ×64 /72-位SDRAM模块3.3 V 32M ×64 /72-位SDRAM模块3.3 V 64M ×64 /72-位SDRAM模块[ 3.3 V 16M x 64/72-Bit SDRAM Modules 3.3 V 32M x 64/72-Bit SDRAM Modules 3.3 V 64M x 64/72-Bit SDRAM Modules ] 17 页

INFINEON

 		HYS6472V4200GU 3.3V 4M ×64 /72- 1位BANK SDRAM模块3.3V 8M ×64 /72- 2位BANK SDRAM模块[ 3.3V 4M x 64/72-Bit 1 BANK SDRAM Module 3.3V 8M x 64/72-Bit 2 BANK SDRAM Module ] 15 页

INFINEON

 		HYS64D128020GBDL-6-A [ DDR DRAM Module, 128MX64, 0.7ns, CMOS, SO-DIMM-200 ] 11 页

ETC

 		HYS64D128020GBDL-7-A ？ 1GB （ 1024Mx64 ） PC2100 2银行？\n[ ?1GB (1024Mx64) PC2100 2-bank? ] 11 页

INFINEON

 		HYS64D128020GU-7-A 2.5 V 184针无缓冲DDR- SDRAM我模块[ 2.5 V 184-pin Unbuffered DDR-I SDRAM Modules ] 18 页

INFINEON

 		HYS64D128020GU-8-A 2.5 V 184针无缓冲DDR- SDRAM我模块[ 2.5 V 184-pin Unbuffered DDR-I SDRAM Modules ] 18 页

QIMONDA

 		HYS64D128020GU-8-A [ DDR DRAM Module, 128MX64, 0.8ns, CMOS, PDMA184 ] 18 页

INFINEON

 		HYS64D128021 200针的小型双列直插式内存模块[ 200-Pin Small Outline Dual-In-Line Memory Modules ] 23 页

购物指南

支付方式

配送服务

售后服务

发票须知

优惠券使用规则

特色服务

PCBA制造

国产品牌推荐

国产料号替代

质量保证

技术资料

行业资讯

关于我们

关于达普

联系我们

联系我们

服务热线：400-618-9990

企业邮箱：smail@ic72.com

服务时间：周一至周六 8:30-17:30

达普官方微信号

PDF索引：

A

B

C

D

E

F

G

H

I

J

K

L

M

N

O

P

Q

R

S

T

U

V

W

X

Y

Z

0

1

2

3

4

5

6

7

8

9

IC型号索引：

A

B

C

D

E

F

G

H

I

J

K

L

M

N

O

P

Q

R

S

T

U

V

W

X

Y

Z

0

1

2

3

4

5

6

7

8

9

Copyright 2024 gkzhan.com Al Rights Reserved 京ICP备06008810号-21 京

深圳网络警察报警平台
公共信息安全网络监察
经营性网站备案信息
不良信息举报中心
工商网监电子标识
全国公安机关备案
0.239633s