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HYS64V32220GD-8A-A

型号：

HYS64V32220GD-8A-A

品牌：

INFINEON[ Infineon ]

页数：

12 页

PDF大小：

90 K

下载PDF手册
3.3V SDRAM Modules  
HYS64V32220GD(L)-8A  
256MB PC100 144 pin SO-DIMM SDRAM Modules  
Preliminary information  
• 144 Pin Eight Byte Small Outline Dual-In-Line Synchronous DRAM Modules  
for PC 100 notebook applications  
• Two bank 32M x 64 non-parity module organisation  
• Performance:  
-8A  
PC100  
100  
Units  
MHz  
fCK  
tAC  
Clock frequency (max.)  
Clock access time  
CAS latency = 3  
6
ns  
• Single +3.3V(± 0.3V ) power supply  
• Programmable CAS Latency, Burst Length and Wrap Sequence  
(Sequential & Interleave)  
• Auto Refresh (CBR) and Self Refresh  
• Decoupling capacitors mounted on substrate  
• All inputs, outputs are LVTTL compatible  
2
• Serial Presence Detect with E PROM  
• Uses 256Mbit SDRAM components in 16M x 16 SDRAM organisation  
• 8192 refresh cycles every 64 ms  
• Gold contact pad  
• This module family is fully compliant with the latest INTEL SO-DIMM layout specification  
INFINEON Technologies  
1
6.99  
HYS64V32220GD(L)-8A  
PC100 144 pin SO-DIMM SDRAM Modules  
This INFINEON modules are industry standard 144 pin 8-byte Synchronous DRAM (SDRAM) Small  
Outline Dual In-line Memory Modules (SO-DIMM) which are organised as x64 high speed memory  
arrays designed for use in non-parity applications. These SO-DIMMs use 256Mbit SDRAMs in  
TSOPII packages. Decoupling capacitors are mounted on the board.  
2
The DIMMs use optional serial presence detects implemented via a serial E PROM using the two  
2
pin I C protocol. The first 128 bytes are utilized by the DIMM manufacturer and the second 128  
bytes are available to the end user.  
All INFINEON 144-pin SO-DIMMs provide a high performance, flexible 8-byte interface in a 67,5  
mm long footprint.  
Product Spectrum:  
SDRAMs RowAddr.  
used  
Bank  
Select  
Column Refresh Period  
Addr.  
32M x 64  
HYS64V32220GD(L)-8A 8 16Mx16  
13  
BA0, BA1  
9
8k  
7,8 µs  
Note: All partnumbers end with a place code (not shown), designating the die revision. Consult factory for current  
revision. Example: HYS64V32220GD-8A-A, indicating Rev.A dies are used for SDRAM components.  
Card Dimensions:  
Organisation  
32M x 64  
PCB-Board  
L x H x T [mm]  
INTEL Rev. 1.0  
67.60 x 31.75 x 3.80  
Pin Names  
A0-A12  
BA0,BA1  
DQ0 - DQ63  
RAS  
Address Inputs for 32M x 64 modules  
Bank Selects  
Data Input/Output  
Row Address Strobe  
Column Address Strobe  
Read / Write Input  
Clock Enable  
CAS  
WE  
CKE0  
CLK0  
Clock Input  
DQMB0 - DQMB7  
CS0 - CS3  
Vcc  
Data Mask  
Chip Select  
Power (+3.3 Volt)  
Ground  
Vss  
SCL  
Clock for Presence Detect  
Serial Data Out for Presence Detect  
No Connection  
SDA  
N.C.  
INFINEON Technologies  
2
HYS64V32220GD(L)-8A  
PC100 144 pin SO-DIMM SDRAM Modules  
Pin Configuration  
Front  
Side  
Back  
Side  
Front  
Side  
Back  
Side  
PIN #  
PIN #  
PIN #  
PIN #  
1
VSS  
2
VSS  
73  
NC  
Vss  
NC  
NC  
Vcc  
74  
CLK1  
3
DQ0  
DQ1  
DQ2  
DQ3  
VCC  
DQ4  
DQ5  
DQ6  
DQ7  
Vss  
4
DQ32  
DQ33  
DQ34  
DQ35  
Vcc  
75  
76  
Vss  
5
6
77  
78  
NC  
7
8
79  
80  
NC  
9
10  
12  
14  
16  
18  
20  
22  
24  
26  
28  
30  
32  
34  
36  
38  
40  
42  
44  
46  
48  
50  
52  
54  
56  
58  
60  
62  
64  
66  
68  
70  
72  
81  
82  
Vcc  
11  
13  
15  
17  
19  
21  
23  
25  
27  
29  
31  
33  
35  
37  
39  
41  
43  
45  
47  
49  
51  
53  
55  
57  
59  
61  
63  
65  
67  
69  
71  
83  
DQ16  
DQ17  
DQ18  
DQ19  
Vss  
84  
DQ48  
DQ49  
DQ50  
DQ51  
Vss  
DQ36  
DQ37  
DQ38  
DQ39  
Vss  
85  
86  
87  
88  
89  
90  
91  
92  
93  
DQ20  
DQ21  
DQ22  
DQ23  
Vcc  
94  
DQ52  
DQ53  
DQ54  
DQ55  
Vcc  
DQMB0  
DQMB1  
Vcc  
DQMB4  
DQMB5  
Vcc  
95  
96  
97  
98  
99  
100  
102  
104  
106  
108  
110  
112  
114  
116  
118  
120  
122  
124  
126  
128  
130  
132  
134  
136  
138  
140  
142  
144  
A0  
A3  
101  
103  
105  
107  
109  
111  
113  
115  
117  
119  
121  
123  
125  
127  
129  
131  
133  
135  
137  
139  
141  
143  
A1  
A4  
A6  
A7  
A2  
A5  
A8  
BA0  
Vss  
Vss  
Vss  
Vss  
DQ8  
DQ9  
DQ10  
DQ11  
Vcc  
DQ40  
DQ41  
DQ42  
DQ43  
Vcc  
A9  
BA1  
A10  
A11  
Vcc  
Vcc  
DQMB2  
DQMB3  
Vss  
DQMB6  
DQMB7  
Vss  
DQ12  
DQ13  
DQ14  
DQ15  
Vss  
DQ44  
DQ45  
DQ46  
DQ47  
Vss  
DQ24  
DQ25  
DQ26  
DQ27  
Vcc  
DQ56  
DQ57  
DQ58  
DQ59  
Vcc  
NC  
NC  
NC  
NC  
DQ28  
DQ29  
DQ30  
DQ31  
Vss  
DQ60  
DQ61  
DQ62  
DQ63  
Vss  
CLK0  
Vcc  
CKE0  
Vcc  
RAS  
WE  
CAS  
CKE1  
A12  
CS0  
CS1  
SDA  
SCL  
NC  
Vcc  
Vcc  
INFINEON Technologies  
3
HYS64V32220GD(L)-8A  
PC100 144 pin SO-DIMM SDRAM Modules  
WE  
CS0  
CS1  
CS WE  
LDQM  
CS WE  
LDQM  
CS WE  
LDQM  
CS WE  
LDQM  
DQMB0  
DQMB4  
DQ0-DQ7  
DQ0-DQ7  
DQ0-DQ7  
UDQM  
DQ32-DQ39  
DQ0-DQ7  
UDQM  
DQ0-DQ7  
DQMB1  
DQMB5  
UDQM  
UDQM  
DQ8-DQ15  
DQ40-DQ47  
DQ8-DQ15  
D0  
DQ8-DQ15  
D4  
DQ8-DQ15  
D2  
DQ8-DQ15  
D6  
CS WE  
LDQM  
CS WE  
LDQM  
CS WE  
LDQM  
CS WE  
LDQM  
DQMB2  
DQMB6  
DQ0-DQ7  
DQ0-DQ7  
DQ0-DQ7  
UDQM  
DQ0-DQ7  
UDQM  
DQ16-DQ23  
DQ48-DQ55  
UDQM  
UDQM  
DQMB3  
DQMB7  
DQ8-DQ15  
D1  
DQ8-DQ15  
D5  
DQ8-DQ15  
D3  
DQ8-DQ15  
D7  
DQ24-DQ31  
DQ56-DQ63  
E2PROM (256wordx8bit)  
A0-A12, BA0, BA1  
D0 - D7  
VCC  
VSS  
SA0  
SA1  
SA2  
D0 - D7  
D0 - D7  
C1-C4  
SCL  
SDA  
RAS  
CAS  
CKE0  
D0 - D7  
D0 - D7  
D0 - D7  
4 SDRAM  
4 SDRAM  
CLK0  
CLK1  
note: all resistors are 10 Ohms  
Block Diagram for two bank 32M x 64 SDRAM DIMM - Module  
INFINEON Technologies  
4
HYS64V32220GD(L)-8A  
PC100 144 pin SO-DIMM SDRAM Modules  
DC Characteristics  
TA = 0 to 70 °C; VSS = 0 V; VDD,VDDQ = 3.3 V ± 0.3 V  
Parameter  
Symbol  
Limit Values  
Unit  
min.  
max.  
Vcc+0.3  
0.8  
Input high voltage  
VIH  
VIL  
2.0  
– 0.5  
2.4  
V
Input low voltage  
V
Output high voltage (IOUT = – 4.0 mA)  
Output low voltage (IOUT = 4.0 mA)  
VOH  
VOL  
II(L)  
–
V
–
0.4  
V
Input leakage current, any input  
– 20  
20  
µA  
(0 V < VIN < 3.6 V, all other inputs = 0 V)  
Output leakage current  
IO(L)  
– 20  
20  
µA  
(DQ is disabled, 0 V < VOUT < VCC)  
Capacitance  
TA = 0 to 70 °C; VDD = 3.3 V ± 0.3 V, f = 1 MHz  
Parameter  
Symbol Limit Values Unit  
32M x 64  
max.  
Input capacitance (A0 to A11, BA0, BA1)  
Input capacitance (RAS, CAS, WE, CKE0)  
Input Capacitance (CLK0, CLK1)  
Input capacitance (CS0)  
CI1  
CI2  
CI3  
CI4  
CI5  
CIO  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
8
pF  
pF  
pF  
pF  
pF  
pF  
pF  
pF  
Input capacitance (DQMB0-DQMB7)  
Input / Output capacitance (DQ0-DQ63)  
Input Capacitance (SCL,SA0-2)  
Input/Output Capacitance  
C
sc  
sd  
C
10  
INFINEON Technologies  
5
HYS64V32220GD(L)-8A  
PC100 144 pin SO-DIMM SDRAM Modules  
o
Operating Currents per memory bank (T = 0 to 70 C, Vdd = 3.3V ± 0.3V  
A
(Recommended Operating Conditions unless otherwise noted)  
Symb.  
Note  
Parameter & Test Condition  
OPERATING CURRENT  
-8A  
trc=trcmin., tck=tckmin.  
ICC1  
TBD  
TBD  
mA  
mA  
mA  
1
1
Ouputs open, Burst Length = 4, CL=3  
All banks operated in random access,  
all banks operated in ping-pong manner  
to maximize gapless data access  
PRECHARGE STANDBY CURRENT in tck = min.  
Power Down Mode  
ICC2P  
mA  
tck = Infinity  
ICC2PS  
ICC2N  
TBD  
TBD  
mA  
mA  
1
1
CS =VIH (min.), CKE<=Vil(max)  
PRECHARGE STANDBY CURRENT in tck = min.  
Non-Power Down Mode  
tck = Infinity  
ICC2NS  
ICC3N  
ICC3P  
ICC4  
TBD  
TBD  
TBD  
TBD  
mA  
mA  
mA  
1
1
1
CS = VIH (min.), CKE>=Vih(min)  
NO OPERATING CURRENT  
CKE>=VIH(min.)  
CKE<=VIL(max.)  
tck = min., CS = VIH(min),  
active state ( max. 4 banks)  
BURST OPERATING CURRENT  
tck = min.,  
Read command cycling  
mA 1,2  
AUTO REFRESH CURRENT  
tck = min.,  
Auto Refresh command cycling  
ICC5  
ICC6  
1
TBD  
TBD  
mA  
SELF REFRESH CURRENT  
Self Refresh Mode, CKE=0.2V  
L-version  
mA  
1
Notes:  
1. These parameters depend on the cycle rate. These values are measured at 100 MHz for -8A modules.  
Input signals are changed once during tck, excepts for ICC6 and for standby currents when tck=infinity.  
2. These parameters are measured with continuous data stream during read access and all DQ toggling. CL=3  
and BL=4 is assumed and the VDDQ current is excluded.  
INFINEON Technologies  
6
HYS64V32220GD(L)-8A  
PC100 144 pin SO-DIMM SDRAM Modules  
AC Characteristics 1)2)  
TA = 0 to 70 °C; VSS = 0 V; VCC = 3.3 V ± 0.3 V, tT = 1 ns  
Symbol  
Unit  
Parameter  
Limit Values  
-8A  
PC100-322  
min.  
max.  
Clock and Access Time  
Clock Cycle Time  
CAS Latency = 3  
CAS Latency = 2  
10  
15  
–
–
ns  
ns  
tCK  
tCK  
tAC  
Clock Frequency  
CAS Latency = 3  
CAS Latency = 2  
–
–
100  
66  
MHz  
MHz  
Access Time from Clock  
CAS Latency = 3  
CAS Latency = 2  
2,  
3
–
–
6
6
ns  
ns  
Clock High Pulse Width  
tCH  
tCL  
tT  
3
3
–
–
ns  
ns  
ns  
Clock Low Pulse Width  
Transition time  
0.5  
10  
Setup and Hold Parameter  
Input Setup Time  
4
4
4
4
tIS  
2
1
1
1
2
–
–
–
–
–
ns  
Input Hold Time  
tIH  
ns  
Power Down Mode Entry Time  
Power Down Mode Exit Setup Time  
Mode Register Set-up time  
tSB  
tPDE  
tRSC  
CLK  
CLK  
CLK  
Common Parameters  
Row to Column Delay Time  
Row Precharge Time  
Row Active Time  
5
5
5
5
5
tRCD  
tRP  
tRAS  
tRC  
20  
20  
50  
70  
20  
ns  
ns  
ns  
ns  
ns  
100k  
Row Cycle Time  
–
Activate(a) to Activate(b) Command  
period  
tRRD  
CAS(a) to CAS(b) Command period  
tCCD  
1
–
CLK  
INFINEON Technologies  
7
HYS64V32220GD(L)-8A  
PC100 144 pin SO-DIMM SDRAM Modules  
Symbol  
Unit  
Parameter  
Limit Values  
-8A  
PC100-322  
min.  
max.  
Refresh Cycle  
Refresh Period (8192 cycles)  
Self Refresh Exit Time  
tREF  
–
1
64  
ms  
tSREX  
CLK  
Read Cycle  
Data Out Hold Time  
tOH  
tLZ  
3
0
3
–
–
–
8
2
ns  
2
Data Out to Low Impedance Time  
Data Out to High Impedance Time  
DQM Data Out Disable Latency  
ns  
tHZ  
ns  
tDQZ  
CLK  
Write Cycle  
Data Input to Precharge  
(write recovery)  
tWR  
2
0
–
–
CLK  
CLK  
DQM Write Mask Latency  
tDQW  
INFINEON Technologies  
8
HYS64V32220GD(L)-8A  
PC100 144 pin SO-DIMM SDRAM Modules  
Notes:  
1. An initial pause of 100µs is required after power-up, then a Precharge All Banks command must  
be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can  
begin.  
2. AC timing tests have V = 0.4 V and V = 2.4 V with the timing referenced to the 1.4 V crossover  
il  
ih  
point. The transition time is measured between V and V . All AC measurements assume t =1ns  
ih  
il  
T
with the AC output load circuit shownSpecified tac and toh parameters are measured with a 50  
pF only, without any resistive termination and with a input signal of 1V / ns edge rate between  
0.8V and 2.0 V.  
.
tCH  
2.4 V  
0.4 V  
CLOCK  
tT  
tCL  
tHOLD  
tSETUP  
INPUT  
1.4 V  
tAC  
tAC  
tLZ  
tOH  
I/O  
50 pF  
OUTPUT  
1.4 V  
tHZ  
Measurement conditions for  
tac and toh  
SPT03404  
3. If clock rising time is longer than 1ns, a time (t -0.5) ns has to be added to this parameter.  
T
4. If t is longer than 1ns, a time (t -1) ns has to be added to this parameter.  
T
T
5. Any time that the refresh Period has been exceeded, a minimum of two Auto (CRB) Refresh  
commands must be given to “wake-up“ the device.  
6. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after  
CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied  
once the Self Refresh Exit command is registered.  
7. Referenced to the time which the output achieves the open circuit condition, not to output voltage  
levels.  
INFINEON Technologies  
9
HYS64V32220GD(L)-8A  
PC100 144 pin SO-DIMM SDRAM Modules  
Serial Presence Detects:  
A serial presence detect storage device - E2PROM - is assembled onto the module. Information about the module  
configuration, speed, etc. is written into the E2PROM device during module production using a serial presence  
detect protocol ( I2C synchronous 2-wire bus)  
SPD-Table:  
Byte#  
Description  
SPD Entry  
Value  
Hex  
32Mx64  
-8A  
0
1
2
3
Number of SPD bytes  
Total bytes in Serial PD  
Memory Type  
128  
256  
80  
08  
04  
0D  
SDRAM  
Number of Row Addresses  
(without BS)  
4
5
Number of Column Addresses  
Number of DIMM Banks  
Module Data Width  
09  
02  
40  
00  
01  
A0  
60  
2
64  
6
7
Module Data Width (cont’d)  
Module Interface Levels  
SDRAM Cycle Time at CL=3  
0
8
LVTTL  
10.0 ns  
6.0 ns  
9
10  
SDRAM Access time from Clock at  
CL=3  
11  
12  
Dimm Config (Error Det/Corr.)  
Refresh Rate/Type  
none  
00  
82  
Self-Refresh,  
7.8µs  
13  
14  
15  
SDRAM width, Primary  
10  
00  
01  
Error Checking SDRAM data width  
n/a / x8  
Minimum clock delay for back-to-  
back random column address  
tccd = 1 CLK  
16  
17  
18  
19  
20  
Burst Length supported  
Number of SDRAM banks  
Supported CAS Latencies  
CS Latencies  
1, 2, 4 & 8  
2
0F  
04  
06  
01  
01  
2, & 3  
CS latency = 0  
WE Latencies  
Write latency=  
0
21  
22  
SDRAM DIMM module attributes  
SDRAM Device Attributes :General  
SDRAM Cycle Time at CL = 2  
non buffered/  
non reg.  
00  
0E  
Vcc tol +/-  
10%  
23  
24  
12.0 ns  
6.0 ns  
F0  
60  
SDRAM Access Time from Clock at  
CL=2  
25  
26  
SDRAM Cycle Time at CL = 1  
not supported  
not supported  
FF  
FF  
SDRAM Access Time from Clock at  
CL=1  
27  
Minimum Row Precharge Time  
20 ns  
14  
INFINEON Technologies  
10  
HYS64V32220GD(L)-8A  
PC100 144 pin SO-DIMM SDRAM Modules  
SPD-Table (cont’d):  
Byte#  
Description  
SPD Entry  
Value  
Hex  
32Mx64  
-8A  
28  
Minimum Row Active to Row Active  
delay  
20 ns  
14  
29  
30  
31  
32  
33  
34  
35  
Minimum RAS to CAS delay  
Minimum Ras pulse width  
Module Bank Density (per bank)  
SDRAM input setup time  
20 ns  
60 ns  
128MB  
2 ns  
14  
32  
20  
20  
10  
20  
10  
FF  
12  
D5  
FF  
SDRAM input hold time  
1 ns  
SDRAM data input setup time  
SDRAM data input hold time  
2 ns  
1 ns  
36-61 Superset information  
62  
63  
SPD Revision  
Revision 1.2  
Checksum for bytes 0 - 62  
64- Manufactures’s information (optional)  
125  
126 Frequency Specification  
127 Details  
PC100  
64  
C7  
FF  
128+ Unused storage locations  
INFINEON Technologies  
11  
HYS64V32220GD(L)-8A  
PC100 144 pin SO-DIMM SDRAM Modules  
64 MByte SO-DIMM Module package  
(144 pin, dual read-out, single in-line memory module)  
67,6  
63,6  
3.8  
1
59  
2.6  
4.6  
61  
143  
144  
1±  
0.1  
3.3  
23.2  
32.8  
±0.1  
1.5  
60  
1.8  
3.7  
2
62  
Detail of Contacts  
±0.05  
0.6  
0.8  
GLD09138  
INFINEON Technologies  
12  
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 		HYS6472V4200GU 3.3V 4M ×64 /72- 1位BANK SDRAM模块3.3V 8M ×64 /72- 2位BANK SDRAM模块[ 3.3V 4M x 64/72-Bit 1 BANK SDRAM Module 3.3V 8M x 64/72-Bit 2 BANK SDRAM Module ] 15 页

INFINEON

 		HYS64D128020GBDL-6-A [ DDR DRAM Module, 128MX64, 0.7ns, CMOS, SO-DIMM-200 ] 11 页

ETC

 		HYS64D128020GBDL-7-A ？ 1GB （ 1024Mx64 ） PC2100 2银行？\n[ ?1GB (1024Mx64) PC2100 2-bank? ] 11 页

INFINEON

 		HYS64D128020GU-7-A 2.5 V 184针无缓冲DDR- SDRAM我模块[ 2.5 V 184-pin Unbuffered DDR-I SDRAM Modules ] 18 页

INFINEON

 		HYS64D128020GU-8-A 2.5 V 184针无缓冲DDR- SDRAM我模块[ 2.5 V 184-pin Unbuffered DDR-I SDRAM Modules ] 18 页

QIMONDA

 		HYS64D128020GU-8-A [ DDR DRAM Module, 128MX64, 0.8ns, CMOS, PDMA184 ] 18 页

INFINEON

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