请登录

免费注册
全部商品
电子元器件
方案中心
工业品
PDF资料
购物车 0
上传BOM

产品分类

找货询价

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

QQ咨询

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

会员中心
购物车
技术支持

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

售后咨询

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

CYM1720PZ-25C

型号：

CYM1720PZ-25C

品牌：

CYPRESS[ CYPRESS ]

页数：

6 页

PDF大小：

104 K

下载PDF手册
1CYM1720  
CYM1720  
32K x 24 Static RAM Module  
constructed using three 32K x 8 static RAMs in SOJ packages  
mounted onto an epoxy laminate board with pins.  
Features  
• High-density 768-kilobit SRAM module  
• High-speed CMOS SRAMs  
— Access time of 15 ns  
Writing to the device is accomplished when the chip select  
(CS) and write enable (WE) inputs are both LOW. Data on  
the input/output pins (I/O through I/O ) of the device is  
0
23  
written into the memory location specified on the address  
pins (A through A ).  
• 56-pin, 0.5-inch-high ZIP package  
• Low active power  
0
14  
Reading the device is accomplished by taking the chip select  
(CS) and output enable (OE) LOW while write enable (WE)  
remains HIGH. Under these conditions, the contents of the  
memory location specified on the address pins will appear  
on the input/output pins.  
— 1.8W (max. for t = 25 ns)  
AA  
• SMD technology  
• TTL-compatible inputs and outputs  
• Commercial temperature range  
• Small PCB footprint  
The input/output pins remain in a high-impedance state unless  
the module is selected, outputs are enabled, and write enable  
is HIGH.  
— 0.66 sq. in.  
Functional Description  
The CYM1720 is a high-performance 768-kilobit static RAM  
module organized as 32K words by 24 bits. This module is  
Pin Configuration  
Logic Block Diagram  
ZIP  
Top View  
V
1
3
CC  
V
CC  
2
I/O  
I/O  
I/O  
I/O  
0
2
4
6
I/O  
I/O  
I/O  
I/O  
4
1
3
5
7
5
6
7
8
9
A − A  
10  
12  
14  
16  
18  
20  
22  
24  
26  
28  
30  
32  
34  
36  
38  
40  
42  
44  
46  
48  
50  
52  
54  
56  
0
14  
GND  
11  
13  
15  
17  
19  
21  
23  
25  
27  
29  
31  
15  
GND  
A
0
OE  
WE  
CS  
32K x 8  
SRAM  
A
1
I/O − I/O  
0
7
A
2
8
8
8
A
3
A
4
A
5
A
7
A
6
CS  
NC  
I/O  
I/O  
10  
NC  
GND  
I/O  
I/O  
11  
I/O  
I/O  
15  
NC  
OE  
8
9
32K x 8  
SRAM  
I/O − I/O  
I/O  
I/O  
14  
8
15  
12  
13  
GND  
WE  
33  
35  
37  
39  
41  
43  
45  
47  
49  
51  
53  
55  
A
8
A
9
A
10  
A
12  
A
14  
A
A
NC  
GND  
I/O  
I/O  
19  
I/O  
I/O  
23  
11  
13  
32K x 8  
SRAM  
I/O − I/O  
16  
23  
GND  
I/O  
I/O  
18  
I/O  
I/O  
V
CC  
16  
17  
1720–1  
20  
21  
22  
V
CC  
1720–2  
Selection Guide  
1720-15  
15  
1720-20  
20  
1720-25  
25  
1720-30  
1720-35  
35  
Maximum Access Time (ns)  
30  
330  
60  
Maximum Operating Current (mA)  
Maximum Standby Current (mA)  
450  
450  
330  
330  
120  
120  
60  
60  
Shaded area contains preliminary information.  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
September 1989 – Revised April 1993  
CYM1720  
DC Voltage Applied to Outputs  
in High Z State................................................–0.5V to +7.0V  
Maximum Ratings  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
DC Input Voltage ............................................–0.5V to +7.0V  
Storage Temperature ................................. –55°C to +125°C  
Operating Range  
Ambient Temperature with  
Power Applied............................................... –10°C to +85°C  
Ambient  
Temperature  
Range  
V
CC  
Supply Voltage to Ground Potential............... –0.5V to +7.0V  
Commercial  
0°C to +70°C  
5V ± 10%  
Electrical Characteristics Over the Operating Range  
CYM1720-15, 20 CYM1720-25, 30, 35  
Parameter  
Description  
Output HIGH Voltage  
Output LOW Voltage  
Input HIGH Voltage  
Input LOW Voltage  
Input Load Current  
Test Conditions  
= Min., I = – 4.0 mA  
Min.  
Max.  
Min.  
Max.  
Unit  
V
V
V
V
V
V
V
2.4  
2.4  
OH  
OL  
IH  
CC  
CC  
OH  
= Min., I = 8.0 mA  
0.4  
0.4  
V
OL  
2.2  
–0.5  
–20  
–10  
V
2.2  
–0.5  
–20  
–10  
V
V
CC  
CC  
0.8  
+20  
+10  
0.8  
+20  
+10  
V
IL  
I
I
GND < V < V  
CC  
µA  
µA  
IX  
I
Output Leakage Current GND < V < V ,  
CC  
OZ  
O
Output Disabled  
= Max., I = 0 mA,  
OUT  
I
I
I
V
Operating Supply  
V
450  
120  
90  
330  
60  
mA  
mA  
mA  
CC  
CC  
CC  
Current  
CS < V  
IL  
Automatic CS  
Power-Down Current  
Max. V , CS > V ,  
CC IH  
Min. Duty Cycle = 100%  
SB1  
SB2  
[1]  
[1]  
Automatic CS  
Power-Down Current  
Max. V , CS > V – 0.2V,  
60  
CC  
CC  
V
> V – 0.2V or V < 0.2V  
IN CC IN  
Shaded area contains preliminary information.  
Capacitance[2]  
Parameter  
Description  
Test Conditions  
T = 25°C, f = 1 MHz,  
Max.  
Unit  
pF  
C
C
Input Capacitance  
Output Capacitance  
35  
25  
IN  
A
V
= 5.0V  
CC  
pF  
OUT  
Notes:  
1. A pull-up resistor to VCC on the CS input is required to keep the device deselected during VCC power-up, otherwise ISB will exceed values given.  
2. Tested on a sample basis.  
AC Test Loads and Waveforms  
481Ω  
481Ω  
ALL INPUT PULSES  
90%  
5V  
5V  
3.0V  
GND  
90%  
10%  
OUTPUT  
OUTPUT  
10%  
255Ω  
255Ω  
30 pF  
5 pF  
< 5 ns  
< 5ns  
INCLUDING  
JIG AND  
SCOPE  
INCLUDING  
JIG AND  
SCOPE  
1720–3  
1720–4  
(a)  
(b)  
Equivalent to:  
OUTPUT  
THÉVENIN EQUIVALENT  
167Ω  
1.73V  
2
CYM1720  
[3]  
Switching Characteristics Over the Operating Range  
1720-15  
1720-20  
1720-25  
1720-30  
1720-35  
Parameter  
Description  
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit  
READ CYCLE  
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time  
15  
3
20  
3
25  
3
30  
3
35  
3
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
RC  
Address to Data Valid  
Data Hold from Address Change  
CS LOW to Data Valid  
OE LOW to Data Valid  
OE LOW to Low Z  
15  
20  
25  
30  
35  
AA  
OHA  
ACS  
DOE  
LZOE  
HZOE  
LZCS  
HZCS  
PU  
15  
8
20  
10  
25  
10  
30  
15  
35  
18  
0
3
0
0
3
0
0
3
0
0
5
0
0
3
0
OE HIGH to High Z  
6
6
8
8
10  
20  
25  
20  
20  
25  
20  
20  
30  
[4]  
CS LOW to Low Z  
[4, 5]  
CS HIGH to High Z  
CS LOW to Power-Up  
CS HIGH to Power-Down  
15  
20  
PD  
[6]  
WRITE CYCLE  
t
t
t
t
t
t
t
t
t
t
Write Cycle Time  
15  
10  
10  
1
20  
12  
12  
2
25  
20  
20  
2
30  
25  
25  
5
35  
30  
30  
5
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
WC  
CS LOW to Write End  
Address Set-Up to Write End  
Address Hold from Write End  
Address Set-Up to Write Start  
WE Pulse Width  
SCS  
AW  
HA  
1
2
5
5
5
SA  
10  
9
12  
10  
2
20  
12  
2
25  
18  
3
25  
18  
3
PWE  
SD  
Data Set-Up to Write End  
Data Hold from Write End  
WE HIGH to Low Z  
1
HD  
3
3
5
5
5
LZWE  
HZWE  
[5]  
WE LOW to High Z  
0
8
0
8
0
10  
0
15  
0
15  
Shaded area contains preliminary information.  
Notes:  
3. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified  
OL/IOH and 30-pF load capacitance.  
I
4. At any given temperature and voltage condition, tHZCS is less than tLZCS for any given device.  
5. tHZOE, tHZCS, and tLZCE are specified with CL = 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured ±500 mV from steady-state voltage.  
6. The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can  
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.  
3
CYM1720  
Switching Waveforms  
[7,8]  
Read  
No. 1  
Cycle  
t
RC  
ADDRESS  
DATA OUT  
t
AA  
t
OHA  
PREVIOUS DATA VALID  
DATA VALID  
1720–5  
[7,9]  
Read Cycle No. 2  
t
RC  
CS  
t
ACS  
OE  
t
HZOE  
t
DOE  
t
t
HZCS  
LZOE  
HIGH  
IMPEDANCE  
HIGH IMPEDANCE  
DATA VALID  
DATA OUT  
t
LZCS  
t
PD  
t
PU  
ICC  
V
CC  
50%  
50%  
SUPPLY  
CURRENT  
ISB  
1720–6  
[6,10]  
Write Cycle No. 1 (WE Controlled)  
t
WC  
ADDRESS  
CS  
t
SCS  
t
t
HA  
AW  
t
SA  
t
PWE  
WE  
t
t
HD  
SD  
DATA IN  
DATA VALID  
t
t
LZWE  
HZWE  
HIGH IMPEDANCE  
DATA UNDEFINED  
DATA I/O  
1720–7  
Notes:  
7. WE is HIGH for read cycle.  
8. Device is continuously selected, CS = VIL and OE= VIL  
9. Address valid prior to or coincident with CS transition LOW.  
10. Data I/O will be high impedance if OE = VIH  
.
.
4
CYM1720  
Switching Waveforms (continued)  
[6,10,11]  
Write Cycle No. 2 (CS Controlled)  
t
WC  
ADDRESS  
t
SA  
t
SCS  
CS  
WE  
t
t
HA  
AW  
t
PWE  
t
t
HD  
SD  
DATA IN  
DATA VALID  
t
HZWE  
HIGH IMPEDANCE  
DATA I/O  
DATA UNDEFINED  
1720–8  
Note:  
11. If CS goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.  
Truth Table  
CS WE OE Input/Outputs  
Mode  
Deselect/Power-Down  
Read Word  
H
L
L
L
X
H
L
X
L
High Z  
Data Out  
Data In  
High Z  
X
H
Write Word  
H
Deselect  
Ordering Information  
Package  
Name  
Package  
Operating  
Speed  
15  
Ordering Code  
Type  
Range  
CYM1720PZ-15C  
CYM1720PZ-20C  
CYM1720PZ-25C  
CYM1720PZ-30C  
CYM1720PZ-35C  
PZ05  
PZ05  
PZ05  
PZ05  
PZ05  
56-Pin ZIP Module  
56-Pin ZIP Module  
56-Pin ZIP Module  
56-Pin ZIP Module  
56-Pin ZIP Module  
Commercial  
Commercial  
Commercial  
Commercial  
Commercial  
20  
25  
30  
35  
Document #: 38-M-00021-A  
5
CYM1720  
Package Diagram  
56-Pin ZIP Module PZ05  
0.200  
MAX  
2.990  
3.010  
0.500  
MAX  
0.050  
TYP  
0.100  
TYP  
0.015  
0.025  
0.100  
TYP  
0.125  
0.150  
0.215  
MAX  
Bottom View  
Pin 1  
DIMENSIONS IN INCHES  
MIN.  
MAX.  
© Cypress Semiconductor Corporation, 1993. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of anycircuitry other than circuitry embodied in a CypressSemiconductor product. Nor does it conveyor imply any license under patent or other rights. CypressSemiconductor does not authorize  
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.  
厂商 型号 描述 页数 下载

MERRIMAC

 		CYM-13R-9G 定向耦合器[ DIRECTIONAL COUPLER ] 2 页

SUMIDA

 		CYM-2B 滤波线圈\u003c SMD型： CYM系列\u003e[ Filter Coils < SMD Type: CYM Series> ] 2 页

ETC

 		CYM1220HD-10C X4 SRAM模块\n[ x4 SRAM Module ] 5 页

ETC

 		CYM1220HD-12C X4 SRAM模块\n[ x4 SRAM Module ] 5 页

ETC

 		CYM1220HD-12MB X4 SRAM模块\n[ x4 SRAM Module ] 5 页

ETC

 		CYM1220HD-15C X4 SRAM模块\n[ x4 SRAM Module ] 5 页

ETC

 		CYM1220HD-15MB X4 SRAM模块\n[ x4 SRAM Module ] 5 页

ETC

 		CYM1220HD-20MB X4 SRAM模块\n[ x4 SRAM Module ] 5 页

CYPRESS

 		CYM1240HD-25C [ SRAM Module, 256KX4, 25ns, CMOS, CDIP28, HERMETIC SEALED, MODULE, DIP-28 ] 1 页

CYPRESS

 		CYM1240HD-25MB [ SRAM Module, 256KX4, 25ns, CMOS, CDIP28, HERMETIC SEALED, MODULE, DIP-28 ] 1 页

购物指南

支付方式

配送服务

售后服务

发票须知

优惠券使用规则

特色服务

PCBA制造

国产品牌推荐

国产料号替代

质量保证

技术资料

行业资讯

关于我们

关于达普

联系我们

联系我们

服务热线：400-618-9990

企业邮箱：smail@ic72.com

服务时间：周一至周六 8:30-17:30

达普官方微信号

PDF索引：

A

B

C

D

E

F

G

H

I

J

K

L

M

N

O

P

Q

R

S

T

U

V

W

X

Y

Z

0

1

2

3

4

5

6

7

8

9

IC型号索引：

A

B

C

D

E

F

G

H

I

J

K

L

M

N

O

P

Q

R

S

T

U

V

W

X

Y

Z

0

1

2

3

4

5

6

7

8

9

Copyright 2024 gkzhan.com Al Rights Reserved 京ICP备06008810号-21 京

深圳网络警察报警平台
公共信息安全网络监察
经营性网站备案信息
不良信息举报中心
工商网监电子标识
全国公安机关备案
0.203604s