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EZ-PD™ CCG3PA Datasheet

USB Type-C Port Controller

General Description

EZ-PD™ CCG3PA is Cypress’ highly integrated USB Type-C port controller that complies with the latest USB Type-C and PD

standards and is targeted for PC power adapters, mobile chargers, car chargers, and power bank applications. In such applications,

CCG3PA provides additional functionalities and BOM integration advantages. CCG3PA uses Cypress’ proprietary M0S8 technology

with a 32-bit Arm^®Cortex™-M0 processor, 64-KB flash, a complete Type-C USB-PD transceiver, all termination resistors required for

a Type-C port, an integrated feedback control circuitry for voltage (VBUS) regulation and system-level ESD protection. It is available

in 24-pin QFN and 16-pin SOIC packages.

32-bit MCU Subsystem

■ Arm Cortex-M0 CPU

Features

Type-C Support and USB-PD Support

■ Supports USB PD3.0 Version 1.1 Spec including Program-

mable Power Supply Mode

■ 64-KB Flash

■ 8-KB SRAM

Clocks and Oscillators

■ Configurable resistors R_Pand R_D

■ Integrated oscillator eliminating the need for external clock

■ Supports one USB Type-C port and one Type-A port

Power

2x Legacy/Proprietary Charging Blocks

■ Supports QC 4.0, Apple charging 2.4A, AFC, BC 1.2

■ Integrates all required terminations on DP/DM lines

■ 3.0-V to 24.5-V operation (30-V tolerant)

System-Level ESD Protection

■ On CC, VBUS_C_MON_DISCHARGE, DP0, DM0, P2.2, and

P2.3 pins

Integrated Voltage (VBUS) Regulation and Current

Sense Amplifier

■ ±8-kVContactDischargeand±15-kVAirGapDischargebased

■ Analog regulation of secondary side feedback node (direct

on IEC61000-4-2 level 4C

feedback or opto coupler)

Packages

■ 24-pin QFN and 16-pin SOIC

■ Integrated shunt regulator function for VBUS control

■ Constant current or constant voltage mode

■ Supports extended industrial temperature range

(–40 °C to +105 °C)

■ Supports low-side current sensing for constant current control

System-Level Fault Protection

■ VBUS to CC Short Protection

■ On-chip OVP, OCP, UVP, and SCP

■ Supports OTP through integrated ADC circuit

Cypress Semiconductor Corporation

Document Number: 002-16951 Rev. *F

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised March 2, 2018

EZ-PD™ CCG3PA Datasheet

Logic Block Diagram

CCG3PA: Single- Chip Type-C Controller

MCU Subsystem

I/O Subsystem

CC

Integrated Digital Blocks

ARM

CORTEX-M0

4x TCPWM

2x SCB

(I²C, SPI, UART)

GPIOs

Flash

(64 KB)

USB PD Subsystem

Baseband PHY

OCP and OVP

Protection

Low- side Current

Sense Amplifier

SRAM

(8 KB)

R_P, R_D

Voltage (VBUS)

Regulation

2x PFET Gate

Drivers

System

Resources

High Voltage

Regulator

2x VBUS Discharge

2x 8-bit SAR ADCs

2x Charger Detect

Internal Block Diagram

VBUS_P_CTRL

VBUS_C_CTRL

VBUS_C_MON_DISCHARGE

VBUS_IN_DISCHARGE

OV/UV,

R-Div

VDDD

VCCD

HV

Reg

DISCH

3.3 V

Prog

DISCH

1.8 V

LDO

CC1

BMC

PHY

CC2

MCU Subsystem

DP0 / GPIO

DM0 / GPIO

DP1 / GPIO

Charger

Detect0

Advanced High- Performance Bus

(AHB)

FB

Flash

SRAM

(8KB)

Cortex-M0

2x ADCs

(64KB)

Charger

Detect1

CATH/

COMP

DM1 / GPIO

2x SCB

(I2C, SPI, UART)

POR

AXRES / GPIO

LSCSA

4x TCPWM

GPIO

GND

CSP

Type-C

Connector

Ground

Rs

Document Number: 002-16951 Rev. *F

Page 2 of 37

EZ-PD™ CCG3PA Datasheet

Contents

Functional Overview ........................................................ 4

MCU Subsystem ......................................................... 4

USB-PD Subsystem (SS)............................................ 4

Integrated Digital Blocks.............................................. 5

I/O Subsystem............................................................. 5

Power Systems Overview................................................ 6

Pinouts .............................................................................. 7

CCG3PA Programming and Bootloading..................... 10

Programming the Device Flash over SWD Interface. 10

Application Diagrams..................................................... 12

Electrical Specifications ................................................ 17

Absolute Maximum Ratings .......................................17

Device-Level Specifications ...................................... 17

Digital Peripherals ..................................................... 21

System Resources .................................................... 23

Ordering Information...................................................... 29

Ordering Code Definitions......................................... 29

Package Diagrams.......................................................... 30

Acronyms........................................................................ 33

Document Conventions ................................................. 34

Units of Measure ....................................................... 34

Document History Page................................................. 35

Sales, Solutions, and Legal Information ...................... 37

Worldwide Sales and Design Support....................... 37

Products.................................................................... 37

PSoC® Solutions ...................................................... 37

Cypress Developer Community................................. 37

Technical Support ..................................................... 37

Document Number: 002-16951 Rev. *F

Page 3 of 37

EZ-PD™ CCG3PA Datasheet

sensing the GPIO pin voltage with an ADC, the pin voltage

cannot exceed the VDDIO supply value.

Functional Overview

MCU Subsystem

Charger Detection

CPU

The two charger detection blocks connected to the two pairs of

DP/DM pins allow CCG3PA to detect conventional battery

chargers conforming to BC 1.2, and the following proprietary

charger specifications: Apple, Qualcomm’s QuickCharge 4.0,

and Samsung AFC.

The Cortex-M0 CPU in EZ-PD CCG3PA is part of the 32-bit MCU

subsystem, which is optimized for low-power operation with

extensive clock gating.

The CPU also includes a serial wire debug (SWD) interface,

which is a 2-wire form of JTAG. The debug configuration used for

EZ-PD CCG3PA has four break-point (address) comparators

and two watchpoint (data) comparators.

VBUS Overcurrent and Overvoltage Protection

The CCG3PA chip has an integrated hardware block for VBUS

overvoltage protection (OVP)/overcurrent protection (OCP) with

configurable thresholds and response times on the Type C port.

Flash

The EZ-PD CCG3PA device has a flash module with one bank

of 64-KB flash, a flash accelerator, tightly coupled to the CPU to

improve average access times from the flash block.

VBUS Short Protection

CCG3PA provides four VBUS short protection pins: CC1, CC2,

P2.2, and P2.3. These pins are protected from accidental shorts

to high-voltage VBUS. Accidental shorts may occur because the

CC1 and CC2 pins are placed next to the VBUS pins in the USB

Type-C connector. A Power Delivery controller without the

high-voltage VBUS short protection will be damaged in the event

of accidental shorts. When the protection circuit is triggered,

CCG3PA can handle up to 17 V forever and between 17 V to

22 VDC for 1000 hours on the OVT pins. When a VBUS short

event occurs on the CC pins, a temporary high-ringing voltage is

observed due to the RLC elements in the USB Type-C cable.

Without CCG3PA connected, this ringing voltage can be twice

(44 V) the maximum VBUS voltage (21.5 V). However, when

CCG3PA is connected, it is capable of clamping temporary

high-ringing voltage and protecting the CC pin using IEC ESD

protection diodes.

SROM

Asupervisory ROM that contains boot and configuration routines

is provided.

USB-PD Subsystem (SS)

The USB-PD subsystem provides the interface to the Type-C

USB port. This subsystem comprises a current sense amplifier,

a high-voltage regulator, OVP, OCP, and supply switch blocks.

This subsystem also includes all ESD required and supported on

the Type-C port.

USB-PD Physical Layer

The USB-PD Physical Layer consists of a transmitter and

receiver that communicate BMC-encoded data over the CC

channel based on the PD 3.0 standard. All communication is

half-duplex. The Physical Layer or PHY practices collision

avoidance to minimize communication errors on the channel.

Low-side Current Sense Amplifier (CSA)

The CCG3PA chip also has an integrated low-side current sense

amplifier that is capable of detecting current in the order of

100 mA across a 5 mΩ external resistor. It also supports

constant current mode of operation in power adapter application

as a provider.

The USB-PD block includes all termination resistors (R_Pand R_D)

and their switches as required by the USB-PD spec. R_Pand R_D

resistors are required to implement connection detection, plug

orientation detection, and for establishing USB DFP/UFP roles.

The R_Presistor is implemented as a current source.

PFET Gate Drivers on VBUS Path

According to the USB Type-C spec, a Type-C controller such as

CCG3PA must present certain termination resistors depending

on its role in its unpowered state. The Sink role in a power bank

application requires R_Dresistors to be present on the CC pins

whereas the DFP role, as in a power adapter, requires both CC

lines to be open. To be flexible for such applications, CCG3PA

includes the resistors required in the unpowered state on

separate pads or pins. The dead battery R_Dresistors are

available on separate pads. The dead battery R_Dis implemented

as a bond option on parts for Power Bank applications. In these

parts, each CC pin is bonded out together with its corresponding

dead battery R_Dresistor. On part numbers for the DFP appli-

cation, the CC pins are not bonded with the dead battery R_D.

CCG3PA has two integrated PFET gate drivers to drive external

PFETs on the VBUS provider and consumer path. The

VBUS_P_CTRL gate driver has an active pull-up, and thus can

drive high, low or High-Z.

The VBUS_C_CTRL gate driver can drive only low or high-Z,

thus requiring an external pull-up. These pins are VBUS

voltage-tolerant.

VBUS Discharge FETs

CCG3PA also has two integrated VBUS discharge FETs used to

discharge VBUS to meet the USB-PD specification timing on a

detach condition. VBUS Discharge FET on the provider side can

be used to accelerate the ramp down of VBUS to default 5V on

the secondary side.

ADC

The ADC is a low-footprint 8-bit SAR ADC that is available for

general-purpose A-D conversion applications in the chip. This

ADC can be accessed from all GPIOs and the DP/DM pins

through an on-chip analog mux. CCG3PAcontains two instances

of the ADC. The voltage reference for the ADCs is generated

either from the VDDD supply or from internal bandgap. When

Voltage (VBUS) Regulation

CCG3PA contains an integrated feedback control circuitry (for

AC/DC applications) for secondary side control with analog

regulation of the feedback/cathode pins to achieve the appro-

Document Number: 002-16951 Rev. *F

Page 4 of 37

EZ-PD™ CCG3PA Datasheet

priate voltage on VBUS pin as per the negotiated contract with

the peer device over Type-C.

find the number of times a particular event occurs (counter),

generate PWM signals, or decode quadrature signals.

I/O Subsystem

Integrated Digital Blocks

EZ-PD CCG3PA has up to 12 GPIOs of which, some of them can

be re-purposed to support functions of SCB (I²C, UART, SPI).

GPIO pins P0.0 and P0.1 are overvoltage-tolerant (OVT) (upto

7V).

Serial Communication Blocks (SCB)

EZ-PD CCG3PA has two SCBs, which can be configured to

implement an I²C, SPI, or UART interface. The hardware I²C

blocks implement full multi-master and slave interfaces capable

of multimaster arbitration. In the SPI mode, the SCB blocks can

be configured to act as master or slave.

In the I²C mode, the SCB blocks are capable of operating at

speeds of up to 1 Mbps (Fast Mode Plus) and have flexible

buffering options to reduce interrupt overhead and latency for the

CPU. These blocks also support I²C that creates a mailbox

address range in the memory of EZ-PD CCG3PA and effectively

reduce I²C communication to reading from and writing to an

array in memory. In addition, the blocks support 8-deep FIFOs

for receive and transmit which, by increasing the time given for

the CPU to read data, greatly reduce the need for clock

stretching caused by the CPU not having read data on time.

The GPIO block implements the following:

■ Seven drive strength modes:

❐ Input only

❐ Weak pull-up with strong pull-down

❐ Strong pull-up with weak pull-down

❐ Open drain with strong pull-down

❐ Open drain with strong pull-up

❐ Strong pull-up with strong pull-down

❐ Weak pull-up with weak pull-down

■ Input threshold select (CMOS or LVTTL)

■ Individual control of input and output buffer enabling/disabling

The I²C peripherals are compatible with the I²C Standard-mode,

Fast-mode, and Fast-mode Plus devices as defined in the NXP

I²C-bus specification and user manual (UM10204). The I²C bus

I/Os are implemented with GPIO in open-drain modes.

in addition to the drive strength modes

■ Hold mode for latching previous state (used for retaining I/O

state in Deep Sleep mode)

■ Selectable slew rates for dV/dt related noise control to improve

EMI

The I²C port on the SCB blocks of EZ-PD CCG3PA are not

completely compliant with the I²C spec in the following aspects:

During power-on and reset, the I/O pins are forced to the disable

state so as not to crowbar any inputs and/or cause excess

turn-on current. A multiplexing network known as a high-speed

I/O matrix is used to multiplex between various signals that may

connect to an I/O pin.

■ The GPIO cells for SCB 1’s I²Cportarenotovervoltage-tolerant

and, therefore, cannot be hot-swapped or powered up

independently of the rest of the I²C system.

■ Fast-mode Plus has an I_OLspecification of 20 mA at a V_OLof

0.4 V. The GPIO cells can sink a maximum of 8-mA I_OLwith a

Port pins P1.0 and P1.1 can be configured to indicate Fault for

OCP/SCP/OVP/UVP conditions. Any two fault conditions can be

mapped to two GPIOs or all the four faults can be OR’ed to

indicate over one GPIO.

V_OLmaximum of 0.6 V.

■ Fast-mode and Fast-mode Plus specify minimum Fall times,

which are not met with the GPIO cell; Slow strong mode can

help meet this spec depending on the bus load.

Timer/Counter/PWM Block (TCPWM)

EZ-PD CCG3PA has four TCPWM blocks. Each implements a

16-bit timer, counter, pulse-width modulator (PWM), and

quadrature decoder functionality. The block can be used to

measure the period and pulse width of an input signal (timer),

Document Number: 002-16951 Rev. *F

Page 5 of 37

EZ-PD™ CCG3PA Datasheet

Power Systems Overview

CCG3PAcan operate from two possible external supply sources:

VBUS_IN_DISCHARGE (3.0 V–24.5 V) or VDDD (2.7 V–5.5 V).

When powered through VBUS_IN_DISCHARGE, the internal

regulator generates VDDD of 3.3 V for chip operation. The

regulated supply, VDDD, is either used directly inside some

analog blocks or further regulated down to VCCD (1.8 V), which

powers majority of the core using the regulators. CCG3PA has

three different power modes: Active, Sleep, and Deep Sleep.

Transitions between these power modes are managed by the

power

system.

When

powered

through

the

VBUS_IN_DISCHARGE pin, VDDD cannot be used to power

external devices and should be connected to a 1-µF capacitor for

the regulator stability only. These pins are not supported as

power supplies. Refer to the application diagrams for capacitor

connections.

Table 1. CCG3PA Power Modes

Mode

Description

Power is valid and an internal reset source is asserted or SleepController is sequencing the system

out of reset.

Power-On Reset (POR)

ACTIVE

Power is valid and CPU is executing instructions.

Power is valid and CPU is not executing instructions. All logic that is not operating is clock gated to

save power.

SLEEP

Main regulator and most blocks are shut off. DeepSleep regulator powers logic, but only

low-frequency clock is available.

DEEP SLEEP

Figure 1. Power System Requirement Block Diagram

SHV

Regulator

VBUS_IN_DISCHARGE

VBUS_C_MON

UV/

_DISCHARGE

OVP

Gate Driver

VBUS_P_CTRL

VBUS_C_CTRL

Gate Driver

VDDD

1uF

1.8-V

Regulator

VCCD

1uF

CC

Tx/Rx

Core

CC1, CC2

VSS

GPIO

VSS

CCG3PA

Document Number: 002-16951 Rev. *F

Page 6 of 37

EZ-PD™ CCG3PA Datasheet

Pinouts

Table 2. CCG3PA Pin Descriptions

24-Pin

QFN

16-Pin

SOIC

Pin Name

Description

Port 1 pin 0: GPIO/UART_1_CTS/I2C_SDA_1^[1]/ TCPWM_line_0^[2], Programmable

1

2

–

P1.0

SCP/OCP/OVP/UVP Fault indication

Port 1 pin 1: GPIO/UART_1_RTS/I2C_SCL_1^[1]/ TCPWM_line_1^[3], Programmable

SCP/OCP/OVP/UVP Fault indication

P1.1

Provider (PMOS) FET control (30-V Tolerant)

3

4

5

–

VBUS_P_CTRL

VBUS_C_CTRL

0: Path ON

1: Path OFF

VBUS Consumer (PMOS) FET Control (30-V Tolerant)

0: Path ON

Z: Path OFF

5

6

–

6

7

8

–

9

DP1/P1.2

DM1/P1.3

USB D+/Port 1 pin 2: GPIO/UART_1_TX1/AFC/QC/BC 1.2/Apple Charging/No IEC

USB D-/Port 1 pin 3: GPIO/UART_1_RX1/AFC/QC/BC 1.2/Apple Charging/No IEC

Port 0 pin 0: GPIO/OVT/I2C_SDA_0/TCPWM_line_0/UART_0_CTS

Port 0 pin 1: GPIO/OVT/I2C_SCL_0/TCPWM_line_1/UART_0_RTS

Port 2 pin 0: GPIO/Alternate XRES^[4]/TCPWM_line_0//UART_0_TX0

Port 2 pin 1: GPIO/TCPWM_line_1//UART_0_RX0

7

SWD_DAT_0/P0.0

SWD_CLK_0/P0.1

AXRES/P2.0

P2.1

8

9

10

11

VBUS_C_MON_DIS-

CHARGE

Type C VBUS Monitor with Internal Discharge FET

Port 2 pin 2: GPIO with Open drain with pull-up assist. Configurable as GPIO_20VT/I2C_SDA_1/IEC.

Tolerant to temporary short to VBUS pin..

12

13

14

–

P2.2

P2.3

CC2

Port 2 pin 3: GPIO with Open drain with pull-up assist. Configurable as GPIO_20VT/I2C_SCL_1/IEC.

Tolerant to temporary short to VBUS pin.

Communication Channel 2 with Dead-battery Rd Bonding Option/IEC. Tolerant to temporary short to

VBUS pin.

10

Communication Channel 1 with Dead-battery Rd Bonding Option/IEC. Tolerant to temporary short to

VBUS pin.

15

16

17

18

19

20

21

22

23

24

11

12

13

14

16

1

CC1

DM0/P3.1

DP0/P3.0

USB D-/Port 3 pin 1: GPIO/UART_1_RX0/AFC/QC/BC 1.2/Apple Charging/IEC

USB D+/Port 3 pin 0: GPIO/UART_1_TX0/AFC/QC/BC 1.2/Apple Charging/IEC

VBUS Power IN (3.0 V–24.5 V) with Internal Discharge FET

CS +: Current sense input

VBUS_IN_DIS

CHARGE

CSP

FB

Voltage regulation feedback pin

2

CATH/COMP

GND

Cathode of voltage regulation and compensation for other applications

Ground

15

3

VDDD

VCCD

EPAD

Power Input: 2.7 V–5.5 V

4

1.8-V Core Voltage pin (not intended for use as a power source)

Ground

–

Note

1. Out of the two SCB blocks (SCB0 and SCB1), while the SCB0’s I2C functionality is mapped out to the P0.0/P0.1 GPIO pins, the I2C functionality

of SCB1 provides flexibility to have it mapped either on P1.0/P1.1 OR P2.2/P2.3 GPIO pins.

2. TCPWM_line_0 can be mapped to port pins P1.0, P0.0, P2.0 or P2.2.

3. TCPWM_line_1 can be mapped to port pins P1.1, P0.1, P2.1 or P2.3.

4. AXRES pin will be internally pulled up during the Power On I/O initialization time (see Table 6 for more details).

5. See Table 9 and Table 10 for specifications related to these pins.

Document Number: 002-16951 Rev. *F

Page 7 of 37

EZ-PD™ CCG3PA Datasheet

Table 3. GPIO Ports, Pins and Their Functionality

Protection

Port 24-QFN 16-SOIC

SCB Function

SPI

USB Charging Signal

AFC QC BC1.2 Apple

IEC4

Capability

Fault

TCPWM

Indicator

VBUS

Pin#

UART

I2C

OVT

Yes



Short

SPI_1_MO I2C_0_ TCPWM_line

P0.0

P0.1

P1.0

P1.1

7

8

1

2

6

7

UART_0_CTS

UART_0_RTS

–

SI

SDA

_0:0

SPI_1_MIS I2C_0_ TCPWM_line

–

O

SCL _1:0

I2C_1_ TCPWM_line

SDA:1 _2:1

UART_1_CTS SPI_0_SEL

Yes

SPI_0_MIS I2C_1_ TCPWM_line

UART_1_RTS

UART_1_TX1



O

SCL:1

_3:1

SPI_0_MO

SI

P1.2

P1.3

P2.0

5

6

9

–

D+

D-

–

D+

D-

–

D+

D-

–

D+

D-

–

UART_1_RX1 SPI_0_CLK

UART_0_TX0 SPI_1_SEL

–

TCPWM_line

_2:0

8

TCPWM_line

_3:0

P2.1

P2.2

P2.3

10

12

13

UART_0_RX0 SPI_1_CLK

–

I2C_1_ TCPWM_line

SDA:0 _0:1

UART_0_TX1

UART_0_RX1

–

Yes

I2C_1_ TCPWM_line

SCL:0

_1:1

P3.0

P3.1

17

16

13

12

UART_1_TX0

UART_1_RX0

–

D+

D-

D+

D-

D+

D-

D+

D-

Yes

–

Document Number: 002-16951 Rev. *F

Page 8 of 37

EZ-PD™ CCG3PA Datasheet

Figure 2. Pinout of 24-QFN Package (Top View)

GPIO

VBUS_IN_DISCHARGE

DP0/GPIO

DM0/GPIO

CC1

1

2

3

4

5

6

18

17

16

15

14

13

VBUS_P_CTRL

VBUS_C_CTRL

DP1/GPIO

EPAD

CC2

DM1/GPIO

GPIO_20VT

Figure 3. Pinout of 16-SOIC Package (Top View)

FB

CATH/COMP

VDDD

CSP

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

GND

VBUS_IN_DISCHARGE

SOIC

VCCD

DP0/ GPIO

(Top View)

DM0/ GPIO

VBUS_P_CTRL

CC1

SWD_DAT_0/GPIO

SWD_CLK_0/GPIO

AXRES/GPIO

CC2

VBUS_C_MON_ DISCHARGE

Document Number: 002-16951 Rev. *F

Page 9 of 37

EZ-PD™ CCG3PA Datasheet

MiniProg3 programmer. There are many third party

programmers that support mass programming in a manufac-

turing environment.

CCG3PA Programming and Bootloading

There are two ways to program application firmware into a

CCG3PA device:

As shown in the block diagram in Figure 4, the SWD_0_DAT and

SWD_0_CLK pins are connected to the host programmer’s

SWDIO (data) and SWDCLK (clock) pins respectively. During

SWD programming, the CCG3PA device has to be powered by

the host programmer by connecting its VTARG (power supply to

the target device) to VDDD pin of CCG3PA device. While

programming over SWD interface, the CCG3PA device cannot

receive power through VBUS_IN_DISCHARGE.

1. Programming the device flash over SWD Interface

2. Application firmware update over CC interface

Generally, the CCG3PA devices are programmed over SWD

interface only during development or during the manufacturing

process of the end product. Once the end product is

manufactured, the CCG3PA device’s application firmware can

be updated via the CC bootloader interface.

The CCG3PA device family does not have the XRES pin. Due to

that, the XRES line from the host programmer remains uncon-

nected, and hence programming using Reset Mode is not

supported. In other words, CCG3PA devices are supported by

Power Cycle programming mode only since XRES line is not

used. Contact Cypress for further details on CYPD3XXX

Programming Specifications.

Programming the Device Flash over SWD Interface

CCG3PA family of devices can be programmed using the SWD

interface. Cypress provides a programming kit (CY8CKIT-002

MiniProg3 Kit) called MiniProg3 and PSoC Programmer

Software which can be used to program the flash as well as

debug firmware. The flash is programmed by downloading the

information from a hex file. This hex file is a binary file generated

as an output of building the firmware project in PSoC Creator

Software. Click here for more information on how to use the

Figure 4. Connecting the Programmer to CYPD317x Device

Programming

Hardware

Target Device from CCG3PA Family

(Only Power Cycle Programming Mode Supported)

V_TARG

V_DDD

1F

10V

X7R

100nF

10V

X7R

SWDCLK

SWDIO

XRES

SWD_0_CLK

SWD_0_DAT

AXRES

V_CCD

1F

10V

X7R

X

While programming over

SWD interface, device cannot

receive power through

GND

V_SS

GND

VBUS_IN_DISHCARGE.

Document Number: 002-16951 Rev. *F

Page 10 of 37

EZ-PD™ CCG3PA Datasheet

Application Firmware Update over CC Interface

For bootloading CCG3PA applications, the CY4532 CCG3PA EVK can be used to send programming and configuration data as

Cypress specific Vendor Defined Messages (VDMs) over the CC line. The CY4532 CCG3PA EVK’s Power Board is connected to the

^{system containing CCG3PA device on one end and a Windows PC running the EZ-PD} Configuration Utility as shown in Figure 5

on the other end to bootload the CCG3PA device.

Figure 5. Application Firmware Update over CC Interface

USB Serial Device of

CY4532 EVK Power

Board

I²C

PC Running

EZ-PD Configuration

Utility

CC Line

USB Mini-B cable

CYPD317x Device to

be Bootloaded

CCG4 Device on

CY4532 EVK Power

Board

Type-C Receptacle

CY4532 CCG3PA EVK’s

Power Board

Mini-B Receptacle

Document Number: 002-16951 Rev. *F

Page 11 of 37

EZ-PD™ CCG3PA Datasheet

Application Diagrams

Figure 6 and Figure 7 show the application diagrams of CCG3PA-based Power Adapter with Opto-Coupler Feedback control using

16-pin SOIC and 24-pin QFN parts respectively. In an opto-feedback power adapter, CCG3PA implements a shunt regulator and the

feedback to the primary controller is through an opto-coupler. The current drawn through the CATH path is proportional to the potential

difference between FB pin and the internal bandgap reference voltage. At default 5-V VBUS, the FB pin will be held at the voltage set

by the bandgap reference voltage using internal VBUS resistor dividers.

If VBUS needs to be changed from default 5 V, using internal IDACs and an error amplifier, CCG3PA draws a proportional current

through the CATH pin. This in turn gets coupled to the primary controller through the opto-coupler.

Figure 6. CCG3PA Based Power Adapter Application Diagram with Opto Coupler Feedback Control (16-pin SOIC Device)

PFET Load Switch

VBUS

50 k

14

5

VBUS_IN_DIS

CHARGE

VBUS_P_CTRL

9

VBUS

VBUS_C_MON_

DISCHARGE

3

4

VDDD

VCCD

1 µF

100 nF

11

10

CC1

CC2

CC1

CC2

1 µF

390 pF

5%

390 pF

5%

CYPD3174-16SXQ

X7R

Type-C

Receptacle

DP0

1

2

R1

C1

FB

13

12

DP0

DM0

C2

8

CATH/

COMP

AXRES/GPIO

SWD_

CLK_0

SWD_

DAT_0

100 nF

CSP

16

GND

15

6

7

Note:

R1, C1, and C2 values are selected

based on primary side controller's design.

5 m

GND

To Programming Header (Not needed for final production)

Document Number: 002-16951 Rev. *F

Page 12 of 37

EZ-PD™ CCG3PA Datasheet

Figure 7. CCG3PA Based Power Adapter Application Diagram with Opto Coupler Feedback Control (24-pin QFN Device)

PFET Load Switch

VBUS

50 k

18

3

4

VBUS_IN_DIS

CHARGE

VBUS_P_CTRL VBUS_C_CTRL

GPIO

VBUS

1, 2, 5,

6, 10

23

24

VDDD

VCCD

11

VBUS_C_MON_

DISCHARGE

1 F

100 nF

15

14

CC1

CC2

CC1

CC2

1 F

390 pF

5%

X7R

390 pF

5%

X7R

CYPD3174-24LQXQ

12, 13

GPIO_20VT

Type-C

Receptacle

DP0

17

20

21

R1

C1

DP0

DM0

FB

16

9

DM0

C2

CATH/

COMP

AXRES/GPIO

SWD_

100 nF

CLK_0

CSP

19

DAT_0

GND

22

7

8

Note:

R1, C1 and, C2 values are selected based on

primary side controller's design.

5 m

GND

To Programming Header (Not needed for final production)

Document Number: 002-16951 Rev. *F

Page 13 of 37

EZ-PD™ CCG3PA Datasheet

Figure 8 shows the application diagram of CCG3PA based power adapter with Direct Feedback control. In this application, VBUS is

maintained at a constant voltage. The default value of VBUS upon power up (which is usually at 5 V) is set up by choosing the

appropriate resistor divider that will set the FB node at a voltage expected by the secondary controller.

Feedback node is regulated using internal IDACs. Whenever a change in VBUS voltage is needed, CCG3PA will either source or sink

a proportional current at feedback node, based on the amount of voltage change needed.

Figure 8. CCG3PA Based Power Adapter Application Diagram with Direct Feedback Control

PFET Load Switch

VBUS

50 k

18

3

VBUS_IN_DIS

CHARGE

VBUS_P_CTRL

11

4

VBUS

VBUS_C_MON_

DISCHARGE

23

24

VDDD

VCCD

VBUS_C_CTRL

1 F

100 nF

R1

15

14

CC1

CC2

CC1

CC2

1 F

21

CATH/

COMP

390 pF

5%

X7R

390 pF

5%

X7R

100 nF

CYPD3175-24LQXQ

SR

Type-C

Receptacle

9

Secondary

Or

Integrated

Controller

20

FB

AXRES/GPIO

FB

17

16

1, 2, 5, 6,

10, 12, 13,

DP0

DM0

DP0

DM0

GPIO

SWD_

CLK_0

SWD_

DAT_0

R2

CSP

19

GND

22

Select R1, R2 to get

the expected FB

7

8

5 m

voltage at 5V VBUS

GND

To Programming Header (Not needed for final production)

Document Number: 002-16951 Rev. *F

Page 14 of 37

EZ-PD™ CCG3PA Datasheet

Figure 9 shows the application diagram of a CCG3PA based power adapter application with direct feedback control for two port car

charger. The car charger application can charge portable devices connected to the Type-C and Type-A port simultaneously. The

Type-C port supports USBPD 3.0 QC 4.0, Apple Charging 2.4A, and AFC. The Type-Aport supports QC 3.0, Apple Charging and AFC.

Figure 9. CCG3PA Based Power Adapter Application with Direct Feedback Control for Two Port Car Charger

DC/DC Regulator 1

VBAT

Provider

FET

4

VBUS_C_CTRL

1

3

P1.0

VBUS_P_CTRL

9

18

P2.0/AXRES

FB

VBUS_IN_DISCHARGE

VBUS_C_MON_DIS

VBUS

11

15

20

CC1

CC2

CC1

CC2

14

2

P1.1

390 pF

5%

X7R

21

390 pF

5%

X7R

12 V

Supply

COMP

CYPD3175-24LQXQ

10

Type-C

P2.1

23

Receptacle

3.3 V/5 V

Regulator

2.7 V to 5.5 V

VDDD

17

16

DP0/P3.0

DM0/P3.1

DPLUS

0.1 F

13

7

DMINUS

P2.3

5

6

P0.0/SWD_DAT_0

DP1/P1.2

DM1/P1.3

8

GND

P0.1/SWD_CLK_0

P2.2

12

VCCD

24

GND

22

CSP

19

1 F

10 V

X7R

10 m 1%

EN

VSEL

VBAT

DC/DC Regulator 2

VBUS

DPLUS

DMINUS

Pins 7 and 8 can also be

connected to the programming

header (not needed for final

production)

Type-A

Receptacle

GND

Document Number: 002-16951 Rev. *F

Page 15 of 37

EZ-PD™ CCG3PA Datasheet

Figure 10 shows the application diagram of a CCG3PA based power bank application. It shows dual port power bank implementation

using CCG3PA device. The power bank application can charge portable devices connected to the Type-C and Type-A port

simultaneously. The Type-C port can be configured to support USBPD 3.0 QC 4.0, Apple Charging 2.4A, and AFC. The Type-A port

can be configured to support QC3.0, Apple Charging, and AFC.

The battery can be charged from Type-C and USBPD power adapters or BC1.2 power adapters.

Figure 10. CCG3PA Power Bank Application Diagram

Battery

Charger

Consumer

FET

EN

ILIM

Provider

FET

Reg

EN

FB

R1

Select R1, R2 to get 5 V VBUS

R2

3

4

20

2

VBUS_P_CTRL

FB

P1.1

VBUS_C_CTRL

9

1

18

11

P2.0/AXRES

P1.0

VBUS_IN_DISCHARGE

VBUS_C_MON_DIS

VBUS

15

14

CC1

CC2

CC1

CC2

23

10

5 V

Regulator

2.7 V to 5.5 V

VDDD

P2.1

0.1 F

390 pF

5%

X7R

390 pF

5%

X7R

Battery

1S/2S

13

VBATT

P2.3

499 k

1%

Type-C

49.9 k

1%

CYPD3171-24LQXQ

Receptacle

17

16

21

COMP

DP0/P3.0

DM0/P3.1

DPLUS

DMINUS

7

5

6

P0.0/SWD_DAT_0

P2.2

DP1/P1.2

DM1/P1.3

12

GND

P0.1/

SWD_CLK_0

VCCD

24

GND

22

CSP

19

8

1 F

10 V

X7R

PWM/

GPIO

5 m 1%

FB

EN

Reg

VBUS

DPLUS

FET

DMINUS

Type-A

Pins 7 and 8 can also be

Receptacle

connected to the programming

header (not needed for final

production)

GND

Type-A

Connect

Detect

Rsense

Document Number: 002-16951 Rev. *F

Page 16 of 37

EZ-PD™ CCG3PA Datasheet

Electrical Specifications

Absolute Maximum Ratings

Table 4. Absolute Maximum Ratings

Parameter

Description

Min

Typ

Max

Units

Details/Conditions

Max supply voltage relative to V_SSon

VBUS_IN_DISCHARGE and

VBUS_C_MON_DISCHARGE pins

V_{BUS_MAX}

–

30

6

V

V_{DDD_MAX}

Max supply voltage relative to V_SS

Max voltage on CC1, CC2 pins and port

pins P2.2 and P2.3 for applicable

devices

Absolute max

V_{CC_PIN_ABS}

22^[6]

V_{GPIO_ABS}

I_{GPIO_ABS}

GPIO voltage

–0.5

–25

–

V_DDD+0.5

25

V

Maximum current per GPIO

mA

GPIO injection current, Max for V_IH

_DDD, and Min for V_IL< V_SS

>

Absolute max, current

injected per pin

I_{GPIO_injection}

–0.5

2200

–

0.5

6

mA

V

Applicable to port pins P0.0

and P0.1

V_{GPIO_OVT_ABS}OVT GPIO voltage

Electrostatic discharge human body

model

ESD_HBM

–

V

–

Electrostatic discharge charged device

model

ESD_CDM

LU

500

–

V

–

Pin current for latch-up

–100

100

mA

Contact discharge on CC1,

CC2, VBUS, P2.2 and P2.3

pins

ESD_IEC_CON Electrostatic discharge IEC61000-4-2

ESD_IEC_AIR Electrostatic discharge IEC61000-4-2

8000

–

V

Air discharge for DPLUS,

DMINUS, CC1, CC2, VBUS,

P2.2 and P2.3 pins

15000

Device-Level Specifications

All specifications are valid for –40 °C  T_A 105 °C and T_J 120 °C, except where noted.

Table 5. DC Specifications

Spec ID

Parameter

V_DDD

Description

Min

2.7

3.0

–

Typ Max Units

Details/Conditions

SID.PWR#2

Power Supply Input Voltage

Output Voltage for core Logic

–

5.5

24.5

–

V

Sink mode, –40 °C  T_A 105 °C.

Source mode, –40 °C  T_A 105 °C.

–40 °C  T_A 105 °C.

–

SID.PWR#2_A V_DDD

SID.PWR#3

SID.PWR#5

V_{BUS_IN}

V_CCD

–

1.8

Power supply decoupling

capacitor for V_DDD

SID.PWR#13

C_exc

0.8

1

–

µF X5R ceramic or better

Power supply decoupling

capacitor for VBUS_IN_DISH-

CARGE

SID.PWR#14

C_exv

–

0.1

–

Note

6. As per USB PD specification, maximum allowed VBUS = 21.5V.

Document Number: 002-16951 Rev. *F

Page 17 of 37

EZ-PD™ CCG3PA Datasheet

Table 5. DC Specifications (continued)

Spec ID Parameter

Description

Min

Typ Max Units

Details/Conditions

Active Mode. Typical values measured at V_DDD= 5.0V or V_BUS= 5.0 V and T_A= 25 °C.

V_DDD= 5 V OR V_BUS= 5 V, T_A=

25 °C. CC1/CC2 in Tx or Rx, no I/O

mA sourcing current, 2 SCBs at 1 Mbps,

EA/ADC/CSA/UVOV ON, CPU at

24 MHz.

Supply current from V_BUSor

V_DDD

SID.PWR#8

I_{DD_A}

–

10

3

–

Sleep Mode. Typical values measured at V_DD= 3.3 V and T_A= 25 °C.

V_DDD= 3.3 V, T_A= 25 °C,

mA All blocks except CPU are on, CC IO

on, EA/ADC/CSA/UVOV On.

CC, I²C, WDT wakeup on.

IMO at 24 MHz.

SID25A

I_{DD_S}

–

Deep Sleep Mode. Typical values measured at T_A= 25 °C.

Power Adapter/Charger application

Power Source = V_BUS= 5 V,

µA T_A= 25 °C,

V_BUS= 4.5 to 5.5 V. CC

SID_PA_DS_UA I_{DD_PA_DS_UA}

–

100

500

100

–

Attach, I²C, WDT Wakeup on

Type-C NotAttached. CCAttach, I²C

and WDT enabled for Wakeup.

Power Adapter/Charger application

V_BUS= 3.0 to 24.5 V. CC, I²C,

SID_PA_DS_A I_{DD_PA_DS_A}

VBUS = 24.5 V, T_A= 25 °C,

Part is in deep sleep. Attached, CC

µA

WDT Wakeup on

I/O on, ADC/CSA/UVOV On

Power Bank application

Power Source = V_DDD= 5 V,

µA T_A= 25 °C,

V_DDD= 3.0 to 5.5 V. CC

SID_PB_DS_UA I_{DD_PB_DS_UA}

Attach, I²C, WDT Wakeup on

Type-C NotAttached. CCAttach, I²C

and WDT enabled for Wakeup.

Power Bank Source application

V_DDD= 5 V, T_A= 25 °C,

Part is in deep sleep. Attached, CC

I/O on, ADC/CSA/UVOV On.

SID_P-

B_DS_A_SRC

I_{DD_P-}

B_DS_A_SRC

V_DDD= 3.0 to 5.5 V.

–

500

–

µA

CC, I²C, WDT Wakeup on

Power Bank Sink application

SID_P-

B_DS_A_SNK

I_{DD_P-}

B_DS_A_SNK

V_BUS4.0 to 24.5 V.

V_BUS= 24.5 V, T_A= 25 °C,

µA

CC, I²C, WDT Wakeup on

Part is in deep sleep. Attached, CC

I/O on, ADC/CSA/UVOV On

Table 6. AC Specifications (Guaranteed by Characterization)

Spec ID

SID.CLK#4

Parameter

F_CPU

Description

CPU input frequency

Wakeup from sleep mode

Min

DC

–

Typ Max Units

Details/Conditions

–

0

48

–

MHz All V_DDD

µs

SID.PWR#17

T_SLEEP

–

Wakeup from Deep Sleep

mode

SID.PWR#18

SYS.FES#1

T_DEEPSLEEP

T_{_PWR_RDY}

–

5

3

35

25

–

µs

ms

Power-up to “Ready to accept

I²C/CC command”

–

Power-on I/O Initialization

Time

SID.PWR#18A T_{POR_HIZ_T}

Document Number: 002-16951 Rev. *F

Page 18 of 37

EZ-PD™ CCG3PA Datasheet

I/O

Table 7. I/O DC Specifications

Spec ID

Parameter

Description

Min

Typ

–

Max

Units

Details/Conditions

CMOS input

SID.GIO#37 V_{IH_CMOS}

SID.GIO#38 V_{IL_CMOS}

Input voltage HIGH threshold 0.7 × V_DDD

–

V

Input voltage LOW threshold

–

0.3 × V_DDD

SID.GIO#39 V_{IH_VDDD2.7-}LVTTL input, V_DDD< 2.7 V

SID.GIO#40 V_{IL_VDDD2.7-}LVTTL input, V_DDD< 2.7 V

SID.GIO#41 V_{IH_VDDD2.7+}LVTTL input, V_DDD 2.7 V

SID.GIO#42 V_{IL_VDDD2.7+}LVTTL input, V_DDD 2.7 V

0.7× V_DDD

–

0.3 × V_DDD

2.0

–

0.8

–

SID.GIO#33 V_{OH_3V}

SID.GIO#36 V_{OL_3V}

Output voltage HIGH level

Output voltage LOW level

Pull-up resistor value

V_DDD–0.6

–

I_OH= 4 mA at 3-V V_DDD

I_OL= 10 mA at 3-V V_DDD

–

0.6

8.5

SID.GIO#5

SID.GIO#6

R_PU

R_PD

3.5

5.6

k +25 °C T_A, all V_DDD

Pull-down resistor value

Input leakage current

(absolute value)

+25 °C T_A, 3-V V_DDD

nA

SID.GIO#16 I_IL

–

2

CapacitanceonDP0,DM0,

DP1, DMI pins.

Guaranteed by characteri-

zation.

SID.GIO#17 C_{PIN_A}

Max pin capacitance

–

22

pF

–40°C to +85°C T_A, All

V_DDD, all other I/O_S.

SID.GIO#17A C_PIN

–

3

7

pF

Guaranteed by characteri-

zation.

Inputhysteresis, LVTTLV_DDD

 2.7 V

Guaranteed by characteri-

zation.

SID.GIO#43 V_HYSTTL

SID.GIO#44 V_HYSCMOS

15

40

–

mV

V_DDD< 4.5 V.

mV Guaranteed by characteri-

zation.

Input hysteresis CMOS

0.05 × V_DDD

Current through protection

diode to V_DDD/V_SS

Guaranteed by design.

SID69

I_DIODE

–

100

85

µA

Maximum total sink chip

current

Guaranteed by design.

mA

SID.GIO#45 I_{TOT_GPIO}

OVT

Input current when Pad >

SID.GIO#46 I_IHS

–

10.00

µA Per I²C specification

V_DDDfor OVT inputs

Table 8. I/O AC Specifications

(Guaranteed by Characterization)

Spec ID Parameter

SID70 T_RISEF

SID71 T_FALLF

Description

Rise time in Fast Strong mode

Fall time in Fast Strong mode

Min Typ Max Units

Details/Conditions

2

–

12

ns 3.3-V V_DDD, C_load= 25 pF

Document Number: 002-16951 Rev. *F

Page 19 of 37

EZ-PD™ CCG3PA Datasheet

Table 9. GPIO_20VT DC Specifications (Applicable to port pins P2.2 and P2.3 only)

(Guaranteed by Characterization)

Spec ID#

Parameter

Description

Min Typ

Max Units

Details / Conditions

SID.GPIO_20VT#4 GPIO_20VT_I_LU

GPIO_20VT Latch up current

limits

–140

–

140

mA Max / min current in to any input

or output, pin-to-pin,

pin-to-supply

SID.GPIO_20VT#5 GPIO_20VT_RPU

SID.GPIO_20VT#6 GPIO_20VT_RPD

SID.GPIO_20VT#16 GPIO_20VT_IIL

SID.GPIO_20VT#17 GPIO_20VT_CPIN

SID.GPIO_20VT#36 GPIO_20VT_Vol

GPIO_20VT Pull-up resistor

value

1

2.5

–

25

20

2

kΩ +25 °C T_A, 1.4 V to

GPIO_20VT_Voh(min)

GPIO_20VT Pull-down resistor

value

kΩ +25°C T_A, 1.4-V to V_DDD

GPIO_20VT Input leakage

current (absolute value)

–

nA +25°C T_A, 3-V V_DDD

GPIO_20VT pin capacitance

15

–

25

0.4

–

pF –40 °C to +85 °C T_A, All V_DDD

F = 1 MHz

,

GPIO_20VT Output Voltage low

level.

–

V

I_OL= 2 mA

SID.GPIO_20VT#41 GPIO_20VT_Vih_LVTTL GPIO_20VTLVTTLInputVoltage

high level.

2

–

V_DDD 2.7 V

SID.GPIO_20VT#42 GPIO_20VT_Vil_LVTTL GPIO_20VTLVTTLInputVoltage

low level.

–

0.8

–

SID.GPIO_20VT#43 GPIO_20VT_Vhysttl

GPIO_20VT Input hysteresis

LVTTL

15

–

40

–

mV V_DDD 2.7 V

SID.GPIO_20VT#69 GPIO_20VT_IDIODE

GPIO_20VT Current through

protection diode to V_DDD/V_SS

100

µA

Table 10. GPIO_20VT AC Specifications (Applicable to port pins P2.2 and P2.3 only)

(Guaranteed by Characterization)

Spec ID#

Parameter

Description

Min

Typ

Max Units

Details / Conditions

SID.GPIO_20VT#70 GPIO_20VT_TriseF GPIO_20VT Rise time in

Fast Strong Mode

1

–

45

15

ns All V_DDD, C_load= 25 pF

SID.GPIO_20VT#71 GPIO_20VT_TfallF GPIO_20VT Fall time in Fast

Strong Mode

2

–

Document Number: 002-16951 Rev. *F

Page 20 of 37

EZ-PD™ CCG3PA Datasheet

Digital Peripherals

The following specifications apply to the Timer/Counter/PWM peripherals in the Timer mode.

Pulse Width Modulation (PWM) for GPIO Pins

Table 11. PWM AC Specifications (Guaranteed by Characterization)

Spec ID

Parameter

Description

Min

–

Typ

–

Max Units

Details/Conditions

Fc max = CLK_SYS.

Maximum = 48 MHz.

SID.TCPWM.3 T_CPWMFREQOperating frequency

SID.TCPWM.4 T_PWMENEXTInput trigger pulse width

Fc

–

MHz

ns

2/Fc

–

For all trigger events

Minimum possible width of

Overflow, Underflow, and CC

(Counter equals Compare

value) outputs

SID.TCPWM.5 T_PWMEXT

Output trigger pulse width

2/Fc

–

ns

Minimum time between

successive counts

SID.TCPWM.5A T_CRES

SID.TCPWM.5B PWM_RES

SID.TCPWM.5C Q_RES

I²C

Resolution of counter

PWM resolution

1/Fc

–

ns

Minimum pulse width of PWM

output

Minimum pulse width between

quadrature-phase inputs

Quadrature inputs resolution

Table 12. Fixed I²C DC Specifications

(Guaranteed by Characterization)

Spec ID

SID149

Parameter

I_I2C1

Description

Min

–

Typ

–

Max Units

Details/Conditions

Block current consumption at 100 kHz

Block current consumption at 400 kHz

Block current consumption at 1 Mbps

I²C enabled in Deep Sleep mode

100

135

310

–

µA

–

SID150

SID151

SID152

I_I2C2

I_I2C3

I_I2C4

–

1.4

Table 13. Fixed I²C AC Specifications

(Guaranteed by Characterization)

Spec ID

SID153

Parameter

Description

Min

Typ Max Units

Details/Conditions

F_I2C1

Bit rate

–

1

Mbps

–

Table 14. Fixed UART DC Specifications

(Guaranteed by Characterization)

Spec ID

SID160

SID161

Parameter

Description

Min

Typ

Max Units

Details/Conditions

Block current consumption at

100 kbps

I_UART1

–

20

µA

–

Block current consumption at

1000 kbps

I_UART2

–

312

–

Table 15. Fixed UART AC Specifications

(Guaranteed by Characterization)

Spec ID

SID162

Parameter

Description

Min

Typ

Max Units

Mbps

Details/Conditions

Bit rate

–

1

–

F_UART

Document Number: 002-16951 Rev. *F

Page 21 of 37

EZ-PD™ CCG3PA Datasheet

Table 16. Fixed SPI DC Specifications

(Guaranteed by Characterization)

Spec ID

SID163

Parameter

I_SPI1

I_SPI2

I_SPI3

Description

Min

–

Typ

–

Max Units

Details/Conditions

Block current consumption at 1 Mb/s

Block current consumption at 4 Mb/s

Block current consumption at 8 Mb/s

360

560

600

µA

–

SID164

SID165

–

Table 17. Fixed SPI AC Specifications

(Guaranteed by Characterization)

Spec ID

SID166

Parameter

F_SPI

Description

Min

Typ

Max Units

MHz

Details/Conditions

SPI Operating frequency (Master; 6X

oversampling)

–

8

–

Table 18. Fixed SPI Master Mode AC Specifications (Guaranteed by Characterization)

Spec ID

SID167

Parameter

Description

Min

Typ

Max Units

Details/Conditions

T_DMO

MOSI Valid after SClock driving edge

–

15

ns

–

MISO Valid before SClock capturing

edge

Full clock, late MISO

sampling

SID168

SID169

T_DSI

20

0

–

ns

Referred to slave capturing

edge

T_HMO

Previous MOSI data hold time

–

ns

Table 19. Fixed SPI Slave Mode AC Specifications

(Guaranteed by Characterization)

Spec ID

SID170

Parameter

T_DMI

Description

Min

40

–

Typ

–

Max

Units Details/Conditions

MOSI Valid before Sclock capturing

edge

–

ns

–

SID171

T_DSO

MISO Valid after Sclock driving edge

–

42 + 3 × T_CPUns T_CPU= 1/F_CPU

MISO Valid after Sclock driving edge

in Ext Clk mode

SID171A

T_{DSO_EXT}

–

48

ns

–

SID172

T_HSO

Previous MISO data hold time

0

–

ns

–

SID172A

T_SSELSCK

SSEL Valid to first SCK Valid edge

100

Document Number: 002-16951 Rev. *F

Page 22 of 37

EZ-PD™ CCG3PA Datasheet

System Resources

Power-on-Reset (POR) with Brown Out SWD Interface

Table 20. Imprecise Power On Reset (PRES) (Guaranteed by Characterization)

Spec ID

Parameter

V_RISEIPOR

V_FALLIPOR

Description

Min

0.80

0.70

Typ

–

Max Units

Details/Conditions

Power-on Reset (POR) rising trip

voltage

SID185

SID186

1.50

1.4

V

–

POR falling trip voltage

–

Table 21. Precise Power On Reset (POR)

(Guaranteed by Characterization)

Spec ID

Parameter

Description

Min

Typ

–

Max Units

Details/Conditions

Brown-out Detect (BOD) trip voltage

in active/sleep modes

SID190

SID192

V_FALLPPOR

1.48

1.62

1.5

V

–

V_FALLDPSLPBOD trip voltage in Deep Sleep mode 1.1

–

Table 22. SWD Interface Specifications

(Guaranteed by Characterization)

Spec ID

Parameter

Description

Min

Typ

Max

Units

Details/Conditions

SWDCLK 1/3 CPU clock

SID.SWD#1

F_SWDCLK1

3.3V  VDDD  5.5V

–

14

7

MHz

frequency

SWDCLK 1/3 CPU clock

frequency

SID.SWD#2

F_SWDCLK2

2.7V  VDDD  3.3V

–

SID.SWD#3

SID.SWD#4

SID.SWD#5

SID.SWD#6

T_SWDI_SETUP T = 1/f SWDCLK

T_SWDI_HOLD T = 1/f SWDCLK

T_SWDO_VALID T = 1/f SWDCLK

T_SWDO_HOLD T = 1/f SWDCLK

0.25 × T

–

ns

0.25 × T

–

1

0.50 × T ns

–

ns

Internal Main Oscillator

Table 23. IMO DC Specifications

(Guaranteed by Design)

Spec ID

SID218

Parameter

I_IMO1

Description

Min

Typ

Max

Units

Details/Conditions

IMO operating current at 48 MHz

–

1000

µA

–

Table 24. IMO AC Specifications

Spec ID

Parameter

Description

Min

Typ

Max

Units

Details/Conditions

Frequency variation at 24, 36, and

48 MHz (trimmed)

SID.CLK#13

F_IMOTOL

–

±2

%

–

Guaranteed by characteri-

zation.

SID226

SID228

T_STARTIMO

IMO start-up time

–

7

–

µs

ps

Guaranteed by characteri-

zation.

T_JITRMSIMO2RMS jitter at 24 MHz

145

Only 3 frequencies

MHz supported: 24 MHz,

36 MHz, and 48 MHz.

SID.CLK#1

F_IMO

IMO frequency

24

36

48

Document Number: 002-16951 Rev. *F

Page 23 of 37

EZ-PD™ CCG3PA Datasheet

Internal Low-Speed Oscillator Power Down

Table 25. ILO DC Specifications

(Guaranteed by Design)

Spec ID

SID231

SID233

Parameter

I_ILO1

I_ILOLEAK

Description

I_LOoperating current

I_LOleakage current

Min Typ Max Units

Details/Conditions

–

0.3 1.05

15

µA

nA

–

2

Table 26. ILO AC Specifications

Spec ID

SID234

Parameter

Description

Min

Typ Max Units

Details/Conditions

Guaranteed by Character-

ization

T_STARTILO1

I_LOstart-up time

–

2

ms

Guaranteed by Character-

ization

SID238

T_ILODUTY

F_ILO

I_LOduty cycle

I_LOfrequency

40

20

50

40

60

80

%

SID.CLK#5

kHz

–

Table 27. PD DC Specifications

Spec ID Parameter

Description

Min

Typ Max Units

80 96 µA

Details/Conditions

DFP CC termination for default USB

Power

SID.PD.1

Rp_std

64

–

SID.PD.2

SID.PD.3

SID.PD.4

Rp_1.5A

Rp_3.0A

Rd

DFP CC termination for 1.5A power

DFP CC termination for 3.0A power

UFP CC termination

166

304

4.59

180 194.4 µA

330 356.4 µA

–

5.1 5.61

kΩ

–

All supplies forced to 0V

kΩ and 1.32 V applied at CC1

UFP (Power Bank) Dead Battery CC

Termination on CC1 and CC2

SID.PD.5

SID.PD.6

Rd_DB

4.08

5.1 6.12

or CC2

Ground offset tolerated by BMC

receiver

Relative to the remote

mV

V_gndoffset

–500

–

500

BMC transmitter.

Table 28. LS-CSA Specifications

Spec ID Parameter

Description

Min

Typ Max Units

Details/Conditions

Guaranteed by

characterization

SID.LSCSA.1 Cin_inp

CSP Input capacitance

7

–

10

pF

SID.LSCSA.2 Csa_Acc1

SID.LSCSA.3 Csa_Acc2

SID.LSCSA.4 Csa_Acc3

SID.LSCSA.5 Csa_Acc4

SID.LSCSA.6 Csa_Acc5

SID.LSCSA.7 Csa_Acc6

CSA accuracy 5 mV < Vsense < 10 mV –15

CSAaccuracy 10 mV < Vsense < 15 mV –10

CSAaccuracy 15 mV < Vsense < 20 mV –6

CSAaccuracy 20 mV < Vsense < 30 mV –5

CSAaccuracy 30 mV < Vsense < 50 mV –4

–

15

10

6

%

5

4

Active Mode

CSA accuracy 50 mV < Vsense

–4

4

SID.LSCSA.8 Csa_SCP_Acc1 CSA SCP 80 mV

SID.LSCSA.9 Csa_SCP_Acc2 CSA SCP 100 mV

SID.LSCSA.10 Csa_SCP_Acc3 CSA SCP 150 mV

SID.LSCSA.11 Csa_SCP_Acc4 CSA SCP 200 mV

–16.5

–13.4

–9.4

30

24

16

12

–7.5

Nominal Gain values supported: 5, 10,

SID.LSCSA.12 Av

5

–

150

3

V/V

%

20, 35, 50, 75, 125, 150

Guaranteed by

characterization

SID.LSCSA.24 Av1_E_Trim

SID.LSCSA.31 Av_E_SCP

Gain Error

–3

Guaranteed by

characterization

Gain Error of SCP stage

–3.5

3.5

%

Document Number: 002-16951 Rev. *F

Page 24 of 37

EZ-PD™ CCG3PA Datasheet

Table 29. LS-CSA AC Specifications

(Guaranteed by Characterization)

Spec ID

Parameter

Description

Min

Typ

Max Units

Details/Conditions

µs Available on P1.0 or P1.1

µs

µs Available on P1.0 or P1.1

µs

µs Available on P1.0 or P1.1

Delay from OCP threshold trip to

output GPIO toggle

SID.LSCSA.AC.1 T_{OCP_GPIO}

SID.LSCSA.AC.2 T_{OCP_Gate}

SID.LSCSA.AC.3 T_{SCP_GPIO}

SID.LSCSA.AC.4 T_{SCP_Gate}

SID.LSCSA.AC.5 T_{SR_GPIO}

–

20

50

15

50

20

Delay from OCP threshold trip to

external PFET Power Gate Turn off

–

Delay from SCP threshold trip to

output GPIO toggle

Delay from SCP threshold trip to

external PFET Power Gate Turn off

–

Delay from SR threshold trip to output

GPIO toggle

Table 30. UV/OV Specifications

(Guaranteed by Characterization)

Spec ID

Parameter

Description

Min

Typ Max Units

Details/Conditions

Overvoltage Threshold Accuracy,

4.0 V to 11.0 V

SID.UVOV.1

V_THOV1

–3

–

3

3.2

4

%

Overvoltage Threshold Accuracy,

11 V to 27.4 V

SID.UVOV.2

SID.UVOV.3

SID.UVOV.4

SID.UVOV.5

SID.UVOV.6

V_THOV2

V_THUV1

V_THUV2

V_THUV3

V_THUV4

–3.2

-4

Undervoltage Threshold Accuracy,

2.7 V to 3.3 V

Active Mode

Undervoltage Threshold Accuracy,

3.3 V to 4.0 V

–3.5

–3

3.5

3

Undervoltage Threshold Accuracy,

4.0 V to 11.0 V

Undervoltage Threshold Accuracy,

11.0 V to 22.0 V

–2.9

2.9

Table 31. UV/OV AC Specifications

(Guaranteed by Characterization)

Spec ID

Parameter

Description

Min

Typ Max Units

Details/Conditions

µs Available on P1.0 or P1.1

µs

µs Available on P1.0 or P1.1

Delay from UV threshold trip to

output GPIO toggle

SID.UVOV.AC.1 T_{OV_GPIO}

SID.UVOV.AC.2 T_{OV_GATE}

SID.UVOV.AC.3 T_{UV_GPIO}

–

20

50

20

Delay from UV threshold trip to

external PFET power gate turn off

–

Delay from UV threshold trip to

output GPIO toggle

Document Number: 002-16951 Rev. *F

Page 25 of 37

EZ-PD™ CCG3PA Datasheet

Gate Driver Specifications

Table 32. Gate Driver DC Specifications

Spec ID

Parameter

Description

Min

Typ

Max Units

Details/Conditions

Applicable on VBUS_P_CTRL and

VBUS_C_CTRL to turn ON external

PFET.

SID.GD.1

R_PD

Pull-down resistance

–

3

kΩ

Applicable on VBUS_P_CTRL to turn

OFF external PFET

SID.GD.2

SID.GD.3

SID.GD.4

SID.GD.5

SID.GD.6

SID.GD.7

R_PU

I_PD0

I_PD1

I_PD2

I_PD3

I_PD4

Pull-up resistance

–

4

kΩ

µA

Pull-down current sink at drive

strength of 1

25

75

Pull-down current sink at drive

strength of 2

50

150

300

580

1200

2300

Pull-down current sink at drive

strength of 4

I-mode (current mode) pull down at

5 V. Applicable on VBUS_P_CTRL

and VBUS_C_CTRL to turn ON

external PFET

140

280

560

1120

Pull-down current sink at drive

strength of 8

Pull-down current sink at drive

strength of 16

Pull-down current sink at drive

strength of 32

SID.GD.8

SID.GD.9

I_PD5

I_leak_p1

Pin leakage on VBUS_P_CTRL

Pin leakage on VBUS_C_CTRL

Pin leakage on VBUS_P_CTRL

Pin leakage on VBUS_C_CTRL

Pin leakage on VBUS_P_CTRL

Pin leakage on VBUS_C_CTRL

–

0.003

–

2

7

µA

+25 °C T_J, 5-V V_DDD, 20-V V_BUS

+25 °C T_J, 5-V V_DDD, 20-V V_BU

+85 °C T_J, 5-V V_DDD, 20-V V_BU

+125 °C T_J, 5-V V_DDD, 20-V V_BU

SID.GD.10 I_leak_c1

SID.GD.11 I_leak_p2

SID.GD.12 I_leak_c2

SID.GD.13 I_leak_p3

SID.GD.14 I_leak_c3

0.003

–

Table 33. Gate Driver AC Specifications

(Guaranteed by Characterization)

Spec ID

Parameter

Description

Min Typ Max Units

Details/Conditions

Cload = 2 nF, Delay to VBUS –1.5 V

from initiation of falling edge, VBUS =

5 V to 20 V, 50 K tied between

VBUS_C_CTRL and VBUS

Pull down delay on

VBUS_C_CTRL

SID.GD.15 T_PD1

–

2

5

2

µs

80% to 20%, 50 K tied between

V/µs VBUS_C_CTRL and VBUS, Cload =

2 nF, Vinitial = 24 V

Discharge rate of output node on

VBUS_C_CTRL

SID.GD.16 T_{r_discharge}

SID.GD.17 T_PD2

Cload = 2 nF, Delay toVBUS–1.5 Vfrom

initiation of falling edge, V_BUS= 5 V to

20 V, 50 K tied between

VBUS_C_CTRL and VBUS

Pull down delay on

VBUS_P_CTRL

µs

Cload = 2 nF, Delay to VBUS–1.5 V from

initiation of falling edge, VBUS = 5 V to

20 V, 50 K tied between

VBUS_C_CTRL and VBUS

SID.GD.18 T_PU

Pull up delay on VBUS_P_CTRL

–

18

µs

Output slew rate on

VBUS_P_CTRL

Cload = 2 nF, 20% to 80% of

V/µs

SID.GD.19 SR_PU

SID.GD.20 SR_PD

–

5

VBUS_P_CTRL range

Output slew rate on

VBUS_P_CTRL

Cload = 2 nF, 80% to 20% of

V/µs

VBUS_P_CTRL range

Document Number: 002-16951 Rev. *F

Page 26 of 37

EZ-PD™ CCG3PA Datasheet

Table 34. VBUS Discharge Specifications

Spec ID# Parameter

Description

Min Typ Max Units

Details / Conditions

SID.VBUS.DISC.6 I1

SID.VBUS.DISC.7 I2

SID.VBUS.DISC.8 I4

SID.VBUS.DISC.9 I8

SID.VBUS.DISC.10 I16

20-V NMOS ON current for DS = 1 0.15

–

1

2

mA

20-V NMOS ON current for DS = 2

20-V NMOS ON current for DS = 4

20-V NMOS ON current for DS = 8

20-V NMOS ON current for DS = 16

0.4

0.9

2

4

mA Measured at 0.5 V

8

mA

4

10

mA

When V_BUSis discharged to

5 V. Guaranteed by Characteri-

zation.

VBUS_Stop Error percentage of final V_BUSvalue

SID.VBUS.DISC.11

–

10

%

_Error

from setting

Table 35. Voltage (VBUS) Regulation DC Specifications

Spec ID#

Parameter

Description

Min Typ Max Units

Details / Conditions

Active mode shunt regulator at

3 V with bandgap

SID.DC.VR.1

SID.DC.VR.2

SID.DC.VR.3

SID.DC.VR.4

SID.DC.VR.5

SID.DC.VR.6

SID.DC.VR.7

SID.DC.VR.8

SID.DC.VR.9

SID.DC.VR.10

V_{_IN_3}

V_{_IN_5}

V_{_IN_9}

V_{_IN_15}

V_{_IN_20}

V(pad_in) at 3-V target

V(pad_in) at 5-V target

V(pad_in) at 9-V target

V(pad_in) at 15-V target

V(pad_in) at 20-V target

2.85

4.75

8.55

3

5

9

3.15

5.25

9.45

V

Active mode shunt regulator at

5 V

Active mode shunt regulator at

9 V

Active mode shunt regulator at

15 V

14.25 15 15.75

Active mode shunt regulator at

20 V

19

2.7

4.5

8.1

20

3

21

3.3

5.5

9.1

Deep Sleep mode shunt

regulator at 3 V with bandgap

V_{_IN_3_DS}V(pad_in) at 3-V target

V_{_IN_5_DS}V(pad_in) at 5-V target

V_{_IN_9_DS}V(pad_in) at 9-V target

V_{_IN_15_DS}V(pad_in) at 15-V target

V_{_IN_20_DS}V(pad_in) at 20-V target

Deep Sleep mode shunt

regulator at 5 V

5

Deep Sleep mode shunt

regulator at 9 V

9

Deep Sleep mode shunt

regulator at 15 V

13.5 15 16.5

Deep Sleep mode shunt

regulator at 20 V

18

20

22

SID.DC.VR.11

SID.DC.VR.12

I_{KA_OFF}

I_{KA_ON}

Off-state cathode current

–

10

µA

-

Current through cathode pin

mA

Table 36. VBUS Short Protection Specifications

Spec ID

Parameter

V_SHORT_ Short-to-VBUSsystem-sideclamping

TRIGGER voltage on the CC/P2.2/P2.3 pins

Description

Min Typ Max Units

Details/Conditions

Guaranteed by Characteri-

zation.

SID.VSP.1

–

9

–

V

Table 37. VBUS DC Regulator Specifications

Spec ID

Parameter

Description

Min Typ Max Units

1.08 2.62

Details/Conditions

VBUS_-

DETECT

SID.VREG.2

VBUS detect threshold voltage

–

V

–

Document Number: 002-16951 Rev. *F

Page 27 of 37

EZ-PD™ CCG3PA Datasheet

Table 38. VBUS AC Regulator Specifications

Spec ID

Parameter

Description

Min

Typ

Max

Units

Details/Conditions

Total startup time for the regulator

supply outputs

Guaranteed by Charac-

terization.

SID.VREG.3 T_start

–

200

µs

Analog to Digital Converter

Table 39. ADC DC Specifications (Guaranteed by Characterization)

Spec ID

Parameter

Description

ADC resolution

Min

Typ

Max

Units

Details/Conditions

SID.ADC.1

Resolution

–

8

–

Bits

–

Reference voltage

generated from VDDD

SID.ADC.2

INL

Integral non-linearity

Differential non-linearity

–2.5

–1.5

–2.5

–

2.5

LSB

Reference voltage

generated from bandgap

SID.ADC.2A INL

SID.ADC.3 DNL

SID.ADC.3A DNL

–

1.5

2.5

Reference voltage

generated from VDDD

Reference voltage

generated from bandgap

Differential non-linearity

Gain error

–1.5

1.96

–

1.5

LSB

V

SID.ADC.4

SID.ADC.6

Gain Error

V_{REF_ADC2}

–

ADC reference voltage when

generated from band gap.

Reference voltage

generated from bandgap

2.0

2.04

Table 40. ADC AC Specifications (Guaranteed by Design)

Spec ID

Parameter

Description

Min

Typ

Max

Units

Details/Conditions

Rate of change of sampled voltage

signal

SID.ADC.7

SLEW_Max

–

3

V/ms

–

Memory

Table 41. Flash AC Specifications

Spec ID Parameter

Description

Row erase time

Min Typ Max Units

Details/Conditions

SID.MEM#3 FLASH_ERASE

–

15.5

ms

–40 °C T_A85 °C, all V_DDD

Row (Block) write time (erase

and program)

SID.MEM#4 FLASH_WRITE

–

20

ms

–40 °C T_A85 °C, all V_DDD

SID.MEM#8 FLASH_ROW_PGM Row program time after erase

–

7

ms

s

25 °C T_A55 °C, all V_DDD

SID178

SID180

T_BULKERASE

T_DEVPROG

Bulk erase time (32 KB)

Total device program time

35

7.5

–

Flash retention, T_A≤ 55 °C,

100K P/E cycles

SID182

F_RET1

F_RET2

F_RET3

20

10

3

–

years

–

Flash retention, T_A≤ 85 °C,

10K P/E cycles

SID182A

SID182B

Flash retention, T_A≤ 105 °C,

10K P/E cycles

Document Number: 002-16951 Rev. *F

Page 28 of 37

EZ-PD™ CCG3PA Datasheet

Ordering Information

Table 42 lists the EZ-PD CCG3PA part numbers and features.

Table 42. CCGPA Ordering Information

Termination

MPN

Application

Role

Bootloader^[7]

Package Type

Si ID

Resistor

CYPD3171-24LQXQ Power Bank

Power Adapter based

CYPD3174-16SXQ on Opto Coupler

Feedback

R_P, R_D, R_D-DBDRP UFP CC Bootloader

24-Pin QFN

2003

DFPCC with Opto Coupler

R_P

DFP

16-Pin SOIC

2001

Feedback Bootloader

Power Adapter based

CYPD3174-24LQXQ on Opto Coupler

Feedback

DFPCC with Opto Coupler

Feedback Bootloader

R_P

DFP

24-Pin QFN

2000

2002

Power Adapter based

CYPD3175-24LQXQ

DFP CC with Direct

Feedback Bootloader

on Direct Feedback

Ordering Code Definitions

-

XX XX

X

PD

X

XX

X

CY

T = Tape and Reel

Temperature Grade:

Q = Extended industrial (–40 °C to +105 °C)

Lead: X = Pb-free

Package Type: LQ = QFN; S = SOIC

Number of pins in the package

Application and Feature Combination Designation

Number of Type-C Ports: 1 = 1 Port, 2 = 2 Port

Product Type: 3 = Third-generation product family

Marketing Code: PD = Power Delivery product family

Company ID: CY = Cypress

Note

7. It is assumed that VBUS is at 5V by default. Bootloader execution is not responsible for controlling the generation of 5V VBUS.

Document Number: 002-16951 Rev. *F

Page 29 of 37

EZ-PD™ CCG3PA Datasheet

Packaging

Table 43. Package Characteristics

Parameter

T_A

Description

Conditions

Min

Typ

Max

105

Units

°C

Operating ambient temperature

Operating junction temperature

Package _JA(24-QFN)

Extended Industrial

-40

25

-

T_J

Extended Industrial

-40

120

°C

T_JA

T_JC

T_JA

T_JC

-

19.98

4.78

84

°C/W

Package _JC(24-QFN)

-

Package _JA(16-SOIC)

-

Package _JC(16-SOIC)

-

33.9

Table 44. Solder Reflow Peak Temperature

Maximum Time within 5° C

Package

Maximum Peak Temperature

of Peak Temperature

24-pin QFN

16-pin SOIC

260 °C

30 seconds

Table 45. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2

Package

24-pin QFN

16-pin SOIC

MSL

MSL3

Document Number: 002-16951 Rev. *F

Page 30 of 37

EZ-PD™ CCG3PA Datasheet

Figure 11. 24-pin QFN Package Outline

ġ

NOTES

DIMENSIONS

1. ALL DIMENSIONS ARE IN MILLIMETERS.

SYMBOL

A

MIN. NOM. MAX.

0.60

2. DIE THICKNESS ALLOWABLE IS 0.305 mm MAXIMUM(.012 INCHES MAXIMUM)

3. DIMENSIONING & TOLERANCES CONFORM TO ASME Y14.5M. -1994.

4. THE PIN #1 IDENTIFIER MUST BE PLACED ON THE TOP SURFACE OF THE

PACKAGE BY USING INDENTATION MARK OR OTHER FEATURE OF

PACKAGE BODY.

A

0.00

0.05

1

2

3

0.40

0.152 REF

0.25

0.425

5. EXACT SHAPE AND SIZE OF THIS FEATURE IS OPTIONAL.

6. PACKAGE WARPAGE MAX 0.08 mm.

0.18

2.65

0.30

2.85

b

7. APPLIED FOR EXPOSED PAD AND TERMINALS. EXCLUDE EMBEDDING PART

OF EXPOSED PAD FROM MEASURING.

D

4.00 BSC

2.75

D

E

L

2

8. APPLIED ONLY TO TERMINALS.

4.00 BSC

2.75

9. JEDEC SPECIFICATION NO. REF: N.A.

2.65

0.30

2.85

0.50

0.40

e

0.50 BSC

002-16934 *A

R

0.09

Document Number: 002-16951 Rev. *F

Page 31 of 37

EZ-PD™ CCG3PA Datasheet

Figure 12. 16-pin SOIC Package Outline

51-85068 *E

Document Number: 002-16951 Rev. *F

Page 32 of 37

EZ-PD™ CCG3PA Datasheet

Table 46. Acronyms Used in this Document (continued)

Acronyms

Acronym

OCP

OTP

OVP

OVT

PCB

PD

Description

overcurrent protection

Table 46. Acronyms Used in this Document

Acronym

ADC

Description

analog-to-digital converter

over temperature protection

overvoltage protection

overvoltage tolerant

printed circuit board

power delivery

AES

advanced encryption standard

application programming interface

advanced RISC machine, a CPU architecture

configuration channel

API

ARM^®

CC

PGA

PHY

POR

PRES

PSoC^®

PWM

RAM

RISC

RMS

RTC

RX

programmable gain amplifier

physical layer

CCG3

CPU

Cable Controller Generation 3

central processing unit

power-on reset

cyclic redundancy check, an error-checking

protocol

CRC

precise power-on reset

Programmable System-on-Chip™

pulse-width modulator

random-access memory

reduced-instruction-set computing

root-mean-square

CS

current sense

DFP

downstream facing port

digital input/output, GPIO with only digital capabil-

ities, no analog. See GPIO.

DIO

DRP

dual role port

electrically erasable programmable read-only

memory

EEPROM

real-time clock

receive

electronically marked cable assembly, a USB

cable that includes an IC that reports cable

characteristics (e.g., current rating) to the Type-C

ports

SAR

SCL

successive approximation register

I²C serial clock

EMCA

SCP

SDA

S/H

short circuit protection

I²C serial data

EMI

ESD

FS

electromagnetic interference

electrostatic discharge

full-speed

sample and hold

SHA

secure hash algorithm

GPIO

IC

general-purpose input/output

integrated circuit

Serial Peripheral Interface, a communications

protocol

SPI

IDE

integrated development environment

SRAM

SWD

TX

static random access memory

serial wire debug, a test protocol

transmit

Inter-Integrated Circuit, a communications

protocol

I²C, or IIC

ILO

internal low-speed oscillator, see also IMO

internal main oscillator, see also ILO

input/output, see also GPIO

low-dropout regulator

a new standard with a slimmer USB connector and

a reversible cable, capable of sourcing up to

100 W of power

IMO

I/O

Type-C

LDO

LVD

Universal Asynchronous Transmitter Receiver, a

communications protocol

UART

USB

low-voltage detect

Universal Serial Bus

LVTTL

MCU

NC

low-voltage transistor-transistor logic

microcontroller unit

USB input/output, CCG2 pins used to connect to a

USB port

USBIO

no connect

UVP

undervoltage protection

external reset I/O pin

NMI

nonmaskable interrupt

XRES

NVIC

opamp

nested vectored interrupt controller

operational amplifier

Document Number: 002-16951 Rev. *F

Page 33 of 37

EZ-PD™ CCG3PA Datasheet

Document Conventions

Units of Measure

Table 47. Units of Measure

Symbol

°C

Unit of Measure

degrees Celsius

hertz

Hz

KB

kHz

k

Mbps

MHz

M

Msps

µA

1024 bytes

kilohertz

kilo ohm

megabits per second

megahertz

mega-ohm

mega samples per second

microampere

microfarad

microsecond

microvolt

µF

µs

µV

µW

mA

ms

mV

nA

microwatt

milliampere

millisecond

millivolt

nanoampere

nanosecond

ohm

ns



pF

picofarad

ppm

ps

parts per million

picosecond

second

s

sps

V

samples per second

volt

Document Number: 002-16951 Rev. *F

Page 34 of 37

EZ-PD™ CCG3PA Datasheet

Document History Page

Document Title: EZ-PD™ CCG3PA Datasheet, USB Type-C Port Controller

Document Number: 002-16951

Orig. of

Change

Submission

Date

Revision

ECN

Description of Change

**

5473667

VGT

10/13/2016 New datasheet

Changed datasheet status to Preliminary.

Updated Features.

Updated Logic Block Diagram.

Updated Functional Overview

Updated Figure 2, Figure 3, Figure 6, Figure 8, Figure 9, and Figure 10.

Updated Pinouts.

*A

5544333

VGT

12/13/2016

Updated Table 4 with VCC_PIN_ABS and VSBU_PIN_ABS parameters.

Added Q-temp parts in Table 42.

Updated General Description, Features, I/O Subsystem, CPU, Charger Detection, and

Ordering Information.

*B

*C

5583660

5665676

VGT

01/18/2017 Updated Table 2 and Table 4.

Updated Figure 6 through Figure 10.

Updated Sales page.

Updated Figure 2, Figure 6, Figure 8, Figure 10, Table 1,Table 2, Table 4, Table 42, Features,

Logic Block Diagram, Functional Overview, Power Systems Overview, Ordering Code

Definitions, Acronyms.

03/22/2017 Added Internal Block Diagram.

Added Table 5 through Table 41 in Device-Level Specifications.

Updated compliance with USB spec in Sales, Solutions, and Legal Information.

Updated Cypress logo.

Added Application Diagram description before Figure 6, Figure 8, Figure 9, and Figure 10.

Added Figure 1.

Added CCG3PA Programming and Bootloading section.

Added Document History Page section.

*D

5738854

VGT

05/19/2017 Added Table 3.

Updated Figure 3, Figure 4, Figure 6, Figure 8, Figure 9, and Figure 10.

Updated Table 2, Table 4, Table 5, and Table 42.

Updated Figure 11 (spec 002-16934 Rev. ** to *A) in Packaging.

Updated Cypress logo, Sales page, and Copyright information.

Removed Preliminary document status.

Updated System-Level Fault Protection, Power, and System-Level ESD Protection.

Updated Internal Block Diagram

Updated Figure 2.

Table 2: Updated Pins 12 and 13. Added Note 5.

Updated Figure 6.

Added Figure 7.

Table 4: Updated max value for V_{CC_PIN_ABS}

Table 5: Removed SID_DS and updated typ value for SID_PB_DS_UA.

Table 7: Added new SID.GIO#17 spec and changed SID.GIO#17 to SID.GIO#17A.

Added Table 9 and Table 10.

Table 12: Updated max value for SID149.

Table 22; Added “Guaranteed by Characterization”

Table 24: Updated Conditions for SID226 and SID228. Updated typ value and conditions for

SID.CLK#1.

*E

5984670

VGT

12/06/2017

Table 26: Updated Conditions for SID234 and SID238.

Table 28: Updated min, typ, and max values for SID.LSCSA.1,SID.LSCSA.7, and

SID.LSCSA.24

Updated Conditions for SID.GIO#17A, SID.GIO#43, SID.GIO#44, SID.GIO#45, and SID69.

Table 31: Added “Guaranteed by Characterization”

Table 32: Added SID.GD.9, SID.GD.10, SID.GD.11, SID.GD.12, SID.GD.13, SID.GD.14.

Changed description of spec IDs SID.GD.1 to SID.GD.8.

Table 33: Renumbered all spec IDs starting from SID.GD.15 to SID.GD.20. Modified max

values of SID.GD.15, SID.GD.17 and SID.GD.18. Modified Details/Conditions of all

parameters.

Table 34: Removed spec IDs SID.VBUS.DISC.1 to SID.VBUS.DISC5. Renumbered

SID.VBUS.DISC6 to SID.VBUS.DISC11. Added new spec IDs SID.VBUS.DISC6 to

SID.VBUS.DISC10.

Document Number: 002-16951 Rev. *F

Page 35 of 37

EZ-PD™ CCG3PA Datasheet

Document Title: EZ-PD™ CCG3PA Datasheet, USB Type-C Port Controller

Document Number: 002-16951

Table 35: Added V_IN_3 and V_IN3_DS parameters and renumbered spec IDs from

SID.DC.VR.1 to SID.DC.VR.12.

Added Table 36.

Table 39: Updated min and max values for SID.ADC.4.

Table 42: Added new MPN CYPD3174-24LQXQ. Modified "Application" column of

CYPD3174-16SXQ and CYPD3175-24LQXQ MPNs.

Removed Errata.

*E (contd)

5984670

VGT

12/06/2017

Added Table 43, Table 44 and Table 45 to Packaging section.

Added “The voltage reference for the ADCs is generated either from the VDDD supply or from

internal bandgap. When sensing the GPIO pin voltage with an ADC, the pin voltage cannot

exceed the VDDIO supply value” to ADC section.

Table 2: Updated the Descripion “GPIO with Open drain with pull-up assist. Configurable as

GPIO_20VT/I2C_SDA_1/IEC. Tolerant to temporary short to VBUS pin” for Pins P2.2 and P2.3.

Table 7: Removed SBU1, SBU2 reference in Details/Conditions for Spec ID SID.GIO#17.

Table 32: Moved “0.003” to Typ column for the Spec ID SID.GD.9 and SID.GD.10.

Table 12: Updated typical and max values for II2C4 parameter.

Table 9: Removed GPIO_20VT_Voh parameter.

Table 28: Updated max values of Csa_SCP_Acc parameters.

*F

6079226

VGT

03/02/2018

Table 39: Updated the Description of Spec ID SID.ADC.6 as “ADC reference voltage when

generated from band gap.”. Removed SID.ADC.5 parameter and added SID.ADC.2A and

SID.ADC.3A parameters. Updated Details/Conditions of SID.ADC.2 and SID.ADC3

parameters.

Table 35: Added units (V) to SID.DC.VR.3, SID.DC.VR.4 and SID.DC.VR.5 parameters.

Updated VBUS Short Protection and I/O Subsystem sections.

Updated Table 3 with information on Fault Indicator and VBUS Short Protection Capability.

Updated Application Diagrams section.

Document Number: 002-16951 Rev. *F

Page 36 of 37

EZ-PD™ CCG3PA Datasheet

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office

closest to you, visit us at Cypress Locations.

®

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Training | Components

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cypress.com/support

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cypress.com/psoc

cypress.com/pmic

cypress.com/touch

cypress.com/usb

Power Management ICs

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cypress.com/wireless

Notice regarding compliance with Universal Serial Bus specification. Cypress offers firmware and hardware solutions that are certified to comply with the Universal Serial Bus specification, USB

Type-C™ Cable and Connector Specification, and other specifications of USB Implementers Forum, Inc (USB-IF). You may use Cypress or third party software tools, including sample code, to modify

the firmware for Cypress USB products. Modification of such firmware could cause the firmware/hardware combination to no longer comply with the relevant USB-IF specification. You are solely

responsible ensuring the compliance of any modifications you make, and you must follow the compliance requirements of USB-IF before using any USB-IF trademarks or logos in connection with any

modifications you make. In addition, if Cypress modifies firmware based on your specifications, then you are responsible for ensuring compliance with any desired standard or specifications as if you

had made the modification. CYPRESS IS NOT RESPONSIBLE IN THE EVENT THAT YOU MODIFY OR HAVE MODIFIED A CERTIFIED CYPRESS PRODUCT AND SUCH MODIFIED PRODUCT

NO LONGER COMPLIES WITH THE RELEVANT USB-IF SPECIFICATIONS.

including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries

worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other

intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress

hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to

modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users

(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as

provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation

of the Software is prohibited.

TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE

OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing

device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress does not assume any liability arising out of any security breach,

such as unauthorized access to or use of a Cypress product. In addition, the products described in these materials may contain design defects or errors known as errata which may cause the product

to deviate from published specifications. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any

liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming

code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this

information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons

systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances

management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device

or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you

shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from

and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress product.

.Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in

the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.

Document Number: 002-16951 Rev. *F

Revised March 2, 2018

Page 37 of 37

厂商	型号	描述	页数
NIDEC	CYP	[ PIANO SWITCHES (FULL PITCH) ]	5 页
NIDEC	CYP-0200MB	[ PIANO SWITCHES (FULL PITCH) ]	5 页
NIDEC	CYP-0200MC	[ PIANO SWITCHES (FULL PITCH) ]	5 页
NIDEC	CYP-0200TB	[ PIANO SWITCHES (FULL PITCH) ]	5 页
NIDEC	CYP-0200TC	[ PIANO SWITCHES (FULL PITCH) ]	5 页
NIDEC	CYP-0201MB	[ PIANO SWITCHES (FULL PITCH) ]	5 页
NIDEC	CYP-0201MC	[ PIANO SWITCHES (FULL PITCH) ]	5 页
NIDEC	CYP-0201TB	[ PIANO SWITCHES (FULL PITCH) ]	5 页
NIDEC	CYP-0201TC	[ PIANO SWITCHES (FULL PITCH) ]	5 页
NIDEC	CYP-0202MB	[ PIANO SWITCHES (FULL PITCH) ]	5 页