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SZCM1213A-01SO

型号：

SZCM1213A-01SO

品牌：

ONSEMI[ ONSEMI ]

页数：

12 页

PDF大小：

570 K

下载PDF手册
CM1213A, SZCM1213A  
1, 2 and 4-Channel  
Low Capacitance  
ESD Protection Arrays  
Product Description  
The CM1213A family of diode arrays has been designed to provide  
ESD protection for electronic components or subsystems requiring  
minimal capacitive loading. These devices are ideal for protecting  
systems with high data and clock rates or for circuits requiring low  
capacitive loading. Each ESD channel consists of a pair of diodes in  
series which steer the positive or negative ESD current pulse to either  
the positive (V ) or negative (V ) supply rail. A Zener diode is  
www.onsemi.com  
SOT23−3  
SO SUFFIX  
CASE 318  
SOT−143  
SR SUFFIX  
CASE 318A  
SC−74  
SO SUFFIX  
CASE 318F  
P
N
embedded between V and V , offering two advantages. First, it  
P
N
protects the V rail against ESD strikes, and second, it eliminates the  
CC  
need for a bypass capacitor that would otherwise be needed for  
absorbing positive ESD strikes to ground. The CM1213A will protect  
against ESD pulses up to 8 kV per the IEC 61000−4−2 standard.  
These devices are particularly well−suited for protecting systems  
MSOP−10  
MR SUFFIX  
CASE 846AE  
SC70−6  
S7 SUFFIX  
CASE 419AD  
®
using high−speed ports such as USB 2.0, IEEE1394 (Firewire ,  
iLinkt), Serial ATA, DVI, HDMI and corresponding ports in  
removable storage, digital camcorders, DVD−RW drives and other  
applications where extremely low loading capacitance with ESD  
protection are required in a small package footprint.  
MARKING DIAGRAM  
XXXMG  
XXXMG  
Features  
G
G
• One, Two, and Four Channels of ESD Protection  
Note: For 6 and 8−channel Devices, See the CM1213 Datasheet  
• Provides ESD Protection to IEC61000−4−2 Level 4  
1
1
XXX  
M
G
= Specific Device Code  
= Date Code  
= Pb−Free Package  
♦
8 kV Contact Discharge  
• Low Channel Input Capacitance of 0.85 pF Typical  
• Minimal Capacitance Change with Temperature and Voltage  
• Channel Input Capacitance Matching of 0.02 pF Typical is Ideal for  
Differential Dignals  
• Each I/O Pin Can Withstand Over 1000 ESD Strikes*  
• SZ Prefix for Automotive and Other Applications Requiring Unique  
Site and Control Change Requirements; AEC−Q101 Qualified and  
PPAP Capable  
(Note: Microdot may be in either location)  
ORDERING INFORMATION  
†
Device  
Package  
Shipping  
CM1213A−01SO,  
SZCM1213A−01SO  
SOT23−3  
(Pb−Free)  
3,000 /  
Tape & Reel  
CM1213A−02SR,  
SZCM1213A−02SR  
SOT143−4  
(Pb−Free)  
3,000 /  
Tape & Reel  
• These Devices are Pb−Free and are RoHS Compliant  
Applications  
CM1213A−02SO  
CM1213A−04S7  
CM1213A−04MR  
SC−74  
(Pb−Free)  
3,000 /  
Tape & Reel  
SC70−6  
(Pb−Free)  
3,000 /  
Tape & Reel  
• USB2.0 Ports at 480 Mbps in Desktop PCs, Notebooks and Peripherals  
®
• IEEE1394 Firewire Ports at 400 Mbps/800 Mbps  
MSOP−10  
(Pb−Free)  
4,000 /  
Tape & Reel  
• DVI Ports, HDMI Ports in Notebooks, Set Top Boxes, Digital TVs,  
LCD Displays  
†For information on tape and reel specifications,  
including part orientation and tape sizes, please  
refer to our Tape and Reel Packaging Specification  
Brochure, BRD8011/D.  
• Serial ATA Ports in Desktop PCs and Hard Disk Drives  
• PCI Express Ports  
• General Purpose High−Speed Data Line ESD Protection  
*Standard test condition is IEC61000−4−2 level 4 test circuit with each pin subjected to 8 kV contact discharge for 1000 pulses. Discharges  
are timed at 1 second intervals and all 1000 strikes are completed in one continuous test run. The part is then subjected to standard production  
test to verify that all of the tested parameters are within spec after the 1000 strikes.  
© Semiconductor Components Industries, LLC, 2011  
1
Publication Order Number:  
October, 2016 − Rev. 11  
CM1213A/D  
CM1213A, SZCM1213A  
BLOCK DIAGRAM  
V
V
V
CH4  
V
V
CH3  
CH2  
P
P
P
CH1  
CH1  
CH2  
V
N
CH1  
CM1213A−04MR  
CM1213A−04S7  
N
N
CM1213A−01SO  
CM1213A−02SR  
CM1213A−02SO  
www.onsemi.com  
2
CM1213A, SZCM1213A  
PACKAGE/PINOUT DIAGRAMS  
Table 1. PIN DESCRIPTIONS  
1−Channel, 3−Lead SOT23−3 Package (CM1213A−01SO)  
Top View  
Pin  
1
Name  
Type  
I/O  
Description  
ESD Channel  
CH1 (1)  
1
CH1  
2
V
PWR  
GND  
Positive Voltage Supply Rail  
Negative Voltage Supply Rail  
3
V (3)  
N
P
3
V
N
V
P
(2)  
2
3−Lead SOT23−3  
2−Channel, 4−Lead SOT143−4 Package (CM1213A−02SR)  
Pin  
1
Name  
Type  
GND  
I/O  
Description  
Negative Voltage Supply Rail  
ESD Channel  
V
N
Top View  
2
CH1  
CH2  
V
N
(1)  
1
4
V (4)  
P
3
I/O  
ESD Channel  
4
V
P
PWR  
Positive Voltage Supply Rail  
CH1 (2)  
2
3
CH2 (3)  
2−Channel, SC−74 Package (CM1213A−02SO)  
4−Lead SOT143−4  
Pin  
1
Name  
NC  
Type  
−
Description  
No Connect  
2
VN  
GND  
I/O  
Negative Voltage Supply Rail  
ESD Channel  
3
CH1  
CH2  
NC  
Top View  
4
I/O  
ESD Channel  
NC (1)  
(2)  
1
2
3
6
5
4
V (6)  
P
5
−
No Connect  
V
NC (5)  
N
6
VP  
PWR  
Positive Voltage Supply Rail  
CH1 (3)  
CH2 (4)  
6−Lead SC−74  
4−Channel, 6−Lead SC70−6 (CM1213A−04S7)  
Pin  
1
Name  
Type  
I/O  
Description  
ESD Channel  
CH1  
2
V
GND  
I/O  
Negative Voltage Supply Rail  
ESD Channel  
N
Top View  
3
CH2  
CH3  
CH1  
1
2
3
6
5
4
CH4  
4
I/O  
ESD Channel  
V
N
V
P
5
V
PWR  
I/O  
Positive Voltage Supply Rail  
ESD Channel  
P
6
CH4  
CH2  
CH3  
6−Lead SC70−6  
4−Channel, 10−Lead MSOP−10 Package (CM1213A04MR)  
Pin  
1
Name  
CH1  
NC  
Type  
I/O  
−
Description  
ESD Channel  
2
No Connect  
Top View  
3
V
PWR  
I/O  
−
Positive Voltage Supply Rail  
ESD Channel  
CH1  
NC  
P
CH2  
NC  
1
2
3
4
5
10  
9
NC  
P
CH4  
4
CH2  
NC  
V
8
V
N
7
6
NC  
CH3  
5
No Connect  
6
CH3  
NC  
I/O  
−
ESD Channel  
10−Lead MSOP−10  
7
No Connect  
8
V
GND  
I/O  
−
Negative Voltage Supply Rail  
ESD Channel  
N
9
CH4  
NC  
10  
No Connect  
www.onsemi.com  
3
CM1213A, SZCM1213A  
SPECIFICATIONS  
Table 2. ABSOLUTE MAXIMUM RATINGS  
Parameter  
Rating  
6.0  
Units  
V
Operating Supply Voltage (V − V )  
P
N
Operating Temperature Range  
–40 to +85  
–65 to +150  
°C  
°C  
V
Storage Temperature Range  
DC Voltage at any channel input  
(V − 0.5) to (V + 0.5)  
N P  
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality  
should not be assumed, damage may occur and reliability may be affected.  
Table 3. STANDARD OPERATING CONDITIONS  
Parameter  
Rating  
Units  
°C  
Operating Temperature Range  
Package Power Rating  
SOT23−3, SOT143−4, SC−74, and SC70−6 Packages  
MSOP−10 Package  
–40 to +85  
mW  
225  
400  
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond  
the Recommended Operating Ranges limits may affect device reliability.  
Table 4. ELECTRICAL OPERATING CHARACTERISTICS (Note1)  
Symbol  
Parameter  
Operating Supply Voltage (V −V )  
Conditions  
Min  
Typ  
Max  
5.5  
Units  
V
V
P
3.3  
P
N
I
Operating Supply Current  
(V −V ) = 3.3 V  
8.0  
mA  
V
P
P
N
V
Diode Forward Voltage  
Top Diode  
Bottom Diode  
I = 8 mA; T = 25°C  
F A  
F
0.60  
0.60  
0.80  
0.80  
0.95  
0.95  
I
Channel Leakage Current  
Channel Input Capacitance  
T = 25°C; V = 5 V, V = 0 V  
0.1  
1.0  
1.2  
mA  
LEAK  
A
P
N
C
At 1 MHz, V = 3.3 V, V = 0 V, V = 1.65 V  
0.85  
pF  
IN  
P
N
IN  
(Note 2)  
Channel Input Capacitance Matching  
At 1 MHz, V = 3.3 V, V = 0 V, V = 1.65 V  
0.02  
pF  
kV  
DC  
P
N
IN  
IN  
(Note 2)  
V
R
ESD Protection − Peak Discharge  
Voltage at any channel input, in system  
Contact discharge per  
ESD  
IEC 61000−4−2 standard  
T = 25°C (Notes 2 and 3)  
A
8
V
Channel Clamp Voltage  
Positive Transients  
Negative Transients  
T = 25°C, I = 1A, t = 8/20 mS  
V
CL  
A
PP  
P
(Note 2)  
+10  
–1.7  
Dynamic Resistance  
Positive Transients  
Negative Transients  
I
= 1A, t = 8/20 mS  
W
DYN  
PP  
P
Any I/O pin to Ground  
(Note 2)  
0.9  
0.5  
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product  
performance may not be indicated by the Electrical Characteristics if operated under different conditions.  
1. All parameters specified at T = –40°C to +85°C unless otherwise noted.  
A
2. Standard IEC 61000−4−2 with C  
= 150 pF, R  
= 330 W, V = 3.3 V, V grounded.  
Discharge  
Discharge P N  
3. These measurements performed with no external capacitor on V (V floating).  
P
P
www.onsemi.com  
4
 
CM1213A, SZCM1213A  
PERFORMANCE INFORMATION  
Input Channel Capacitance Performance Curves  
Figure 1. Typical Variation of CIN vs. VIN  
(f = 1 MHz, VP = 3.3 V, VN = 0 V, 0.1 ꢀF Chip Capacitor between VP and VN, 255C)  
Figure 2. Typical Variation of CIN vs. Temp  
(f = 1 MHz, VIN = 30 mV, VP = 3.3 V, VN = 0 V, 0.1 ꢀ F Chip Capacitor between VP and VN)  
www.onsemi.com  
5
CM1213A, SZCM1213A  
PERFORMANCE INFORMATION (Cont’d)  
Typical Filter Performance (nominal conditions unless specified otherwise, 50 Ohm Environment)  
Figure 3. Insertion Loss (S21) vs. Frequency (0 V DC Bias, VP=3.3 V)  
Figure 4. Insertion Loss (S21) vs. Frequency (2.5 V DC Bias, VP=3.3 V)  
www.onsemi.com  
6
CM1213A, SZCM1213A  
APPLICATION INFORMATION  
Design Considerations  
In order to realize the maximum protection against ESD pulses, care must be taken in the PCB layout to minimize parasitic  
series inductances on the Supply/Ground rails as well as the signal trace segment between the signal input (typically  
a connector) and the ESD protection device. Refer to Application of Positive ESD Pulse between Input Channel and Ground,  
which illustrates an example of a positive ESD pulse striking an input channel. The parasitic series inductance back to the power  
supply is represented by L and L . The voltage V on the line being protected is:  
1
2
CL  
V
CL  
= Fwd Voltage Drop of D + V  
+ L x d(I  
) / dt + L x d(I  
) / dt  
1
SUPPLY  
1
ESD  
2
ESD  
where I  
is the ESD current pulse, and V  
is the positive supply voltage.  
ESD  
SUPPLY  
An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact discharge  
per the IEC61000−4−2 standard results in a current pulse that rises from zero to 30 Amps in 1 ns. Here d(I  
)/dt can be  
ESD  
−9  
approximated by DI  
/Dt, or 30/(1x10 ). So just 10 nH of series inductance (L and L combined) will lead to a 300 V  
ESD  
1
2
increment in V  
!
CL  
Similarly for negative ESD pulses, parasitic series inductance from the V pin to the ground rail will lead to drastically  
N
increased negative voltage on the line being protected.  
The CM1213A has an integrated Zener diode between V and V . This greatly reduces the effect of supply rail inductance  
P
N
L on V by clamping V at the breakdown voltage of the Zener diode. However, for the lowest possible V , especially when  
2
CL  
P
CL  
V is biased at a voltage significantly below the Zener breakdown voltage, it is recommended that a 0.22 mF ceramic chip  
P
capacitor be connected between V and the ground plane.  
P
As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of expected  
electrostatic discharges. The power supply bypass capacitor mentioned above should be as close to the V pin of the Protection  
P
Array as possible, with minimum PCB trace lengths to the power supply, ground planes and between the signal input and the  
ESD device to minimize stray series inductance.  
Additional Information  
See also ON Semiconductor Application Note “Design Considerations for ESD Protection”, in the Applications section.  
L
2
V
CC  
POSITIVE SUPPLY RAIL  
V
P
PATH OF ESD CURRENT PULSE I  
ESO  
LINE BEING  
PROTECTED  
SYSTEM OR  
CIRCUITRY  
BEING  
PROTECTED  
L
1
D
D
1
0.22 mF  
CHANNEL  
INPUT  
ONE  
CHANNEL  
OF  
2
V
CL  
25 A  
CM1213  
0 A  
GROUND RAIL  
V
N
CHASSIS GROUND  
Figure 5. Application of Positive ESD Pulse between Input Channel and Ground  
www.onsemi.com  
7
CM1213A, SZCM1213A  
PACKAGE DIMENSIONS  
SOT−23 (TO−236)  
CASE 318−08  
ISSUE AR  
NOTES:  
D
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.  
2. CONTROLLING DIMENSION: MILLIMETERS.  
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH.  
MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF  
THE BASE MATERIAL.  
0.25  
3
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH,  
PROTRUSIONS, OR GATE BURRS.  
T
H
E
E
1
2
MILLIMETERS  
INCHES  
NOM  
0.039  
0.002  
0.017  
0.006  
0.114  
0.051  
0.075  
0.017  
0.021  
0.094  
−−−  
DIM  
A
A1  
b
c
D
E
e
L
MIN  
0.89  
0.01  
0.37  
0.08  
2.80  
1.20  
1.78  
0.30  
0.35  
2.10  
0_  
NOM  
1.00  
0.06  
0.44  
0.14  
2.90  
1.30  
1.90  
0.43  
0.54  
2.40  
−−−  
MAX  
MIN  
MAX  
0.044  
0.004  
0.020  
0.008  
0.120  
0.055  
0.080  
0.022  
0.027  
0.104  
10 _  
L
1.11  
0.10  
0.50  
0.20  
3.04  
1.40  
2.04  
0.55  
0.69  
2.64  
10 _  
0.035  
0.000  
0.015  
0.003  
0.110  
0.047  
0.070  
0.012  
0.014  
0.083  
0 _  
3X  
b
L1  
VIEW C  
e
TOP VIEW  
L1  
A
H
E
T
c
A1  
SEE VIEW C  
SIDE VIEW  
END VIEW  
RECOMMENDED  
SOLDERING FOOTPRINT*  
3X  
0.90  
2.90  
3X  
0.95  
PITCH  
0.80  
DIMENSIONS: MILLIMETERS  
*For additional information on our Pb−Free strategy and soldering  
details, please download the ON Semiconductor Soldering and  
Mounting Techniques Reference Manual, SOLDERRM/D.  
www.onsemi.com  
8
CM1213A, SZCM1213A  
PACKAGE DIMENSIONS  
SOT−143  
CASE 318A−06  
ISSUE U  
D
e
NOTES:  
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.  
2. CONTROLLING DIMENSION: MILLIMETERS.  
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIM­  
UM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE  
MATERIAL.  
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PRO­  
TRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS,  
AND GATE BURRS SHALL NOT EXCEED 0.25 PER SIDE.  
DIMENSION E1 DOES NOT INCLUDE INTERLEAD FLASH OR  
PROTRUSION. INTERLEAD FLASH AND PROTRUSION SHALL  
NOT EXCEED 0.25 PER SIDE.  
D
E
A
GAUGE  
PLANE  
SEATING  
PLANE  
L
L2  
5. DIMENSIONS D AND E1 ARE DETERMINED AT DATUM H.  
6. DATUMS A AND B ARE DETERMINED AT DATUM H.  
DETAIL A  
E1  
MILLIMETERS  
b1  
e1  
DIM MIN  
MAX  
1.12  
0.15  
0.51  
0.94  
0.20  
3.05  
2.64  
1.40  
3X  
b
B
A
A1  
b
0.80  
0.01  
0.30  
0.76  
0.08  
2.80  
2.10  
1.20  
M
0.20  
C A-B D  
TOP VIEW  
b1  
c
D
H
c
E
c
0.10  
C
E1  
e
1.92 BSC  
0.20 BSC  
0.35 0.70  
0.25 BSC  
A
DETAIL A  
e1  
L
A1  
SEATING  
PLANE  
C
SIDE VIEW  
END VIEW  
L2  
RECOMMENDED  
SOLDERING FOOTPRINT*  
1.92  
4X  
0.75  
2.70  
0.20  
0.96  
3X  
0.54  
DIMENSIONS: MILLIMETERS  
*For additional information on our Pb−Free strategy and soldering  
details, please download the ON Semiconductor Soldering and  
Mounting Techniques Reference Manual, SOLDERRM/D.  
www.onsemi.com  
9
CM1213A, SZCM1213A  
PACKAGE DIMENSIONS  
SC−88 (SC−70 6 Lead), 1.25x2  
CASE 419AD  
ISSUE A  
SYMBOL  
MIN  
NOM  
MAX  
D
0.80  
A
1.10  
e
e
A1  
A2  
0.00  
0.80  
0.10  
1.00  
b
c
0.15  
0.10  
1.80  
1.80  
1.15  
0.30  
0.18  
2.20  
2.40  
1.35  
D
2.00  
2.10  
E1  
E
E
E1  
e
1.25  
0.65 BSC  
0.36  
L
0.26  
0.46  
L1  
L2  
0.42 REF  
0.15 BSC  
TOP VIEW  
0º  
4º  
8º  
θ
10º  
θ1  
q1  
A2  
A1  
A
q
L
b
L1  
q1  
c
L2  
SIDE VIEW  
END VIEW  
Notes:  
(1) All dimensions are in millimeters. Angles in degrees.  
(2) Complies with JEDEC MO-203.  
www.onsemi.com  
10  
CM1213A, SZCM1213A  
PACKAGE DIMENSIONS  
SC−74  
CASE 318F−05  
ISSUE N  
SCALE 2:1  
NOTES:  
1. DIMENSIONING AND TOLERANCING PER  
D
ANSI Y14.5M, 1982.  
2. CONTROLLING DIMENSION: INCH.  
3. MAXIMUM LEAD THICKNESS INCLUDES  
LEAD FINISH THICKNESS. MINIMUM LEAD  
THICKNESS IS THE MINIMUM THICKNESS  
OF BASE MATERIAL.  
4. 318F−01, −02, −03, −04 OBSOLETE. NEW  
STANDARD 318F−05.  
6
5
2
4
E
H
E
1
3
MILLIMETERS  
INCHES  
NOM  
0.039  
0.002  
0.015  
0.007  
0.118  
0.059  
0.037  
0.016  
0.108  
−
DIM  
A
A1  
b
c
D
E
e
L
MIN  
0.90  
0.01  
0.25  
0.10  
2.90  
1.30  
0.85  
0.20  
2.50  
0°  
NOM  
1.00  
0.06  
0.37  
0.18  
3.00  
1.50  
0.95  
0.40  
2.75  
−
MAX  
1.10  
0.10  
0.50  
0.26  
3.10  
1.70  
1.05  
0.60  
3.00  
10°  
MIN  
0.035  
0.001  
0.010  
0.004  
0.114  
0.051  
0.034  
0.008  
0.099  
0°  
MAX  
0.043  
0.004  
0.020  
0.010  
0.122  
0.067  
0.041  
0.024  
0.118  
10°  
b
e
ꢁ
C
A
0.05 (0.002)  
H
E
L
ꢁ
A1  
SOLDERING FOOTPRINT*  
2.4  
0.094  
0.95  
0.037  
1.9  
0.074  
0.95  
0.037  
0.7  
0.028  
1.0  
0.039  
mm  
inches  
ǒ
Ǔ
SCALE 10:1  
*For additional information on our Pb−Free strategy and soldering  
details, please download the ON Semiconductor Soldering and  
Mounting Techniques Reference Manual, SOLDERRM/D.  
www.onsemi.com  
11  
CM1213A, SZCM1213A  
PACKAGE DIMENSIONS  
MSOP 10, 3x3  
CASE 846AE  
ISSUE O  
SYMBOL  
MIN  
NOM  
MAX  
A
A1  
A2  
b
1.10  
0.15  
0.95  
0.27  
0.23  
3.10  
5.05  
3.10  
0.00  
0.75  
0.17  
0.13  
2.90  
4.75  
2.90  
0.05  
0.85  
c
D
3.00  
4.90  
E
E1  
E
E1  
e
3.00  
0.50 BSC  
0.60  
L
0.40  
0.80  
L1  
L2  
θ
0.95 REF  
0.25 BSC  
0º  
8º  
DETAIL A  
TOP VIEW  
D
END VIEW  
A2  
A
c
A1  
e
b
q
SIDE VIEW  
L2  
Notes:  
L
(1) All dimensions are in millimeters. Angles in degrees.  
(2) Complies with JEDEC MO-187.  
L1  
DETAIL A  
FireWire is a registered trademark of Apple Computer, Inc.  
iLink is a trademark of S. J. Electro Systems, Inc.  
ON Semiconductor and  
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ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent  
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.  
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability  
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.  
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,  
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or  
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application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not  
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PUBLICATION ORDERING INFORMATION  
LITERATURE FULFILLMENT:  
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USA/Canada  
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Order Literature: http://www.onsemi.com/orderlit  
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For additional information, please contact your local  
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CM1213A/D  
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