CYPD4255-96BZXI,PDF,CYPD4255-96BZXI PDF资料,Datasheet,下载CYPD4255-96BZXI技术资料

PRELIMINARY

EZ-PD™ CCG4M

USB Type-C Dual Port Controller with

USB 3.1 Gen 1/DP1.2 Mux

General Description

EZ-PD™ CCG4M is a USB Type-C dual port controller that complies with the latest USB Type-C and PD standards. EZ-PD CCG4M

provides a complete dual USB Type-C and USB-Power Delivery port control solution for notebooks and PCs. EZ-PD CCG4M uses

Cypress’s proprietary M0S8 technology with a 32-bit, 48-MHz ARM^®Cortex^®-M0 processor with 128-KB flash and integrates two

complete Type-C Transceivers including the Type-C termination resistors R_Pand R_Das well as a 6:4 mux for USB 3.0 and DisplayPort

signals.

Type-C Support

Applications

■ Two integrated transceivers (baseband PHY)

■ Notebooks and PCs

■ Integrated UFP (R_D) and current sources for DFP (R_P) on both

Type-C ports

Features

32-bit MCU Subsystem

■ Integrated dead battery termination for DRP applications

■ Supports two USB Type-C ports

■ 48-MHz ARM Cortex-M0 CPU

Low-Power Operation

■ 128-KB Flash

■ 2.7-V to 5.5-V operation

■ 8-KB SRAM

■ Integrated VCONN FETs to power EMCA cables

■ In-system reprogrammable

■ Independent supply voltage pin for GPIO that allows 1.71-V to

5.5-V signaling on the I/Os

Integrated Digital Blocks

■ Four integrated timers or counters to meet response times

required by the USB-PD protocol

System-Level ESD on CC Pins

■ ±8-kVContactDischargeand±15-kVAirGapDischargebased

on IEC61000-4-2 level 4C

■ Four run-time serial communication blocks (SCBs) with

reconfigurable I²C, SPI, or UART functionality

Hot Swappable I/Os

Integrated 6:4 Mux

■ Six differential channels to 4 differential channels

■ Port 1 I2C pins and CC1, CC2 pins are hot-swappable

■ Multiplexes USB 3.0 (5 Gbps) and DisplayPort 1.2 (5.4 Gbps)

signals to the USB Type-C connector

Packages

■ 6.0 mm  6.0 mm, 0.5 mm, 96-ball BGA

■ Supports industrial temperature range (–40 °C to +85 °C)

■ With DisplayPort 1.2, AUX signals are multiplexed to SBU pins

Clocks and Oscillators

■ Integrated oscillator eliminating the need for external clock

Cypress Semiconductor Corporation

Document Number: 002-11084 Rev. **

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised February 18, 2016

PRELIMINARY

EZ-PD™ CCG4M

Logic Block Diagram

CCG4M: Single-Chip Type-C Controller

MCU Subsystem

I/O Subsystem

CC_PORT1⁵

Integrated Digital Blocks

4 x TCPWM¹

4 x SCB²

CORTEX-M0

48 MHz

CC_PORT2⁵

(I²C, SPI, UART)

Profiles and

Configurations

2x V_CONN

FETs

(PORT1)

2 x Baseband MAC

2 x Baseband PHY

Integrated R_d³and R_p

4 x 8-bit SAR ADC

Flash

2x V_CONN

FETs

(128KB)

(PORT2)

GPIOs⁶

4

SRAM

(8KB)

Integrated 6:4

Mux for USB 3.0

and DisplayPort

Serial Wire Debug

¹Timer, counter, pulse-width modulation block

²Serial communication block configurable as UART, SPI, or I²C

³Termination resistor denoting a UFP

⁴Current source to indicate a DFP

⁵Configuration Channel

⁶General-purpose input/output

Document Number: 002-11084 Rev. **

Page 2 of 34

PRELIMINARY

EZ-PD™ CCG4M

Contents

Functional Overview ........................................................ 4

CPU and Memory Subsystem..................................... 4

USB-PD Subsystem (SS)............................................ 4

System Resources ...................................................... 5

Peripherals .................................................................. 5

GPIO ........................................................................... 6

Mux.............................................................................. 6

Pinouts .............................................................................. 7

Power............................................................................... 16

Electrical Specifications ................................................ 19

Absolute Maximum Ratings....................................... 19

Device-Level Specifications ...................................... 19

Digital Peripherals ..................................................... 23

Memory ..................................................................... 25

System Resources .................................................... 25

Ordering Information...................................................... 28

Ordering Code Definitions......................................... 28

Packaging........................................................................ 29

Acronyms........................................................................ 31

Document Conventions ................................................. 32

Units of Measure ....................................................... 32

Document History Page................................................. 33

Sales, Solutions, and Legal Information ...................... 34

Worldwide Sales and Design Support....................... 34

Products.................................................................... 34

PSoC® Solutions ...................................................... 34

Cypress Developer Community................................. 34

Technical Support ..................................................... 34

Document Number: 002-11084 Rev. **

Page 3 of 34

PRELIMINARY

EZ-PD™ CCG4M

USB-PD Subsystem (SS)

Functional Overview

CPU and Memory Subsystem

CPU

EZ-PD CCG4M has a USB-PD subsystem consisting of two USB

Type-C baseband transceivers and physical-layer logic. These

transceivers perform the BMC and the 4b/5b encoding and

decoding functions as well as the 1.2-V analog front end. This

subsystem integrates the required termination resistors to

identify the role of the EZ-PD CCG4M solution. R_Dis used to

identify EZ-PD CCG4M as a UFP in a DRP application. When

configured as a DFP, integrated current sources perform the role

of R_Por pull-up resistors. These current sources can be

programmed to indicate the complete range of current capacity

on VBUS defined in the USB Type-C spec. EZ-PD CCG4M

responds to all USB-PD communication.

The Cortex-M0 CPU in EZ-PD CCG4M is part of the 32-bit MCU

subsystem, which is optimized for low-power operation with

extensive clock gating. It mostly uses 16-bit instructions and

executes a subset of the Thumb-2 instruction set. This enables

fully compatible binary upward migration of the code to higher

performance processors such as the Cortex-M3 and M4, thus

enabling upward compatibility. The Cypress implementation

includes a hardware multiplier that provides a 32-bit result in one

cycle. It includes a nested vectored interrupt controller (NVIC)

block with 32 interrupt inputs and also includes a Wakeup

Interrupt Controller (WIC). The WIC can wake the processor up

from the Deep Sleep mode, allowing power to be switched off to

the main processor when the chip is in the Deep Sleep mode.

The Cortex-M0 CPU provides a Non-Maskable Interrupt (NMI)

input, which is made available to the user when it is not in use

for system functions requested by the user.

The USB-PD sub-system contains two 8-bit SAR (Successive

Approximation Register) ADC per port for analog to digital

conversions. The ADC includes a 8-bit DAC and a comparator.

The DAC output forms the positive input of the comparator. The

negative input of the comparator is from a 4-input multiplexer.

The four inputs of the multiplexer are a pair of global analog

multiplex busses an internal bandgap voltage and an internal

voltage proportional to the absolute temperature. All GPIO inputs

can be connected to the global Analog Multiplex Busses through

a switch at each GPIO that can enable that GPIO to be

connected to the mux bus for ADC use. The CC1 and CC2 pins

of both Type-C ports are not available to connect to the mux

busses.

The CPU also includes a serial wire debug (SWD) interface,

which is a 2-wire form of JTAG. The debug configuration used for

EZ-PD CCG4M has four break-point (address) comparators and

two watchpoint (data) comparators.

Flash

The EZ-PD CCG4M device has a flash module with a flash

accelerator, tightly coupled to the CPU to improve average

access times from the flash block. The flash block is designed to

deliver two wait-states (WS) access time at 48 MHz and with

0-WS access time at 16 MHz. The flash accelerator delivers 85%

of single-cycle SRAM access performance on average. Part of

the flash module can be used to emulate EEPROM operation if

required.

SROM

A supervisory ROM that contains boot and configuration routines

is provided.

Document Number: 002-11084 Rev. **

Page 4 of 34

PRELIMINARY

EZ-PD™ CCG4M

Figure 1. USB-PD Subsystem

To/From System Resources

vref

iref

To/ from AHB

From AMUX

2 x 8-bit ADC

per Type-C port

VCONN FET Enable

TxRx Enable

V5V

VCONN

FETs

2 x Digital Baseband PHY

Tx_data

Enable Logic

from AHB

Tx

SRAM

4b5b

Encoder

BMC

Encoder

SOP

Insert

Rp

TX

CC1

RD1

CRC

Rx_data

to AHB

RX

Rx

4b5b

SOP

BMC

SRAM

Decoder

Detect

Decoder

CC2

Ref

DB

Rd

Comp

RD2

Active

Rd

CC control

CC detect

8kV IEC ESD

2 x Analog Baseband PHY

Deep Sleep Reference Enable

Functional, Wakeup Interrupts

Deep Sleep

Vref & Iref Gen

RD1 shorted to CC1 and RD2 shorted to CC2 for DRP applications using

bondwire. For DFP applications, RD1 and RD2 not shorted to CC1 and CC2.

Dead Battery (DB) Rd termination removed after MCU boots up

vref, iref

System Resources

Power System

Peripherals

Serial Communication Blocks (SCB)

The power system is described in detail in the section “Power”

on page 16. It provides assurance that voltage levels are as

required for each respective mode and either delay mode entry

(on power-on reset (POR), for example) until voltage levels are

as required for proper function or generate resets (Brown-Out

Detect (BOD)) or interrupts (Low Voltage Detect (LVD)). EZ-PD

CCG4M can operate from three different power sources over the

range of 2.7 to 5.5 V and has three different power modes,

transitions between which are managed by the power system.

EZ-PD CCG4M provides Sleep and Deep Sleep low-power

modes.

EZ-PD CCG4M has four SCBs, which can be configured to

implement an I²C, SPI, or UART interface. The hardware I²C

blocks implement full multi-master and slave interfaces capable

of multimaster arbitration. In the SPI mode, the SCB blocks can

be configured to act as a master or a slave.

In the I²C mode, the SCB blocks are capable of operating at

speeds up to 1 Mbps (Fast Mode Plus) and have flexible

buffering options to reduce interrupt overhead and latency for the

CPU. These blocks also support I²C that creates a mailbox

address range in the memory of EZ-PD CCG4M and effectively

reduce I²C communication to reading from and writing to an

array in memory. In addition, the blocks support 8-deep FIFOs

for receive and transmit which, by increasing the time given for

the CPU to read data, greatly reduce the need for clock

stretching caused by the CPU not having read data on time.

Clock System

The clock system for EZ-PD CCG4M consists of the Internal

Main Oscillator (IMO) and the Internal Low-power Oscillator

(ILO).

The I²C peripherals are compatible with the I²C Standard-mode,

Fast-mode, and Fast-mode Plus devices as defined in the NXP

I²C-bus specification and user manual (UM10204). The I²C bus

I/Os are implemented with GPIO in open-drain modes.

Document Number: 002-11084 Rev. **

Page 5 of 34

PRELIMINARY

EZ-PD™ CCG4M

The I²C port on SCB2, SCB3, and SCB4 blocks of EZ-PD

❐ Open drain with strong pull-down

CCG4M are not completely compliant with the I²C spec in the

following:

❐ Open drain with strong pull-up

❐ Strong pull-up with strong pull-down

❐ Weak pull-up with weak pull-down

■ The GPIO cells for SCB2, SCB3, and SCB4 I²C port are not

overvoltage-tolerant and, therefore, cannot be hot-swapped or

powered up independently of the rest of the I²C system.

■ Input threshold select (CMOS or LVTTL)

■ Individual control of input and output buffer enabling/disabling

in addition to the drive strength modes

■ Fast-mode Plus has an I_OLspecification of 20 mA at a V_OLof

0.4 V. The GPIO cells can sink a maximum of 8-mA I_OLwith a

V_OLmaximum of 0.6 V.

■ Hold mode for latching previous state (used for retaining I/O

state in Deep Sleep mode)

■ Fast-mode and Fast-mode Plus specify minimum Fall times,

which are not met with the GPIO cell; Slow strong mode can

help meet this spec depending on the bus load.

■ Selectable slew rates for dV/dt related noise control to improve

EMI

During power-on and reset, the I/O pins are forced to the disable

state so as not to crowbar any inputs and/or cause excess

turn-on current. A multiplexing network known as a high-speed

I/O matrix is used to multiplex between various signals that may

connect to an I/O pin.

Timer/Counter/PWM Block (TCPWM)

EZ-PD CCG4M has four TCPWM blocks. Each implements a

16-bit timer, counter, pulse-width modulator (PWM), and

quadrature decoder functionality. The block can be used to

measure the period and pulse width of an input signal (timer),

find the number of times a particular event occurs (counter),

generate PWM signals, or decode quadrature signals.

Mux

EZ-PD CCG4M integrates a 6:4 differential channel mux used

for switching USB 3.0 and/or DP 1.2 signals through the USB

Type-C connector. CCG4M can mux the following signals to the

USB Type-C connector:

GPIO

EZ-PD CCG4M has 30 GPIOs that includes the I²C and SWD

pins, which can also be used as GPIOs. The I²C pins from only

SCB 1 are overvoltage-tolerant. The number of available GPIOs

vary with the part numbers. The GPIO block implements the

following:

■ USB 3.0 signals only

■ One lane of USB 3.0 signals and two lanes of DP 1.2 signals

■ Four lanes of DP 1.2 signals

■ Seven drive strength modes:

❐ Input only

❐ Weak pull-up with strong pull-down

❐ Strong pull-up with weak pull-down

In addition, the AUX signals are also multiplexed to the SBU pins.

The insertion loss is –1.2 dB and the return loss –21 dB at

5-Gbps USB 3.0 speed.

Document Number: 002-11084 Rev. **

Page 6 of 34

PRELIMINARY

EZ-PD™ CCG4M

Pinouts

Table 1. Pinout for CYPD4255-96BZXI

Group

Name

Ball Location

Description

CC1_P1

CC2_P1

CC1_P2

CC2_P2

TX_P

K2

H2

USB PD connector detect/Configuration Channel 1

USB PD connector detect/Configuration Channel 2

USB PD connector detect/Configuration Channel 1

USB PD connector detect/Configuration Channel 2

Differential USB 3.0 transmit signal

Differential USB 3.0 receive signal

Differential transmit signal 1

USB Type-C Port 1

K9

USB Type-C Port 2

K10

L11

K11

H11

G11

A8

TX_M

RX_P

RX_M

TX1_P

TX1_M

RX1_P

RX1_M

TX2_P

TX2_M

RX2_P

RX2_M

AUX_P

AUX_M

DP0_P

DP0_M

DP1_P

DP1_M

DP2_P

DP2_M

DP3_P

DP3_M

SBU1

A7

Differential transmit signal 1

A11

A10

A4

Differential receive signal 1

Differential transmit signal 2

A5

Differential transmit signal 2

A1

Differential receive signal 2

A2

Differential receive signal 2

Mux

F11

E11

C1

Auxiliary signal for DisplayPort

Differential DisplayPort 0 signal

Differential DisplayPort 1 signal

Differential DisplayPort 2 signal

Differential DisplayPort 3 signal

Sideband Use signal

D1

F1

G1

J1

K1

L2

L3

B11

C11

SBU2

Sideband Use signal31

Full rail control I/O for enabling/disabling Provider load FET

of USB Type-C port 1

VBUS_P_CTRL_P1

K3

Full rail control I/O for enabling/disabling Consumer load FET

of USB Type-C port 1 or SCB1 (see Table 3 through Table 6)

VBUS_C_CTRL_P1

VBUS_DISCHARGE_P1

VBUS_P_CTRL_P2

K4

K8

B4

I/O used for discharging VBUS line during voltage change

VBUS Control

Full rail control I/O for enabling/disabling Provider load FET

of USB Type-C port 2

Full rail control I/O for enabling/disabling Consumer load FET

of USB Type-C port 2

VBUS_C_CTRL_P2

B5

B3

L7

VBUS_DISCHARGE_P2

I/O used for discharging VBUS line during voltage change

VCONN_MON_P1/GPIO/

VSEL_1_P1

Monitor VCONN for UVP condition on port 1 or GPIO or

Voltage selection control for VBUS on port 1

VCONN Control

SCB3 (see Table 3 through Table 6) or Monitor VCONN for

UVP condition on port 2 or Voltage selection control for VBUS

on port 2

SCL_3/VCONN_MON_P2/

VSEL_1_P2

L10

Document Number: 002-11084 Rev. **

Page 7 of 34

PRELIMINARY

EZ-PD™ CCG4M

Table 1. Pinout for CYPD4255-96BZXI (continued)

Group

Name

Ball Location

Description

VBUS overvoltage output indicator for port 1 or voltage

selection control for VBUS on port 1 or SCB1 (see Table 3

through Table 6)

OVP_TRIP_P1/

VSEL_2_P1

K5

Overvoltage Protection

(OVP)

VBUS overvoltage output indicator for port 2 or SCB3 (see

Table 3 through Table 6)

OVP_TRIP_P2

L8

VBUS_MON_P1/GPIO

VBUS_MON_P2

L4

B6

VBUS overvoltage protection monitoring signal or GPIO

VBUS overvoltage protection monitoring signal

Hot Plug Detect I/O for port 1 or GPIO

Hot Plug Detect I/O for port 2 or GPIO

Mux control for port 2 or GPIO

HPD_P1/GPIO

K7

HPD_P2/GPIO

E10

B9

GPIO/MUX_CTRL_3_P2

Mux control for port 2 or GPIO or SCB4 (see Table 3 through

Table 6)

GPIO/MUX_CTRL_2_P2

GPIO/MUX_CTRL_1_P2

B8

B7

Mux control for port 2 or GPIO or SCB4 (see Table 3 through

Table 6)

VSEL_2_P2/GPIO

H10

Voltage selection control for VBUS on port 2 or GPIO

GPIOs and Serial

Interfaces

I2C_SCL_SCB1_EC

I2C_SDA_SCB1_EC

L6

SCB1 (see Table 3 through Table 6)

SCB1 (see Table 3 through Table 6) or SCB3 (see Table 3

through Table 6)

K6

I2C_INT_EC

I2C_SCL_SCB2_AR/GPIO

I2C_SDA_SCB2_AR/GPIO

I2C_INT_AR_P1

I2C_INT_AR_P2

SDA_3/GPIO

L5

E2

I2C interrupt line

SCB2 (see Table 3 through Table 6) or GPIO

I2C interrupt line

D2

F2

G2

J10

F10

G10

B2

I2C interrupt line or SCB2 (see Table 3 through Table 6)

SCB3 (see Table 3 through Table 6) or GPIO

SCB4 (see Table 3 through Table 6)

Serial Wire Debug I/O or SCB2 (see Table 3 through Table 6)

SWD Clock or I2C config line

SCL_4

SDA_4

SWD_IO/AR_RST#

SWD_CLK/I2C_CFG_EC

XRES

C2

Reset

H6

Reset input

Document Number: 002-11084 Rev. **

Page 8 of 34

PRELIMINARY

EZ-PD™ CCG4M

Table 1. Pinout for CYPD4255-96BZXI (continued)

Group

Name

VDDM

VDDD

Ball Location

Description

A3

A6

3.0-V to 3.6-V supply for integrated mux

VDDD supply input/output (2.7-V to 5.5-V)

A9

B1

D11

E1

H1

J11

L1

Power

D10

1.8-V regulator output for filter capacitor. This pin cannot drive

external load.

VCCD

B10

VDDIO

V5V_P1

V5V_P2

GND

NC

C10

J2

1.71-V to 5.5-V supply for I/Os

2.7-V to 5.5-V supply for VCONN FET of Type-C port 1

L9

2.7-V to 5.5-V supply for VCONN FET of Type-C port 2

D5

D6

D7

D8

E4

E5

E6

E7

E8

F4

F5

F6

F7

F8

G4

G5

G6

G7

H7

G8

H4

H5

H8

Ground

No connect

Ground

NC

No Connect

NC

Document Number: 002-11084 Rev. **

Page 9 of 34

PRELIMINARY

EZ-PD™ CCG4M

Figure 2. 96-Ball BGA Map for CYPD4255-96BZXI

1

2

3

4

5

6

7

8

9

10

11

A

B

C

D

E

F

RX2_P

RX2_M

VDDM

TX2_P

TX2_M

VDDM

TX1_M

TX1_P

VDDM

RX1_M

RX1_P

SWD_IO/AR VBUS_DISC VBUS_P_C VBUS_C_CT VBUS_MON GPIO/MUX_ GPIO/MUX_ GPIO/MUX_

_RST#

VDDM

DP0_P

DP0_M

VDDM

DP1_P

DP1_M

VDDM

DP2_P

DP2_M

VDDM

VCCD

VDDIO

VDDD

SBU1

SBU2

HARGE_P2

TRL_P2

RL_P2

_P2

CTRL_1_P2 CTRL_2_P2 CTRL_3_P2

SWD_CLK/I2

C_CFG_EC

I2C_SDA_S

CB2_AR/

GPIO

GND

NC

GND

XRES

GND

NC

VDDM

AUX_M

AUX_P

RX_M

RX_P

I2C_SCL_SC

B2_AR/GPIO

HPD_P2/

GPIO

GND

NC

I2C_INT_AR

_P1

SCL_4

SDA_4

I2C_INT_AR

_P2

G

H

J

VSEL_2_P2/

GPIO

CC2_P1

V5V_P1

CC1_P1

DP3_P

NC

SDA_3/GPIO

CC2_P2

VDDM

TX_M

TX_P

OVP_TRIP_

P1/VSEL_2_

P1

VBUS_P_CT VBUS_C_C

RL_P1

I2C_SDA_S

CB1_EC

HPD_P1/

GPIO

VBUS_DISC

HARGE_P1

K

L

CC1_P2

V5V_P2

TRL_P1

VCONN_MO

N_P1/GPIO/

VSEL_1_P1

SCL_3/VCON

N_MON_P2/

VSEL_1_P2

VBUS_MON

_P1/GPIO

I2C_SCL_SC

B1_EC

OVP_TRIP_

P2

DP3_M

I2C_INT_EC

Document Number: 002-11084 Rev. **

Page 10 of 34

PRELIMINARY

EZ-PD™ CCG4M

Table 2. Pinout for CYPD4155-96BZXI

Group

Name

CC1_P1

CC2_P1

TX_P

Ball Location

Description

K2

H2

USB PD connector detect/Configuration Channel 1

USB PD connector detect/Configuration Channel 2

Differential USB 3.0 transmit signal

Differential USB 3.0 receive signal

Differential transmit signal 1

USB Type-C Port 1

L11

K11

H11

G11

A8

TX_M

RX_P

RX_M

TX1_P

TX1_M

RX1_P

RX1_M

TX2_P

TX2_M

RX2_P

RX2_M

AUX_P

AUX_M

DP0_P

DP0_M

DP1_P

DP1_M

DP2_P

DP2_M

DP3_P

DP3_M

SBU1

A7

Differential transmit signal 1

A11

A10

A4

Differential receive signal 1

Differential transmit signal 2

A5

Differential transmit signal 2

A1

Differential receive signal 2

A2

Differential receive signal 2

Mux

F11

E11

C1

Auxiliary signal for DisplayPort

Differential DisplayPort 0 signal

Differential DisplayPort 1 signal

Differential DisplayPort 2 signal

Differential DisplayPort 3 signal

Sideband Use signal

D1

F1

G1

J1

K1

L2

L3

B11

C11

SBU2

Sideband Use signal

Full rail control I/O for enabling/disabling Provider load FET of

USB Type-C port 1

VBUS_P_CTRL_P1

K3

VBUS Control

Full rail control I/O for enabling/disabling Consumer load FET

of USB Type-C port 1 or SCB1 (see Table 3 through Table 6)

VBUS_C_CTRL_P1

K4

K8

L7

VBUS_DISCHARGE_P1

I/O used for discharging VBUS line during voltage change

VCONN_MON_P1/GPIO/V

SEL_1_P1

Monitor VCONN for UVP condition on port 1 or GPIO or Voltage

selection control for VBUS on port 1

VCONN Control

VBUS overvoltage output indicator for port 1 or Voltage

selection control for VBUS on port 1 or SCB1 (see Table 3

through Table 6)

Overvoltage

Protection (OVP)

OVP_TRIP_P1/

VSEL_2_P1

K5

Document Number: 002-11084 Rev. **

Page 11 of 34

PRELIMINARY

EZ-PD™ CCG4M

Table 2. Pinout for CYPD4155-96BZXI (continued)

Group

Name

VBUS_MON_P1/GPIO

HPD_P1/GPIO

SCL_3/GPIO

SDA_3/GPIO

SCL_4

Ball Location

Description

L4

K7

VBUS overvoltage protection monitoring signal or GPIO

Hot Plug Detect I/O for port 1 or GPIO

SCB3 (see Table 3 through Table 6) or GPIO

SCB4 (see Table 3 through Table 6)

L10

J10

F10

G10

L6

SDA_4

SCB4 (see Table 3 through Table 6)

I2C_SCL_SCB1_EC

SCB1 (see Table 3 through Table 6)

SCB1 (see Table 3 through Table 6) or SCB3 (see Table 3

through Table 6)

I2C_SDA_SCB1_EC

K6

L5

E2

I2C_INT_EC

I2C interrupt line

I2C_SCL_SCB2_AR/

GPIO

SCB2 (see Table 3 through Table 6) or GPIO

I2C_SDA_SCB2_AR/

GPIO

D2

SCB2 (see Table 3 through Table 6) or GPIO

GPIOs and Serial

Interfaces

I2C_INT_AR_P1

F2

B3

B4

B5

B6

B7

B8

B9

E10

G2

H10

L8

I2C interrupt line

GPIO

GPIO or SCB4 (see Table 3 through Table 6)

GPIO

GPIO or SCB2 (seeTable 3 through Table 6)

GPIO

GPIO or SCB3 (see Table 3 through Table 6)

Serial Wire Debug I/O or SCB2 (see Table 3 through Table 6)

SWD Clock or I2C config line

Reset input

SWD_IO/AR_RST#

SWD_CLK/I2C_CFG_EC

XRES

B2

C2

H6

A3

A6

A9

B1

D11

E1

H1

J11

L1

Reset

VDDM

3.0-V to 3.6-V supply for integrated mux

VDDD supply input/output (2.7-V to 5.5-V)

VDDM

Power

VDDM

VDDD

D10

1.8-V regulator output for filter capacitor. This pin cannot drive

external load.

VCCD

B10

VDDIO

C10

J2

1.71-V to 5.5-V supply for I/Os

V5V_P1

2.7-V to 5.5-V supply for VCONN FET of Type-C port 1

Document Number: 002-11084 Rev. **

Page 12 of 34

PRELIMINARY

EZ-PD™ CCG4M

Table 2. Pinout for CYPD4155-96BZXI (continued)

Group

Name

GND

NC

Ball Location

Description

D5

D6

D7

D8

E4

E5

E6

E7

E8

F4

F5

F6

F7

F8

G4

G5

G6

G7

H7

G8

H4

H5

H8

K9

K10

L9

Ground

No connect

NC

No Connect

NC

Document Number: 002-11084 Rev. **

Page 13 of 34

PRELIMINARY

EZ-PD™ CCG4M

Figure 3. 96-Ball BGA Ball Map for CYPD4155-96BZXI

1

2

3

4

5

6

7

8

9

10

11

A

B

C

D

E

F

RX2_P

RX2_M

VDDM

TX2_P

TX2_M

VDDM

TX1_M

TX1_P

VDDM

RX1_M

RX1_P

SWD_IO/AR

_RST#

VDDM

DP0_P

DP0_M

VDDM

DP1_P

DP1_M

VDDM

DP2_P

DP2_M

VDDM

GPIO

VCCD

VDDIO

VDDD

GPIO

SBU1

SBU2

SWD_CLK/I

2C_CFG_EC

I2C_SDA_S

CB2_AR/

GPIO

GND

NC

GND

XRES

GND

NC

VDDM

AUX_M

AUX_P

RX_M

RX_P

I2C_SCL_S

CB2_AR/

GPIO

GND

NC

I2C_INT_AR

_P1

SCL_4

SDA_4

GPIO

G

H

J

GPIO

CC2_P1

V5V_P1

CC1_P1

DP3_P

NC

SDA_3/

GPIO

VDDM

TX_M

TX_P

OVP_TRIP_

P1/VSEL_2

_P1

VBUS_DIS

CHARGE_

P1

VBUS_P_C VBUS_C_C

TRL_P1

I2C_SDA_S HPD_P1/

CB1_EC

K

L

NC

TRL_P1

GPIO

VCONN_M

VBUS_MON I2C_INT_ I2C_SCL_S ON_P1/GPI

_P1/GPIO

SCL_3/

GPIO

DP3_M

GPIO

EC

CB1_EC

O/VSEL_1_

P1

Document Number: 002-11084 Rev. **

Page 14 of 34

PRELIMINARY

EZ-PD™ CCG4M

Table 3. Serial Communication Block (SCB1) Configuration

UART

SPI Master

SPI Slave

I2C Master

I2C Slave

K4

UART_TX_SCB1

SPI_MOSI_SCB1

VBUS_C_CTRL_P1

VSEL_2_P1/

VCONN_MON_P1

VSEL_2_P1/

VCONN_MON_P1

K5

UART_RX_SCB1

SPI_CLK_SCB1

L6

K6

UART_RTS_SCB1

UART_CTS_SCB1

SPI_MISO_SCB1

SPI_SEL_SCB1

SPI_MISO_SCB1

SPI_SEL_SCB1

I2C_SDA_SCB1

I2C_SCL_SCB1

I2C_SDA_SCB1

I2C_SCL_SCB1

Table 4. Serial Communication Block (SCB2) Configuration

E2

D2

G2

B2

UART

SPI Master

SPI_CLK_SCB2

SPI_MISO_SCB2

SPI_SEL_SCB2

SPI_MOSI_SCB2

SPI Slave

SPI_CLK_SCB2

SPI_MISO_SCB2

SPI_SEL_SCB2

SPI_MOSI_SCB2

I2C Master

I2C_SCL_SCB2

I2C_SDA_SCB2

GPIO

I2C Slave

I2C_SCL_SCB2

I2C_SDA_SCB2

GPIO

UART_TX_SCB2

UART_RX_SCB2

UART_RTS_SCB2

UART_CTS_SCB2

SWD_IO

Table 5. Serial Communication Block (SCB3) Configuration

J10

L10

K6

UART

SPI Master

SPI_MISO_SCB3

SPI_MOSI_SCB3

SPI_SEL_SCB3

SPI_CLK_SCB3

SPI Slave

SPI_MISO_SCB2

SPI_MOSI_SCB3

SPI_SEL_SCB3

SPI_CLK_SCB3

I2C Master

I2C_SDA_SCB3

I2C_SCL_SCB3

I2C_SCL_SCB1

AR_RST#

I2C Slave

I2C_SDA_SCB3

I2C_SCL_SCB3

I2C_SCL_SCB1

AR_RST#

UART_TX_SCB3

UART_RX_SCB3

UART_RTS_SCB3

UART_CTS_SCB3

L8

Table 6. Serial Communication Block (SCB4) Configuration

G10

F10

B7

UART

SPI Master

SPI_MOSI_SCB4

SPI_MISO_SCB4

SPI_SEL_SCB4

SPI_CLK_SCB4

SPI Slave

SPI_MOSI_SCB4

SPI_MISO_SCB4

SPI_SEL_SCB4

SPI_CLK_SCB4

I2C Master

I2C_SDA_SCB4

I2C_SCL_SCB4

GPIO

I2C Slave

I2C_SDA_SCB4

I2C_SCL_SCB4

GPIO

UART_TX_SCB4

UART_RX_SCB4

UART_RTS_SCB4

UART_CTS_SCB4

B8

GPIO

Document Number: 002-11084 Rev. **

Page 15 of 34

PRELIMINARY

EZ-PD™ CCG4M

Power

The following power system diagram shows the set of power

supply pins as implemented in EZ-PD CCG4M.

The VCCD output of EZ-PD CCG4M must be bypassed to

ground via an external capacitor (in the range of 1 to 1.6 µF; X5R

ceramic or better).

CCG4M shall be able to operate from three possible external

supply sources: V5V_P1 for first Type-C port, V5V_P2 for

second Type- C port and VDDD.

Bypass capacitors must be used from VDDD and V5V_P1 or

V5V_P2 pins to ground; typical practice for systems in this

frequency range is to use a 0.1-µF capacitor on VDDD, V5V_P1

and V5V_P2. Note that these are simply rules of thumb and that

for critical applications, the PCB layout, lead inductance, and the

bypass capacitor parasitic should be simulated to design and

obtain optimal bypassing.

CCG4M has the power supply input V5V_P1 and V5V_P2 pins

for providing power to EMCA cables through integrated VCONN

FETs. There are two VCONN FETs in CCG4M per Type-C port

to power either CC1 or CC2 pin. These FETs are capable of

providing a minimum of 1W on the CC1 and CC2 pins for the

EMCA cables. In USB-PD applications, the valid levels on

V5V_P1 and V5V_P2 supplies can range from 4.85 – 5.5 V.

Figure 4 shows an example of the power supply bypass

capacitors.

The chip’s internal operating power supply is derived from

VDDD. In UFP mode, CCG4M operates in 2.7 – 5.5V. In DFP

and DRP modes, it operates at 3.0 – 5.5V range.

A separate I/O supply pin, VDDIO, allows the GPIOs to operate

at levels from 1.71 to 5.5 V. The VDDIO pin can be equal to or

less than the voltages connected to the V5V_P1 or V5V_P2 and

VDDD pins.

Figure 4. EZ-PD CCG4M Power and Bypass Scheme Example

[3]

[2]

CC1_P2

CC2_P2

[1]

V5V_P2

CC1_P1

CC2_P1

VDDD

V5V_P1

Core Regulator

(SRSS-Lite)

VDDIO

VCCD

VSS

2 x CC

Tx/Rx

GPIOs

Core

Note

1. V5V_P1 denoted power supply input for Type-C port 1

V5V_P2 denoted power supply input for Type-C port 2

2. CC1_1:USB PD connector detect/Configuration Channel 1 for Type-C port 1

CC1_2:USB PD connector detect/Configuration Channel 1 for Type-C port 2

3. CC2_1:USB PD connector detect/Configuration Channel 2 for Type-C port 1

CC2_2:USB PD connector detect/Configuration Channel 2 for Type-C port 2

Document Number: 002-11084 Rev. **

Page 16 of 34

PRELIMINARY

EZ-PD™ CCG4M

Figure 5. Dual Port Notebook Application Using CCG4M (CYD4255-96BZXI)

VBUS_SINK

100 KO

10 O

VBUS_C_CTRL_P1

100 KO

VBUS_SOURCE

VBUS_1

49.9KO

100 KO

10

O

VBUS_P_CTRL_P1

100 KO

3.3V

5.0V

10O

1µF

VBUS_DISCHARGE_P1 10

100 KO

O

0.1µF

B2 SWD_IO/

AR_RST#/GPIO

SWD_CLK/I2C_CFG_EC/

GPIO

C2

1µF

0.1µF

VDDM

2

A3, A6, A9,

B1, D11, E1,

H1, J11, L1

HS

L11

K11

RX

+

TX +

TX -

RX -

USB 3.0 HOST

SSTX/RX

H11

G11

K4

K3

TX +

TX -

RX +

RX -

VBUS_C_CTRL_P1

VBUS_P_CTRL_P1

HS

K8

2

VBUS_DISCHARGE_P1

2

C1

D1

DP0

DP0 -

+

DP0

+

-

VBUS

A8

A7

TX1 +

TX1 -

TX1 +

TX1 -

F1

DP1

+

-

DP1

DP1 -

+

A4

A5

G1

TX2 +

TX2 -

TX2 +

TX2 -

J1

A11

A10

DP2

+

-

DP2

+

-

RX1 +

RX1 -

RX1 +

RX1 -

DISPLAY PORT

SOURCE

K1

A1

A2

CCG4M

(CYPD4255-96BZXI)

RX2 +

RX2 -

RX2 +

RX2 -

L2

L3

DP3

DP3 -

+

DP3

DP3 -

+

B11

C11

SBU1

SBU2

SBU1

SBU2

F11

E11

AUX

AUX -

+

AUX +

AUX -

TYPE-C

RECEPTACLE 1

HPD_P1

HPD_P2

VBUS_1

11 KO

K7

HPD

HPD_P1/GPIO

E10

TO DISPLAY PORT

CONTROLLER 2

HPD_P2/GPIO

L4

VBUS_MON_P1/GPIO

VSEL_1_P1/

VCONN_MON_P1/GPIO

0.1µF

L7

K5

1

KO

H2

K2

VSEL_2_P1/

OVP_TRIP_P1

CC2

CC2_P1

CC1_P1

H10

CC1

VSEL_2_P2/GPIO

VDDIO

390pF

POWER

SUB-SYSTEM

390pF

H4, H5,

H8, G8

NC

4.7 KO

0.1µF

H6

L8

L5

VBUS_2

XRES

GND

11 KO

2.2 KO

OVP_TRIP_P2

B6

B9

2.2 KO

VBUS_MON_P2

2.2 KO

0.1µF

1

KO

EMBEDDED

CONTROLLER

I2C_INT_EC

MUX_CTRL_3_P2/GPIO

MUX_CTRL_2_P2/GPIO

GND

L6

K6

I2C_SCL_SCB1_EC

I2C_SDA_SCB1_EC

B8

B7

E2

D2

MUX_CTRL_1_P2/GPIO

GND

I2C_SCL_SCB2_AR/GPIO

D5, D6, D7, D8, E4, E5, E6, E7, E8,

F4, F5, F6, F7, F8, G4, G5, G6, G7, H7

I2C_SDA_SCB2_AR/GPIO

I2C_INT_AR_P1/GPIO

I2C_INT_AR_P2/GPIO

F2

G2

VDDIO

2.2 KO 2.2 KO

L10

VSEL_1_P2/SCL_3/VCONN_MON_P2/GPIO

K10

K9

CC2_P2

CC1_P2

CC2

CC1

J10

F10

SDA_3/GPIO

SCL_4

I2C_SCL

I2C_SDA

TYPE-C

RECEPTACLE 2

G10

B5

390pF

SDA_4

VBUS_C_CTRL_P2

VBUS_DISCHARGE_P2

B3

VBUS_P_CTRL_P2

B4

VBUS_SINK

VBUS

100 KO

2

100 KO

2

100 KO

O

10

VBUS_C_CTRL_P2

100 KO

VBUS_2

VBUS_SOURCE

49.9KO

100 KO

10

O

VBUS_P_CTRL_P2

100 KO

10

O

10

O

VBUS_DISCHARGE_P2

100 KO

2

4

HS

USB 3.0

HOST

SSTX/RX

TX

4

HPD_P2

RX

MUX

4

2

ML_LANE_[0:3]N

SBU

2

ML_LANE_[0:3]P

AUX P/N

DISPLAY PORT

CONTROLLER 2

HPD_P2

I2C_SCL I2C_SDA

Document Number: 002-11084 Rev. **

Page 17 of 34

PRELIMINARY

EZ-PD™ CCG4M

Figure 6. Single Port Notebook Application Using CCG4M (CYD4155-96BZXI)

VBUS_SINK

100 KO

10 O

VBUS_C_CTRL_P1

100 KO

VBUS_SOURCE

VBUS

49.9KO

100 KO

10 O

VBUS_P_CTRL_P1

100 KO

5.0V

3.3V

10 O

10O

1µF

VBUS_DISCHARGE_P1 10 O

100 KO

1µF

0.1µF

B2 SWD_IO/

AR_RST#/GPIO

1µF

A3, A6, A9,

B1, D11, E1,

H1, J11, L1

0.1µF

SWD_CLK/I2C_CFG_EC/

GPIO

C2

VDDM

2

HS

L11

K11

RX

+

TX +

TX -

RX -

USB 3.0 HOST

SSTX/RX

K4

H11

G11

TX +

TX -

RX +

RX -

VBUS_C_CTRL_P1

VBUS_P_CTRL_P1

K3

K8

HS

VBUS_DISCHARGE_P1

2

C1

D1

DP0 +

DP0 -

DP0 +

DP0 -

VBUS

A8

TX1 +

TX1 -

TX1 +

TX1 -

A7

F1

DP1 +

DP1 -

DP1 +

DP1 -

A4

A5

G1

TX2 +

TX2 -

TX2 +

TX2 -

J1

A11

A10

DP2 +

DP2 -

DP2 +

DP2 -

RX1 +

RX1 -

RX1 +

RX1 -

DISPLAY PORT

SOURCE

K1

A1

A2

CCG4M

(CYPD4155-96BZXI)

RX2 +

RX2 -

RX2 +

RX2 -

L2

L3

DP3 +

DP3 -

DP3 +

DP3 -

B11

C11

SBU1

SBU2

SBU1

SBU2

F11

E11

AUX

+

AUX +

AUX -

VBUS

HPD_P1

K7

TYPE-C

HPD

HPD_P1/GPIO

RECEPTACLE 1

11 KO

E10

GPIO

L4

VBUS_MON_P1/GPIO

VSEL_1_P1/

VCONN_MON_P1/GPIO

0.1µF

L7

1 KO

H2

K2

K5

VSEL_2_P1/

OVP_TRIP_P1

CC2

CC1

CC2_P1

CC1_P1

H10

GPIO

VDDIO

4.7 KO

0.1µF

2.2 KO

VDDIO

390pF

POWER

SUB-SYSTEM

390pF

H6

L8

L5

XRES

GPIO

GND

2.2 KO

EMBEDDED

CONTROLLER

I2C_INT_EC

B9

GPIO

L6

I2C_SCL_SCB1_EC

I2C_SDA_SCB1_EC

B8

B7

B5

K6

E2

D2

GPIO

I2C_SCL_SCB2_AR/GPIO

I2C_SDA_SCB2_AR/GPIO

I2C_INT_AR_P1/GPIO

GPIO

F2

B4

B3

B6

GPIO

G2

VDDIO

2.2 KO 2.2 KO

L10

SCL_3/GPIO

GPIO

J10

F10

SDA_3/GPIO

SCL_4

I2C_SCL

I2C_SDA

G10

SDA_4

GND

D5, D6, D7, D8, E4, E5, E6, E7, E8, F4,

F5, F6, F7, F8, G4, G5, G6, G7, H7

NC

H4, H5,

H8, G8,

K9, K10

Document Number: 002-11084 Rev. **

Page 18 of 34

PRELIMINARY

EZ-PD™ CCG4M

Electrical Specifications

Absolute Maximum Ratings

Table 7. Absolute Maximum Ratings^[4]

Parameter

V_{DDD_MAX}

Description

Min

Typ

Max

Units

Details/Conditions

Digital supply relative to V_SS

Mux supply relative to V_SS

Max supply voltage relative to V_SS

Mux USB/DP signal voltage

Mux AUX signal voltage

–0.5

–0.3

–

6

V

Absolute max

Absolute Max

Absolute max

V_{DDM_MAX}

V5V_P1

4.3

6

V

V5V_P2

–

6

V

V_{DDIO_MAX}

V_{MUX_ABS}

V_{AUX_ABS}

V_{GPIO_ABS}

I_{GPIO_ABS}

–

6

1.2

V

– 0.3

– 0.35

–0.5

–25

V

V_DDM

V_DDIO+ 0.5

25

V

GPIO voltage

V

Maximum current per GPIO

mA

GPIO injection current, Max for V_IH

> V_DDD, and Min for V_IL< V_SS

Absolute max, current

injected per pin

I_{GPIO_injection}

ESD_HBM

–0.5

–

0.5

–

mA

V

Electrostatic discharge human

body model

2200

–

Electrostatic discharge charged

device model

ESD_CDM

LU

500

–200

8000

–

200

–

V

mA

V

–

Pin current for latch-up

Electrostatic discharge

IEC61000-4-2

Contact discharge on

CC1, CC2 pins

ESD_IEC_CON

Electrostatic discharge

IEC61000-4-2

Air discharge for pins

CC1, CC2

ESD_IEC_AIR

15000

–

V

Device-Level Specifications

All specifications are valid for –40 °C  TA  85 °C and TJ  100 °C, except where noted. Specifications are valid for 3.0 V to 5.5 V,

except where noted.

Table 8. DC Specifications

Spec ID

Parameter

Description

Min

2.7

3.0

Typ

–

Max

5.5

Units

Details/Conditions

UFP Applications

SID.PWR#1

V_DDD

Power supply input voltage

V

SID.PWR#1_A V_DDD

–

5.5

DFP/DRP Applications

V5V_P1,

V5V_P2

SID.PWR#26

SID.VDDM

Power supply input voltage

4.85

3.0

–

5.5

3.6

V

–

Mux power supply input

voltage

V_DDM

3.3

SID.IDDM

PWR#13

I_DDM

V_DDMcurrent supply

–

1.71

–

300

–

350

5.5

–

µA

V

V_DDIO

V_CCD

GPIO power supply

–

SID.PWR#24

Output voltage (for core logic)

1.8

V

External regulator voltage

bypass on V_CCD

SID.PWR#15

SID.PWR#16

Note

C_EFC

C_EXC

80

100

1

120

–

nF

X5R ceramic or better

Power supply decoupling

capacitor on V_DDD

0.8

µF

4. Usage above the absolute maximum conditions listed in Table 7 may cause permanent damage to the device. Exposure to absolute maximum conditions for extended

periods of time may affect device reliability. The maximum storage temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature

Storage Life. When used below absolute maximum conditions but above normal operating conditions, the device may not operate to specification.

Document Number: 002-11084 Rev. **

Page 19 of 34

PRELIMINARY

EZ-PD™ CCG4M

Table 8. DC Specifications (continued)

Spec ID

Parameter

Description

Min

Typ

Max

Units

Details/Conditions

Power Supply Decoupling

Capacitor on V5V_P1 and

V5V_P2

SID.PWR#27

C_EXV

–

0.1

–

µF

X5R ceramic or better

Active Mode, V_DDD= 2.7 to 5.5 V. Typical values measured at V_DD= 3.3 V.

V5V_P1 and V5V_P2 = 5 V,

T_A= 25 °C,

CC I/O IN Transmit or Receive,

no I/O sourcing current, CPU at

24 MHz, two PD ports active

SID.PWR#4

I_DD12

Supply current

–

10

–

mA

Sleep Mode, V_DDD= 2.7 to 5.5 V

I²C wakeup

SID25A

V_DDD= 3.3 V, T_A= 25 °C, all

blocks except CPU are ON, CC

I/O ON, no I/O sourcing current

I_DD20A

WDT ON

IMO at 48 MHz

–

2.5

4.0

Deep Sleep Mode, V_DDD= 2.7 to 3.6 V (Regulator on)

V_DDD= 2.7 to 3.6 V

SID34

I_DD29

–

360

–

µA

V_DDD= 3.3 V, T_A= 25 °C

I²C wakeup and WDT ON

Power source = V_DDD, Type-C

not attached, CC enabled for

wakeup, R_Pdisabled

V_DDD= 2.7 to 3.6 V

CC wakeup ON

SID_DS

I_{DD_DS}

32.5

Power source = V_DDD, Type-C

not attached, CC enabled for

wakeup, R_Pand R_Dconnected at

70 ms intervals by CPU. R_P, R_D

connection should be enabled for

both PD ports.

V_DDD= 2.7 to 3.6 V

CC wakeup ON

SID_DS1

I_{DD_DS1}

–

130

–

µA

XRES Current

Supply current while XRES

asserted

SID307

I_{DD_XR}

1

10

µA

–

Table 9. AC Specifications

Spec ID

SID.CLK#4

SID.PWR#20

Parameter

F_CPU

Description

CPU frequency

Min

DC

–

Typ

–

Max

Units

Details/Conditions

48

–

MHz 3.0 V V_DDD5.5 V

T_SLEEP

Wakeup from sleep mode

0

µs

ms

Guaranteed by characterization

Wakeup from Deep Sleep

mode

24-MHz IMO. Guaranteed by

characterization.

SID.PWR#21

SID.XRES#5

SYS.FES#1

T_DEEPSLEEP

T_XRES

–

5

–

5

35

–

External reset pulse width

Guaranteed by characterization

Power-up to “Ready to accept

I2C / CC command”

T_{_PWR_RDY}

25

Guaranteed by characterization

Document Number: 002-11084 Rev. **

Page 20 of 34

PRELIMINARY

EZ-PD™ CCG4M

MUX

Table 10. Mux Specifications

Spec ID

Parameter

Min

Typ

Max

Units

Details/Conditions

V_IOM= GND

f = 1 MHz

C_OFF

C_ON

C_OFF

C_ON

USB 3.0/DP switch OFF capacitance

USB 3.0/DP switch ON capacitance

AUX+/AUX– switch OFF capacitance

AUX+/AUX– switch ON capacitance

–

1.2

–

pF

V_IOM= GND

f = 1 MHz

–

2.3

4.0

7.0

–

pF

V_IOM= GND

f = 1 MHz

V_IOM= GND

f = 1 MHz

V

_DDM= 3.6 V

_IOM(USB 3.0) = 0 V

_IOM(DP) = 0 V

I/O leakage for TX_to_TX1/TX2,

RX_toRX1/RX2, DPx_to_TX/RX (x =

0,1, 2, 3), AUX_to_SBUy (y = 1, 2)

I_OZL

–

1

5

µA



V_IOM(AUX) = 0 V

_DDM= 3.6 V

V_IOM(USB 3.0) = 1.2 V

V

I/O leakage for TX_to_TX1/TX2,

RX_toRX1/RX2, DPx_to_TX/RX

(x = 0,1, 2, 3), AUX_to_SBUy (y = 1, 2)

I_OZH

15

V

_IOM(DP) = 1.2 V

_IOM(AUX) = 4.0 V

V

_DDM= min, I_ON= –40 mA

_IN= 0 V

_IN= 1.2 V

Switch on resistance USB 3.0/DP

AUX Switch

7.0

9.0

10.0

12.0

R_ON

V_DDM= min, I_IN= –40 mA



V_IN= 0 V

3.5

4.5

5.0

7.0

V_IN= 3.0 V

Linear region for analog switch

V_DDM= 3.3 V

_PASS= 10 mA

VP_IO

TX_to_TX1/TX2, RX_to_RX1/RX2,

DPx_to_TX/RX (x = 0, 1, 2, 3)

1.4

4.0

1.6

4.2

–

V

I

Linear region for analog switch

AUX_to_SBUx (x = 1, 2)

V_DDM= 3.3 V

I_PASS= 10 mA

VP_IOSB

Table 11. Dynamic Mux Characteristics

Min and max apply for T_Abetween –40 °C to 85 °C. Typical values are referenced to T_A= 25 °C.

Spec ID

Parameter

Min

Typ

Max

Units

Details/Conditions

Supply voltage valid or the device is

powered up and the channel is turned

on to its specified characteristics

tstartup

Startup time

–

10

20

µs

V_DDM= 3 V

Propagation delay 1

Propagation delay 2

–

80

–

ps

From input port to output port USB/DP

From input port to output port AUX

tpd

tsk

150

From input port to output USB/DP. Bit

to bit skew

Skew time 1

Skew time 2

–

10

20

–

ps

From input port to output AUX. Bit to

bit skew

VI_sub_dp

VI_aux

USB/DP input signal

–0.3

–

1.2

V

USB/DP switch analog signal

AUX switch analog signal

AUX+/AUX– input signal

–0.35

V_DDM

Document Number: 002-11084 Rev. **

Page 21 of 34

PRELIMINARY

EZ-PD™ CCG4M

Table 12. Mux Switch AC Electrical Characteristics

Min and max apply for T_Abetween –40 °C to 85 °C and T_Jup to +125 °C (unless otherwise noted). Typical values are referenced to

T_A= 25 °C, V_DDM= 3.3 V.

Details/

Spec ID

BW_usb

Parameter

Frequency

Min

Typ

Max

Units

Conditions

–3 dB bandwidth of USB 3.0

Differential insertion loss

Differential return loss

–

6

–

GHz

dB

I_L

2.5/2.7 GHz

–1.2/–1.3

–21/–20

–38/–37

–25/–24

–23/–22

Vcom = 0 V

R_L

2.5/2.7 GHz

dB

Vcom = 0 V

USB

DP

dB

Xtalk

Differential crosstalk

Off isolation

dB

Xoff

–

dB

I/O

Table 13. I/O DC Specifications

Spec ID

SID.GIO#37

SID.GIO#38

SID.GIO#39

SID.GIO#40

SID.GIO#41

SID.GIO#42

SID.GIO#33

SID.GIO#34

SID.GIO#35

SID.GIO#36

SID.GIO#5

SID.GIO#6

Parameter

Description

Min

Typ

Max

Units

V

Details/Conditions

CMOS input

[5]

V_IH

Input voltage HIGH threshold 0.7 × V_DDIO

–

V_IL

V_IH

V_IL

V_IH

V_IL

Input voltage LOW threshold

LVTTL input, V_DDIO< 2.7 V

LVTTL input, V_DDIO 2.7 V

Output voltage HIGH level

Output voltage LOW level

Pull-up resistor

–

0.3 × V_DDIO

V

[5]

0.7× V_DDIO

–

V

–

0.3 × V_DDIO

V

2.0

–

V

–

0.8

–

V

V_OH

V_DDIO–0.6

–

V

I_OH= 4 mA at 3-V V_DDIO

V_OH

V_DDIO–0.5

–

V

I_OH= 1 mA at 1.8-V V_DDIO

V_OL

–

0.6

8.5

V

I_OL= 4 mA at 1.8-V V_DDIO

V_OL

–

V

I_OL= 8 mA at 3 V V_DDIO

R_PULLUP

3.5

5.6

kΩ

–

R_PULLDOWNPull-down resistor

Input leakage current

(absolute value)

SID.GIO#16

SID.GIO#17

SID.GIO#43

I_IL

–

2

7

–

nA 25 °C, V_DDIO= 3.0 V

C_IN

Input capacitance

pF

–

V_DDIO 2.7 V. Guaranteed

by characterization.

V_HYSTTL

Input hysteresis LVTTL

25

40

mV

Guaranteed by

characterization

SID.GPIO#44 V_HYSCMOS

Input hysteresis CMOS

0.05 × V_DDIO

–

mV

µA

Current through protection

diode to V_DDIO/Vss

Guaranteed by

characterization

SID69

I_DIODE

–

100

200

Maximum total source or sink

chip current

Guaranteed by

characterization

SID.GIO#45

I_{TOT_GPIO}

mA

Table 14. I/O AC Specifications

(Guaranteed by Characterization)

Spec ID

SID70

Parameter

T_RISEF

Description

Min

2

Typ Max Units

Details/Conditions

Rise time

Fall time

–

12

ns 3.3-V V_DDIO, Cload = 25 pF

SID71

T_FALLF

2

Note

5.

V

must not exceed V

+ 0.2 V.

IH

DDIO

Document Number: 002-11084 Rev. **

Page 22 of 34

PRELIMINARY

EZ-PD™ CCG4M

XRES

Table 15. XRES DC Specifications

Spec ID

SID.XRES#1

SID.XRES#2

SID.XRES#3

Parameter

V_IH

Description

Min

Typ

Max

Units

V

Details/Conditions

CMOS input

–

Input voltage HIGH threshold 0.7 × V_DDIO

–

V_IL

Input voltage LOW threshold

Input capacitance

–

0.3 × V_DDIO

7

V

C_IN

pF

Guaranteed by

characterization

SID.XRES#4

V_HYSXRES

Input voltage hysteresis

–

0.05 × V_DDIOmV

Digital Peripherals

The following specifications apply to the Timer/Counter/PWM peripherals in the Timer mode.

Pulse Width Modulation (PWM) for GPIO Pins

Table 16. PWM AC Specifications

(Guaranteed by Characterization)

Spec ID

SID.TCPWM.3

SID.TCPWM.4

Parameter

Description

Min Typ Max Units

Details/Conditions

T_CPWMFREQOperating frequency

–

Fc

–

MHz Fc max = CLK_SYS. Maximum = 48 MHz

ns For all trigger events

T_PWMENEXTInput trigger pulse width

2/Fc

Minimum possible width of Overflow,

ns Underflow, and CC (Counter equals

Compare value) outputs

SID.TCPWM.5

T_PWMEXT

Output trigger pulse width

–

2/Fc

–

Minimum time between successive

counts

SID.TCPWM.5A T_CRES

SID.TCPWM.5B PWM_RES

SID.TCPWM.5C Q_RES

Resolution of counter

PWM resolution

–

1/Fc

–

ns

ns Minimum pulse width of PWM output

Minimum pulse width between

quadrature-phase inputs

Quadrature inputs resolution

ns

I²C

Table 17. Fixed I²C DC Specifications

(Guaranteed by Characterization)

Spec ID

SID149

Parameter

I_I2C1

Description

Min Typ Max Units

Details/Conditions

Block current consumption at 100 kbps

Block current consumption at 400 kbps

Block current consumption at 1 Mbps

I²C enabled in Deep Sleep mode

–

60

µA

–

SID150

SID151

SID152

I_I2C2

I_I2C3

I_I2C4

185

390

1.4

Table 18. Fixed I²C AC Specifications

(Guaranteed by Characterization)

Spec ID

SID153

Parameter

F_I2C1

Description

Min

Typ Max Units

Mbps

Details/Conditions

Bit rate

–

1

–

Table 19. Fixed UART DC Specifications

(Guaranteed by Characterization)

Spec ID

Parameter

Description

Min Typ

Max Units

Details/Conditions

Block current consumption at

100 Kbit/sec

SID160

I_UART1

–

125

312

µA

–

Block current consumption at

1000 Kbit/sec

SID161

I_UART2

–

Document Number: 002-11084 Rev. **

Page 23 of 34

PRELIMINARY

EZ-PD™ CCG4M

Table 20. Fixed UART AC Specifications

(Guaranteed by Characterization)

Spec ID

Parameter

Description

Bit rate

Min

Typ

Max Units

Mbps

Details/Conditions

SID162

F_UART

–

1

–

Table 21. Fixed SPI DC Specifications

(Guaranteed by Characterization)

Spec ID

Parameter

Description

Min

Typ

Max

Units

Details/Conditions

Block current consumption

at 1 Mbit/sec

SID163

I_SPI1

–

360

µA

–

Block current consumption

at 4 Mbit/sec

SID164

SID165

I_SPI2

I_SPI3

–

560

600

–

Block current consumption

at 8 Mbit/sec

Table 22. Fixed SPI AC Specifications

(Guaranteed by Characterization)

Spec ID

Parameter

Description

Min

Typ

Max

Units

Details/Conditions

SPI Operating frequency

(Master; 6X oversampling)

SID166

F_SPI

–

8

MHz

–

Table 23. Fixed SPI Master Mode AC Specifications

(Guaranteed by Characterization)

Spec ID

Parameter

Description

Min

Typ

Max

Units

Details / Conditions

MOSI Valid after SClock

driving edge

SID167

T_DMO

–

15

ns

–

MISO Valid before SClock

capturing edge

Full clock, late MISO

sampling

SID168

SID169

T_DSI

20

0

–

ns

Previous MOSI data hold

time

Referred to Slave capturing

edge

T_HMO

Table 24. Fixed SPI Slave Mode AC Specifications

(Guaranteed by Characterization)

Spec ID Parameter

Description

Min

Typ

Max

Units

Details / Conditions

MOSI Valid before Sclock

capturing edge

SID170

SID171

T_DMI

T_DSO

T_{DSO_EXT}

40

–

ns

–

MISO Valid after Sclock

driving edge

–

48 + 3 * T_SCB

T_SCB= T_CPU= 1/24 MHz

MISO Valid after Sclock

driving edge in Ext Clk mode

SID171A

SID172

48

–

Previous MISO data hold

time

T_HSO

0

SSEL Valid to first SCK valid

edge

SID172A

T_SSELSCK

100

–

Document Number: 002-11084 Rev. **

Page 24 of 34

PRELIMINARY

EZ-PD™ CCG4M

Memory

Table 25. Flash AC Specifications

Spec ID

Parameter

Description

Min

Typ

Max

Units

Details/Conditions

Row (block) write time (erase and

program)

[6]

SID.MEM#4 T_ROWWRITE

–

20

ms

–

[6]

SID.MEM#3 T_ROWERASE

Row erase time

–

13

7

ms

–

[6]

SID.MEM#8 T_ROWPROGRAM

Row program time after erase

Bulk erase time (128 KB)

[6]

SID178

T_BULKERASE

35

Guaranteed by

characterization

[6]

SID180

T_DEVPROG

Total device program time

Flash endurance

–

100 K

20

–

25

–

seconds

cycles

years

Guaranteed by

characterization

SID.MEM#6 F_END

Flash retention. T_A 55 °C, 100 K

P/E cycles

Guaranteed by

characterization

SID182

F_RET1

F_RET2

–

Flash retention. T_A 85 °C, 10 K

P/E cycles

Guaranteed by

characterization

SID182A

10

–

years

System Resources

Power-on-Reset (POR) with Brown Out

Table 26. Imprecise Power On Reset (PRES)

Spec ID

SID185

Parameter

V_RISEIPOR

Description

Rising trip voltage

Min

Typ

Max

Units

Details/Conditions

Guaranteed by

characterization

0.80

–

1.50

1.4

V

Guaranteed by

characterization

SID186

V_FALLIPOR

Falling trip voltage

0.75

V

Table 27. Precise Power On Reset (POR)

Spec ID Parameter

SID190 V_FALLPPOR

Description

Min

Typ

Max

Units

Details/Conditions

BOD trip voltage in active and

sleep modes

Guaranteed by

characterization

1.48

–

1.62

V

Guaranteed by

characterization

SID192

V_FALLDPSLP

BOD trip voltage in Deep Sleep

1.1

–

1.5

V

SWD Interface

Table 28. SWD Interface Specifications

Spec ID

Parameter

Description

Min

Typ

–

Max

Units

Details/Conditions

SID.SWD#1 F_SWDCLK1

SID.SWD#2 F_SWDCLK2

3.3 V  V_DDIO 5.5 V

1.8 V  V_DDIO 3.3 V

–

14

MHz SWDCLK ≤ 1/3 CPU clock frequency

–

0.25 * T

–

7

SID.SWD#3 T_SWDI_SETUP T = 1/f SWDCLK

SID.SWD#4 T_SWDI_HOLD T = 1/f SWDCLK

–

ns

Guaranteed by characterization

–

SID.SWD#5 T_SWDO_VALID T = 1/f SWDCLK

SID.SWD#6 T_SWDO_HOLD T = 1/f SWDCLK

–

0.5*T

–

1

–

Note

6. It can take as much as 20 milliseconds to write to Flash. During this time the device should not be Reset, or Flash operations will be interrupted and cannot be relied

on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs.

Make certain that these are not inadvertently activated.

Document Number: 002-11084 Rev. **

Page 25 of 34

PRELIMINARY

EZ-PD™ CCG4M

Internal Main Oscillator

Table 29. IMO DC Specifications

(Guaranteed by Design)

Spec ID

SID218

Parameter

I_IMO

Description

Min

Typ

Max

Units

Details/Conditions

IMO operating current at 48 MHz

–

1000

µA

–

Table 30. IMO AC Specifications

Spec ID Parameter

SID.CLK#13 F_IMOTOL

Description

Min

Typ

Max

Units

Details/Conditions

Frequency variation at 24, 36,

and 48 MHz (trimmed)

–

±2

%

–

SID226

SID229

F_IMO

T_STARTIMO

T_JITRMSIMO

–

IMO startup time

RMS jitter at 48 MHz

IMO frequency

–

145

–

7

–

µs

ps

–

24

48

MHz

Internal Low-Speed Oscillator

Table 31. ILO DC Specifications

(Guaranteed by Design)

Spec ID

SID231

SID233

Parameter

I_ILO

I_ILOLEAK

Description

Min

–

Typ

0.3

2

Max

1.05

15

Units

µA

Details/Conditions

Guaranteed by

Characterization

ILO operating current at 32 kHz

ILO leakage current

–

nA

Guaranteed by Design

Table 32. ILO AC Specifications

Spec ID

Parameter

T_STARTILO

Description

Min

Typ

Max

Units

Details/Conditions

Guaranteed by

characterization

SID234

ILO startup time

–

2

ms

Guaranteed by

characterization

SID236

T_ILODUTY

ILO duty cycle

ILO Frequency

40

20

50

40

60

80

%

SID.CLK#5 F_ILO

kHz

–

Power Down

Table 33. PD DC Specifications

Spec ID

Parameter

Description

Min Typ Max Units

Details/Conditions

DFP CC termination for default USB

Power

SID.PD.1 Rp_std

64

80

96

µA

–

SID.PD.2 Rp_1.5A

SID.PD.3 Rp_3.0A

SID.PD.4 Rd

DFP CC termination for 1.5A power

DFP CC termination for 3.0A power

UFP CC termination

166 180 194

304 330 356

µA

–

4.59 5.1 5.61 kꢀ

–

All supplies forced to 0 V and 0.6 V

4.08 5.1 6.12 kꢀ applied at CC1 or CC2. Applicable

UFP Dead Battery CC termination on

CC1 and CC2

SID.PD.5 Rd_DB

for DRP applications only.

Voltage drop from V5V_P1 and

SID.PD.15 Vdrop_V5V_CC1 V5V_P2 pins to CC1 pin while

sourcing 215 mA

–

100 mV

–

Voltage drop from V5V_P1 and

SID.PD.16 Vdrop_V5V_CC2 V5V_P2 pins to CC2 pin while

sourcing 215 mA

Document Number: 002-11084 Rev. **

Page 26 of 34

PRELIMINARY

EZ-PD™ CCG4M

Analog to Digital Converter

Table 34. ADC DC Specifications

Spec ID

Parameter

Description

Min Typ Max Units

Details/Conditions

SID.ADC.1 Resolution ADC resolution

–

8

–

bits

LSB

–

SID.ADC.2 INL

SID.ADC.3 DNL

Integral non-linearity

Differential non-linearity

–1.5

–2.5

–1.0

1.5

2.5

1.0

SID.ADC.4 Gain Error Gain error

Table 35. ADC AC Specifications

Spec ID

Parameter

Description

Min Typ Max Units

V/ms

Details/Conditions

Rate of change of sampled voltage

signal

SID.ADC.5 SLEW_Max

–

3

–

Document Number: 002-11084 Rev. **

Page 27 of 34

PRELIMINARY

EZ-PD™ CCG4M

Ordering Information

The EZ-PD CCG4M part numbers and features are listed in Table 36.

Table 36. EZ-PD CCG4M Ordering Information

Type-C

Ports

Dead Battery

Termination

Resistor

Part Number

Application

Role

Package

[8]

CYPD4255-96BZXI

CYPD4155-96BZXI

Notebooks, Desktops

2

1

Yes

R_P^[7], R_D

DRP

96-ball BGA

[8]

Yes

Ordering Code Definitions

0

X

XX XX

X

I

T

4

CY PD

-

1/2

T = Tape and Reel

Temperature Grade:

I = Industrial

Pb-free

Package Type: XX = BZ

BZ = BGA

Number of pins in the package: XX = 96

Device Role: Unique combination of role and termination:

X = 2 or 3 or 4 or 5

Feature: Unique Applications

Number of Type-C Ports: 1 = 1 Port, 2 = 2 Ports

Product Type: 4 = Fourth-generation product family

Marketing Code: PD = Power Delivery product family

Company ID: CY = Cypress

Notes

7. Termination resistor denoting an accessory or downstream facing port.

8. Termination resistor denoting a upstream facing port.

Document Number: 002-11084 Rev. **

Page 28 of 34

PRELIMINARY

EZ-PD™ CCG4M

Packaging

Table 37. Package Characteristics

Parameter

T_A

Description

Conditions

Min

–40

–

Typ

25

–

Max

85

100

–

Units

°C

Operating ambient temperature

Operating junction temperature

Package θ_JA(96-ball BGA)

Package θ_JC(96-ball BGA)

–

T_J

°C

T_JA

T_JC

62

23

°C/W

–

Table 38. Solder Reflow Peak Temperature

Package

Maximum Peak Temperature

245 °C

Maximum Time within 5 °C of Peak Temperature

96-ball BGA

30 seconds

Table 39. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2

Package

MSL

96-ball BGA

MSL 3

Document Number: 002-11084 Rev. **

Page 29 of 34

PRELIMINARY

EZ-PD™ CCG4M

Figure 7. 96-Ball BGA(6 × 6 × 0.5 mm), 002-10631

E1

2X

0.10 C

(datum B)

A1 CORNER

E

B

A

1110 9

8

7 6 5 4 3 2 1

A

7

B

C

D

E

A1 CORNER

6

SD

D1

F

D

G

H

(datum A)

J

K

L

eD

6

2X

0.10 C

eE

SE

TOP VIEW

BOTTOM VIEW

DETAIL A

0.10 C

A

A1

0.08 C

C

96XØb

5

SIDE VIEW

Ø0.15 M C A B

Ø0.05 M C

DETAIL A

NOTES:

1. ALL DIMENSIONS ARE IN MILLIMETERS.

DIMENSIONS

SYMBOL

2. SOLDER BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020.

3. "e" REPRESENTS THE SOLDER BALL GRID PITCH.

MIN.

NOM.

MAX.

A

1.00

-

4. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.

SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.

N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX

SIZE MD X ME.

A1

D

0.16

6.00 BSC

E

6.00 BSC

5.00 BSC

11

D1

E1

MD

ME

N

5.

DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A

PLANE PARALLEL TO DATUM C.

6.

"SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND

DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.

11

96

WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW,

"SD" OR "SE" = 0.

0.30

b

0.25

0.35

eD

eE

SD

SE

0.50 BSC

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW,

"SD" = eD/2 AND "SE" = eE/2.

0.50 BSC

0.00

A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK

METALIZED MARK, INDENTATION OR OTHER MEANS.

7.

0.00

8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED SOLDER

BALLS.

9. JEDEC SPECIFICATION NO. REF. : MO-225.

002-10631 **

Document Number: 002-11084 Rev. **

Page 30 of 34

PRELIMINARY

EZ-PD™ CCG4M

Table 40. Acronyms Used in this Document (continued)

Acronyms

Acronym

opamp

OCP

OVP

PCB

Description

operational amplifier

Table 40. Acronyms Used in this Document

Acronym

ADC

Description

analog-to-digital converter

overcurrent protection

overvoltage protection

printed circuit board

power delivery

API

ARM^®

application programming interface

advanced RISC machine, a CPU architecture

configuration channel

PD

CC

PGA

PHY

programmable gain amplifier

physical layer

CPU

central processing unit

cyclic redundancy check, an error-checking

protocol

CRC

POR

PRES

PSoC^®

PWM

RAM

RISC

RMS

RTC

power-on reset

CS

current sense

precise power-on reset

Programmable System-on-Chip™

pulse-width modulator

random-access memory

reduced-instruction-set computing

root-mean-square

DFP

downstream facing port

digital input/output, GPIO with only digital

capabilities, no analog. See GPIO.

DIO

DRP

dual role port

electrically erasable programmable read-only

memory

EEPROM

real-time clock

a USB cable that includes an IC that reports cable

characteristics (e.g., current rating) to the Type-C

ports

EMCA

RX

receive

SAR

successive approximation register

I²C serial clock

I²C serial data

EMI

ESD

FPB

FS

electromagnetic interference

electrostatic discharge

flash patch and breakpoint

full-speed

SCL

SDA

S/H

sample and hold

Serial Peripheral Interface, a communications

protocol

SPI

GPIO

IC

general-purpose input/output

integrated circuit

SRAM

SWD

TX

static random access memory

serial wire debug, a test protocol

transmit

IDE

integrated development environment

I²C, or IIC Inter-Integrated Circuit, a communications protocol

ILO

internal low-speed oscillator, see also IMO

internal main oscillator, see also ILO

input/output, see also GPIO

low-voltage detect

a new standard with a slimmer USB connector and

a reversible cable, capable of sourcing up to 100 W

of power

Type-C

IMO

I/O

Universal Asynchronous Transmitter Receiver, a

communications protocol

UART

USB

LVD

LVTTL

MCU

NC

low-voltage transistor-transistor logic

microcontroller unit

Universal Serial Bus

USB input/output, CCG4M pins used to connect to

a USB port

USBIO

XRES

no connect

external reset I/O pin

NMI

NVIC

nonmaskable interrupt

nested vectored interrupt controller

Document Number: 002-11084 Rev. **

Page 31 of 34

PRELIMINARY

EZ-PD™ CCG4M

Document Conventions

Units of Measure

Table 41. Units of Measure

Symbol

°C

Unit of Measure

degrees Celsius

hertz

Hz

KB

kHz

k

Mbps

MHz

M

Msps

µA

1024 bytes

kilohertz

kilo ohm

megabits per second

megahertz

mega-ohm

megasamples per second

microampere

microfarad

microsecond

microvolt

µF

µs

µV

µW

mA

ms

mV

nA

microwatt

milliampere

millisecond

millivolt

nanoampere

nanosecond

ohm

ns



pF

picofarad

ppm

ps

parts per million

picosecond

second

s

sps

V

samples per second

volt

Document Number: 002-11084 Rev. **

Page 32 of 34

PRELIMINARY

EZ-PD™ CCG4M

Document History Page

Document Title: EZ-PD™ CCG4M USB Type-C Dual Port Controller with USB 3.1 Gen 1/DP1.2 Mux

Document Number: 002-11084

Orig. of

Change

Submission

Date

Revision

ECN

Description of Change

**

5131574

VGT

02/18/2016 New datasheet

Document Number: 002-11084 Rev. **

Page 33 of 34

PRELIMINARY

EZ-PD™ CCG4M

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office

closest to you, visit us at Cypress Locations.

®

Products

PSoC Solutions

Automotive

cypress.com/go/automotive

cypress.com/go/clocks

cypress.com/go/interface

cypress.com/go/powerpsoc

cypress.com/go/memory

cypress.com/go/psoc

psoc.cypress.com/solutions

PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP

Clocks & Buffers

Interface

Cypress Developer Community

Lighting & Power Control

Memory

Community | Forums | Blogs | Video | Training

Technical Support

PSoC

cypress.com/go/support

Touch Sensing

USB Controllers

Wireless/RF

cypress.com/go/touch

cypress.com/go/USB

cypress.com/go/wireless

any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide.

Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual

property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby

grants you under its copyright rights in the Software, a personal, non-exclusive, nontransferable license (without the right to sublicense) (a) for Software provided in source code form, to modify and

reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either

directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units. Cypress also grants you a personal, non-exclusive, nontransferable, license (without the right

to sublicense) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely to the minimum

extent that is necessary for you to exercise your rights under the copyright license granted in the previous sentence. Any other use, reproduction, modification, translation, or compilation of the Software

is prohibited.

CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED

WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes to this document without further notice. Cypress does not

assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or

programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application

made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of

weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or

hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any

component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole

or in part, and Company shall and hereby does release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. Company shall indemnify

and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress

products.

Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United

States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.

Document Number: 002-11084 Rev. **

Revised February 18, 2016

Page 34 of 34

All products and company names mentioned in this document may be the trademarks of their respective holders.

厂商	型号	描述	页数
NIDEC	CYP	[ PIANO SWITCHES (FULL PITCH) ]	5 页
NIDEC	CYP-0200MB	[ PIANO SWITCHES (FULL PITCH) ]	5 页
NIDEC	CYP-0200MC	[ PIANO SWITCHES (FULL PITCH) ]	5 页
NIDEC	CYP-0200TB	[ PIANO SWITCHES (FULL PITCH) ]	5 页
NIDEC	CYP-0200TC	[ PIANO SWITCHES (FULL PITCH) ]	5 页
NIDEC	CYP-0201MB	[ PIANO SWITCHES (FULL PITCH) ]	5 页
NIDEC	CYP-0201MC	[ PIANO SWITCHES (FULL PITCH) ]	5 页
NIDEC	CYP-0201TB	[ PIANO SWITCHES (FULL PITCH) ]	5 页
NIDEC	CYP-0201TC	[ PIANO SWITCHES (FULL PITCH) ]	5 页
NIDEC	CYP-0202MB	[ PIANO SWITCHES (FULL PITCH) ]	5 页